1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2021 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K344_SCB.h 10 * @version 1.5 11 * @date 2020-11-11 12 * @brief Peripheral Access Layer for S32K344_SCB 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K344_SCB_H_) /* Check if memory map has not been already included */ 58 #define S32K344_SCB_H_ 59 60 #include "S32K344_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- S32_SCB Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup S32_SCB_Peripheral_Access_Layer S32_SCB Peripheral Access Layer 68 * @{ 69 */ 70 71 /** S32_SCB - Size of Registers Arrays */ 72 #define S32_SCB_ID_MMFR_COUNT 4u 73 #define S32_SCB_ID_ISAR_COUNT 5u 74 #define S32_SCB_PID_COUNT 8u 75 #define S32_SCB_CID_COUNT 4u 76 77 /** S32_SCB - Register Layout Typedef */ 78 typedef struct { 79 uint8_t RESERVED_0[8]; 80 __IO uint32_t ACTLR; /**< Auxiliary Control Register, offset: 0x8 */ 81 uint8_t RESERVED_1[3316]; 82 __I uint32_t CPUID; /**< CPUID Base Register, offset: 0xD00 */ 83 __IO uint32_t ICSR; /**< Interrupt Control and State Register, offset: 0xD04 */ 84 __IO uint32_t VTOR; /**< Vector Table Offset Register, offset: 0xD08 */ 85 __IO uint32_t AIRCR; /**< Application Interrupt and Reset Control Register, offset: 0xD0C */ 86 __IO uint32_t SCR; /**< System Control Register, offset: 0xD10 */ 87 __IO uint32_t CCR; /**< Configuration and Control Register, offset: 0xD14 */ 88 __IO uint32_t SHPR1; /**< System Handler Priority Register 1, offset: 0xD18 */ 89 __IO uint32_t SHPR2; /**< System Handler Priority Register 2, offset: 0xD1C */ 90 __IO uint32_t SHPR3; /**< System Handler Priority Register 3, offset: 0xD20 */ 91 __IO uint32_t SHCSR; /**< System Handler Control and State Register, offset: 0xD24 */ 92 __IO uint32_t CFSR; /**< Configurable Fault Status Registers, offset: 0xD28 */ 93 __IO uint32_t HFSR; /**< HardFault Status Register, offset: 0xD2C */ 94 __IO uint32_t DFSR; /**< Debug Fault Status Register, offset: 0xD30 */ 95 __IO uint32_t MMFAR; /**< Memanage Fault Address Register, offset: 0xD34 */ 96 __IO uint32_t BFAR; /**< BusFault Address Registerd, offset: 0xD38 */ 97 __IO uint32_t AFSR; /**< Auxiliary Fault Status Register, offset: 0xD3C */ 98 __I uint32_t ID_PFR0; /**< Processor Feature Register 0, offset: 0xD40 */ 99 __I uint32_t ID_PFR1; /**< Processor Feature Register 1, offset: 0xD44 */ 100 __I uint32_t ID_DFR0; /**< Debug Feature Register 0, offset: 0xD48 */ 101 __I uint32_t ID_AFR0; /**< Auxiliary Feature Register 0, offset: 0xD4C */ 102 __I uint32_t ID_MMFR[S32_SCB_ID_MMFR_COUNT]; /**< Memory Model Feature Register 0..Memory Model Feature Register 3, array offset: 0xD50, array step: 0x4 */ 103 __I uint32_t ID_ISAR[S32_SCB_ID_ISAR_COUNT]; /**< Instruction Set Attributes Register 0..Instruction Set Attributes Register 4, array offset: 0xD60, array step: 0x4 */ 104 uint8_t RESERVED_2[4]; 105 __I uint32_t CLIDR; /**< Cache Level ID Register, offset: 0xD78 */ 106 __I uint32_t CTR; /**< Cache Type Register, offset: 0xD7C */ 107 __I uint32_t CCSIDR; /**< Cache Size ID Register, offset: 0xD80 */ 108 __IO uint32_t CSSELR; /**< Cache Size Selection Register, offset: 0xD84 */ 109 __IO uint32_t CPACR; /**< Coprocessor Access Control Register, offset: 0xD88 */ 110 uint8_t RESERVED_3[372]; 111 __O uint32_t STIR; /**< Software Triggered Interrupt Register, offset: 0xF00 */ 112 uint8_t RESERVED_4[48]; 113 __IO uint32_t FPCCR; /**< Floating-point Context Control Register, offset: 0xF34 */ 114 __IO uint32_t FPCAR; /**< Floating-point Context Address Register, offset: 0xF38 */ 115 __IO uint32_t FPDSCR; /**< Floating-point Default Status Control Register, offset: 0xF3C */ 116 uint8_t RESERVED_5[16]; 117 __O uint32_t ICIALLU; /**< Instruction cache invalidate all to Point of Unification (PoU), offset: 0xF50 */ 118 uint8_t RESERVED_6[4]; 119 __O uint32_t ICIMVAU; /**< Instruction cache invalidate by address to PoU, offset: 0xF58 */ 120 __O uint32_t DCIMVAC; /**< Data cache invalidate by address to Point of Coherency (PoC), offset: 0xF5C */ 121 __O uint32_t DCISW; /**< Data cache invalidate by set/way, offset: 0xF60 */ 122 __O uint32_t DCCMVAU; /**< Data cache by address to PoU, offset: 0xF64 */ 123 __O uint32_t DCCMVAC; /**< Data cache clean by address to PoC, offset: 0xF68 */ 124 __O uint32_t DCCSW; /**< Data cache clean by set/way, offset: 0xF6C */ 125 __O uint32_t DCCIMVAC; /**< Data cache clean and invalidate by address to PoC, offset: 0xF70 */ 126 __O uint32_t DCCISW; /**< Data cache clean and invalidate by set/way, offset: 0xF74 */ 127 __I uint32_t BPIALL; /**< Not implemented - RAZ/WI, offset: 0xF78 */ 128 uint8_t RESERVED_7[20]; 129 __IO uint32_t ITCMCR; /**< Instruction Tightly-Coupled Memory Control Register, offset: 0xF90 */ 130 __IO uint32_t DTCMCR; /**< Data Tightly-Coupled Memory Control Register, offset: 0xF94 */ 131 __IO uint32_t AHBPCR; /**< AHBP control register, offset: 0xF98 */ 132 __IO uint32_t CACR; /**< L1 Cache Control Register, offset: 0xF9C */ 133 __IO uint32_t AHBSCR; /**< AHB Slave Control Register, offset: 0xFA0 */ 134 uint8_t RESERVED_8[4]; 135 __IO uint32_t ABFSR; /**< Asynchronous Bus Fault Status Register, offset: 0xFA8 */ 136 uint8_t RESERVED_9[4]; 137 __IO uint32_t IEBR0; /**< Instruction Error bank Register 0, offset: 0xFB0 */ 138 __IO uint32_t IEBR1h; /**< Instruction Error bank Register 1, offset: 0xFB4 */ 139 __IO uint32_t DEBR0h; /**< Data Error bank Register 0, offset: 0xFB8 */ 140 __IO uint32_t DEBR1h; /**< Data Error bank Register 1, offset: 0xFBC */ 141 uint8_t RESERVED_10[16]; 142 __I uint32_t PID[S32_SCB_PID_COUNT]; /**< Peripheral identification register 0..Peripheral identification register 7, array offset: 0xFD0, array step: 0x4 */ 143 __I uint32_t CID[S32_SCB_CID_COUNT]; /**< Component identification register 0..Component identification register 3, array offset: 0xFF0, array step: 0x4 */ 144 } S32_SCB_Type, *S32_SCB_MemMapPtr; 145 146 /** Number of instances of the S32_SCB module. */ 147 #define S32_SCB_INSTANCE_COUNT (1u) 148 149 /* S32_SCB - Peripheral instance base addresses */ 150 /** Peripheral S32_SCB base address */ 151 #define S32_SCB_BASE (0xE000E000u) 152 /** Peripheral S32_SCB base pointer */ 153 #define S32_SCB ((S32_SCB_Type *)S32_SCB_BASE) 154 /** Array initializer of S32_SCB peripheral base addresses */ 155 #define S32_SCB_BASE_ADDRS { S32_SCB_BASE } 156 /** Array initializer of S32_SCB peripheral base pointers */ 157 #define S32_SCB_BASE_PTRS { S32_SCB } 158 159 /* ---------------------------------------------------------------------------- 160 -- S32_SCB Register Masks 161 ---------------------------------------------------------------------------- */ 162 163 /*! 164 * @addtogroup S32_SCB_Register_Masks S32_SCB Register Masks 165 * @{ 166 */ 167 168 /* ACTLR Bit Fields */ 169 #define S32_SCB_ACTLR_ACTLR_MASK 0xFFFFFFFFu 170 #define S32_SCB_ACTLR_ACTLR_SHIFT 0u 171 #define S32_SCB_ACTLR_ACTLR_WIDTH 32u 172 #define S32_SCB_ACTLR_ACTLR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ACTLR_ACTLR_SHIFT))&S32_SCB_ACTLR_ACTLR_MASK) 173 /* CPUID Bit Fields */ 174 #define S32_SCB_CPUID_REVISION_MASK 0xFu 175 #define S32_SCB_CPUID_REVISION_SHIFT 0u 176 #define S32_SCB_CPUID_REVISION_WIDTH 4u 177 #define S32_SCB_CPUID_REVISION(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CPUID_REVISION_SHIFT))&S32_SCB_CPUID_REVISION_MASK) 178 #define S32_SCB_CPUID_PARTNO_MASK 0xFFF0u 179 #define S32_SCB_CPUID_PARTNO_SHIFT 4u 180 #define S32_SCB_CPUID_PARTNO_WIDTH 12u 181 #define S32_SCB_CPUID_PARTNO(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CPUID_PARTNO_SHIFT))&S32_SCB_CPUID_PARTNO_MASK) 182 #define S32_SCB_CPUID_VARIANT_MASK 0xF00000u 183 #define S32_SCB_CPUID_VARIANT_SHIFT 20u 184 #define S32_SCB_CPUID_VARIANT_WIDTH 4u 185 #define S32_SCB_CPUID_VARIANT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CPUID_VARIANT_SHIFT))&S32_SCB_CPUID_VARIANT_MASK) 186 #define S32_SCB_CPUID_IMPLEMENTER_MASK 0xFF000000u 187 #define S32_SCB_CPUID_IMPLEMENTER_SHIFT 24u 188 #define S32_SCB_CPUID_IMPLEMENTER_WIDTH 8u 189 #define S32_SCB_CPUID_IMPLEMENTER(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CPUID_IMPLEMENTER_SHIFT))&S32_SCB_CPUID_IMPLEMENTER_MASK) 190 /* ICSR Bit Fields */ 191 #define S32_SCB_ICSR_VECTACTIVE_MASK 0x1FFu 192 #define S32_SCB_ICSR_VECTACTIVE_SHIFT 0u 193 #define S32_SCB_ICSR_VECTACTIVE_WIDTH 9u 194 #define S32_SCB_ICSR_VECTACTIVE(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_VECTACTIVE_SHIFT))&S32_SCB_ICSR_VECTACTIVE_MASK) 195 #define S32_SCB_ICSR_RETTOBASE_MASK 0x800u 196 #define S32_SCB_ICSR_RETTOBASE_SHIFT 11u 197 #define S32_SCB_ICSR_RETTOBASE_WIDTH 1u 198 #define S32_SCB_ICSR_RETTOBASE(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_RETTOBASE_SHIFT))&S32_SCB_ICSR_RETTOBASE_MASK) 199 #define S32_SCB_ICSR_VECTPENDING_MASK 0x3F000u 200 #define S32_SCB_ICSR_VECTPENDING_SHIFT 12u 201 #define S32_SCB_ICSR_VECTPENDING_WIDTH 6u 202 #define S32_SCB_ICSR_VECTPENDING(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_VECTPENDING_SHIFT))&S32_SCB_ICSR_VECTPENDING_MASK) 203 #define S32_SCB_ICSR_ISRPENDING_MASK 0x400000u 204 #define S32_SCB_ICSR_ISRPENDING_SHIFT 22u 205 #define S32_SCB_ICSR_ISRPENDING_WIDTH 1u 206 #define S32_SCB_ICSR_ISRPENDING(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_ISRPENDING_SHIFT))&S32_SCB_ICSR_ISRPENDING_MASK) 207 #define S32_SCB_ICSR_ISRPREEMPT_MASK 0x800000u 208 #define S32_SCB_ICSR_ISRPREEMPT_SHIFT 23u 209 #define S32_SCB_ICSR_ISRPREEMPT_WIDTH 1u 210 #define S32_SCB_ICSR_ISRPREEMPT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_ISRPREEMPT_SHIFT))&S32_SCB_ICSR_ISRPREEMPT_MASK) 211 #define S32_SCB_ICSR_PENDSTCLR_MASK 0x2000000u 212 #define S32_SCB_ICSR_PENDSTCLR_SHIFT 25u 213 #define S32_SCB_ICSR_PENDSTCLR_WIDTH 1u 214 #define S32_SCB_ICSR_PENDSTCLR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_PENDSTCLR_SHIFT))&S32_SCB_ICSR_PENDSTCLR_MASK) 215 #define S32_SCB_ICSR_PENDSTSET_MASK 0x4000000u 216 #define S32_SCB_ICSR_PENDSTSET_SHIFT 26u 217 #define S32_SCB_ICSR_PENDSTSET_WIDTH 1u 218 #define S32_SCB_ICSR_PENDSTSET(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_PENDSTSET_SHIFT))&S32_SCB_ICSR_PENDSTSET_MASK) 219 #define S32_SCB_ICSR_PENDSVCLR_MASK 0x8000000u 220 #define S32_SCB_ICSR_PENDSVCLR_SHIFT 27u 221 #define S32_SCB_ICSR_PENDSVCLR_WIDTH 1u 222 #define S32_SCB_ICSR_PENDSVCLR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_PENDSVCLR_SHIFT))&S32_SCB_ICSR_PENDSVCLR_MASK) 223 #define S32_SCB_ICSR_PENDSVSET_MASK 0x10000000u 224 #define S32_SCB_ICSR_PENDSVSET_SHIFT 28u 225 #define S32_SCB_ICSR_PENDSVSET_WIDTH 1u 226 #define S32_SCB_ICSR_PENDSVSET(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_PENDSVSET_SHIFT))&S32_SCB_ICSR_PENDSVSET_MASK) 227 #define S32_SCB_ICSR_NMIPENDSET_MASK 0x80000000u 228 #define S32_SCB_ICSR_NMIPENDSET_SHIFT 31u 229 #define S32_SCB_ICSR_NMIPENDSET_WIDTH 1u 230 #define S32_SCB_ICSR_NMIPENDSET(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_NMIPENDSET_SHIFT))&S32_SCB_ICSR_NMIPENDSET_MASK) 231 /* VTOR Bit Fields */ 232 #define S32_SCB_VTOR_TBLOFF_MASK 0xFFFFFF80u 233 #define S32_SCB_VTOR_TBLOFF_SHIFT 7u 234 #define S32_SCB_VTOR_TBLOFF_WIDTH 25u 235 #define S32_SCB_VTOR_TBLOFF(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_VTOR_TBLOFF_SHIFT))&S32_SCB_VTOR_TBLOFF_MASK) 236 /* AIRCR Bit Fields */ 237 #define S32_SCB_AIRCR_AIRCR_MASK 0xFFFFFFFFu 238 #define S32_SCB_AIRCR_AIRCR_SHIFT 0u 239 #define S32_SCB_AIRCR_AIRCR_WIDTH 32u 240 #define S32_SCB_AIRCR_AIRCR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_AIRCR_AIRCR_SHIFT))&S32_SCB_AIRCR_AIRCR_MASK) 241 /* SCR Bit Fields */ 242 #define S32_SCB_SCR_SLEEPONEXIT_MASK 0x2u 243 #define S32_SCB_SCR_SLEEPONEXIT_SHIFT 1u 244 #define S32_SCB_SCR_SLEEPONEXIT_WIDTH 1u 245 #define S32_SCB_SCR_SLEEPONEXIT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SCR_SLEEPONEXIT_SHIFT))&S32_SCB_SCR_SLEEPONEXIT_MASK) 246 #define S32_SCB_SCR_SLEEPDEEP_MASK 0x4u 247 #define S32_SCB_SCR_SLEEPDEEP_SHIFT 2u 248 #define S32_SCB_SCR_SLEEPDEEP_WIDTH 1u 249 #define S32_SCB_SCR_SLEEPDEEP(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SCR_SLEEPDEEP_SHIFT))&S32_SCB_SCR_SLEEPDEEP_MASK) 250 #define S32_SCB_SCR_SEVONPEND_MASK 0x10u 251 #define S32_SCB_SCR_SEVONPEND_SHIFT 4u 252 #define S32_SCB_SCR_SEVONPEND_WIDTH 1u 253 #define S32_SCB_SCR_SEVONPEND(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SCR_SEVONPEND_SHIFT))&S32_SCB_SCR_SEVONPEND_MASK) 254 /* CCR Bit Fields */ 255 #define S32_SCB_CCR_CCR_MASK 0xFFFFFFFFu 256 #define S32_SCB_CCR_CCR_SHIFT 0u 257 #define S32_SCB_CCR_CCR_WIDTH 32u 258 #define S32_SCB_CCR_CCR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CCR_CCR_SHIFT))&S32_SCB_CCR_CCR_MASK) 259 /* SHPR1 Bit Fields */ 260 #define S32_SCB_SHPR1_SHPR1_MASK 0xFFFFFFFFu 261 #define S32_SCB_SHPR1_SHPR1_SHIFT 0u 262 #define S32_SCB_SHPR1_SHPR1_WIDTH 32u 263 #define S32_SCB_SHPR1_SHPR1(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHPR1_SHPR1_SHIFT))&S32_SCB_SHPR1_SHPR1_MASK) 264 /* SHPR2 Bit Fields */ 265 #define S32_SCB_SHPR2_SHPR2_MASK 0xFFFFFFFFu 266 #define S32_SCB_SHPR2_SHPR2_SHIFT 0u 267 #define S32_SCB_SHPR2_SHPR2_WIDTH 32u 268 #define S32_SCB_SHPR2_SHPR2(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHPR2_SHPR2_SHIFT))&S32_SCB_SHPR2_SHPR2_MASK) 269 /* SHPR3 Bit Fields */ 270 #define S32_SCB_SHPR3_SHPR3_MASK 0xFFFFFFFFu 271 #define S32_SCB_SHPR3_SHPR3_SHIFT 0u 272 #define S32_SCB_SHPR3_SHPR3_WIDTH 32u 273 #define S32_SCB_SHPR3_SHPR3(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHPR3_SHPR3_SHIFT))&S32_SCB_SHPR3_SHPR3_MASK) 274 /* SHCSR Bit Fields */ 275 #define S32_SCB_SHCSR_MEMFAULTACT_MASK 0x1u 276 #define S32_SCB_SHCSR_MEMFAULTACT_SHIFT 0u 277 #define S32_SCB_SHCSR_MEMFAULTACT_WIDTH 1u 278 #define S32_SCB_SHCSR_MEMFAULTACT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_MEMFAULTACT_SHIFT))&S32_SCB_SHCSR_MEMFAULTACT_MASK) 279 #define S32_SCB_SHCSR_BUSFAULTACT_MASK 0x2u 280 #define S32_SCB_SHCSR_BUSFAULTACT_SHIFT 1u 281 #define S32_SCB_SHCSR_BUSFAULTACT_WIDTH 1u 282 #define S32_SCB_SHCSR_BUSFAULTACT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_BUSFAULTACT_SHIFT))&S32_SCB_SHCSR_BUSFAULTACT_MASK) 283 #define S32_SCB_SHCSR_USGFAULTACT_MASK 0x8u 284 #define S32_SCB_SHCSR_USGFAULTACT_SHIFT 3u 285 #define S32_SCB_SHCSR_USGFAULTACT_WIDTH 1u 286 #define S32_SCB_SHCSR_USGFAULTACT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_USGFAULTACT_SHIFT))&S32_SCB_SHCSR_USGFAULTACT_MASK) 287 #define S32_SCB_SHCSR_SVCALLACT_MASK 0x80u 288 #define S32_SCB_SHCSR_SVCALLACT_SHIFT 7u 289 #define S32_SCB_SHCSR_SVCALLACT_WIDTH 1u 290 #define S32_SCB_SHCSR_SVCALLACT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_SVCALLACT_SHIFT))&S32_SCB_SHCSR_SVCALLACT_MASK) 291 #define S32_SCB_SHCSR_MONITORACT_MASK 0x100u 292 #define S32_SCB_SHCSR_MONITORACT_SHIFT 8u 293 #define S32_SCB_SHCSR_MONITORACT_WIDTH 1u 294 #define S32_SCB_SHCSR_MONITORACT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_MONITORACT_SHIFT))&S32_SCB_SHCSR_MONITORACT_MASK) 295 #define S32_SCB_SHCSR_PENDSVACT_MASK 0x400u 296 #define S32_SCB_SHCSR_PENDSVACT_SHIFT 10u 297 #define S32_SCB_SHCSR_PENDSVACT_WIDTH 1u 298 #define S32_SCB_SHCSR_PENDSVACT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_PENDSVACT_SHIFT))&S32_SCB_SHCSR_PENDSVACT_MASK) 299 #define S32_SCB_SHCSR_SYSTICKACT_MASK 0x800u 300 #define S32_SCB_SHCSR_SYSTICKACT_SHIFT 11u 301 #define S32_SCB_SHCSR_SYSTICKACT_WIDTH 1u 302 #define S32_SCB_SHCSR_SYSTICKACT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_SYSTICKACT_SHIFT))&S32_SCB_SHCSR_SYSTICKACT_MASK) 303 #define S32_SCB_SHCSR_USGFAULTPENDED_MASK 0x1000u 304 #define S32_SCB_SHCSR_USGFAULTPENDED_SHIFT 12u 305 #define S32_SCB_SHCSR_USGFAULTPENDED_WIDTH 1u 306 #define S32_SCB_SHCSR_USGFAULTPENDED(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_USGFAULTPENDED_SHIFT))&S32_SCB_SHCSR_USGFAULTPENDED_MASK) 307 #define S32_SCB_SHCSR_MEMFAULTPENDED_MASK 0x2000u 308 #define S32_SCB_SHCSR_MEMFAULTPENDED_SHIFT 13u 309 #define S32_SCB_SHCSR_MEMFAULTPENDED_WIDTH 1u 310 #define S32_SCB_SHCSR_MEMFAULTPENDED(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_MEMFAULTPENDED_SHIFT))&S32_SCB_SHCSR_MEMFAULTPENDED_MASK) 311 #define S32_SCB_SHCSR_BUSFAULTPENDED_MASK 0x4000u 312 #define S32_SCB_SHCSR_BUSFAULTPENDED_SHIFT 14u 313 #define S32_SCB_SHCSR_BUSFAULTPENDED_WIDTH 1u 314 #define S32_SCB_SHCSR_BUSFAULTPENDED(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_BUSFAULTPENDED_SHIFT))&S32_SCB_SHCSR_BUSFAULTPENDED_MASK) 315 #define S32_SCB_SHCSR_SVCALLPENDED_MASK 0x8000u 316 #define S32_SCB_SHCSR_SVCALLPENDED_SHIFT 15u 317 #define S32_SCB_SHCSR_SVCALLPENDED_WIDTH 1u 318 #define S32_SCB_SHCSR_SVCALLPENDED(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_SVCALLPENDED_SHIFT))&S32_SCB_SHCSR_SVCALLPENDED_MASK) 319 #define S32_SCB_SHCSR_MEMFAULTENA_MASK 0x10000u 320 #define S32_SCB_SHCSR_MEMFAULTENA_SHIFT 16u 321 #define S32_SCB_SHCSR_MEMFAULTENA_WIDTH 1u 322 #define S32_SCB_SHCSR_MEMFAULTENA(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_MEMFAULTENA_SHIFT))&S32_SCB_SHCSR_MEMFAULTENA_MASK) 323 #define S32_SCB_SHCSR_BUSFAULTENA_MASK 0x20000u 324 #define S32_SCB_SHCSR_BUSFAULTENA_SHIFT 17u 325 #define S32_SCB_SHCSR_BUSFAULTENA_WIDTH 1u 326 #define S32_SCB_SHCSR_BUSFAULTENA(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_BUSFAULTENA_SHIFT))&S32_SCB_SHCSR_BUSFAULTENA_MASK) 327 #define S32_SCB_SHCSR_USGFAULTENA_MASK 0x40000u 328 #define S32_SCB_SHCSR_USGFAULTENA_SHIFT 18u 329 #define S32_SCB_SHCSR_USGFAULTENA_WIDTH 1u 330 #define S32_SCB_SHCSR_USGFAULTENA(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_USGFAULTENA_SHIFT))&S32_SCB_SHCSR_USGFAULTENA_MASK) 331 /* CFSR Bit Fields */ 332 #define S32_SCB_CFSR_MMFSR_IACCVIOL_MASK 0x1u 333 #define S32_SCB_CFSR_MMFSR_IACCVIOL_SHIFT 0u 334 #define S32_SCB_CFSR_MMFSR_IACCVIOL_WIDTH 1u 335 #define S32_SCB_CFSR_MMFSR_IACCVIOL(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_MMFSR_IACCVIOL_SHIFT))&S32_SCB_CFSR_MMFSR_IACCVIOL_MASK) 336 #define S32_SCB_CFSR_MMFSR_DACCVIOL_MASK 0x2u 337 #define S32_SCB_CFSR_MMFSR_DACCVIOL_SHIFT 1u 338 #define S32_SCB_CFSR_MMFSR_DACCVIOL_WIDTH 1u 339 #define S32_SCB_CFSR_MMFSR_DACCVIOL(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_MMFSR_DACCVIOL_SHIFT))&S32_SCB_CFSR_MMFSR_DACCVIOL_MASK) 340 #define S32_SCB_CFSR_MMFSR_MUNSTKERR_MASK 0x8u 341 #define S32_SCB_CFSR_MMFSR_MUNSTKERR_SHIFT 3u 342 #define S32_SCB_CFSR_MMFSR_MUNSTKERR_WIDTH 1u 343 #define S32_SCB_CFSR_MMFSR_MUNSTKERR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_MMFSR_MUNSTKERR_SHIFT))&S32_SCB_CFSR_MMFSR_MUNSTKERR_MASK) 344 #define S32_SCB_CFSR_MMFSR_MSTKERR_MASK 0x10u 345 #define S32_SCB_CFSR_MMFSR_MSTKERR_SHIFT 4u 346 #define S32_SCB_CFSR_MMFSR_MSTKERR_WIDTH 1u 347 #define S32_SCB_CFSR_MMFSR_MSTKERR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_MMFSR_MSTKERR_SHIFT))&S32_SCB_CFSR_MMFSR_MSTKERR_MASK) 348 #define S32_SCB_CFSR_MMFSR_MLSPERR_MASK 0x20u 349 #define S32_SCB_CFSR_MMFSR_MLSPERR_SHIFT 5u 350 #define S32_SCB_CFSR_MMFSR_MLSPERR_WIDTH 1u 351 #define S32_SCB_CFSR_MMFSR_MLSPERR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_MMFSR_MLSPERR_SHIFT))&S32_SCB_CFSR_MMFSR_MLSPERR_MASK) 352 #define S32_SCB_CFSR_MMFSR_MMARVALID_MASK 0x80u 353 #define S32_SCB_CFSR_MMFSR_MMARVALID_SHIFT 7u 354 #define S32_SCB_CFSR_MMFSR_MMARVALID_WIDTH 1u 355 #define S32_SCB_CFSR_MMFSR_MMARVALID(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_MMFSR_MMARVALID_SHIFT))&S32_SCB_CFSR_MMFSR_MMARVALID_MASK) 356 #define S32_SCB_CFSR_BFSR_IBUSERR_MASK 0x100u 357 #define S32_SCB_CFSR_BFSR_IBUSERR_SHIFT 8u 358 #define S32_SCB_CFSR_BFSR_IBUSERR_WIDTH 1u 359 #define S32_SCB_CFSR_BFSR_IBUSERR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_BFSR_IBUSERR_SHIFT))&S32_SCB_CFSR_BFSR_IBUSERR_MASK) 360 #define S32_SCB_CFSR_BFSR_PRECISERR_MASK 0x200u 361 #define S32_SCB_CFSR_BFSR_PRECISERR_SHIFT 9u 362 #define S32_SCB_CFSR_BFSR_PRECISERR_WIDTH 1u 363 #define S32_SCB_CFSR_BFSR_PRECISERR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_BFSR_PRECISERR_SHIFT))&S32_SCB_CFSR_BFSR_PRECISERR_MASK) 364 #define S32_SCB_CFSR_BFSR_IMPRECISERR_MASK 0x400u 365 #define S32_SCB_CFSR_BFSR_IMPRECISERR_SHIFT 10u 366 #define S32_SCB_CFSR_BFSR_IMPRECISERR_WIDTH 1u 367 #define S32_SCB_CFSR_BFSR_IMPRECISERR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_BFSR_IMPRECISERR_SHIFT))&S32_SCB_CFSR_BFSR_IMPRECISERR_MASK) 368 #define S32_SCB_CFSR_BFSR_UNSTKERR_MASK 0x800u 369 #define S32_SCB_CFSR_BFSR_UNSTKERR_SHIFT 11u 370 #define S32_SCB_CFSR_BFSR_UNSTKERR_WIDTH 1u 371 #define S32_SCB_CFSR_BFSR_UNSTKERR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_BFSR_UNSTKERR_SHIFT))&S32_SCB_CFSR_BFSR_UNSTKERR_MASK) 372 #define S32_SCB_CFSR_BFSR_STKERR_MASK 0x1000u 373 #define S32_SCB_CFSR_BFSR_STKERR_SHIFT 12u 374 #define S32_SCB_CFSR_BFSR_STKERR_WIDTH 1u 375 #define S32_SCB_CFSR_BFSR_STKERR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_BFSR_STKERR_SHIFT))&S32_SCB_CFSR_BFSR_STKERR_MASK) 376 #define S32_SCB_CFSR_BFSR_LSPERR_MASK 0x2000u 377 #define S32_SCB_CFSR_BFSR_LSPERR_SHIFT 13u 378 #define S32_SCB_CFSR_BFSR_LSPERR_WIDTH 1u 379 #define S32_SCB_CFSR_BFSR_LSPERR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_BFSR_LSPERR_SHIFT))&S32_SCB_CFSR_BFSR_LSPERR_MASK) 380 #define S32_SCB_CFSR_BFSR_BFARVALID_MASK 0x8000u 381 #define S32_SCB_CFSR_BFSR_BFARVALID_SHIFT 15u 382 #define S32_SCB_CFSR_BFSR_BFARVALID_WIDTH 1u 383 #define S32_SCB_CFSR_BFSR_BFARVALID(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_BFSR_BFARVALID_SHIFT))&S32_SCB_CFSR_BFSR_BFARVALID_MASK) 384 #define S32_SCB_CFSR_UFSR_UNDEFINSTR_MASK 0x10000u 385 #define S32_SCB_CFSR_UFSR_UNDEFINSTR_SHIFT 16u 386 #define S32_SCB_CFSR_UFSR_UNDEFINSTR_WIDTH 1u 387 #define S32_SCB_CFSR_UFSR_UNDEFINSTR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_UFSR_UNDEFINSTR_SHIFT))&S32_SCB_CFSR_UFSR_UNDEFINSTR_MASK) 388 #define S32_SCB_CFSR_UFSR_INVSTATE_MASK 0x20000u 389 #define S32_SCB_CFSR_UFSR_INVSTATE_SHIFT 17u 390 #define S32_SCB_CFSR_UFSR_INVSTATE_WIDTH 1u 391 #define S32_SCB_CFSR_UFSR_INVSTATE(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_UFSR_INVSTATE_SHIFT))&S32_SCB_CFSR_UFSR_INVSTATE_MASK) 392 #define S32_SCB_CFSR_UFSR_INVPC_MASK 0x40000u 393 #define S32_SCB_CFSR_UFSR_INVPC_SHIFT 18u 394 #define S32_SCB_CFSR_UFSR_INVPC_WIDTH 1u 395 #define S32_SCB_CFSR_UFSR_INVPC(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_UFSR_INVPC_SHIFT))&S32_SCB_CFSR_UFSR_INVPC_MASK) 396 #define S32_SCB_CFSR_UFSR_NOCP_MASK 0x80000u 397 #define S32_SCB_CFSR_UFSR_NOCP_SHIFT 19u 398 #define S32_SCB_CFSR_UFSR_NOCP_WIDTH 1u 399 #define S32_SCB_CFSR_UFSR_NOCP(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_UFSR_NOCP_SHIFT))&S32_SCB_CFSR_UFSR_NOCP_MASK) 400 #define S32_SCB_CFSR_UFSR_UNALIGNED_MASK 0x1000000u 401 #define S32_SCB_CFSR_UFSR_UNALIGNED_SHIFT 24u 402 #define S32_SCB_CFSR_UFSR_UNALIGNED_WIDTH 1u 403 #define S32_SCB_CFSR_UFSR_UNALIGNED(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_UFSR_UNALIGNED_SHIFT))&S32_SCB_CFSR_UFSR_UNALIGNED_MASK) 404 #define S32_SCB_CFSR_UFSR_DIVBYZERO_MASK 0x2000000u 405 #define S32_SCB_CFSR_UFSR_DIVBYZERO_SHIFT 25u 406 #define S32_SCB_CFSR_UFSR_DIVBYZERO_WIDTH 1u 407 #define S32_SCB_CFSR_UFSR_DIVBYZERO(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_UFSR_DIVBYZERO_SHIFT))&S32_SCB_CFSR_UFSR_DIVBYZERO_MASK) 408 /* HFSR Bit Fields */ 409 #define S32_SCB_HFSR_HFSR_MASK 0xFFFFFFFFu 410 #define S32_SCB_HFSR_HFSR_SHIFT 0u 411 #define S32_SCB_HFSR_HFSR_WIDTH 32u 412 #define S32_SCB_HFSR_HFSR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_HFSR_HFSR_SHIFT))&S32_SCB_HFSR_HFSR_MASK) 413 /* DFSR Bit Fields */ 414 #define S32_SCB_DFSR_DFSR_MASK 0xFFFFFFFFu 415 #define S32_SCB_DFSR_DFSR_SHIFT 0u 416 #define S32_SCB_DFSR_DFSR_WIDTH 32u 417 #define S32_SCB_DFSR_DFSR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_DFSR_DFSR_SHIFT))&S32_SCB_DFSR_DFSR_MASK) 418 /* MMFAR Bit Fields */ 419 #define S32_SCB_MMFAR_MMFAR_MASK 0xFFFFFFFFu 420 #define S32_SCB_MMFAR_MMFAR_SHIFT 0u 421 #define S32_SCB_MMFAR_MMFAR_WIDTH 32u 422 #define S32_SCB_MMFAR_MMFAR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_MMFAR_MMFAR_SHIFT))&S32_SCB_MMFAR_MMFAR_MASK) 423 /* BFAR Bit Fields */ 424 #define S32_SCB_BFAR_BFAR_MASK 0xFFFFFFFFu 425 #define S32_SCB_BFAR_BFAR_SHIFT 0u 426 #define S32_SCB_BFAR_BFAR_WIDTH 32u 427 #define S32_SCB_BFAR_BFAR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_BFAR_BFAR_SHIFT))&S32_SCB_BFAR_BFAR_MASK) 428 /* AFSR Bit Fields */ 429 #define S32_SCB_AFSR_AFSR_MASK 0xFFFFFFFFu 430 #define S32_SCB_AFSR_AFSR_SHIFT 0u 431 #define S32_SCB_AFSR_AFSR_WIDTH 32u 432 #define S32_SCB_AFSR_AFSR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_AFSR_AFSR_SHIFT))&S32_SCB_AFSR_AFSR_MASK) 433 /* ID_PFR0 Bit Fields */ 434 #define S32_SCB_ID_PFR0_ID_PFR0_MASK 0xFFFFFFFFu 435 #define S32_SCB_ID_PFR0_ID_PFR0_SHIFT 0u 436 #define S32_SCB_ID_PFR0_ID_PFR0_WIDTH 32u 437 #define S32_SCB_ID_PFR0_ID_PFR0(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ID_PFR0_ID_PFR0_SHIFT))&S32_SCB_ID_PFR0_ID_PFR0_MASK) 438 /* ID_PFR1 Bit Fields */ 439 #define S32_SCB_ID_PFR1_ID_PFR1_MASK 0xFFFFFFFFu 440 #define S32_SCB_ID_PFR1_ID_PFR1_SHIFT 0u 441 #define S32_SCB_ID_PFR1_ID_PFR1_WIDTH 32u 442 #define S32_SCB_ID_PFR1_ID_PFR1(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ID_PFR1_ID_PFR1_SHIFT))&S32_SCB_ID_PFR1_ID_PFR1_MASK) 443 /* ID_DFR0 Bit Fields */ 444 #define S32_SCB_ID_DFR0_ID_DFR0_MASK 0xFFFFFFFFu 445 #define S32_SCB_ID_DFR0_ID_DFR0_SHIFT 0u 446 #define S32_SCB_ID_DFR0_ID_DFR0_WIDTH 32u 447 #define S32_SCB_ID_DFR0_ID_DFR0(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ID_DFR0_ID_DFR0_SHIFT))&S32_SCB_ID_DFR0_ID_DFR0_MASK) 448 /* ID_AFR0 Bit Fields */ 449 #define S32_SCB_ID_AFR0_ID_AFR0_MASK 0xFFFFFFFFu 450 #define S32_SCB_ID_AFR0_ID_AFR0_SHIFT 0u 451 #define S32_SCB_ID_AFR0_ID_AFR0_WIDTH 32u 452 #define S32_SCB_ID_AFR0_ID_AFR0(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ID_AFR0_ID_AFR0_SHIFT))&S32_SCB_ID_AFR0_ID_AFR0_MASK) 453 /* ID_MMFR Bit Fields */ 454 #define S32_SCB_ID_MMFR_ID_MMFR0_MASK 0xFFFFFFFFu 455 #define S32_SCB_ID_MMFR_ID_MMFR0_SHIFT 0u 456 #define S32_SCB_ID_MMFR_ID_MMFR0_WIDTH 32u 457 #define S32_SCB_ID_MMFR_ID_MMFR0(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ID_MMFR_ID_MMFR0_SHIFT))&S32_SCB_ID_MMFR_ID_MMFR0_MASK) 458 #define S32_SCB_ID_MMFR_ID_MMFR1_MASK 0xFFFFFFFFu 459 #define S32_SCB_ID_MMFR_ID_MMFR1_SHIFT 0u 460 #define S32_SCB_ID_MMFR_ID_MMFR1_WIDTH 32u 461 #define S32_SCB_ID_MMFR_ID_MMFR1(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ID_MMFR_ID_MMFR1_SHIFT))&S32_SCB_ID_MMFR_ID_MMFR1_MASK) 462 #define S32_SCB_ID_MMFR_ID_MMFR2_MASK 0xFFFFFFFFu 463 #define S32_SCB_ID_MMFR_ID_MMFR2_SHIFT 0u 464 #define S32_SCB_ID_MMFR_ID_MMFR2_WIDTH 32u 465 #define S32_SCB_ID_MMFR_ID_MMFR2(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ID_MMFR_ID_MMFR2_SHIFT))&S32_SCB_ID_MMFR_ID_MMFR2_MASK) 466 #define S32_SCB_ID_MMFR_ID_MMFR3_MASK 0xFFFFFFFFu 467 #define S32_SCB_ID_MMFR_ID_MMFR3_SHIFT 0u 468 #define S32_SCB_ID_MMFR_ID_MMFR3_WIDTH 32u 469 #define S32_SCB_ID_MMFR_ID_MMFR3(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ID_MMFR_ID_MMFR3_SHIFT))&S32_SCB_ID_MMFR_ID_MMFR3_MASK) 470 /* ID_ISAR Bit Fields */ 471 #define S32_SCB_ID_ISAR_ID_ISAR0_MASK 0xFFFFFFFFu 472 #define S32_SCB_ID_ISAR_ID_ISAR0_SHIFT 0u 473 #define S32_SCB_ID_ISAR_ID_ISAR0_WIDTH 32u 474 #define S32_SCB_ID_ISAR_ID_ISAR0(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ID_ISAR_ID_ISAR0_SHIFT))&S32_SCB_ID_ISAR_ID_ISAR0_MASK) 475 #define S32_SCB_ID_ISAR_ID_ISAR1_MASK 0xFFFFFFFFu 476 #define S32_SCB_ID_ISAR_ID_ISAR1_SHIFT 0u 477 #define S32_SCB_ID_ISAR_ID_ISAR1_WIDTH 32u 478 #define S32_SCB_ID_ISAR_ID_ISAR1(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ID_ISAR_ID_ISAR1_SHIFT))&S32_SCB_ID_ISAR_ID_ISAR1_MASK) 479 #define S32_SCB_ID_ISAR_ID_ISAR2_MASK 0xFFFFFFFFu 480 #define S32_SCB_ID_ISAR_ID_ISAR2_SHIFT 0u 481 #define S32_SCB_ID_ISAR_ID_ISAR2_WIDTH 32u 482 #define S32_SCB_ID_ISAR_ID_ISAR2(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ID_ISAR_ID_ISAR2_SHIFT))&S32_SCB_ID_ISAR_ID_ISAR2_MASK) 483 #define S32_SCB_ID_ISAR_ID_ISAR3_MASK 0xFFFFFFFFu 484 #define S32_SCB_ID_ISAR_ID_ISAR3_SHIFT 0u 485 #define S32_SCB_ID_ISAR_ID_ISAR3_WIDTH 32u 486 #define S32_SCB_ID_ISAR_ID_ISAR3(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ID_ISAR_ID_ISAR3_SHIFT))&S32_SCB_ID_ISAR_ID_ISAR3_MASK) 487 #define S32_SCB_ID_ISAR_ID_ISAR4_MASK 0xFFFFFFFFu 488 #define S32_SCB_ID_ISAR_ID_ISAR4_SHIFT 0u 489 #define S32_SCB_ID_ISAR_ID_ISAR4_WIDTH 32u 490 #define S32_SCB_ID_ISAR_ID_ISAR4(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ID_ISAR_ID_ISAR4_SHIFT))&S32_SCB_ID_ISAR_ID_ISAR4_MASK) 491 /* CLIDR Bit Fields */ 492 #define S32_SCB_CLIDR_CLIDR_MASK 0xFFFFFFFFu 493 #define S32_SCB_CLIDR_CLIDR_SHIFT 0u 494 #define S32_SCB_CLIDR_CLIDR_WIDTH 32u 495 #define S32_SCB_CLIDR_CLIDR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CLIDR_CLIDR_SHIFT))&S32_SCB_CLIDR_CLIDR_MASK) 496 /* CTR Bit Fields */ 497 #define S32_SCB_CTR_CTR_MASK 0xFFFFFFFFu 498 #define S32_SCB_CTR_CTR_SHIFT 0u 499 #define S32_SCB_CTR_CTR_WIDTH 32u 500 #define S32_SCB_CTR_CTR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CTR_CTR_SHIFT))&S32_SCB_CTR_CTR_MASK) 501 /* CCSIDR Bit Fields */ 502 #define S32_SCB_CCSIDR_CCSIDR_MASK 0xFFFFFFFFu 503 #define S32_SCB_CCSIDR_CCSIDR_SHIFT 0u 504 #define S32_SCB_CCSIDR_CCSIDR_WIDTH 32u 505 #define S32_SCB_CCSIDR_CCSIDR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CCSIDR_CCSIDR_SHIFT))&S32_SCB_CCSIDR_CCSIDR_MASK) 506 /* CSSELR Bit Fields */ 507 #define S32_SCB_CSSELR_CSSELR_MASK 0xFFFFFFFFu 508 #define S32_SCB_CSSELR_CSSELR_SHIFT 0u 509 #define S32_SCB_CSSELR_CSSELR_WIDTH 32u 510 #define S32_SCB_CSSELR_CSSELR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CSSELR_CSSELR_SHIFT))&S32_SCB_CSSELR_CSSELR_MASK) 511 /* STIR Bit Fields */ 512 #define S32_SCB_STIR_STIR_MASK 0xFFFFFFFFu 513 #define S32_SCB_STIR_STIR_SHIFT 0u 514 #define S32_SCB_STIR_STIR_WIDTH 32u 515 #define S32_SCB_STIR_STIR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_STIR_STIR_SHIFT))&S32_SCB_STIR_STIR_MASK) 516 /* FPCCR Bit Fields */ 517 #define S32_SCB_FPCCR_FPCCR_MASK 0xFFFFFFFFu 518 #define S32_SCB_FPCCR_FPCCR_SHIFT 0u 519 #define S32_SCB_FPCCR_FPCCR_WIDTH 32u 520 #define S32_SCB_FPCCR_FPCCR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPCCR_FPCCR_SHIFT))&S32_SCB_FPCCR_FPCCR_MASK) 521 /* FPCAR Bit Fields */ 522 #define S32_SCB_FPCAR_FPCAR_MASK 0xFFFFFFFFu 523 #define S32_SCB_FPCAR_FPCAR_SHIFT 0u 524 #define S32_SCB_FPCAR_FPCAR_WIDTH 32u 525 #define S32_SCB_FPCAR_FPCAR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPCAR_FPCAR_SHIFT))&S32_SCB_FPCAR_FPCAR_MASK) 526 /* FPDSCR Bit Fields */ 527 #define S32_SCB_FPDSCR_FPDSCR_MASK 0xFFFFFFFFu 528 #define S32_SCB_FPDSCR_FPDSCR_SHIFT 0u 529 #define S32_SCB_FPDSCR_FPDSCR_WIDTH 32u 530 #define S32_SCB_FPDSCR_FPDSCR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPDSCR_FPDSCR_SHIFT))&S32_SCB_FPDSCR_FPDSCR_MASK) 531 /* ICIALLU Bit Fields */ 532 #define S32_SCB_ICIALLU_ICIALLU_MASK 0xFFFFFFFFu 533 #define S32_SCB_ICIALLU_ICIALLU_SHIFT 0u 534 #define S32_SCB_ICIALLU_ICIALLU_WIDTH 32u 535 #define S32_SCB_ICIALLU_ICIALLU(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICIALLU_ICIALLU_SHIFT))&S32_SCB_ICIALLU_ICIALLU_MASK) 536 /* ICIMVAU Bit Fields */ 537 #define S32_SCB_ICIMVAU_ICIMVAU_MASK 0xFFFFFFFFu 538 #define S32_SCB_ICIMVAU_ICIMVAU_SHIFT 0u 539 #define S32_SCB_ICIMVAU_ICIMVAU_WIDTH 32u 540 #define S32_SCB_ICIMVAU_ICIMVAU(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICIMVAU_ICIMVAU_SHIFT))&S32_SCB_ICIMVAU_ICIMVAU_MASK) 541 /* DCIMVAC Bit Fields */ 542 #define S32_SCB_DCIMVAC_DCIMVAC_MASK 0xFFFFFFFFu 543 #define S32_SCB_DCIMVAC_DCIMVAC_SHIFT 0u 544 #define S32_SCB_DCIMVAC_DCIMVAC_WIDTH 32u 545 #define S32_SCB_DCIMVAC_DCIMVAC(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_DCIMVAC_DCIMVAC_SHIFT))&S32_SCB_DCIMVAC_DCIMVAC_MASK) 546 /* DCISW Bit Fields */ 547 #define S32_SCB_DCISW_DCISW_MASK 0xFFFFFFFFu 548 #define S32_SCB_DCISW_DCISW_SHIFT 0u 549 #define S32_SCB_DCISW_DCISW_WIDTH 32u 550 #define S32_SCB_DCISW_DCISW(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_DCISW_DCISW_SHIFT))&S32_SCB_DCISW_DCISW_MASK) 551 /* DCCMVAU Bit Fields */ 552 #define S32_SCB_DCCMVAU_DCCMVAU_MASK 0xFFFFFFFFu 553 #define S32_SCB_DCCMVAU_DCCMVAU_SHIFT 0u 554 #define S32_SCB_DCCMVAU_DCCMVAU_WIDTH 32u 555 #define S32_SCB_DCCMVAU_DCCMVAU(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_DCCMVAU_DCCMVAU_SHIFT))&S32_SCB_DCCMVAU_DCCMVAU_MASK) 556 /* DCCMVAC Bit Fields */ 557 #define S32_SCB_DCCMVAC_DCCMVAC_MASK 0xFFFFFFFFu 558 #define S32_SCB_DCCMVAC_DCCMVAC_SHIFT 0u 559 #define S32_SCB_DCCMVAC_DCCMVAC_WIDTH 32u 560 #define S32_SCB_DCCMVAC_DCCMVAC(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_DCCMVAC_DCCMVAC_SHIFT))&S32_SCB_DCCMVAC_DCCMVAC_MASK) 561 /* DCCSW Bit Fields */ 562 #define S32_SCB_DCCSW_DCCSW_MASK 0xFFFFFFFFu 563 #define S32_SCB_DCCSW_DCCSW_SHIFT 0u 564 #define S32_SCB_DCCSW_DCCSW_WIDTH 32u 565 #define S32_SCB_DCCSW_DCCSW(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_DCCSW_DCCSW_SHIFT))&S32_SCB_DCCSW_DCCSW_MASK) 566 /* DCCIMVAC Bit Fields */ 567 #define S32_SCB_DCCIMVAC_DCCIMVAC_MASK 0xFFFFFFFFu 568 #define S32_SCB_DCCIMVAC_DCCIMVAC_SHIFT 0u 569 #define S32_SCB_DCCIMVAC_DCCIMVAC_WIDTH 32u 570 #define S32_SCB_DCCIMVAC_DCCIMVAC(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_DCCIMVAC_DCCIMVAC_SHIFT))&S32_SCB_DCCIMVAC_DCCIMVAC_MASK) 571 /* DCCISW Bit Fields */ 572 #define S32_SCB_DCCISW_DCCISW_MASK 0xFFFFFFFFu 573 #define S32_SCB_DCCISW_DCCISW_SHIFT 0u 574 #define S32_SCB_DCCISW_DCCISW_WIDTH 32u 575 #define S32_SCB_DCCISW_DCCISW(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_DCCISW_DCCISW_SHIFT))&S32_SCB_DCCISW_DCCISW_MASK) 576 /* BPIALL Bit Fields */ 577 #define S32_SCB_BPIALL_BPIALL_MASK 0xFFFFFFFFu 578 #define S32_SCB_BPIALL_BPIALL_SHIFT 0u 579 #define S32_SCB_BPIALL_BPIALL_WIDTH 32u 580 #define S32_SCB_BPIALL_BPIALL(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_BPIALL_BPIALL_SHIFT))&S32_SCB_BPIALL_BPIALL_MASK) 581 /* ITCMCR Bit Fields */ 582 #define S32_SCB_ITCMCR_ITCMCR_MASK 0xFFFFFFFFu 583 #define S32_SCB_ITCMCR_ITCMCR_SHIFT 0u 584 #define S32_SCB_ITCMCR_ITCMCR_WIDTH 32u 585 #define S32_SCB_ITCMCR_ITCMCR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ITCMCR_ITCMCR_SHIFT))&S32_SCB_ITCMCR_ITCMCR_MASK) 586 /* DTCMCR Bit Fields */ 587 #define S32_SCB_DTCMCR_DTCMCR_MASK 0xFFFFFFFFu 588 #define S32_SCB_DTCMCR_DTCMCR_SHIFT 0u 589 #define S32_SCB_DTCMCR_DTCMCR_WIDTH 32u 590 #define S32_SCB_DTCMCR_DTCMCR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_DTCMCR_DTCMCR_SHIFT))&S32_SCB_DTCMCR_DTCMCR_MASK) 591 /* AHBPCR Bit Fields */ 592 #define S32_SCB_AHBPCR_AHBPCR_MASK 0xFFFFFFFFu 593 #define S32_SCB_AHBPCR_AHBPCR_SHIFT 0u 594 #define S32_SCB_AHBPCR_AHBPCR_WIDTH 32u 595 #define S32_SCB_AHBPCR_AHBPCR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_AHBPCR_AHBPCR_SHIFT))&S32_SCB_AHBPCR_AHBPCR_MASK) 596 /* CACR Bit Fields */ 597 #define S32_SCB_CACR_CACR_MASK 0xFFFFFFFFu 598 #define S32_SCB_CACR_CACR_SHIFT 0u 599 #define S32_SCB_CACR_CACR_WIDTH 32u 600 #define S32_SCB_CACR_CACR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CACR_CACR_SHIFT))&S32_SCB_CACR_CACR_MASK) 601 /* AHBSCR Bit Fields */ 602 #define S32_SCB_AHBSCR_AHBSCR_MASK 0xFFFFFFFFu 603 #define S32_SCB_AHBSCR_AHBSCR_SHIFT 0u 604 #define S32_SCB_AHBSCR_AHBSCR_WIDTH 32u 605 #define S32_SCB_AHBSCR_AHBSCR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_AHBSCR_AHBSCR_SHIFT))&S32_SCB_AHBSCR_AHBSCR_MASK) 606 /* ABFSR Bit Fields */ 607 #define S32_SCB_ABFSR_ABFSR_MASK 0xFFFFFFFFu 608 #define S32_SCB_ABFSR_ABFSR_SHIFT 0u 609 #define S32_SCB_ABFSR_ABFSR_WIDTH 32u 610 #define S32_SCB_ABFSR_ABFSR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ABFSR_ABFSR_SHIFT))&S32_SCB_ABFSR_ABFSR_MASK) 611 /* IEBR0 Bit Fields */ 612 #define S32_SCB_IEBR0_IEBR0_MASK 0xFFFFFFFFu 613 #define S32_SCB_IEBR0_IEBR0_SHIFT 0u 614 #define S32_SCB_IEBR0_IEBR0_WIDTH 32u 615 #define S32_SCB_IEBR0_IEBR0(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_IEBR0_IEBR0_SHIFT))&S32_SCB_IEBR0_IEBR0_MASK) 616 /* IEBR1h Bit Fields */ 617 #define S32_SCB_IEBR1h_IEBR1h_MASK 0xFFFFFFFFu 618 #define S32_SCB_IEBR1h_IEBR1h_SHIFT 0u 619 #define S32_SCB_IEBR1h_IEBR1h_WIDTH 32u 620 #define S32_SCB_IEBR1h_IEBR1h(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_IEBR1h_IEBR1h_SHIFT))&S32_SCB_IEBR1h_IEBR1h_MASK) 621 /* DEBR0h Bit Fields */ 622 #define S32_SCB_DEBR0h_DEBR0h_MASK 0xFFFFFFFFu 623 #define S32_SCB_DEBR0h_DEBR0h_SHIFT 0u 624 #define S32_SCB_DEBR0h_DEBR0h_WIDTH 32u 625 #define S32_SCB_DEBR0h_DEBR0h(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_DEBR0h_DEBR0h_SHIFT))&S32_SCB_DEBR0h_DEBR0h_MASK) 626 /* DEBR1h Bit Fields */ 627 #define S32_SCB_DEBR1h_DEBR1h_MASK 0xFFFFFFFFu 628 #define S32_SCB_DEBR1h_DEBR1h_SHIFT 0u 629 #define S32_SCB_DEBR1h_DEBR1h_WIDTH 32u 630 #define S32_SCB_DEBR1h_DEBR1h(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_DEBR1h_DEBR1h_SHIFT))&S32_SCB_DEBR1h_DEBR1h_MASK) 631 /* PID Bit Fields */ 632 #define S32_SCB_PID_PID0_MASK 0xFFFFFFFFu 633 #define S32_SCB_PID_PID0_SHIFT 0u 634 #define S32_SCB_PID_PID0_WIDTH 32u 635 #define S32_SCB_PID_PID0(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_PID_PID0_SHIFT))&S32_SCB_PID_PID0_MASK) 636 #define S32_SCB_PID_PID1_MASK 0xFFFFFFFFu 637 #define S32_SCB_PID_PID1_SHIFT 0u 638 #define S32_SCB_PID_PID1_WIDTH 32u 639 #define S32_SCB_PID_PID1(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_PID_PID1_SHIFT))&S32_SCB_PID_PID1_MASK) 640 #define S32_SCB_PID_PID2_MASK 0xFFFFFFFFu 641 #define S32_SCB_PID_PID2_SHIFT 0u 642 #define S32_SCB_PID_PID2_WIDTH 32u 643 #define S32_SCB_PID_PID2(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_PID_PID2_SHIFT))&S32_SCB_PID_PID2_MASK) 644 #define S32_SCB_PID_PID3_MASK 0xFFFFFFFFu 645 #define S32_SCB_PID_PID3_SHIFT 0u 646 #define S32_SCB_PID_PID3_WIDTH 32u 647 #define S32_SCB_PID_PID3(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_PID_PID3_SHIFT))&S32_SCB_PID_PID3_MASK) 648 #define S32_SCB_PID_PID4_MASK 0xFFFFFFFFu 649 #define S32_SCB_PID_PID4_SHIFT 0u 650 #define S32_SCB_PID_PID4_WIDTH 32u 651 #define S32_SCB_PID_PID4(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_PID_PID4_SHIFT))&S32_SCB_PID_PID4_MASK) 652 #define S32_SCB_PID_PID5_MASK 0xFFFFFFFFu 653 #define S32_SCB_PID_PID5_SHIFT 0u 654 #define S32_SCB_PID_PID5_WIDTH 32u 655 #define S32_SCB_PID_PID5(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_PID_PID5_SHIFT))&S32_SCB_PID_PID5_MASK) 656 #define S32_SCB_PID_PID6_MASK 0xFFFFFFFFu 657 #define S32_SCB_PID_PID6_SHIFT 0u 658 #define S32_SCB_PID_PID6_WIDTH 32u 659 #define S32_SCB_PID_PID6(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_PID_PID6_SHIFT))&S32_SCB_PID_PID6_MASK) 660 #define S32_SCB_PID_PID7_MASK 0xFFFFFFFFu 661 #define S32_SCB_PID_PID7_SHIFT 0u 662 #define S32_SCB_PID_PID7_WIDTH 32u 663 #define S32_SCB_PID_PID7(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_PID_PID7_SHIFT))&S32_SCB_PID_PID7_MASK) 664 /* CID Bit Fields */ 665 #define S32_SCB_CID_CID0_MASK 0xFFFFFFFFu 666 #define S32_SCB_CID_CID0_SHIFT 0u 667 #define S32_SCB_CID_CID0_WIDTH 32u 668 #define S32_SCB_CID_CID0(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CID_CID0_SHIFT))&S32_SCB_CID_CID0_MASK) 669 #define S32_SCB_CID_CID1_MASK 0xFFFFFFFFu 670 #define S32_SCB_CID_CID1_SHIFT 0u 671 #define S32_SCB_CID_CID1_WIDTH 32u 672 #define S32_SCB_CID_CID1(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CID_CID1_SHIFT))&S32_SCB_CID_CID1_MASK) 673 #define S32_SCB_CID_CID2_MASK 0xFFFFFFFFu 674 #define S32_SCB_CID_CID2_SHIFT 0u 675 #define S32_SCB_CID_CID2_WIDTH 32u 676 #define S32_SCB_CID_CID2(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CID_CID2_SHIFT))&S32_SCB_CID_CID2_MASK) 677 #define S32_SCB_CID_CID3_MASK 0xFFFFFFFFu 678 #define S32_SCB_CID_CID3_SHIFT 0u 679 #define S32_SCB_CID_CID3_WIDTH 32u 680 #define S32_SCB_CID_CID3(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CID_CID3_SHIFT))&S32_SCB_CID_CID3_MASK) 681 682 /*! 683 * @} 684 */ /* end of group S32_SCB_Register_Masks */ 685 686 /*! 687 * @} 688 */ /* end of group S32_SCB_Peripheral_Access_Layer */ 689 690 #endif /* #if !defined(S32K344_SCB_H_) */ 691
