1 /*
2  * Copyright 1997-2016 Freescale Semiconductor, Inc.
3  * Copyright 2016-2021 NXP
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 /*!
9  * @file S32K344_FIRC.h
10  * @version 1.9
11  * @date 2021-10-27
12  * @brief Peripheral Access Layer for S32K344_FIRC
13  *
14  * This file contains register definitions and macros for easy access to their
15  * bit fields.
16  *
17  * This file assumes LITTLE endian system.
18  */
19 
20 /**
21 * @page misra_violations MISRA-C:2012 violations
22 *
23 * @section [global]
24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced
25 * The SoC header defines typedef for all modules.
26 *
27 * @section [global]
28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced
29 * The SoC header defines macros for all modules and registers.
30 *
31 * @section [global]
32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro
33 * These are generated macros used for accessing the bit-fields from registers.
34 *
35 * @section [global]
36 * Violates MISRA 2012 Required Rule 5.1, identifier clash
37 * The supported compilers use more than 31 significant characters for identifiers.
38 *
39 * @section [global]
40 * Violates MISRA 2012 Required Rule 5.2, identifier clash
41 * The supported compilers use more than 31 significant characters for identifiers.
42 *
43 * @section [global]
44 * Violates MISRA 2012 Required Rule 5.4, identifier clash
45 * The supported compilers use more than 31 significant characters for identifiers.
46 *
47 * @section [global]
48 * Violates MISRA 2012 Required Rule 5.5, identifier clash
49 * The supported compilers use more than 31 significant characters for identifiers.
50 *
51 * @section [global]
52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler
53 * This type qualifier is needed to ensure correct I/O access and addressing.
54 */
55 
56 /* Prevention from multiple including the same memory map */
57 #if !defined(S32K344_FIRC_H_)  /* Check if memory map has not been already included */
58 #define S32K344_FIRC_H_
59 
60 #include "S32K344_COMMON.h"
61 
62 /* ----------------------------------------------------------------------------
63    -- FIRC Peripheral Access Layer
64    ---------------------------------------------------------------------------- */
65 
66 /*!
67  * @addtogroup FIRC_Peripheral_Access_Layer FIRC Peripheral Access Layer
68  * @{
69  */
70 
71 /** FIRC - Register Layout Typedef */
72 typedef struct {
73   uint8_t RESERVED_0[4];
74   __I  uint32_t STATUS_REGISTER;                   /**< Status Register, offset: 0x4 */
75   __IO uint32_t STDBY_ENABLE;                      /**< Standby Enable Register, offset: 0x8 */
76 } FIRC_Type, *FIRC_MemMapPtr;
77 
78 /** Number of instances of the FIRC module. */
79 #define FIRC_INSTANCE_COUNT                      (1u)
80 
81 /* FIRC - Peripheral instance base addresses */
82 /** Peripheral FIRC base address */
83 #define IP_FIRC_BASE                             (0x402D0000u)
84 /** Peripheral FIRC base pointer */
85 #define IP_FIRC                                  ((FIRC_Type *)IP_FIRC_BASE)
86 /** Array initializer of FIRC peripheral base addresses */
87 #define IP_FIRC_BASE_ADDRS                       { IP_FIRC_BASE }
88 /** Array initializer of FIRC peripheral base pointers */
89 #define IP_FIRC_BASE_PTRS                        { IP_FIRC }
90 
91 /* ----------------------------------------------------------------------------
92    -- FIRC Register Masks
93    ---------------------------------------------------------------------------- */
94 
95 /*!
96  * @addtogroup FIRC_Register_Masks FIRC Register Masks
97  * @{
98  */
99 
100 /*! @name STATUS_REGISTER - Status Register */
101 /*! @{ */
102 
103 #define FIRC_STATUS_REGISTER_STATUS_MASK         (0x1U)
104 #define FIRC_STATUS_REGISTER_STATUS_SHIFT        (0U)
105 #define FIRC_STATUS_REGISTER_STATUS_WIDTH        (1U)
106 #define FIRC_STATUS_REGISTER_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << FIRC_STATUS_REGISTER_STATUS_SHIFT)) & FIRC_STATUS_REGISTER_STATUS_MASK)
107 /*! @} */
108 
109 /*! @name STDBY_ENABLE - Standby Enable Register */
110 /*! @{ */
111 
112 #define FIRC_STDBY_ENABLE_STDBY_EN_MASK          (0x1U)
113 #define FIRC_STDBY_ENABLE_STDBY_EN_SHIFT         (0U)
114 #define FIRC_STDBY_ENABLE_STDBY_EN_WIDTH         (1U)
115 #define FIRC_STDBY_ENABLE_STDBY_EN(x)            (((uint32_t)(((uint32_t)(x)) << FIRC_STDBY_ENABLE_STDBY_EN_SHIFT)) & FIRC_STDBY_ENABLE_STDBY_EN_MASK)
116 /*! @} */
117 
118 /*!
119  * @}
120  */ /* end of group FIRC_Register_Masks */
121 
122 /*!
123  * @}
124  */ /* end of group FIRC_Peripheral_Access_Layer */
125 
126 #endif  /* #if !defined(S32K344_FIRC_H_) */
127