1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2021 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K116_SCB.h 10 * @version 1.0 11 * @date 2021-02-18 12 * @brief Peripheral Access Layer for S32K116_SCB 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K116_SCB_H_) /* Check if memory map has not been already included */ 58 #define S32K116_SCB_H_ 59 60 #include "S32K116_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- S32_SCB Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup S32_SCB_Peripheral_Access_Layer S32_SCB Peripheral Access Layer 68 * @{ 69 */ 70 71 72 /** S32_SCB - Size of Registers Arrays */ 73 74 /** S32_SCB - Register Layout Typedef */ 75 typedef struct { 76 uint8_t RESERVED_0[8]; 77 __I uint32_t ACTLR; /**< Auxiliary Control Register,, offset: 0x8 */ 78 uint8_t RESERVED_1[3316]; 79 __I uint32_t CPUID; /**< CPUID Base Register, offset: 0xD00 */ 80 __IO uint32_t ICSR; /**< Interrupt Control and State Register, offset: 0xD04 */ 81 __IO uint32_t VTOR; /**< Vector Table Offset Register, offset: 0xD08 */ 82 __IO uint32_t AIRCR; /**< Application Interrupt and Reset Control Register, offset: 0xD0C */ 83 __IO uint32_t SCR; /**< System Control Register, offset: 0xD10 */ 84 __I uint32_t CCR; /**< Configuration and Control Register, offset: 0xD14 */ 85 uint8_t RESERVED_2[4]; 86 __IO uint32_t SHPR2; /**< System Handler Priority Register 2, offset: 0xD1C */ 87 __IO uint32_t SHPR3; /**< System Handler Priority Register 3, offset: 0xD20 */ 88 __IO uint32_t SHCSR; /**< System Handler Control and State Register, offset: 0xD24 */ 89 uint8_t RESERVED_3[8]; 90 __IO uint32_t DFSR; /**< Debug Fault Status Register, offset: 0xD30 */ 91 } S32_SCB_Type, *S32_SCB_MemMapPtr; 92 93 /** Number of instances of the S32_SCB module. */ 94 #define S32_SCB_INSTANCE_COUNT (1u) 95 96 97 /* S32_SCB - Peripheral instance base addresses */ 98 /** Peripheral S32_SCB base address */ 99 #define S32_SCB_BASE (0xE000E000u) 100 /** Peripheral S32_SCB base pointer */ 101 #define S32_SCB ((S32_SCB_Type *)S32_SCB_BASE) 102 /** Array initializer of S32_SCB peripheral base addresses */ 103 #define S32_SCB_BASE_ADDRS { S32_SCB_BASE } 104 /** Array initializer of S32_SCB peripheral base pointers */ 105 #define S32_SCB_BASE_PTRS { S32_SCB } 106 107 /* ---------------------------------------------------------------------------- 108 -- S32_SCB Register Masks 109 ---------------------------------------------------------------------------- */ 110 111 /*! 112 * @addtogroup S32_SCB_Register_Masks S32_SCB Register Masks 113 * @{ 114 */ 115 116 /* CPUID Bit Fields */ 117 #define S32_SCB_CPUID_REVISION_MASK 0xFu 118 #define S32_SCB_CPUID_REVISION_SHIFT 0u 119 #define S32_SCB_CPUID_REVISION_WIDTH 4u 120 #define S32_SCB_CPUID_REVISION(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CPUID_REVISION_SHIFT))&S32_SCB_CPUID_REVISION_MASK) 121 #define S32_SCB_CPUID_PARTNO_MASK 0xFFF0u 122 #define S32_SCB_CPUID_PARTNO_SHIFT 4u 123 #define S32_SCB_CPUID_PARTNO_WIDTH 12u 124 #define S32_SCB_CPUID_PARTNO(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CPUID_PARTNO_SHIFT))&S32_SCB_CPUID_PARTNO_MASK) 125 #define S32_SCB_CPUID_VARIANT_MASK 0xF00000u 126 #define S32_SCB_CPUID_VARIANT_SHIFT 20u 127 #define S32_SCB_CPUID_VARIANT_WIDTH 4u 128 #define S32_SCB_CPUID_VARIANT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CPUID_VARIANT_SHIFT))&S32_SCB_CPUID_VARIANT_MASK) 129 #define S32_SCB_CPUID_IMPLEMENTER_MASK 0xFF000000u 130 #define S32_SCB_CPUID_IMPLEMENTER_SHIFT 24u 131 #define S32_SCB_CPUID_IMPLEMENTER_WIDTH 8u 132 #define S32_SCB_CPUID_IMPLEMENTER(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CPUID_IMPLEMENTER_SHIFT))&S32_SCB_CPUID_IMPLEMENTER_MASK) 133 /* ICSR Bit Fields */ 134 #define S32_SCB_ICSR_VECTACTIVE_MASK 0x3Fu 135 #define S32_SCB_ICSR_VECTACTIVE_SHIFT 0u 136 #define S32_SCB_ICSR_VECTACTIVE_WIDTH 6u 137 #define S32_SCB_ICSR_VECTACTIVE(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_VECTACTIVE_SHIFT))&S32_SCB_ICSR_VECTACTIVE_MASK) 138 #define S32_SCB_ICSR_VECTPENDING_MASK 0x3F000u 139 #define S32_SCB_ICSR_VECTPENDING_SHIFT 12u 140 #define S32_SCB_ICSR_VECTPENDING_WIDTH 6u 141 #define S32_SCB_ICSR_VECTPENDING(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_VECTPENDING_SHIFT))&S32_SCB_ICSR_VECTPENDING_MASK) 142 #define S32_SCB_ICSR_ISRPENDING_MASK 0x400000u 143 #define S32_SCB_ICSR_ISRPENDING_SHIFT 22u 144 #define S32_SCB_ICSR_ISRPENDING_WIDTH 1u 145 #define S32_SCB_ICSR_ISRPENDING(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_ISRPENDING_SHIFT))&S32_SCB_ICSR_ISRPENDING_MASK) 146 #define S32_SCB_ICSR_PENDSTCLR_MASK 0x2000000u 147 #define S32_SCB_ICSR_PENDSTCLR_SHIFT 25u 148 #define S32_SCB_ICSR_PENDSTCLR_WIDTH 1u 149 #define S32_SCB_ICSR_PENDSTCLR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_PENDSTCLR_SHIFT))&S32_SCB_ICSR_PENDSTCLR_MASK) 150 #define S32_SCB_ICSR_PENDSTSET_MASK 0x4000000u 151 #define S32_SCB_ICSR_PENDSTSET_SHIFT 26u 152 #define S32_SCB_ICSR_PENDSTSET_WIDTH 1u 153 #define S32_SCB_ICSR_PENDSTSET(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_PENDSTSET_SHIFT))&S32_SCB_ICSR_PENDSTSET_MASK) 154 #define S32_SCB_ICSR_PENDSVCLR_MASK 0x8000000u 155 #define S32_SCB_ICSR_PENDSVCLR_SHIFT 27u 156 #define S32_SCB_ICSR_PENDSVCLR_WIDTH 1u 157 #define S32_SCB_ICSR_PENDSVCLR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_PENDSVCLR_SHIFT))&S32_SCB_ICSR_PENDSVCLR_MASK) 158 #define S32_SCB_ICSR_PENDSVSET_MASK 0x10000000u 159 #define S32_SCB_ICSR_PENDSVSET_SHIFT 28u 160 #define S32_SCB_ICSR_PENDSVSET_WIDTH 1u 161 #define S32_SCB_ICSR_PENDSVSET(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_PENDSVSET_SHIFT))&S32_SCB_ICSR_PENDSVSET_MASK) 162 #define S32_SCB_ICSR_NMIPENDSET_MASK 0x80000000u 163 #define S32_SCB_ICSR_NMIPENDSET_SHIFT 31u 164 #define S32_SCB_ICSR_NMIPENDSET_WIDTH 1u 165 #define S32_SCB_ICSR_NMIPENDSET(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_NMIPENDSET_SHIFT))&S32_SCB_ICSR_NMIPENDSET_MASK) 166 /* VTOR Bit Fields */ 167 #define S32_SCB_VTOR_TBLOFF_MASK 0xFFFFFF80u 168 #define S32_SCB_VTOR_TBLOFF_SHIFT 7u 169 #define S32_SCB_VTOR_TBLOFF_WIDTH 25u 170 #define S32_SCB_VTOR_TBLOFF(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_VTOR_TBLOFF_SHIFT))&S32_SCB_VTOR_TBLOFF_MASK) 171 /* AIRCR Bit Fields */ 172 #define S32_SCB_AIRCR_VECTCLRACTIVE_MASK 0x2u 173 #define S32_SCB_AIRCR_VECTCLRACTIVE_SHIFT 1u 174 #define S32_SCB_AIRCR_VECTCLRACTIVE_WIDTH 1u 175 #define S32_SCB_AIRCR_VECTCLRACTIVE(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_AIRCR_VECTCLRACTIVE_SHIFT))&S32_SCB_AIRCR_VECTCLRACTIVE_MASK) 176 #define S32_SCB_AIRCR_SYSRESETREQ_MASK 0x4u 177 #define S32_SCB_AIRCR_SYSRESETREQ_SHIFT 2u 178 #define S32_SCB_AIRCR_SYSRESETREQ_WIDTH 1u 179 #define S32_SCB_AIRCR_SYSRESETREQ(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_AIRCR_SYSRESETREQ_SHIFT))&S32_SCB_AIRCR_SYSRESETREQ_MASK) 180 #define S32_SCB_AIRCR_ENDIANNESS_MASK 0x8000u 181 #define S32_SCB_AIRCR_ENDIANNESS_SHIFT 15u 182 #define S32_SCB_AIRCR_ENDIANNESS_WIDTH 1u 183 #define S32_SCB_AIRCR_ENDIANNESS(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_AIRCR_ENDIANNESS_SHIFT))&S32_SCB_AIRCR_ENDIANNESS_MASK) 184 #define S32_SCB_AIRCR_VECTKEY_MASK 0xFFFF0000u 185 #define S32_SCB_AIRCR_VECTKEY_SHIFT 16u 186 #define S32_SCB_AIRCR_VECTKEY_WIDTH 16u 187 #define S32_SCB_AIRCR_VECTKEY(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_AIRCR_VECTKEY_SHIFT))&S32_SCB_AIRCR_VECTKEY_MASK) 188 /* SCR Bit Fields */ 189 #define S32_SCB_SCR_SLEEPONEXIT_MASK 0x2u 190 #define S32_SCB_SCR_SLEEPONEXIT_SHIFT 1u 191 #define S32_SCB_SCR_SLEEPONEXIT_WIDTH 1u 192 #define S32_SCB_SCR_SLEEPONEXIT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SCR_SLEEPONEXIT_SHIFT))&S32_SCB_SCR_SLEEPONEXIT_MASK) 193 #define S32_SCB_SCR_SLEEPDEEP_MASK 0x4u 194 #define S32_SCB_SCR_SLEEPDEEP_SHIFT 2u 195 #define S32_SCB_SCR_SLEEPDEEP_WIDTH 1u 196 #define S32_SCB_SCR_SLEEPDEEP(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SCR_SLEEPDEEP_SHIFT))&S32_SCB_SCR_SLEEPDEEP_MASK) 197 #define S32_SCB_SCR_SEVONPEND_MASK 0x10u 198 #define S32_SCB_SCR_SEVONPEND_SHIFT 4u 199 #define S32_SCB_SCR_SEVONPEND_WIDTH 1u 200 #define S32_SCB_SCR_SEVONPEND(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SCR_SEVONPEND_SHIFT))&S32_SCB_SCR_SEVONPEND_MASK) 201 /* CCR Bit Fields */ 202 #define S32_SCB_CCR_UNALIGN_TRP_MASK 0x8u 203 #define S32_SCB_CCR_UNALIGN_TRP_SHIFT 3u 204 #define S32_SCB_CCR_UNALIGN_TRP_WIDTH 1u 205 #define S32_SCB_CCR_UNALIGN_TRP(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CCR_UNALIGN_TRP_SHIFT))&S32_SCB_CCR_UNALIGN_TRP_MASK) 206 #define S32_SCB_CCR_STKALIGN_MASK 0x200u 207 #define S32_SCB_CCR_STKALIGN_SHIFT 9u 208 #define S32_SCB_CCR_STKALIGN_WIDTH 1u 209 #define S32_SCB_CCR_STKALIGN(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CCR_STKALIGN_SHIFT))&S32_SCB_CCR_STKALIGN_MASK) 210 /* SHPR2 Bit Fields */ 211 #define S32_SCB_SHPR2_PRI_11_MASK 0xFF000000u 212 #define S32_SCB_SHPR2_PRI_11_SHIFT 24u 213 #define S32_SCB_SHPR2_PRI_11_WIDTH 8u 214 #define S32_SCB_SHPR2_PRI_11(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHPR2_PRI_11_SHIFT))&S32_SCB_SHPR2_PRI_11_MASK) 215 /* SHPR3 Bit Fields */ 216 #define S32_SCB_SHPR3_PRI_14_MASK 0xFF0000u 217 #define S32_SCB_SHPR3_PRI_14_SHIFT 16u 218 #define S32_SCB_SHPR3_PRI_14_WIDTH 8u 219 #define S32_SCB_SHPR3_PRI_14(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHPR3_PRI_14_SHIFT))&S32_SCB_SHPR3_PRI_14_MASK) 220 #define S32_SCB_SHPR3_PRI_15_MASK 0xFF000000u 221 #define S32_SCB_SHPR3_PRI_15_SHIFT 24u 222 #define S32_SCB_SHPR3_PRI_15_WIDTH 8u 223 #define S32_SCB_SHPR3_PRI_15(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHPR3_PRI_15_SHIFT))&S32_SCB_SHPR3_PRI_15_MASK) 224 /* SHCSR Bit Fields */ 225 #define S32_SCB_SHCSR_SVCALLPENDED_MASK 0x8000u 226 #define S32_SCB_SHCSR_SVCALLPENDED_SHIFT 15u 227 #define S32_SCB_SHCSR_SVCALLPENDED_WIDTH 1u 228 #define S32_SCB_SHCSR_SVCALLPENDED(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_SVCALLPENDED_SHIFT))&S32_SCB_SHCSR_SVCALLPENDED_MASK) 229 /* DFSR Bit Fields */ 230 #define S32_SCB_DFSR_HALTED_MASK 0x1u 231 #define S32_SCB_DFSR_HALTED_SHIFT 0u 232 #define S32_SCB_DFSR_HALTED_WIDTH 1u 233 #define S32_SCB_DFSR_HALTED(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_DFSR_HALTED_SHIFT))&S32_SCB_DFSR_HALTED_MASK) 234 #define S32_SCB_DFSR_BKPT_MASK 0x2u 235 #define S32_SCB_DFSR_BKPT_SHIFT 1u 236 #define S32_SCB_DFSR_BKPT_WIDTH 1u 237 #define S32_SCB_DFSR_BKPT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_DFSR_BKPT_SHIFT))&S32_SCB_DFSR_BKPT_MASK) 238 #define S32_SCB_DFSR_DWTTRAP_MASK 0x4u 239 #define S32_SCB_DFSR_DWTTRAP_SHIFT 2u 240 #define S32_SCB_DFSR_DWTTRAP_WIDTH 1u 241 #define S32_SCB_DFSR_DWTTRAP(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_DFSR_DWTTRAP_SHIFT))&S32_SCB_DFSR_DWTTRAP_MASK) 242 #define S32_SCB_DFSR_VCATCH_MASK 0x8u 243 #define S32_SCB_DFSR_VCATCH_SHIFT 3u 244 #define S32_SCB_DFSR_VCATCH_WIDTH 1u 245 #define S32_SCB_DFSR_VCATCH(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_DFSR_VCATCH_SHIFT))&S32_SCB_DFSR_VCATCH_MASK) 246 #define S32_SCB_DFSR_EXTERNAL_MASK 0x10u 247 #define S32_SCB_DFSR_EXTERNAL_SHIFT 4u 248 #define S32_SCB_DFSR_EXTERNAL_WIDTH 1u 249 #define S32_SCB_DFSR_EXTERNAL(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_DFSR_EXTERNAL_SHIFT))&S32_SCB_DFSR_EXTERNAL_MASK) 250 251 /*! 252 * @} 253 */ /* end of group S32_SCB_Register_Masks */ 254 255 256 /*! 257 * @} 258 */ /* end of group S32_SCB_Peripheral_Access_Layer */ 259 260 #endif /* #if !defined(S32K116_SCB_H_) */ 261
