1 /*
2 * Copyright 2017-2023 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7 #ifndef _FSL_SEMC_H_
8 #define _FSL_SEMC_H_
9
10 #include "fsl_common.h"
11
12 /*!
13 * @addtogroup semc
14 * @{
15 */
16
17 /*******************************************************************************
18 * Definitions
19 ******************************************************************************/
20
21 /*! @name Driver version */
22 /*@{*/
23 /*! @brief SEMC driver version. */
24 #define FSL_SEMC_DRIVER_VERSION (MAKE_VERSION(2, 6, 0))
25 /*@}*/
26
27 /*! @brief SEMC status, _semc_status. */
28 enum
29 {
30 kStatus_SEMC_InvalidDeviceType = MAKE_STATUS(kStatusGroup_SEMC, 0), /*!< Invalid device type. */
31 kStatus_SEMC_IpCommandExecutionError = MAKE_STATUS(kStatusGroup_SEMC, 1), /*!< IP command execution error. */
32 kStatus_SEMC_AxiCommandExecutionError = MAKE_STATUS(kStatusGroup_SEMC, 2), /*!< AXI command execution error. */
33 kStatus_SEMC_InvalidMemorySize = MAKE_STATUS(kStatusGroup_SEMC, 3), /*!< Invalid memory sie. */
34 kStatus_SEMC_InvalidIpcmdDataSize = MAKE_STATUS(kStatusGroup_SEMC, 4), /*!< Invalid IP command data size. */
35 kStatus_SEMC_InvalidAddressPortWidth = MAKE_STATUS(kStatusGroup_SEMC, 5), /*!< Invalid address port width. */
36 kStatus_SEMC_InvalidDataPortWidth = MAKE_STATUS(kStatusGroup_SEMC, 6), /*!< Invalid data port width. */
37 kStatus_SEMC_InvalidSwPinmuxSelection = MAKE_STATUS(kStatusGroup_SEMC, 7), /*!< Invalid SW pinmux selection. */
38 kStatus_SEMC_InvalidBurstLength = MAKE_STATUS(kStatusGroup_SEMC, 8), /*!< Invalid burst length */
39 /*! Invalid column address bit width. */
40 kStatus_SEMC_InvalidColumnAddressBitWidth = MAKE_STATUS(kStatusGroup_SEMC, 9),
41 kStatus_SEMC_InvalidBaseAddress = MAKE_STATUS(kStatusGroup_SEMC, 10), /*!< Invalid base address. */
42 kStatus_SEMC_InvalidTimerSetting = MAKE_STATUS(kStatusGroup_SEMC, 11), /*!< Invalid timer setting. */
43 };
44
45 /*! @brief SEMC memory device type. */
46 typedef enum _semc_mem_type
47 {
48 kSEMC_MemType_SDRAM = 0, /*!< SDRAM */
49 kSEMC_MemType_SRAM, /*!< SRAM */
50 kSEMC_MemType_NOR, /*!< NOR */
51 kSEMC_MemType_NAND, /*!< NAND */
52 kSEMC_MemType_8080 /*!< 8080. */
53 } semc_mem_type_t;
54
55 /*! @brief SEMC WAIT/RDY polarity. */
56 typedef enum _semc_waitready_polarity
57 {
58 kSEMC_LowActive = 0, /*!< Low active. */
59 kSEMC_HighActive, /*!< High active. */
60 } semc_waitready_polarity_t;
61
62 /*! @brief SEMC SDRAM Chip selection . */
63 typedef enum _semc_sdram_cs
64 {
65 kSEMC_SDRAM_CS0 = 0, /*!< SEMC SDRAM CS0. */
66 kSEMC_SDRAM_CS1, /*!< SEMC SDRAM CS1. */
67 kSEMC_SDRAM_CS2, /*!< SEMC SDRAM CS2. */
68 kSEMC_SDRAM_CS3 /*!< SEMC SDRAM CS3. */
69 } semc_sdram_cs_t;
70
71 /*! @brief SEMC SRAM Chip selection . */
72 typedef enum _semc_sram_cs
73 {
74 #if defined(FSL_FEATURE_SEMC_SUPPORT_SRAM_COUNT) && (FSL_FEATURE_SEMC_SUPPORT_SRAM_COUNT == 0x04U)
75 kSEMC_SRAM_CS0 = 0, /*!< SEMC SRAM CS0. */
76 kSEMC_SRAM_CS1, /*!< SEMC SRAM CS1. */
77 kSEMC_SRAM_CS2, /*!< SEMC SRAM CS2. */
78 kSEMC_SRAM_CS3 /*!< SEMC SRAM CS3. */
79 #else
80 kSEMC_SRAM_CS0 = 0, /*!< SEMC SRAM CS0. */
81 #endif /* FSL_FEATURE_SEMC_SUPPORT_SRAM_COUNT */
82 } semc_sram_cs_t;
83
84 /*! @brief SEMC NAND device type. */
85 typedef enum _semc_nand_access_type
86 {
87 kSEMC_NAND_ACCESS_BY_AXI = 0, /*!< Access to NAND flash by AXI bus. */
88 kSEMC_NAND_ACCESS_BY_IPCMD, /*!< Access to NAND flash by IP bus. */
89 } semc_nand_access_type_t;
90
91 /*! @brief SEMC interrupts . */
92 typedef enum _semc_interrupt_enable
93 {
94 kSEMC_IPCmdDoneInterrupt = SEMC_INTEN_IPCMDDONEEN_MASK, /*!< Ip command done interrupt. */
95 kSEMC_IPCmdErrInterrupt = SEMC_INTEN_IPCMDERREN_MASK, /*!< Ip command error interrupt. */
96 kSEMC_AXICmdErrInterrupt = SEMC_INTEN_AXICMDERREN_MASK, /*!< AXI command error interrupt. */
97 kSEMC_AXIBusErrInterrupt = SEMC_INTEN_AXIBUSERREN_MASK /*!< AXI bus error interrupt. */
98 } semc_interrupt_enable_t;
99
100 /*! @brief SEMC IP command data size in bytes. */
101 typedef enum _semc_ipcmd_datasize
102 {
103 kSEMC_IPcmdDataSize_1bytes = 1, /*!< The IP command data size 1 byte. */
104 kSEMC_IPcmdDataSize_2bytes, /*!< The IP command data size 2 byte. */
105 kSEMC_IPcmdDataSize_3bytes, /*!< The IP command data size 3 byte. */
106 kSEMC_IPcmdDataSize_4bytes /*!< The IP command data size 4 byte. */
107 } semc_ipcmd_datasize_t;
108
109 /*! @brief SEMC auto-refresh timing. */
110 typedef enum _semc_refresh_time
111 {
112 kSEMC_RefreshThreeClocks = 0x0U, /*!< The refresh timing with three bus clocks. */
113 kSEMC_RefreshSixClocks, /*!< The refresh timing with six bus clocks. */
114 kSEMC_RefreshNineClocks /*!< The refresh timing with nine bus clocks. */
115 } semc_refresh_time_t;
116
117 /*! @brief CAS latency */
118 typedef enum _semc_caslatency
119 {
120 kSEMC_LatencyOne = 1, /*!< Latency 1. */
121 kSEMC_LatencyTwo, /*!< Latency 2. */
122 kSEMC_LatencyThree, /*!< Latency 3. */
123 } semc_caslatency_t;
124
125 /*! @brief SEMC sdram column address bit number. */
126 typedef enum _semc_sdram_column_bit_num
127 {
128 kSEMC_SdramColunm_12bit = 0x0U, /*!< 12 bit. */
129 kSEMC_SdramColunm_11bit, /*!< 11 bit. */
130 kSEMC_SdramColunm_10bit, /*!< 10 bit. */
131 kSEMC_SdramColunm_9bit, /*!< 9 bit. */
132 #if defined(FSL_FEATURE_SEMC_SDRAM_SUPPORT_COLUMN_ADDRESS_8BIT) && (FSL_FEATURE_SEMC_SDRAM_SUPPORT_COLUMN_ADDRESS_8BIT)
133 kSEMC_SdramColunm_8bit, /*!< 8 bit. */
134 #endif /* FSL_FEATURE_SEMC_SDRAM_SUPPORT_COLUMN_ADDRESS_8BIT */
135 } semc_sdram_column_bit_num_t;
136
137 /*! @brief SEMC sdram burst length. */
138 typedef enum _semc_sdram_burst_len
139 {
140 /*! According to ERR050577, Auto-refresh command may possibly fail to be triggered during
141 long time back-to-back write (or read) when SDRAM controller's burst length is greater than 1. */
142 #if defined(FSL_FEATURE_SEMC_ERRATA_050577) && (FSL_FEATURE_SEMC_ERRATA_050577 == 0x01U)
143 kSEMC_Sdram_BurstLen1 = 0, /*!< Burst length 1*/
144 #else
145 kSEMC_Sdram_BurstLen1 = 0, /*!< Burst length 1*/
146 kSEMC_Sdram_BurstLen2, /*!< Burst length 2*/
147 kSEMC_Sdram_BurstLen4, /*!< Burst length 4*/
148 kSEMC_Sdram_BurstLen8 /*!< Burst length 8*/
149 #endif /* FSL_FEATURE_SEMC_ERRATA_050577 */
150 } sem_sdram_burst_len_t;
151
152 /*! @brief SEMC nand column address bit number. */
153 typedef enum _semc_nand_column_bit_num
154 {
155 kSEMC_NandColum_16bit = 0x0U, /*!< 16 bit. */
156 kSEMC_NandColum_15bit, /*!< 15 bit. */
157 kSEMC_NandColum_14bit, /*!< 14 bit. */
158 kSEMC_NandColum_13bit, /*!< 13 bit. */
159 kSEMC_NandColum_12bit, /*!< 12 bit. */
160 kSEMC_NandColum_11bit, /*!< 11 bit. */
161 kSEMC_NandColum_10bit, /*!< 10 bit. */
162 kSEMC_NandColum_9bit, /*!< 9 bit. */
163 } semc_nand_column_bit_num_t;
164
165 /*! @brief SEMC nand burst length. */
166 typedef enum _semc_nand_burst_len
167 {
168 kSEMC_Nand_BurstLen1 = 0, /*!< Burst length 1*/
169 kSEMC_Nand_BurstLen2, /*!< Burst length 2*/
170 kSEMC_Nand_BurstLen4, /*!< Burst length 4*/
171 kSEMC_Nand_BurstLen8, /*!< Burst length 8*/
172 kSEMC_Nand_BurstLen16, /*!< Burst length 16*/
173 kSEMC_Nand_BurstLen32, /*!< Burst length 32*/
174 kSEMC_Nand_BurstLen64 /*!< Burst length 64*/
175 } sem_nand_burst_len_t;
176
177 /*! @brief SEMC nor/sram column address bit number. */
178 typedef enum _semc_norsram_column_bit_num
179 {
180 kSEMC_NorColum_12bit = 0x0U, /*!< 12 bit. */
181 kSEMC_NorColum_11bit, /*!< 11 bit. */
182 kSEMC_NorColum_10bit, /*!< 10 bit. */
183 kSEMC_NorColum_9bit, /*!< 9 bit. */
184 kSEMC_NorColum_8bit, /*!< 8 bit. */
185 kSEMC_NorColum_7bit, /*!< 7 bit. */
186 kSEMC_NorColum_6bit, /*!< 6 bit. */
187 kSEMC_NorColum_5bit, /*!< 5 bit. */
188 kSEMC_NorColum_4bit, /*!< 4 bit. */
189 kSEMC_NorColum_3bit, /*!< 3 bit. */
190 kSEMC_NorColum_2bit /*!< 2 bit. */
191 } semc_norsram_column_bit_num_t;
192
193 /*! @brief SEMC nor/sram burst length. */
194 typedef enum _semc_norsram_burst_len
195 {
196 kSEMC_Nor_BurstLen1 = 0, /*!< Burst length 1*/
197 kSEMC_Nor_BurstLen2, /*!< Burst length 2*/
198 kSEMC_Nor_BurstLen4, /*!< Burst length 4*/
199 kSEMC_Nor_BurstLen8, /*!< Burst length 8*/
200 kSEMC_Nor_BurstLen16, /*!< Burst length 16*/
201 kSEMC_Nor_BurstLen32, /*!< Burst length 32*/
202 kSEMC_Nor_BurstLen64 /*!< Burst length 64*/
203 } sem_norsram_burst_len_t;
204
205 /*! @brief SEMC dbi column address bit number. */
206 typedef enum _semc_dbi_column_bit_num
207 {
208 kSEMC_Dbi_Colum_12bit = 0x0U, /*!< 12 bit. */
209 kSEMC_Dbi_Colum_11bit, /*!< 11 bit. */
210 kSEMC_Dbi_Colum_10bit, /*!< 10 bit. */
211 kSEMC_Dbi_Colum_9bit, /*!< 9 bit. */
212 kSEMC_Dbi_Colum_8bit, /*!< 8 bit. */
213 kSEMC_Dbi_Colum_7bit, /*!< 7 bit. */
214 kSEMC_Dbi_Colum_6bit, /*!< 6 bit. */
215 kSEMC_Dbi_Colum_5bit, /*!< 5 bit. */
216 kSEMC_Dbi_Colum_4bit, /*!< 4 bit. */
217 kSEMC_Dbi_Colum_3bit, /*!< 3 bit. */
218 kSEMC_Dbi_Colum_2bit /*!< 2 bit. */
219 } semc_dbi_column_bit_num_t;
220
221 /*! @brief SEMC dbi burst length. */
222 typedef enum _semc_dbi_burst_len
223 {
224 kSEMC_Dbi_BurstLen1 = 0, /*!< Burst length 1*/
225 kSEMC_Dbi_BurstLen2, /*!< Burst length 2*/
226 kSEMC_Dbi_Dbi_BurstLen4, /*!< Burst length 4*/
227 kSEMC_Dbi_BurstLen8, /*!< Burst length 8*/
228 kSEMC_Dbi_BurstLen16, /*!< Burst length 16*/
229 kSEMC_Dbi_BurstLen32, /*!< Burst length 32*/
230 kSEMC_Dbi_BurstLen64 /*!< Burst length 64*/
231 } sem_dbi_burst_len_t;
232
233 /*! @brief SEMC IOMUXC. */
234 typedef enum _semc_iomux_pin
235 {
236 kSEMC_MUXA8 = SEMC_IOCR_MUX_A8_SHIFT, /*!< MUX A8 pin. */
237 kSEMC_MUXCSX0 = SEMC_IOCR_MUX_CSX0_SHIFT, /*!< MUX CSX0 pin */
238 kSEMC_MUXCSX1 = SEMC_IOCR_MUX_CSX1_SHIFT, /*!< MUX CSX1 Pin.*/
239 kSEMC_MUXCSX2 = SEMC_IOCR_MUX_CSX2_SHIFT, /*!< MUX CSX2 Pin. */
240 kSEMC_MUXCSX3 = SEMC_IOCR_MUX_CSX3_SHIFT, /*!< MUX CSX3 Pin. */
241 kSEMC_MUXRDY = SEMC_IOCR_MUX_RDY_SHIFT /*!< MUX RDY pin. */
242 } semc_iomux_pin;
243
244 /*! @brief SEMC NOR/PSRAM Address bit 27 A27. */
245 typedef enum _semc_iomux_nora27_pin
246 {
247 kSEMC_MORA27_NONE = 0, /*!< No NOR/SRAM A27 pin. */
248 kSEMC_NORA27_MUXCSX3 = SEMC_IOCR_MUX_CSX3_SHIFT, /*!< MUX CSX3 Pin. */
249 kSEMC_NORA27_MUXRDY = SEMC_IOCR_MUX_RDY_SHIFT /*!< MUX RDY pin. */
250 } semc_iomux_nora27_pin;
251
252 /*! @brief SEMC port size. */
253 typedef enum _semc_port_size
254 {
255 kSEMC_PortSize8Bit = 0, /*!< 8-Bit port size. */
256 kSEMC_PortSize16Bit, /*!< 16-Bit port size. */
257 #if defined(FSL_FEATURE_SEMC_SUPPORT_SDRAM_PS_BITWIDTH) && (FSL_FEATURE_SEMC_SUPPORT_SDRAM_PS_BITWIDTH == 0x02U)
258 kSEMC_PortSize32Bit /*!< 32-Bit port size. */
259 #endif /* FSL_FEATURE_SEMC_SUPPORT_SDRAM_PS_BITWIDTH */
260 } smec_port_size_t;
261
262 /*! @brief SEMC address mode. */
263 typedef enum _semc_addr_mode
264 {
265 kSEMC_AddrDataMux = 0, /*!< SEMC address/data mux mode. */
266 kSEMC_AdvAddrdataMux, /*!< Advanced address/data mux mode. */
267 kSEMC_AddrDataNonMux /*!< Address/data non-mux mode. */
268 } semc_addr_mode_t;
269
270 /*! @brief SEMC DQS read strobe mode. */
271 typedef enum _semc_dqs_mode
272 {
273 kSEMC_Loopbackinternal = 0, /*!< Dummy read strobe loopbacked internally. */
274 kSEMC_Loopbackdqspad, /*!< Dummy read strobe loopbacked from DQS pad. */
275 } semc_dqs_mode_t;
276
277 /*! @brief SEMC ADV signal active polarity. */
278 typedef enum _semc_adv_polarity
279 {
280 kSEMC_AdvActiveLow = 0, /*!< Adv active low. */
281 kSEMC_AdvActiveHigh, /*!< Adv active high. */
282 } semc_adv_polarity_t;
283
284 /*! @brief SEMC sync mode. */
285 typedef enum _semc_sync_mode
286 {
287 kSEMC_AsyncMode = 0, /*!< Async mode. */
288 kSEMC_SyncMode, /*!< Sync mode. */
289 } semc_sync_mode_t;
290
291 /*! @brief SEMC ADV signal level control. */
292 typedef enum _semc_adv_level_control
293 {
294 kSEMC_AdvHigh = 0, /*!< Adv is high during address hold state. */
295 kSEMC_AdvLow, /*!< Adv is low during address hold state. */
296 } semc_adv_level_control_t;
297
298 /*! @brief SEMC RDY signal active polarity. */
299 typedef enum _semc_rdy_polarity
300 {
301 kSEMC_RdyActiveLow = 0, /*!< Adv active low. */
302 kSEMC_RdyActivehigh, /*!< Adv active low. */
303 } semc_rdy_polarity_t;
304
305 /*! @brief SEMC IP command for NAND: address mode. */
306 typedef enum _semc_ipcmd_nand_addrmode
307 {
308 kSEMC_NANDAM_ColumnRow = 0x0U, /*!< Address mode: column and row address(5Byte-CA0/CA1/RA0/RA1/RA2). */
309 kSEMC_NANDAM_ColumnCA0, /*!< Address mode: column address only(1 Byte-CA0). */
310 kSEMC_NANDAM_ColumnCA0CA1, /*!< Address mode: column address only(2 Byte-CA0/CA1). */
311 kSEMC_NANDAM_RawRA0, /*!< Address mode: row address only(1 Byte-RA0). */
312 kSEMC_NANDAM_RawRA0RA1, /*!< Address mode: row address only(2 Byte-RA0/RA1). */
313 kSEMC_NANDAM_RawRA0RA1RA2 /*!< Address mode: row address only(3 Byte-RA0). */
314 } semc_ipcmd_nand_addrmode_t;
315
316 /*! @brief SEMC IP command for NAND： command mode. */
317 typedef enum _semc_ipcmd_nand_cmdmode
318 {
319 kSEMC_NANDCM_Command = 0x2U, /*!< command. */
320 kSEMC_NANDCM_CommandHold, /*!< Command hold. */
321 kSEMC_NANDCM_CommandAddress, /*!< Command address. */
322 kSEMC_NANDCM_CommandAddressHold, /*!< Command address hold. */
323 kSEMC_NANDCM_CommandAddressRead, /*!< Command address read. */
324 kSEMC_NANDCM_CommandAddressWrite, /*!< Command address write. */
325 kSEMC_NANDCM_CommandRead, /*!< Command read. */
326 kSEMC_NANDCM_CommandWrite, /*!< Command write. */
327 kSEMC_NANDCM_Read, /*!< Read. */
328 kSEMC_NANDCM_Write /*!< Write. */
329 } semc_ipcmd_nand_cmdmode_t;
330
331 /*! @brief SEMC NAND address option. */
332 typedef enum _semc_nand_address_option
333 {
334 kSEMC_NandAddrOption_5byte_CA2RA3 = 0U, /*!< CA0+CA1+RA0+RA1+RA2 */
335 kSEMC_NandAddrOption_4byte_CA2RA2 = 2U, /*!< CA0+CA1+RA0+RA1 */
336 kSEMC_NandAddrOption_3byte_CA2RA1 = 4U, /*!< CA0+CA1+RA0 */
337 kSEMC_NandAddrOption_4byte_CA1RA3 = 1U, /*!< CA0+RA0+RA1+RA2 */
338 kSEMC_NandAddrOption_3byte_CA1RA2 = 3U, /*!< CA0+RA0+RA1 */
339 kSEMC_NandAddrOption_2byte_CA1RA1 = 7U, /*!< CA0+RA0 */
340 } semc_nand_address_option_t;
341
342 /*! @brief SEMC IP command for NOR. */
343 typedef enum _semc_ipcmd_nor_dbi
344 {
345 kSEMC_NORDBICM_Read = 0x2U, /*!< NOR read. */
346 kSEMC_NORDBICM_Write /*!< NOR write. */
347 } semc_ipcmd_nor_dbi_t;
348
349 /*! @brief SEMC IP command for SRAM. */
350 typedef enum _semc_ipcmd_sram
351 {
352 kSEMC_SRAMCM_ArrayRead = 0x2U, /*!< SRAM memory array read. */
353 kSEMC_SRAMCM_ArrayWrite, /*!< SRAM memory array write. */
354 kSEMC_SRAMCM_RegRead, /*!< SRAM memory register read. */
355 kSEMC_SRAMCM_RegWrite /*!< SRAM memory register write. */
356 } semc_ipcmd_sram_t;
357
358 /*! @brief SEMC IP command for SDARM. */
359 typedef enum _semc_ipcmd_sdram
360 {
361 kSEMC_SDRAMCM_Read = 0x8U, /*!< SDRAM memory read. */
362 kSEMC_SDRAMCM_Write, /*!< SDRAM memory write. */
363 kSEMC_SDRAMCM_Modeset, /*!< SDRAM MODE SET. */
364 kSEMC_SDRAMCM_Active, /*!< SDRAM active. */
365 kSEMC_SDRAMCM_AutoRefresh, /*!< SDRAM auto-refresh. */
366 kSEMC_SDRAMCM_SelfRefresh, /*!< SDRAM self-refresh. */
367 kSEMC_SDRAMCM_Precharge, /*!< SDRAM precharge. */
368 kSEMC_SDRAMCM_Prechargeall /*!< SDRAM precharge all. */
369 } semc_ipcmd_sdram_t;
370
371 /*! @brief SEMC SDRAM configuration structure.
372 *
373 * 1. The memory size in the configuration is in the unit of KB. So memsize_kbytes
374 * should be set as 2^2, 2^3, 2^4 .etc which is base 2KB exponential function.
375 * Take refer to BR0~BR3 register in RM for details.
376 * 2. The prescalePeriod_N16Cycle is in unit of 16 clock cycle. It is a exception for prescaleTimer_n16cycle = 0,
377 * it means the prescaler timer period is 256 * 16 clock cycles. For precalerIf precalerTimer_n16cycle not equal to 0,
378 * The prescaler timer period is prescalePeriod_N16Cycle * 16 clock cycles.
379 * idleTimeout_NprescalePeriod, refreshUrgThreshold_NprescalePeriod, refreshPeriod_NprescalePeriod are
380 * similar to prescalePeriod_N16Cycle.
381 *
382 */
383 typedef struct _semc_sdram_config
384 {
385 semc_iomux_pin csxPinMux; /*!< CS pin mux. The kSEMC_MUXA8 is not valid in sdram pin mux setting. */
386 uint32_t address; /*!< The base address. */
387 uint32_t memsize_kbytes; /*!< The memory size in unit of kbytes. */
388 smec_port_size_t portSize; /*!< Port size. */
389 sem_sdram_burst_len_t burstLen; /*!< Burst length. */
390 semc_sdram_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */
391 semc_caslatency_t casLatency; /*!< CAS latency. */
392 uint8_t tPrecharge2Act_Ns; /*!< Precharge to active wait time in unit of nanosecond. */
393 uint8_t tAct2ReadWrite_Ns; /*!< Act to read/write wait time in unit of nanosecond. */
394 uint8_t tRefreshRecovery_Ns; /*!< Refresh recovery time in unit of nanosecond. */
395 uint8_t tWriteRecovery_Ns; /*!< write recovery time in unit of nanosecond. */
396 uint8_t tCkeOff_Ns; /*!< CKE off minimum time in unit of nanosecond. */
397 uint8_t tAct2Prechage_Ns; /*!< Active to precharge in unit of nanosecond. */
398 uint8_t tSelfRefRecovery_Ns; /*!< Self refresh recovery time in unit of nanosecond. */
399 uint8_t tRefresh2Refresh_Ns; /*!< Refresh to refresh wait time in unit of nanosecond. */
400 uint8_t tAct2Act_Ns; /*!< Active to active wait time in unit of nanosecond. */
401 uint32_t tPrescalePeriod_Ns; /*!< Prescaler timer period should not be larger than 256 * 16 * clock cycle. */
402 uint32_t tIdleTimeout_Ns; /*!< Idle timeout in unit of prescale time period. */
403 uint32_t refreshPeriod_nsPerRow; /*!< Refresh timer period like 64ms * 1000000/8192 . */
404 uint32_t refreshUrgThreshold; /*!< Refresh urgent threshold. */
405 uint8_t refreshBurstLen; /*!< Refresh burst length. */
406 #if defined(FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL) && (FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL)
407 uint8_t delayChain; /*!< Delay chain, which adds delays on DQS clock to compensate timings while DQS is faster than
408 read data. */
409 #endif /* FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL */
410 } semc_sdram_config_t;
411
412 /*! @brief SEMC NAND device timing configuration structure. */
413 typedef struct _semc_nand_timing_config
414 {
415 uint8_t tCeSetup_Ns; /*!< CE setup time: tCS. */
416 uint8_t tCeHold_Ns; /*!< CE hold time: tCH. */
417 uint8_t tCeInterval_Ns; /*!< CE interval time:tCEITV. */
418 uint8_t tWeLow_Ns; /*!< WE low time: tWP. */
419 uint8_t tWeHigh_Ns; /*!< WE high time: tWH. */
420 uint8_t tReLow_Ns; /*!< RE low time: tRP. */
421 uint8_t tReHigh_Ns; /*!< RE high time: tREH. */
422 uint8_t tTurnAround_Ns; /*!< Turnaround time for async mode: tTA. */
423 uint8_t tWehigh2Relow_Ns; /*!< WE# high to RE# wait time: tWHR. */
424 uint8_t tRehigh2Welow_Ns; /*!< RE# high to WE# low wait time: tRHW. */
425 uint8_t tAle2WriteStart_Ns; /*!< ALE to write start wait time: tADL. */
426 uint8_t tReady2Relow_Ns; /*!< Ready to RE# low min wait time: tRR. */
427 uint8_t tWehigh2Busy_Ns; /*!< WE# high to busy wait time: tWB. */
428 } semc_nand_timing_config_t;
429
430 /*! @brief SEMC NAND configuration structure. */
431 typedef struct _semc_nand_config
432 {
433 semc_iomux_pin cePinMux; /*!< The CE pin mux setting. The kSEMC_MUXRDY is not valid for CE pin setting. */
434 uint32_t axiAddress; /*!< The base address for AXI nand. */
435 uint32_t axiMemsize_kbytes; /*!< The memory size in unit of kbytes for AXI nand. */
436 uint32_t ipgAddress; /*!< The base address for IPG nand . */
437 uint32_t ipgMemsize_kbytes; /*!< The memory size in unit of kbytes for IPG nand. */
438 semc_rdy_polarity_t rdyactivePolarity; /*!< Wait ready polarity. */
439 bool edoModeEnabled; /*!< EDO mode enabled. */
440 semc_nand_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */
441 semc_nand_address_option_t arrayAddrOption; /*!< Address option. */
442 sem_nand_burst_len_t burstLen; /*!< Burst length. */
443 smec_port_size_t portSize; /*!< Port size. */
444 semc_nand_timing_config_t *timingConfig; /*!< SEMC nand timing configuration. */
445 } semc_nand_config_t;
446
447 /*! @brief SEMC NOR configuration structure. */
448 typedef struct _semc_nor_config
449 {
450 semc_iomux_pin cePinMux; /*!< The CE# pin mux setting. */
451 semc_iomux_nora27_pin addr27; /*!< The Addr bit 27 pin mux setting. */
452 uint32_t address; /*!< The base address. */
453 uint32_t memsize_kbytes; /*!< The memory size in unit of kbytes. */
454 uint8_t addrPortWidth; /*!< The address port width. */
455 semc_rdy_polarity_t rdyactivePolarity; /*!< Wait ready polarity. */
456 semc_adv_polarity_t advActivePolarity; /*!< ADV# polarity. */
457 semc_norsram_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */
458 semc_addr_mode_t addrMode; /*!< Address mode. */
459 sem_norsram_burst_len_t burstLen; /*!< Burst length. */
460 smec_port_size_t portSize; /*!< Port size. */
461 uint8_t tCeSetup_Ns; /*!< The CE setup time. */
462 uint8_t tCeHold_Ns; /*!< The CE hold time. */
463 uint8_t tCeInterval_Ns; /*!< CE interval minimum time. */
464 uint8_t tAddrSetup_Ns; /*!< The address setup time. */
465 uint8_t tAddrHold_Ns; /*!< The address hold time. */
466 uint8_t tWeLow_Ns; /*!< WE low time for async mode. */
467 uint8_t tWeHigh_Ns; /*!< WE high time for async mode. */
468 uint8_t tReLow_Ns; /*!< RE low time for async mode. */
469 uint8_t tReHigh_Ns; /*!< RE high time for async mode. */
470 uint8_t tTurnAround_Ns; /*!< Turnaround time for async mode. */
471 uint8_t tAddr2WriteHold_Ns; /*!< Address to write data hold time for async mode. */
472 #if defined(FSL_FEATURE_SEMC_HAS_NOR_WDS_TIME) && (FSL_FEATURE_SEMC_HAS_NOR_WDS_TIME)
473 uint8_t tWriteSetup_Ns; /*!< Write data setup time for sync mode.*/
474 #endif
475 #if defined(FSL_FEATURE_SEMC_HAS_NOR_WDH_TIME) && (FSL_FEATURE_SEMC_HAS_NOR_WDH_TIME)
476 uint8_t tWriteHold_Ns; /*!< Write hold time for sync mode. */
477 #endif
478 #if defined(FSL_FEATURE_SEMC_HAS_NOR_LC_TIME) && (FSL_FEATURE_SEMC_HAS_NOR_LC_TIME)
479 uint8_t latencyCount; /*!< Latency count for sync mode. */
480 #endif
481 #if defined(FSL_FEATURE_SEMC_HAS_NOR_RD_TIME) && (FSL_FEATURE_SEMC_HAS_NOR_RD_TIME)
482 uint8_t readCycle; /*!< Read cycle time for sync mode. */
483 #endif
484 #if defined(FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL) && (FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL)
485 uint8_t delayChain; /*!< Delay chain, which adds delays on DQS clock to compensate timings while DQS is faster than
486 read data. */
487 #endif /* FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL */
488 } semc_nor_config_t;
489
490 /*! @brief SEMC SRAM configuration structure. */
491 typedef struct _semc_sram_config
492 {
493 semc_iomux_pin cePinMux; /*!< The CE# pin mux setting. */
494 semc_iomux_nora27_pin addr27; /*!< The Addr bit 27 pin mux setting. */
495 uint32_t address; /*!< The base address. */
496 uint32_t memsize_kbytes; /*!< The memory size in unit of kbytes. */
497 uint8_t addrPortWidth; /*!< The address port width. */
498 semc_adv_polarity_t advActivePolarity; /*!< ADV# polarity 1: active high, 0: active low. */
499 semc_addr_mode_t addrMode; /*!< Address mode. */
500 sem_norsram_burst_len_t burstLen; /*!< Burst length. */
501 smec_port_size_t portSize; /*!< Port size. */
502 #if defined(FSL_FEATURE_SEMC_HAS_SRAM_SYNCEN) && (FSL_FEATURE_SEMC_HAS_SRAM_SYNCEN)
503 semc_sync_mode_t syncMode; /*!< Sync mode. */
504 #endif /* FSL_FEATURE_SEMC_HAS_SRAM_SYNCEN */
505 #if defined(FSL_FEATURE_SEMC_HAS_SRAM_WAITEN) && (FSL_FEATURE_SEMC_HAS_SRAM_WAITEN)
506 bool waitEnable; /*!< Wait enable. */
507 #endif /* FSL_FEATURE_SEMC_HAS_SRAM_WAITEN */
508 #if defined(FSL_FEATURE_SEMC_HAS_SRAM_WAITSP) && (FSL_FEATURE_SEMC_HAS_SRAM_WAITSP)
509 uint8_t waitSample; /*!< Wait sample. */
510 #endif /* FSL_FEATURE_SEMC_HAS_SRAM_WAITSP */
511 #if defined(FSL_FEATURE_SEMC_HAS_SRAM_ADVH) && (FSL_FEATURE_SEMC_HAS_SRAM_ADVH)
512 semc_adv_level_control_t advLevelCtrl; /*!< ADV# level control during address hold state, 1: low, 0: high. */
513 #endif /* FSL_FEATURE_SEMC_HAS_SRAM_ADVH */
514 uint8_t tCeSetup_Ns; /*!< The CE setup time. */
515 uint8_t tCeHold_Ns; /*!< The CE hold time. */
516 uint8_t tCeInterval_Ns; /*!< CE interval minimum time. */
517 #if defined(FSL_FEATURE_SEMC_HAS_SRAM_RDH_TIME) && (FSL_FEATURE_SEMC_HAS_SRAM_RDH_TIME)
518 uint8_t readHoldTime_Ns; /*!< read hold time. */
519 #endif /* FSL_FEATURE_SEMC_HAS_SRAM_RDH_TIME */
520 uint8_t tAddrSetup_Ns; /*!< The address setup time. */
521 uint8_t tAddrHold_Ns; /*!< The address hold time. */
522 uint8_t tWeLow_Ns; /*!< WE low time for async mode. */
523 uint8_t tWeHigh_Ns; /*!< WE high time for async mode. */
524 uint8_t tReLow_Ns; /*!< RE low time for async mode. */
525 uint8_t tReHigh_Ns; /*!< RE high time for async mode. */
526 uint8_t tTurnAround_Ns; /*!< Turnaround time for async mode. */
527 uint8_t tAddr2WriteHold_Ns; /*!< Address to write data hold time for async mode. */
528 #if defined(FSL_FEATURE_SEMC_HAS_SRAM_WDS_TIME) && (FSL_FEATURE_SEMC_HAS_SRAM_WDS_TIME)
529 uint8_t tWriteSetup_Ns; /*!<Write data setup time for sync mode. */
530 #endif
531 #if defined(FSL_FEATURE_SEMC_HAS_SRAM_WDH_TIME) && (FSL_FEATURE_SEMC_HAS_SRAM_WDH_TIME)
532 uint8_t tWriteHold_Ns; /*!<Write hold time for sync mode. */
533 #endif
534 #if defined(FSL_FEATURE_SEMC_HAS_SRAM_LC_TIME) && (FSL_FEATURE_SEMC_HAS_SRAM_LC_TIME)
535 uint8_t latencyCount; /*!<Latency count for sync mode. */
536 #endif
537 #if defined(FSL_FEATURE_SEMC_HAS_SRAM_RD_TIME) && (FSL_FEATURE_SEMC_HAS_SRAM_RD_TIME)
538 uint8_t readCycle; /*!<Read cycle time for sync mode. */
539 #endif
540 #if defined(FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL) && (FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL)
541 uint8_t delayChain; /*!< Delay chain, which adds delays on DQS clock to compensate timings while DQS is faster than
542 read data. */
543 #endif /* FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL */
544 } semc_sram_config_t;
545
546 /*! @brief SEMC DBI configuration structure. */
547 typedef struct _semc_dbi_config
548 {
549 semc_iomux_pin csxPinMux; /*!< The CE# pin mux. */
550 uint32_t address; /*!< The base address. */
551 uint32_t memsize_kbytes; /*!< The memory size in unit of 4kbytes. */
552 semc_dbi_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */
553 sem_dbi_burst_len_t burstLen; /*!< Burst length. */
554 smec_port_size_t portSize; /*!< Port size. */
555 uint8_t tCsxSetup_Ns; /*!< The CSX setup time. */
556 uint8_t tCsxHold_Ns; /*!< The CSX hold time. */
557 uint8_t tWexLow_Ns; /*!< WEX low time. */
558 uint8_t tWexHigh_Ns; /*!< WEX high time. */
559 uint8_t tRdxLow_Ns; /*!< RDX low time. */
560 uint8_t tRdxHigh_Ns; /*!< RDX high time. */
561 uint8_t tCsxInterval_Ns; /*!< Write data setup time.*/
562 } semc_dbi_config_t;
563
564 /*! @brief SEMC AXI queue a weight setting structure. */
565 typedef struct _semc_queuea_weight_struct
566 {
567 uint32_t qos : 4; /*!< weight of qos for queue 0 . */
568 uint32_t aging : 4; /*!< weight of aging for queue 0.*/
569 uint32_t slaveHitNoswitch : 8; /*!< weight of read/write no switch for queue 0 .*/
570 uint32_t slaveHitSwitch : 8; /*!< weight of read/write switch for queue 0.*/
571 } semc_queuea_weight_struct_t;
572
573 /*! @brief SEMC AXI queue a weight setting union. */
574 typedef union _semc_queuea_weight
575 {
576 semc_queuea_weight_struct_t queueaConfig; /*!< Structure configuration for queueA. */
577 uint32_t queueaValue; /*!< Configuration value for queueA which could directly write to the reg. */
578 } semc_queuea_weight_t;
579
580 /*! @brief SEMC AXI queue b weight setting structure. */
581 typedef struct _semc_queueb_weight_struct
582 {
583 uint32_t qos : 4; /*!< weight of qos for queue 1. */
584 uint32_t aging : 4; /*!< weight of aging for queue 1.*/
585 uint32_t weightPagehit : 8; /*!< weight of page hit for queue 1 only .*/
586 uint32_t slaveHitNoswitch : 8; /*!< weight of read/write no switch for queue 1.*/
587 uint32_t bankRotation : 8; /*!< weight of bank rotation for queue 1 only .*/
588 } semc_queueb_weight_struct_t;
589
590 /*! @brief SEMC AXI queue b weight setting union. */
591 typedef union _semc_queueb_weight
592 {
593 semc_queueb_weight_struct_t queuebConfig; /*!< Structure configuration for queueB. */
594 uint32_t queuebValue; /*!< Configuration value for queueB which could directly write to the reg. */
595 } semc_queueb_weight_t;
596
597 /*! @brief SEMC AXI queue weight setting. */
598 typedef struct _semc_axi_queueweight
599 {
600 bool queueaEnable; /*!< Enable queue a. */
601 semc_queuea_weight_t queueaWeight; /*!< Weight settings for queue a. */
602 bool queuebEnable; /*!< Enable queue b. */
603 semc_queueb_weight_t queuebWeight; /*!< Weight settings for queue b. */
604 } semc_axi_queueweight_t;
605
606 /*!
607 * @brief SEMC configuration structure.
608 *
609 * busTimeoutCycles: when busTimeoutCycles is zero, the bus timeout cycle is
610 * 255*1024. otherwise the bus timeout cycles is busTimeoutCycles*1024.
611 * cmdTimeoutCycles: is used for command execution timeout cycles. it's
612 * similar to the busTimeoutCycles.
613 */
614 typedef struct _semc_config_t
615 {
616 semc_dqs_mode_t dqsMode; /*!< Dummy read strobe mode: use enum in "semc_dqs_mode_t". */
617 uint8_t cmdTimeoutCycles; /*!< Command execution timeout cycles. */
618 uint8_t busTimeoutCycles; /*!< Bus timeout cycles. */
619 semc_axi_queueweight_t queueWeight; /*!< AXI queue weight. */
620 } semc_config_t;
621
622 /*******************************************************************************
623 * API
624 ******************************************************************************/
625
626 #if defined(__cplusplus)
627 extern "C" {
628 #endif
629
630 /*!
631 * @name SEMC Initialization and De-initialization
632 * @{
633 */
634
635 /*!
636 * @brief Gets the SEMC default basic configuration structure.
637 *
638 * The purpose of this API is to get the default SEMC
639 * configure structure for SEMC_Init(). User may use the initialized
640 * structure unchanged in SEMC_Init(), or modify some fields of the
641 * structure before calling SEMC_Init().
642 * Example:
643 @code
644 semc_config_t config;
645 SEMC_GetDefaultConfig(&config);
646 @endcode
647 * @param config The SEMC configuration structure pointer.
648 */
649 void SEMC_GetDefaultConfig(semc_config_t *config);
650
651 /*!
652 * @brief Initializes SEMC.
653 * This function ungates the SEMC clock and initializes SEMC.
654 * This function must be called before calling any other SEMC driver functions.
655 *
656 * @param base SEMC peripheral base address.
657 * @param configure The SEMC configuration structure pointer.
658 */
659 void SEMC_Init(SEMC_Type *base, semc_config_t *configure);
660
661 /*!
662 * @brief Deinitializes the SEMC module and gates the clock.
663 *
664 * This function gates the SEMC clock. As a result, the SEMC module doesn't work after
665 * calling this function, for some IDE, calling this API may cause the next downloading
666 * operation failed. so, please call this API cautiously. Additional, users can
667 * using "#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL (1)" to disable the clock control
668 * operation in drivers.
669 *
670 * @param base SEMC peripheral base address.
671 */
672 void SEMC_Deinit(SEMC_Type *base);
673
674 /* @} */
675
676 /*!
677 * @name SEMC Configuration Operation For Each Memory Type
678 * @{
679 */
680
681 /*!
682 * @brief Configures SDRAM controller in SEMC.
683 *
684 * @param base SEMC peripheral base address.
685 * @param cs The chip selection.
686 * @param config The sdram configuration.
687 * @param clkSrc_Hz The SEMC clock frequency.
688 */
689 status_t SEMC_ConfigureSDRAM(SEMC_Type *base, semc_sdram_cs_t cs, semc_sdram_config_t *config, uint32_t clkSrc_Hz);
690
691 /*!
692 * @brief Configures NAND controller in SEMC.
693 *
694 * @param base SEMC peripheral base address.
695 * @param config The nand configuration.
696 * @param clkSrc_Hz The SEMC clock frequency.
697 */
698 status_t SEMC_ConfigureNAND(SEMC_Type *base, semc_nand_config_t *config, uint32_t clkSrc_Hz);
699
700 /*!
701 * @brief Configures NOR controller in SEMC.
702 *
703 * @param base SEMC peripheral base address.
704 * @param config The nor configuration.
705 * @param clkSrc_Hz The SEMC clock frequency.
706 */
707 status_t SEMC_ConfigureNOR(SEMC_Type *base, semc_nor_config_t *config, uint32_t clkSrc_Hz);
708
709 /*!
710 * @brief Configures SRAM controller in SEMC.
711 *
712 * @param base SEMC peripheral base address.
713 * @param cs The chip selection.
714 * @param config The sram configuration.
715 * @param clkSrc_Hz The SEMC clock frequency.
716 */
717 status_t SEMC_ConfigureSRAMWithChipSelection(SEMC_Type *base,
718 semc_sram_cs_t cs,
719 semc_sram_config_t *config,
720 uint32_t clkSrc_Hz);
721
722 /*!
723 * @brief Configures SRAM controller in SEMC.
724 * @deprecated Do not use this function. It has been superceded by @ref SEMC_ConfigureSRAMWithChipSelection.
725 * @param base SEMC peripheral base address.
726 * @param config The sram configuration.
727 * @param clkSrc_Hz The SEMC clock frequency.
728 */
729 status_t SEMC_ConfigureSRAM(SEMC_Type *base, semc_sram_config_t *config, uint32_t clkSrc_Hz);
730
731 /*!
732 * @brief Configures DBI controller in SEMC.
733 *
734 * @param base SEMC peripheral base address.
735 * @param config The dbi configuration.
736 * @param clkSrc_Hz The SEMC clock frequency.
737 */
738 status_t SEMC_ConfigureDBI(SEMC_Type *base, semc_dbi_config_t *config, uint32_t clkSrc_Hz);
739
740 /* @} */
741
742 /*!
743 * @name SEMC Interrupt Operation
744 * @{
745 */
746
747 /*!
748 * @brief Enables the SEMC interrupt.
749 *
750 * This function enables the SEMC interrupts according to the provided mask. The mask
751 * is a logical OR of enumeration members. See @ref semc_interrupt_enable_t.
752 * For example, to enable the IP command done and error interrupt, do the following.
753 * @code
754 * SEMC_EnableInterrupts(ENET, kSEMC_IPCmdDoneInterrupt | kSEMC_IPCmdErrInterrupt);
755 * @endcode
756 *
757 * @param base SEMC peripheral base address.
758 * @param mask SEMC interrupts to enable. This is a logical OR of the
759 * enumeration :: semc_interrupt_enable_t.
760 */
SEMC_EnableInterrupts(SEMC_Type * base,uint32_t mask)761 static inline void SEMC_EnableInterrupts(SEMC_Type *base, uint32_t mask)
762 {
763 base->INTEN |= mask;
764 }
765
766 /*!
767 * @brief Disables the SEMC interrupt.
768 *
769 * This function disables the SEMC interrupts according to the provided mask. The mask
770 * is a logical OR of enumeration members. See @ref semc_interrupt_enable_t.
771 * For example, to disable the IP command done and error interrupt, do the following.
772 * @code
773 * SEMC_DisableInterrupts(ENET, kSEMC_IPCmdDoneInterrupt | kSEMC_IPCmdErrInterrupt);
774 * @endcode
775 *
776 * @param base SEMC peripheral base address.
777 * @param mask SEMC interrupts to disable. This is a logical OR of the
778 * enumeration :: semc_interrupt_enable_t.
779 */
SEMC_DisableInterrupts(SEMC_Type * base,uint32_t mask)780 static inline void SEMC_DisableInterrupts(SEMC_Type *base, uint32_t mask)
781 {
782 base->INTEN &= ~mask;
783 }
784
785 /*!
786 * @brief Gets the SEMC status.
787 *
788 * This function gets the SEMC interrupts event status.
789 * User can use the a logical OR of enumeration member as a mask.
790 * See @ref semc_interrupt_enable_t.
791 *
792 * @param base SEMC peripheral base address.
793 * @return status flag, use status flag in semc_interrupt_enable_t to get the related status.
794 */
SEMC_GetStatusFlag(SEMC_Type * base)795 static inline bool SEMC_GetStatusFlag(SEMC_Type *base)
796 {
797 return (base->INTR != 0x00U) ? true : false;
798 }
799
800 /*!
801 * @brief Clears the SEMC status flag state.
802 *
803 * The following status register flags can be cleared SEMC interrupt status.
804 *
805 * @param base SEMC base pointer
806 * @param mask The status flag mask, a logical OR of enumeration member @ref semc_interrupt_enable_t.
807 */
SEMC_ClearStatusFlags(SEMC_Type * base,uint32_t mask)808 static inline void SEMC_ClearStatusFlags(SEMC_Type *base, uint32_t mask)
809 {
810 base->INTR |= mask;
811 }
812
813 /* @} */
814
815 /*!
816 * @name SEMC Memory Access Operation
817 * @{
818 */
819
820 /*!
821 * @brief Check if SEMC is in idle.
822 *
823 * @param base SEMC peripheral base address.
824 * @return True SEMC is in idle, false is not in idle.
825 */
SEMC_IsInIdle(SEMC_Type * base)826 static inline bool SEMC_IsInIdle(SEMC_Type *base)
827 {
828 return ((base->STS0 & SEMC_STS0_IDLE_MASK) != 0x00U) ? true : false;
829 }
830
831 /*!
832 * @brief SEMC IP command access.
833 *
834 * @param base SEMC peripheral base address.
835 * @param memType SEMC memory type. refer to "semc_mem_type_t"
836 * @param address SEMC device address.
837 * @param command SEMC IP command.
838 * For NAND device, we should use the SEMC_BuildNandIPCommand to get the right nand command.
839 * For NOR/DBI device, take refer to "semc_ipcmd_nor_dbi_t".
840 * For SRAM device, take refer to "semc_ipcmd_sram_t".
841 * For SDRAM device, take refer to "semc_ipcmd_sdram_t".
842 * @param write Data for write access.
843 * @param read Data pointer for read data out.
844 */
845 status_t SEMC_SendIPCommand(
846 SEMC_Type *base, semc_mem_type_t memType, uint32_t address, uint32_t command, uint32_t write, uint32_t *read);
847
848 /*!
849 * @brief Build SEMC IP command for NAND.
850 *
851 * This function build SEMC NAND IP command. The command is build of user command code,
852 * SEMC address mode and SEMC command mode.
853 *
854 * @param userCommand NAND device normal command.
855 * @param addrMode NAND address mode. Refer to "semc_ipcmd_nand_addrmode_t".
856 * @param cmdMode NAND command mode. Refer to "semc_ipcmd_nand_cmdmode_t".
857 */
SEMC_BuildNandIPCommand(uint8_t userCommand,semc_ipcmd_nand_addrmode_t addrMode,semc_ipcmd_nand_cmdmode_t cmdMode)858 static inline uint16_t SEMC_BuildNandIPCommand(uint8_t userCommand,
859 semc_ipcmd_nand_addrmode_t addrMode,
860 semc_ipcmd_nand_cmdmode_t cmdMode)
861 {
862 return ((uint16_t)userCommand << 8U) | ((uint16_t)addrMode << 4U) | ((uint16_t)cmdMode & 0x000FU);
863 }
864
865 /*!
866 * @brief Check if the NAND device is ready.
867 *
868 * @param base SEMC peripheral base address.
869 * @return True NAND is ready, false NAND is not ready.
870 */
SEMC_IsNandReady(SEMC_Type * base)871 static inline bool SEMC_IsNandReady(SEMC_Type *base)
872 {
873 return ((base->STS0 & SEMC_STS0_NARDY_MASK) != 0x00U) ? true : false;
874 }
875
876 /*!
877 * @brief SEMC NAND device memory write through IP command.
878 *
879 * @param base SEMC peripheral base address.
880 * @param address SEMC NAND device address.
881 * @param data Data for write access.
882 * @param size_bytes Data length.
883 */
884 status_t SEMC_IPCommandNandWrite(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes);
885
886 /*!
887 * @brief SEMC NAND device memory read through IP command.
888 *
889 * @param base SEMC peripheral base address.
890 * @param address SEMC NAND device address.
891 * @param data Data pointer for data read out.
892 * @param size_bytes Data length.
893 */
894 status_t SEMC_IPCommandNandRead(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes);
895
896 /*!
897 * @brief SEMC NOR device memory write through IP command.
898 *
899 * @param base SEMC peripheral base address.
900 * @param address SEMC NOR device address.
901 * @param data Data for write access.
902 * @param size_bytes Data length.
903 */
904 status_t SEMC_IPCommandNorWrite(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes);
905
906 /*!
907 * @brief SEMC NOR device memory read through IP command.
908 *
909 * @param base SEMC peripheral base address.
910 * @param address SEMC NOR device address.
911 * @param data Data pointer for data read out.
912 * @param size_bytes Data length.
913 */
914 status_t SEMC_IPCommandNorRead(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes);
915
916 /* @} */
917
918 #if defined(__cplusplus)
919 }
920 #endif
921
922 /*! @}*/
923
924 #endif /* _FSL_SEMC_H_*/
925
