1 /*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016-2022 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8 #ifndef _FSL_LPSPI_H_
9 #define _FSL_LPSPI_H_
10
11 #include "fsl_common.h"
12
13 /*!
14 * @addtogroup lpspi_driver
15 * @{
16 */
17
18 /**********************************************************************************************************************
19 * Definitions
20 *********************************************************************************************************************/
21
22 /*! @name Driver version */
23 /*@{*/
24 /*! @brief LPSPI driver version. */
25 #define FSL_LPSPI_DRIVER_VERSION (MAKE_VERSION(2, 4, 5))
26 /*@}*/
27
28 #ifndef LPSPI_DUMMY_DATA
29 /*! @brief LPSPI dummy data if no Tx data.*/
30 #define LPSPI_DUMMY_DATA (0x00U) /*!< Dummy data used for tx if there is not txData. */
31 #endif
32
33 /*! @brief Retry times for waiting flag. */
34 #ifndef SPI_RETRY_TIMES
35 #define SPI_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */
36 #endif
37
38 /*! @brief Global variable for dummy data value setting. */
39 extern volatile uint8_t g_lpspiDummyData[];
40
41 /*! @brief Status for the LPSPI driver.*/
42 enum
43 {
44 kStatus_LPSPI_Busy = MAKE_STATUS(kStatusGroup_LPSPI, 0), /*!< LPSPI transfer is busy.*/
45 kStatus_LPSPI_Error = MAKE_STATUS(kStatusGroup_LPSPI, 1), /*!< LPSPI driver error. */
46 kStatus_LPSPI_Idle = MAKE_STATUS(kStatusGroup_LPSPI, 2), /*!< LPSPI is idle.*/
47 kStatus_LPSPI_OutOfRange = MAKE_STATUS(kStatusGroup_LPSPI, 3), /*!< LPSPI transfer out Of range. */
48 kStatus_LPSPI_Timeout = MAKE_STATUS(kStatusGroup_LPSPI, 4) /*!< LPSPI timeout polling status flags. */
49 };
50
51 /*! @brief LPSPI status flags in SPIx_SR register.*/
52 enum _lpspi_flags
53 {
54 kLPSPI_TxDataRequestFlag = LPSPI_SR_TDF_MASK, /*!< Transmit data flag */
55 kLPSPI_RxDataReadyFlag = LPSPI_SR_RDF_MASK, /*!< Receive data flag */
56 kLPSPI_WordCompleteFlag = LPSPI_SR_WCF_MASK, /*!< Word Complete flag */
57 kLPSPI_FrameCompleteFlag = LPSPI_SR_FCF_MASK, /*!< Frame Complete flag */
58 kLPSPI_TransferCompleteFlag = LPSPI_SR_TCF_MASK, /*!< Transfer Complete flag */
59 kLPSPI_TransmitErrorFlag = LPSPI_SR_TEF_MASK, /*!< Transmit Error flag (FIFO underrun) */
60 kLPSPI_ReceiveErrorFlag = LPSPI_SR_REF_MASK, /*!< Receive Error flag (FIFO overrun) */
61 kLPSPI_DataMatchFlag = LPSPI_SR_DMF_MASK, /*!< Data Match flag */
62 kLPSPI_ModuleBusyFlag = LPSPI_SR_MBF_MASK, /*!< Module Busy flag */
63 kLPSPI_AllStatusFlag = (LPSPI_SR_TDF_MASK | LPSPI_SR_RDF_MASK | LPSPI_SR_WCF_MASK | LPSPI_SR_FCF_MASK |
64 LPSPI_SR_TCF_MASK | LPSPI_SR_TEF_MASK | LPSPI_SR_REF_MASK | LPSPI_SR_DMF_MASK |
65 LPSPI_SR_MBF_MASK) /*!< Used for clearing all w1c status flags */
66 };
67
68 /*! @brief LPSPI interrupt source.*/
69 enum _lpspi_interrupt_enable
70 {
71 kLPSPI_TxInterruptEnable = LPSPI_IER_TDIE_MASK, /*!< Transmit data interrupt enable */
72 kLPSPI_RxInterruptEnable = LPSPI_IER_RDIE_MASK, /*!< Receive data interrupt enable */
73 kLPSPI_WordCompleteInterruptEnable = LPSPI_IER_WCIE_MASK, /*!< Word complete interrupt enable */
74 kLPSPI_FrameCompleteInterruptEnable = LPSPI_IER_FCIE_MASK, /*!< Frame complete interrupt enable */
75 kLPSPI_TransferCompleteInterruptEnable = LPSPI_IER_TCIE_MASK, /*!< Transfer complete interrupt enable */
76 kLPSPI_TransmitErrorInterruptEnable = LPSPI_IER_TEIE_MASK, /*!< Transmit error interrupt enable(FIFO underrun)*/
77 kLPSPI_ReceiveErrorInterruptEnable = LPSPI_IER_REIE_MASK, /*!< Receive Error interrupt enable (FIFO overrun) */
78 kLPSPI_DataMatchInterruptEnable = LPSPI_IER_DMIE_MASK, /*!< Data Match interrupt enable */
79 kLPSPI_AllInterruptEnable =
80 (LPSPI_IER_TDIE_MASK | LPSPI_IER_RDIE_MASK | LPSPI_IER_WCIE_MASK | LPSPI_IER_FCIE_MASK | LPSPI_IER_TCIE_MASK |
81 LPSPI_IER_TEIE_MASK | LPSPI_IER_REIE_MASK | LPSPI_IER_DMIE_MASK) /*!< All above interrupts enable.*/
82 };
83
84 /*! @brief LPSPI DMA source.*/
85 enum _lpspi_dma_enable
86 {
87 kLPSPI_TxDmaEnable = LPSPI_DER_TDDE_MASK, /*!< Transmit data DMA enable */
88 kLPSPI_RxDmaEnable = LPSPI_DER_RDDE_MASK /*!< Receive data DMA enable */
89 };
90
91 /*! @brief LPSPI master or slave mode configuration.*/
92 typedef enum _lpspi_master_slave_mode
93 {
94 kLPSPI_Master = 1U, /*!< LPSPI peripheral operates in master mode.*/
95 kLPSPI_Slave = 0U /*!< LPSPI peripheral operates in slave mode.*/
96 } lpspi_master_slave_mode_t;
97
98 /*! @brief LPSPI Peripheral Chip Select (PCS) configuration (which PCS to configure).*/
99 typedef enum _lpspi_which_pcs_config
100 {
101 kLPSPI_Pcs0 = 0U, /*!< PCS[0] */
102 kLPSPI_Pcs1 = 1U, /*!< PCS[1] */
103 kLPSPI_Pcs2 = 2U, /*!< PCS[2] */
104 kLPSPI_Pcs3 = 3U /*!< PCS[3] */
105 } lpspi_which_pcs_t;
106
107 /*! @brief LPSPI Peripheral Chip Select (PCS) Polarity configuration.*/
108 typedef enum _lpspi_pcs_polarity_config
109 {
110 kLPSPI_PcsActiveHigh = 1U, /*!< PCS Active High (idles low) */
111 kLPSPI_PcsActiveLow = 0U /*!< PCS Active Low (idles high) */
112 } lpspi_pcs_polarity_config_t;
113
114 /*! @brief LPSPI Peripheral Chip Select (PCS) Polarity.*/
115 enum _lpspi_pcs_polarity
116 {
117 kLPSPI_Pcs0ActiveLow = 1U << 0, /*!< Pcs0 Active Low (idles high). */
118 kLPSPI_Pcs1ActiveLow = 1U << 1, /*!< Pcs1 Active Low (idles high). */
119 kLPSPI_Pcs2ActiveLow = 1U << 2, /*!< Pcs2 Active Low (idles high). */
120 kLPSPI_Pcs3ActiveLow = 1U << 3, /*!< Pcs3 Active Low (idles high). */
121 kLPSPI_PcsAllActiveLow = 0xFU /*!< Pcs0 to Pcs5 Active Low (idles high). */
122 };
123
124 /*! @brief LPSPI clock polarity configuration.*/
125 typedef enum _lpspi_clock_polarity
126 {
127 kLPSPI_ClockPolarityActiveHigh = 0U, /*!< CPOL=0. Active-high LPSPI clock (idles low)*/
128 kLPSPI_ClockPolarityActiveLow = 1U /*!< CPOL=1. Active-low LPSPI clock (idles high)*/
129 } lpspi_clock_polarity_t;
130
131 /*! @brief LPSPI clock phase configuration.*/
132 typedef enum _lpspi_clock_phase
133 {
134 kLPSPI_ClockPhaseFirstEdge = 0U, /*!< CPHA=0. Data is captured on the leading edge of the SCK and changed on the
135 following edge.*/
136 kLPSPI_ClockPhaseSecondEdge = 1U /*!< CPHA=1. Data is changed on the leading edge of the SCK and captured on the
137 following edge.*/
138 } lpspi_clock_phase_t;
139
140 /*! @brief LPSPI data shifter direction options.*/
141 typedef enum _lpspi_shift_direction
142 {
143 kLPSPI_MsbFirst = 0U, /*!< Data transfers start with most significant bit.*/
144 kLPSPI_LsbFirst = 1U /*!< Data transfers start with least significant bit.*/
145 } lpspi_shift_direction_t;
146
147 /*! @brief LPSPI Host Request select configuration. */
148 typedef enum _lpspi_host_request_select
149 {
150 kLPSPI_HostReqExtPin = 0U, /*!< Host Request is an ext pin. */
151 kLPSPI_HostReqInternalTrigger = 1U /*!< Host Request is an internal trigger. */
152 } lpspi_host_request_select_t;
153
154 /*! @brief LPSPI Match configuration options. */
155 typedef enum _lpspi_match_config
156 {
157 kLPSI_MatchDisabled = 0x0U, /*!< LPSPI Match Disabled. */
158 kLPSI_1stWordEqualsM0orM1 = 0x2U, /*!< LPSPI Match Enabled. */
159 kLPSI_AnyWordEqualsM0orM1 = 0x3U, /*!< LPSPI Match Enabled. */
160 kLPSI_1stWordEqualsM0and2ndWordEqualsM1 = 0x4U, /*!< LPSPI Match Enabled. */
161 kLPSI_AnyWordEqualsM0andNxtWordEqualsM1 = 0x5U, /*!< LPSPI Match Enabled. */
162 kLPSI_1stWordAndM1EqualsM0andM1 = 0x6U, /*!< LPSPI Match Enabled. */
163 kLPSI_AnyWordAndM1EqualsM0andM1 = 0x7U, /*!< LPSPI Match Enabled. */
164 } lpspi_match_config_t;
165
166 /*! @brief LPSPI pin (SDO and SDI) configuration. */
167 typedef enum _lpspi_pin_config
168 {
169 kLPSPI_SdiInSdoOut = 0U, /*!< LPSPI SDI input, SDO output. */
170 kLPSPI_SdiInSdiOut = 1U, /*!< LPSPI SDI input, SDI output. */
171 kLPSPI_SdoInSdoOut = 2U, /*!< LPSPI SDO input, SDO output. */
172 kLPSPI_SdoInSdiOut = 3U /*!< LPSPI SDO input, SDI output. */
173 } lpspi_pin_config_t;
174
175 /*! @brief LPSPI data output configuration. */
176 typedef enum _lpspi_data_out_config
177 {
178 kLpspiDataOutRetained = 0U, /*!< Data out retains last value when chip select is de-asserted */
179 kLpspiDataOutTristate = 1U /*!< Data out is tristated when chip select is de-asserted */
180 } lpspi_data_out_config_t;
181
182 /*! @brief LPSPI transfer width configuration. */
183 typedef enum _lpspi_transfer_width
184 {
185 kLPSPI_SingleBitXfer = 0U, /*!< 1-bit shift at a time, data out on SDO, in on SDI (normal mode) */
186 kLPSPI_TwoBitXfer = 1U, /*!< 2-bits shift out on SDO/SDI and in on SDO/SDI */
187 kLPSPI_FourBitXfer = 2U /*!< 4-bits shift out on SDO/SDI/PCS[3:2] and in on SDO/SDI/PCS[3:2] */
188 } lpspi_transfer_width_t;
189
190 /*! @brief LPSPI delay type selection.*/
191 typedef enum _lpspi_delay_type
192 {
193 kLPSPI_PcsToSck = 1U, /*!< PCS-to-SCK delay. */
194 kLPSPI_LastSckToPcs, /*!< Last SCK edge to PCS delay. */
195 kLPSPI_BetweenTransfer /*!< Delay between transfers. */
196 } lpspi_delay_type_t;
197
198 #define LPSPI_MASTER_PCS_SHIFT (4U) /*!< LPSPI master PCS shift macro , internal used. */
199 #define LPSPI_MASTER_PCS_MASK (0xF0U) /*!< LPSPI master PCS shift macro , internal used. */
200
201 /*! @brief Use this enumeration for LPSPI master transfer configFlags. */
202 enum _lpspi_transfer_config_flag_for_master
203 {
204 kLPSPI_MasterPcs0 = 0U << LPSPI_MASTER_PCS_SHIFT, /*!< LPSPI master transfer use PCS0 signal */
205 kLPSPI_MasterPcs1 = 1U << LPSPI_MASTER_PCS_SHIFT, /*!< LPSPI master transfer use PCS1 signal */
206 kLPSPI_MasterPcs2 = 2U << LPSPI_MASTER_PCS_SHIFT, /*!< LPSPI master transfer use PCS2 signal */
207 kLPSPI_MasterPcs3 = 3U << LPSPI_MASTER_PCS_SHIFT, /*!< LPSPI master transfer use PCS3 signal */
208
209 kLPSPI_MasterPcsContinuous = 1U << 20, /*!< Is PCS signal continuous */
210
211 kLPSPI_MasterByteSwap =
212 1U << 22 /*!< Is master swap the byte.
213 * For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set
214 * lpspi_shift_direction_t to MSB).
215 * 1. If you set bitPerFrame = 8 , no matter the kLPSPI_MasterByteSwapyou flag is used
216 * or not, the waveform is 1 2 3 4 5 6 7 8.
217 * 2. If you set bitPerFrame = 16 :
218 * (1) the waveform is 2 1 4 3 6 5 8 7 if you do not use the kLPSPI_MasterByteSwap flag.
219 * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_MasterByteSwap flag.
220 * 3. If you set bitPerFrame = 32 :
221 * (1) the waveform is 4 3 2 1 8 7 6 5 if you do not use the kLPSPI_MasterByteSwap flag.
222 * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_MasterByteSwap flag.
223 */
224 };
225
226 #define LPSPI_SLAVE_PCS_SHIFT (4U) /*!< LPSPI slave PCS shift macro , internal used. */
227 #define LPSPI_SLAVE_PCS_MASK (0xF0U) /*!< LPSPI slave PCS shift macro , internal used. */
228
229 /*! @brief Use this enumeration for LPSPI slave transfer configFlags. */
230 enum _lpspi_transfer_config_flag_for_slave
231 {
232 kLPSPI_SlavePcs0 = 0U << LPSPI_SLAVE_PCS_SHIFT, /*!< LPSPI slave transfer use PCS0 signal */
233 kLPSPI_SlavePcs1 = 1U << LPSPI_SLAVE_PCS_SHIFT, /*!< LPSPI slave transfer use PCS1 signal */
234 kLPSPI_SlavePcs2 = 2U << LPSPI_SLAVE_PCS_SHIFT, /*!< LPSPI slave transfer use PCS2 signal */
235 kLPSPI_SlavePcs3 = 3U << LPSPI_SLAVE_PCS_SHIFT, /*!< LPSPI slave transfer use PCS3 signal */
236
237 kLPSPI_SlaveByteSwap =
238 1U << 22 /*!< Is slave swap the byte.
239 * For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set
240 * lpspi_shift_direction_t to MSB).
241 * 1. If you set bitPerFrame = 8 , no matter the kLPSPI_SlaveByteSwap flag is used
242 * or not, the waveform is 1 2 3 4 5 6 7 8.
243 * 2. If you set bitPerFrame = 16 :
244 * (1) the waveform is 2 1 4 3 6 5 8 7 if you do not use the kLPSPI_SlaveByteSwap flag.
245 * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_SlaveByteSwap flag.
246 * 3. If you set bitPerFrame = 32 :
247 * (1) the waveform is 4 3 2 1 8 7 6 5 if you do not use the kLPSPI_SlaveByteSwap flag.
248 * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_SlaveByteSwap flag.
249 */
250 };
251
252 /*! @brief LPSPI transfer state, which is used for LPSPI transactional API state machine. */
253 enum _lpspi_transfer_state
254 {
255 kLPSPI_Idle = 0x0U, /*!< Nothing in the transmitter/receiver. */
256 kLPSPI_Busy, /*!< Transfer queue is not finished. */
257 kLPSPI_Error /*!< Transfer error. */
258 };
259
260 /*! @brief LPSPI master configuration structure.*/
261 typedef struct _lpspi_master_config
262 {
263 uint32_t baudRate; /*!< Baud Rate for LPSPI. */
264 uint32_t bitsPerFrame; /*!< Bits per frame, minimum 8, maximum 4096.*/
265 lpspi_clock_polarity_t cpol; /*!< Clock polarity. */
266 lpspi_clock_phase_t cpha; /*!< Clock phase. */
267 lpspi_shift_direction_t direction; /*!< MSB or LSB data shift direction. */
268
269 uint32_t pcsToSckDelayInNanoSec; /*!< PCS to SCK delay time in nanoseconds, setting to 0 sets the minimum delay.
270 It sets the boundary value if out of range.*/
271 uint32_t lastSckToPcsDelayInNanoSec; /*!< Last SCK to PCS delay time in nanoseconds, setting to 0 sets the minimum
272 delay. It sets the boundary value if out of range.*/
273 uint32_t betweenTransferDelayInNanoSec; /*!< After the SCK delay time with nanoseconds, setting to 0 sets the
274 minimum delay. It sets the boundary value if out of range.*/
275
276 lpspi_which_pcs_t whichPcs; /*!< Desired Peripheral Chip Select (PCS). */
277 lpspi_pcs_polarity_config_t pcsActiveHighOrLow; /*!< Desired PCS active high or low */
278
279 lpspi_pin_config_t pinCfg; /*!< Configures which pins are used for input and output data
280 *during single bit transfers.*/
281
282 lpspi_data_out_config_t dataOutConfig; /*!< Configures if the output data is tristated
283 * between accesses (LPSPI_PCS is negated). */
284 bool enableInputDelay; /*!< Enable master to sample the input data on a delayed SCK. This can help improve slave
285 setup time. Refer to device data sheet for specific time length. */
286 } lpspi_master_config_t;
287
288 /*! @brief LPSPI slave configuration structure.*/
289 typedef struct _lpspi_slave_config
290 {
291 uint32_t bitsPerFrame; /*!< Bits per frame, minimum 8, maximum 4096.*/
292 lpspi_clock_polarity_t cpol; /*!< Clock polarity. */
293 lpspi_clock_phase_t cpha; /*!< Clock phase. */
294 lpspi_shift_direction_t direction; /*!< MSB or LSB data shift direction. */
295
296 lpspi_which_pcs_t whichPcs; /*!< Desired Peripheral Chip Select (pcs) */
297 lpspi_pcs_polarity_config_t pcsActiveHighOrLow; /*!< Desired PCS active high or low */
298
299 lpspi_pin_config_t pinCfg; /*!< Configures which pins are used for input and output data
300 *during single bit transfers.*/
301
302 lpspi_data_out_config_t dataOutConfig; /*!< Configures if the output data is tristated
303 * between accesses (LPSPI_PCS is negated). */
304 } lpspi_slave_config_t;
305
306 /*!
307 * @brief Forward declaration of the _lpspi_master_handle typedefs.
308 */
309 typedef struct _lpspi_master_handle lpspi_master_handle_t;
310
311 /*!
312 * @brief Forward declaration of the _lpspi_slave_handle typedefs.
313 */
314 typedef struct _lpspi_slave_handle lpspi_slave_handle_t;
315
316 /*!
317 * @brief Master completion callback function pointer type.
318 *
319 * @param base LPSPI peripheral address.
320 * @param handle Pointer to the handle for the LPSPI master.
321 * @param status Success or error code describing whether the transfer is completed.
322 * @param userData Arbitrary pointer-dataSized value passed from the application.
323 */
324 typedef void (*lpspi_master_transfer_callback_t)(LPSPI_Type *base,
325 lpspi_master_handle_t *handle,
326 status_t status,
327 void *userData);
328
329 /*!
330 * @brief Slave completion callback function pointer type.
331 *
332 * @param base LPSPI peripheral address.
333 * @param handle Pointer to the handle for the LPSPI slave.
334 * @param status Success or error code describing whether the transfer is completed.
335 * @param userData Arbitrary pointer-dataSized value passed from the application.
336 */
337 typedef void (*lpspi_slave_transfer_callback_t)(LPSPI_Type *base,
338 lpspi_slave_handle_t *handle,
339 status_t status,
340 void *userData);
341
342 /*! @brief LPSPI master/slave transfer structure.*/
343 typedef struct _lpspi_transfer
344 {
345 uint8_t *txData; /*!< Send buffer. */
346 uint8_t *rxData; /*!< Receive buffer. */
347 volatile size_t dataSize; /*!< Transfer bytes. */
348
349 uint32_t configFlags; /*!< Transfer transfer configuration flags. Set from _lpspi_transfer_config_flag_for_master if
350 the transfer is used for master or _lpspi_transfer_config_flag_for_slave enumeration if the
351 transfer is used for slave.*/
352 } lpspi_transfer_t;
353
354 /*! @brief LPSPI master transfer handle structure used for transactional API. */
355 struct _lpspi_master_handle
356 {
357 volatile bool isPcsContinuous; /*!< Is PCS continuous in transfer. */
358 volatile bool writeTcrInIsr; /*!< A flag that whether should write TCR in ISR. */
359
360 volatile bool isByteSwap; /*!< A flag that whether should byte swap. */
361 volatile bool isTxMask; /*!< A flag that whether TCR[TXMSK] is set. */
362 volatile uint16_t bytesPerFrame; /*!< Number of bytes in each frame */
363
364 volatile uint8_t fifoSize; /*!< FIFO dataSize. */
365
366 volatile uint8_t rxWatermark; /*!< Rx watermark. */
367
368 volatile uint8_t bytesEachWrite; /*!< Bytes for each write TDR. */
369 volatile uint8_t bytesEachRead; /*!< Bytes for each read RDR. */
370
371 uint8_t *volatile txData; /*!< Send buffer. */
372 uint8_t *volatile rxData; /*!< Receive buffer. */
373 volatile size_t txRemainingByteCount; /*!< Number of bytes remaining to send.*/
374 volatile size_t rxRemainingByteCount; /*!< Number of bytes remaining to receive.*/
375
376 volatile uint32_t writeRegRemainingTimes; /*!< Write TDR register remaining times. */
377 volatile uint32_t readRegRemainingTimes; /*!< Read RDR register remaining times. */
378
379 uint32_t totalByteCount; /*!< Number of transfer bytes*/
380
381 uint32_t txBuffIfNull; /*!< Used if the txData is NULL. */
382
383 volatile uint8_t state; /*!< LPSPI transfer state , _lpspi_transfer_state.*/
384
385 lpspi_master_transfer_callback_t callback; /*!< Completion callback. */
386 void *userData; /*!< Callback user data. */
387 };
388
389 /*! @brief LPSPI slave transfer handle structure used for transactional API. */
390 struct _lpspi_slave_handle
391 {
392 volatile bool isByteSwap; /*!< A flag that whether should byte swap. */
393
394 volatile uint8_t fifoSize; /*!< FIFO dataSize. */
395
396 volatile uint8_t rxWatermark; /*!< Rx watermark. */
397
398 volatile uint8_t bytesEachWrite; /*!< Bytes for each write TDR. */
399 volatile uint8_t bytesEachRead; /*!< Bytes for each read RDR. */
400
401 uint8_t *volatile txData; /*!< Send buffer. */
402 uint8_t *volatile rxData; /*!< Receive buffer. */
403
404 volatile size_t txRemainingByteCount; /*!< Number of bytes remaining to send.*/
405 volatile size_t rxRemainingByteCount; /*!< Number of bytes remaining to receive.*/
406
407 volatile uint32_t writeRegRemainingTimes; /*!< Write TDR register remaining times. */
408 volatile uint32_t readRegRemainingTimes; /*!< Read RDR register remaining times. */
409
410 uint32_t totalByteCount; /*!< Number of transfer bytes*/
411
412 volatile uint8_t state; /*!< LPSPI transfer state , _lpspi_transfer_state.*/
413
414 volatile uint32_t errorCount; /*!< Error count for slave transfer.*/
415
416 lpspi_slave_transfer_callback_t callback; /*!< Completion callback. */
417 void *userData; /*!< Callback user data. */
418 };
419
420 /**********************************************************************************************************************
421 * API
422 *********************************************************************************************************************/
423 #if defined(__cplusplus)
424 extern "C" {
425 #endif /*_cplusplus*/
426
427 /*!
428 * @name Initialization and deinitialization
429 * @{
430 */
431
432 /*!
433 * @brief Initializes the LPSPI master.
434 *
435 * @param base LPSPI peripheral address.
436 * @param masterConfig Pointer to structure lpspi_master_config_t.
437 * @param srcClock_Hz Module source input clock in Hertz
438 */
439 void LPSPI_MasterInit(LPSPI_Type *base, const lpspi_master_config_t *masterConfig, uint32_t srcClock_Hz);
440
441 /*!
442 * @brief Sets the lpspi_master_config_t structure to default values.
443 *
444 * This API initializes the configuration structure for LPSPI_MasterInit().
445 * The initialized structure can remain unchanged in LPSPI_MasterInit(), or can be modified
446 * before calling the LPSPI_MasterInit().
447 * Example:
448 * @code
449 * lpspi_master_config_t masterConfig;
450 * LPSPI_MasterGetDefaultConfig(&masterConfig);
451 * @endcode
452 * @param masterConfig pointer to lpspi_master_config_t structure
453 */
454 void LPSPI_MasterGetDefaultConfig(lpspi_master_config_t *masterConfig);
455
456 /*!
457 * @brief LPSPI slave configuration.
458 *
459 * @param base LPSPI peripheral address.
460 * @param slaveConfig Pointer to a structure lpspi_slave_config_t.
461 */
462 void LPSPI_SlaveInit(LPSPI_Type *base, const lpspi_slave_config_t *slaveConfig);
463
464 /*!
465 * @brief Sets the lpspi_slave_config_t structure to default values.
466 *
467 * This API initializes the configuration structure for LPSPI_SlaveInit().
468 * The initialized structure can remain unchanged in LPSPI_SlaveInit() or can be modified
469 * before calling the LPSPI_SlaveInit().
470 * Example:
471 * @code
472 * lpspi_slave_config_t slaveConfig;
473 * LPSPI_SlaveGetDefaultConfig(&slaveConfig);
474 * @endcode
475 * @param slaveConfig pointer to lpspi_slave_config_t structure.
476 */
477 void LPSPI_SlaveGetDefaultConfig(lpspi_slave_config_t *slaveConfig);
478
479 /*!
480 * @brief De-initializes the LPSPI peripheral. Call this API to disable the LPSPI clock.
481 * @param base LPSPI peripheral address.
482 */
483 void LPSPI_Deinit(LPSPI_Type *base);
484
485 /*!
486 * @brief Restores the LPSPI peripheral to reset state. Note that this function
487 * sets all registers to reset state. As a result, the LPSPI module can't work after calling
488 * this API.
489 * @param base LPSPI peripheral address.
490 */
491 void LPSPI_Reset(LPSPI_Type *base);
492
493 /*!
494 * @brief Get the LPSPI instance from peripheral base address.
495 *
496 * @param base LPSPI peripheral base address.
497 * @return LPSPI instance.
498 */
499 uint32_t LPSPI_GetInstance(LPSPI_Type *base);
500
501 /*!
502 * @brief Enables the LPSPI peripheral and sets the MCR MDIS to 0.
503 *
504 * @param base LPSPI peripheral address.
505 * @param enable Pass true to enable module, false to disable module.
506 */
LPSPI_Enable(LPSPI_Type * base,bool enable)507 static inline void LPSPI_Enable(LPSPI_Type *base, bool enable)
508 {
509 if (enable)
510 {
511 base->CR |= LPSPI_CR_MEN_MASK;
512 }
513 else
514 {
515 base->CR &= ~LPSPI_CR_MEN_MASK;
516 }
517 #if defined(FSL_FEATURE_LPSPI_HAS_ERRATA_051472) && FSL_FEATURE_LPSPI_HAS_ERRATA_051472
518 /* ERRATA051472: The SR[REF] would assert if software disables the LPSPI module
519 after receiving some data and then enabled the LPSPI again without performing a software reset.
520 Clear SR[REF] flag after LPSPI module enabled*/
521 if ((base->SR & (uint32_t)kLPSPI_ReceiveErrorFlag) != 0U)
522 {
523 base->SR = (uint32_t)kLPSPI_ReceiveErrorFlag;
524 }
525 #endif
526 }
527
528 /*!
529 *@}
530 */
531
532 /*!
533 * @name Status
534 * @{
535 */
536
537 /*!
538 * @brief Gets the LPSPI status flag state.
539 * @param base LPSPI peripheral address.
540 * @return The LPSPI status(in SR register).
541 */
LPSPI_GetStatusFlags(LPSPI_Type * base)542 static inline uint32_t LPSPI_GetStatusFlags(LPSPI_Type *base)
543 {
544 return (base->SR);
545 }
546
547 /*!
548 * @brief Gets the LPSPI Tx FIFO size.
549 * @param base LPSPI peripheral address.
550 * @return The LPSPI Tx FIFO size.
551 */
LPSPI_GetTxFifoSize(LPSPI_Type * base)552 static inline uint8_t LPSPI_GetTxFifoSize(LPSPI_Type *base)
553 {
554 return (1U << ((base->PARAM & LPSPI_PARAM_TXFIFO_MASK) >> LPSPI_PARAM_TXFIFO_SHIFT));
555 }
556
557 /*!
558 * @brief Gets the LPSPI Rx FIFO size.
559 * @param base LPSPI peripheral address.
560 * @return The LPSPI Rx FIFO size.
561 */
LPSPI_GetRxFifoSize(LPSPI_Type * base)562 static inline uint8_t LPSPI_GetRxFifoSize(LPSPI_Type *base)
563 {
564 return (1U << ((base->PARAM & LPSPI_PARAM_RXFIFO_MASK) >> LPSPI_PARAM_RXFIFO_SHIFT));
565 }
566
567 /*!
568 * @brief Gets the LPSPI Tx FIFO count.
569 * @param base LPSPI peripheral address.
570 * @return The number of words in the transmit FIFO.
571 */
LPSPI_GetTxFifoCount(LPSPI_Type * base)572 static inline uint32_t LPSPI_GetTxFifoCount(LPSPI_Type *base)
573 {
574 return ((base->FSR & LPSPI_FSR_TXCOUNT_MASK) >> LPSPI_FSR_TXCOUNT_SHIFT);
575 }
576
577 /*!
578 * @brief Gets the LPSPI Rx FIFO count.
579 * @param base LPSPI peripheral address.
580 * @return The number of words in the receive FIFO.
581 */
LPSPI_GetRxFifoCount(LPSPI_Type * base)582 static inline uint32_t LPSPI_GetRxFifoCount(LPSPI_Type *base)
583 {
584 return ((base->FSR & LPSPI_FSR_RXCOUNT_MASK) >> LPSPI_FSR_RXCOUNT_SHIFT);
585 }
586
587 /*!
588 * @brief Clears the LPSPI status flag.
589 *
590 * This function clears the desired status bit by using a write-1-to-clear. The user passes in the base and the
591 * desired status flag bit to clear. The list of status flags is defined in the _lpspi_flags.
592 * Example usage:
593 * @code
594 * LPSPI_ClearStatusFlags(base, kLPSPI_TxDataRequestFlag|kLPSPI_RxDataReadyFlag);
595 * @endcode
596 *
597 * @param base LPSPI peripheral address.
598 * @param statusFlags The status flag used from type _lpspi_flags.
599 */
LPSPI_ClearStatusFlags(LPSPI_Type * base,uint32_t statusFlags)600 static inline void LPSPI_ClearStatusFlags(LPSPI_Type *base, uint32_t statusFlags)
601 {
602 base->SR = statusFlags; /*!< The status flags are cleared by writing 1 (w1c).*/
603 }
604
605 /*!
606 *@}
607 */
608
609 /*!
610 * @name Interrupts
611 * @{
612 */
613
614 /*!
615 * @brief Enables the LPSPI interrupts.
616 *
617 * This function configures the various interrupt masks of the LPSPI. The parameters are base and an interrupt mask.
618 * Note that, for Tx fill and Rx FIFO drain requests, enabling the interrupt request disables the DMA request.
619 *
620 * @code
621 * LPSPI_EnableInterrupts(base, kLPSPI_TxInterruptEnable | kLPSPI_RxInterruptEnable );
622 * @endcode
623 *
624 * @param base LPSPI peripheral address.
625 * @param mask The interrupt mask; Use the enum _lpspi_interrupt_enable.
626 */
LPSPI_EnableInterrupts(LPSPI_Type * base,uint32_t mask)627 static inline void LPSPI_EnableInterrupts(LPSPI_Type *base, uint32_t mask)
628 {
629 base->IER |= mask;
630 }
631
632 /*!
633 * @brief Disables the LPSPI interrupts.
634 *
635 * @code
636 * LPSPI_DisableInterrupts(base, kLPSPI_TxInterruptEnable | kLPSPI_RxInterruptEnable );
637 * @endcode
638 *
639 * @param base LPSPI peripheral address.
640 * @param mask The interrupt mask; Use the enum _lpspi_interrupt_enable.
641 */
LPSPI_DisableInterrupts(LPSPI_Type * base,uint32_t mask)642 static inline void LPSPI_DisableInterrupts(LPSPI_Type *base, uint32_t mask)
643 {
644 base->IER &= ~mask;
645 }
646
647 /*!
648 *@}
649 */
650
651 /*!
652 * @name DMA Control
653 * @{
654 */
655
656 /*!
657 * @brief Enables the LPSPI DMA request.
658 *
659 * This function configures the Rx and Tx DMA mask of the LPSPI. The parameters are base and a DMA mask.
660 * @code
661 * LPSPI_EnableDMA(base, kLPSPI_TxDmaEnable | kLPSPI_RxDmaEnable);
662 * @endcode
663 *
664 * @param base LPSPI peripheral address.
665 * @param mask The interrupt mask; Use the enum _lpspi_dma_enable.
666 */
LPSPI_EnableDMA(LPSPI_Type * base,uint32_t mask)667 static inline void LPSPI_EnableDMA(LPSPI_Type *base, uint32_t mask)
668 {
669 base->DER |= mask;
670 }
671
672 /*!
673 * @brief Disables the LPSPI DMA request.
674 *
675 * This function configures the Rx and Tx DMA mask of the LPSPI. The parameters are base and a DMA mask.
676 * @code
677 * SPI_DisableDMA(base, kLPSPI_TxDmaEnable | kLPSPI_RxDmaEnable);
678 * @endcode
679 *
680 * @param base LPSPI peripheral address.
681 * @param mask The interrupt mask; Use the enum _lpspi_dma_enable.
682 */
LPSPI_DisableDMA(LPSPI_Type * base,uint32_t mask)683 static inline void LPSPI_DisableDMA(LPSPI_Type *base, uint32_t mask)
684 {
685 base->DER &= ~mask;
686 }
687
688 /*!
689 * @brief Gets the LPSPI Transmit Data Register address for a DMA operation.
690 *
691 * This function gets the LPSPI Transmit Data Register address because this value is needed
692 * for the DMA operation.
693 * This function can be used for either master or slave mode.
694 *
695 * @param base LPSPI peripheral address.
696 * @return The LPSPI Transmit Data Register address.
697 */
LPSPI_GetTxRegisterAddress(LPSPI_Type * base)698 static inline uint32_t LPSPI_GetTxRegisterAddress(LPSPI_Type *base)
699 {
700 return (uint32_t) & (base->TDR);
701 }
702
703 /*!
704 * @brief Gets the LPSPI Receive Data Register address for a DMA operation.
705 *
706 * This function gets the LPSPI Receive Data Register address because this value is needed
707 * for the DMA operation.
708 * This function can be used for either master or slave mode.
709 *
710 * @param base LPSPI peripheral address.
711 * @return The LPSPI Receive Data Register address.
712 */
LPSPI_GetRxRegisterAddress(LPSPI_Type * base)713 static inline uint32_t LPSPI_GetRxRegisterAddress(LPSPI_Type *base)
714 {
715 return (uint32_t) & (base->RDR);
716 }
717
718 /*!
719 *@}
720 */
721
722 /*!
723 * @name Bus Operations
724 * @{
725 */
726
727 /*!
728 * @brief Check the argument for transfer .
729 *
730 * @param base LPSPI peripheral address.
731 * @param transfer the transfer struct to be used.
732 * @param isEdma True to check for EDMA transfer, false to check interrupt non-blocking transfer
733 * @return Return true for right and false for wrong.
734 */
735 bool LPSPI_CheckTransferArgument(LPSPI_Type *base, lpspi_transfer_t *transfer, bool isEdma);
736
737 /*!
738 * @brief Configures the LPSPI for either master or slave.
739 *
740 * Note that the CFGR1 should only be written when the LPSPI is disabled (LPSPIx_CR_MEN = 0).
741 *
742 * @param base LPSPI peripheral address.
743 * @param mode Mode setting (master or slave) of type lpspi_master_slave_mode_t.
744 */
LPSPI_SetMasterSlaveMode(LPSPI_Type * base,lpspi_master_slave_mode_t mode)745 static inline void LPSPI_SetMasterSlaveMode(LPSPI_Type *base, lpspi_master_slave_mode_t mode)
746 {
747 base->CFGR1 = (base->CFGR1 & (~LPSPI_CFGR1_MASTER_MASK)) | LPSPI_CFGR1_MASTER(mode);
748 }
749
750 /*!
751 * @brief Configures the peripheral chip select used for the transfer.
752 *
753 * @param base LPSPI peripheral address.
754 * @param select LPSPI Peripheral Chip Select (PCS) configuration.
755 */
LPSPI_SelectTransferPCS(LPSPI_Type * base,lpspi_which_pcs_t select)756 static inline void LPSPI_SelectTransferPCS(LPSPI_Type *base, lpspi_which_pcs_t select)
757 {
758 base->TCR = (base->TCR & (~LPSPI_TCR_PCS_MASK)) | LPSPI_TCR_PCS((uint8_t)select);
759 }
760
761 /*!
762 * @brief Set the PCS signal to continuous or uncontinuous mode.
763 *
764 * @note In master mode, continuous transfer will keep the PCS asserted at the end of the frame size, until a command
765 * word is received that starts a new frame. So PCS must be set back to uncontinuous when transfer finishes.
766 * In slave mode, when continuous transfer is enabled, the LPSPI will only transmit the first frame size bits, after
767 * that the LPSPI will transmit received data back (assuming a 32-bit shift register).
768 *
769 * @param base LPSPI peripheral address.
770 * @param IsContinous True to set the transfer PCS to continuous mode, false to set to uncontinuous mode.
771 */
LPSPI_SetPCSContinous(LPSPI_Type * base,bool IsContinous)772 static inline void LPSPI_SetPCSContinous(LPSPI_Type *base, bool IsContinous)
773 {
774 if (IsContinous)
775 {
776 base->TCR |= LPSPI_TCR_CONT_MASK;
777 }
778 else
779 {
780 base->TCR &= ~LPSPI_TCR_CONT_MASK;
781 }
782 }
783
784 /*!
785 * @brief Returns whether the LPSPI module is in master mode.
786 *
787 * @param base LPSPI peripheral address.
788 * @return Returns true if the module is in master mode or false if the module is in slave mode.
789 */
LPSPI_IsMaster(LPSPI_Type * base)790 static inline bool LPSPI_IsMaster(LPSPI_Type *base)
791 {
792 return (bool)((base->CFGR1) & LPSPI_CFGR1_MASTER_MASK);
793 }
794
795 /*!
796 * @brief Flushes the LPSPI FIFOs.
797 *
798 * @param base LPSPI peripheral address.
799 * @param flushTxFifo Flushes (true) the Tx FIFO, else do not flush (false) the Tx FIFO.
800 * @param flushRxFifo Flushes (true) the Rx FIFO, else do not flush (false) the Rx FIFO.
801 */
LPSPI_FlushFifo(LPSPI_Type * base,bool flushTxFifo,bool flushRxFifo)802 static inline void LPSPI_FlushFifo(LPSPI_Type *base, bool flushTxFifo, bool flushRxFifo)
803 {
804 #if defined(FSL_FEATURE_LPSPI_HAS_ERRATA_050456) && FSL_FEATURE_LPSPI_HAS_ERRATA_050456
805 /*
806 * Resetting the FIFO using CR[RTF] and CR[RRF] does not clear the FIFO pointers completely.
807 * Workaround by reseting the entire module using CR[RST] bit.
808 */
809
810 (void)flushTxFifo;
811 (void)flushRxFifo;
812
813 /* Save current state before resetting */
814 bool enabled = base->CR & LPSPI_CR_MEN_MASK;
815 uint32_t cfgr1 = base->CFGR1;
816 uint32_t ccr = base->CCR;
817 uint32_t ccr1 = base->CCR1;
818
819 /* To read the current state of the existing command word, LPSPI must be enabled */
820 LPSPI_Enable(base, true);
821 uint32_t tcr = base->TCR;
822
823 /* Reset all internal logic and registers. Bit remains set until cleared by software */
824 LPSPI_Enable(base, false);
825 base->CR |= LPSPI_CR_RST_MASK;
826 base->CR &= ~LPSPI_CR_RST_MASK;
827
828 /* Restore saved registers */
829 base->CFGR1 = cfgr1;
830 base->CCR = ccr;
831 base->CCR1 = ccr1;
832 base->TCR = tcr;
833
834 LPSPI_Enable(base, enabled);
835 #else
836 base->CR |= ((uint32_t)flushTxFifo << LPSPI_CR_RTF_SHIFT) | ((uint32_t)flushRxFifo << LPSPI_CR_RRF_SHIFT);
837 #endif
838 }
839
840 /*!
841 * @brief Sets the transmit and receive FIFO watermark values.
842 *
843 * This function allows the user to set the receive and transmit FIFO watermarks. The function
844 * does not compare the watermark settings to the FIFO size. The FIFO watermark should not be
845 * equal to or greater than the FIFO size. It is up to the higher level driver to make this check.
846 *
847 * @param base LPSPI peripheral address.
848 * @param txWater The TX FIFO watermark value. Writing a value equal or greater than the FIFO size is truncated.
849 * @param rxWater The RX FIFO watermark value. Writing a value equal or greater than the FIFO size is truncated.
850 */
LPSPI_SetFifoWatermarks(LPSPI_Type * base,uint32_t txWater,uint32_t rxWater)851 static inline void LPSPI_SetFifoWatermarks(LPSPI_Type *base, uint32_t txWater, uint32_t rxWater)
852 {
853 base->FCR = LPSPI_FCR_TXWATER(txWater) | LPSPI_FCR_RXWATER(rxWater);
854 }
855
856 /*!
857 * @brief Configures all LPSPI peripheral chip select polarities simultaneously.
858 *
859 * Note that the CFGR1 should only be written when the LPSPI is disabled (LPSPIx_CR_MEN = 0).
860 *
861 * This is an example: PCS0 and PCS1 set to active low and other PCSs set to active high. Note that the number of
862 * PCS is device-specific.
863 * @code
864 * LPSPI_SetAllPcsPolarity(base, kLPSPI_Pcs0ActiveLow | kLPSPI_Pcs1ActiveLow);
865 * @endcode
866 *
867 * @param base LPSPI peripheral address.
868 * @param mask The PCS polarity mask; Use the enum _lpspi_pcs_polarity.
869 */
LPSPI_SetAllPcsPolarity(LPSPI_Type * base,uint32_t mask)870 static inline void LPSPI_SetAllPcsPolarity(LPSPI_Type *base, uint32_t mask)
871 {
872 base->CFGR1 = (base->CFGR1 & ~LPSPI_CFGR1_PCSPOL_MASK) | LPSPI_CFGR1_PCSPOL(~mask);
873 }
874
875 /*!
876 * @brief Configures the frame size.
877 *
878 * The minimum frame size is 8-bits and the maximum frame size is 4096-bits. If the frame size is less than or equal
879 * to 32-bits, the word size and frame size are identical. If the frame size is greater than 32-bits, the word
880 * size is 32-bits for each word except the last (the last word contains the remainder bits if the frame size is not
881 * divisible by 32). The minimum word size is 2-bits. A frame size of 33-bits (or similar) is not supported.
882 *
883 * Note 1: The transmit command register should be initialized before enabling the LPSPI in slave mode, although
884 * the command register does not update until after the LPSPI is enabled. After it is enabled, the transmit command
885 * register
886 * should only be changed if the LPSPI is idle.
887 *
888 * Note 2: The transmit and command FIFO is a combined FIFO that includes both transmit data and command words. That
889 * means the TCR register should be written to when the Tx FIFO is not full.
890 *
891 * @param base LPSPI peripheral address.
892 * @param frameSize The frame size in number of bits.
893 */
LPSPI_SetFrameSize(LPSPI_Type * base,uint32_t frameSize)894 static inline void LPSPI_SetFrameSize(LPSPI_Type *base, uint32_t frameSize)
895 {
896 base->TCR = (base->TCR & ~LPSPI_TCR_FRAMESZ_MASK) | LPSPI_TCR_FRAMESZ(frameSize - 1U);
897 }
898
899 /*!
900 * @brief Sets the LPSPI baud rate in bits per second.
901 *
902 * This function takes in the desired bitsPerSec (baud rate) and calculates the nearest
903 * possible baud rate without exceeding the desired baud rate and returns the
904 * calculated baud rate in bits-per-second. It requires the caller to provide
905 * the frequency of the module source clock (in Hertz). Note that the baud rate
906 * does not go into effect until the Transmit Control Register (TCR) is programmed
907 * with the prescale value. Hence, this function returns the prescale tcrPrescaleValue
908 * parameter for later programming in the TCR. The higher level
909 * peripheral driver should alert the user of an out of range baud rate input.
910 *
911 * Note that the LPSPI module must first be disabled before configuring this.
912 * Note that the LPSPI module must be configured for master mode before configuring this.
913 *
914 * @param base LPSPI peripheral address.
915 * @param baudRate_Bps The desired baud rate in bits per second.
916 * @param srcClock_Hz Module source input clock in Hertz.
917 * @param tcrPrescaleValue The TCR prescale value needed to program the TCR.
918 * @return The actual calculated baud rate. This function may also return a "0" if the
919 * LPSPI is not configured for master mode or if the LPSPI module is not disabled.
920 */
921
922 uint32_t LPSPI_MasterSetBaudRate(LPSPI_Type *base,
923 uint32_t baudRate_Bps,
924 uint32_t srcClock_Hz,
925 uint32_t *tcrPrescaleValue);
926
927 /*!
928 * @brief Manually configures a specific LPSPI delay parameter (module must be disabled to
929 * change the delay values).
930 *
931 * This function configures the following:
932 * SCK to PCS delay, or
933 * PCS to SCK delay, or
934 * The configurations must occur between the transfer delay.
935 *
936 * The delay names are available in type lpspi_delay_type_t.
937 *
938 * The user passes the desired delay along with the delay value.
939 * This allows the user to directly set the delay values if they have
940 * pre-calculated them or if they simply wish to manually increment the value.
941 *
942 * Note that the LPSPI module must first be disabled before configuring this.
943 * Note that the LPSPI module must be configured for master mode before configuring this.
944 *
945 * @param base LPSPI peripheral address.
946 * @param scaler The 8-bit delay value 0x00 to 0xFF (255).
947 * @param whichDelay The desired delay to configure, must be of type lpspi_delay_type_t.
948 */
949 void LPSPI_MasterSetDelayScaler(LPSPI_Type *base, uint32_t scaler, lpspi_delay_type_t whichDelay);
950
951 /*!
952 * @brief Calculates the delay based on the desired delay input in nanoseconds (module must be
953 * disabled to change the delay values).
954 *
955 * This function calculates the values for the following:
956 * SCK to PCS delay, or
957 * PCS to SCK delay, or
958 * The configurations must occur between the transfer delay.
959 *
960 * The delay names are available in type lpspi_delay_type_t.
961 *
962 * The user passes the desired delay and the desired delay value in
963 * nano-seconds. The function calculates the value needed for the desired delay parameter
964 * and returns the actual calculated delay because an exact delay match may not be possible. In this
965 * case, the closest match is calculated without going below the desired delay value input.
966 * It is possible to input a very large delay value that exceeds the capability of the part, in
967 * which case the maximum supported delay is returned. It is up to the higher level
968 * peripheral driver to alert the user of an out of range delay input.
969 *
970 * Note that the LPSPI module must be configured for master mode before configuring this. And note that
971 * the delayTime = LPSPI_clockSource / (PRESCALE * Delay_scaler).
972 *
973 * @param base LPSPI peripheral address.
974 * @param delayTimeInNanoSec The desired delay value in nano-seconds.
975 * @param whichDelay The desired delay to configuration, which must be of type lpspi_delay_type_t.
976 * @param srcClock_Hz Module source input clock in Hertz.
977 * @return actual Calculated delay value in nano-seconds.
978 */
979 uint32_t LPSPI_MasterSetDelayTimes(LPSPI_Type *base,
980 uint32_t delayTimeInNanoSec,
981 lpspi_delay_type_t whichDelay,
982 uint32_t srcClock_Hz);
983
984 /*!
985 * @brief Writes data into the transmit data buffer.
986 *
987 * This function writes data passed in by the user to the Transmit Data Register (TDR).
988 * The user can pass up to 32-bits of data to load into the TDR. If the frame size exceeds 32-bits,
989 * the user has to manage sending the data one 32-bit word at a time.
990 * Any writes to the TDR result in an immediate push to the transmit FIFO.
991 * This function can be used for either master or slave modes.
992 *
993 * @param base LPSPI peripheral address.
994 * @param data The data word to be sent.
995 */
LPSPI_WriteData(LPSPI_Type * base,uint32_t data)996 static inline void LPSPI_WriteData(LPSPI_Type *base, uint32_t data)
997 {
998 base->TDR = data;
999 }
1000
1001 /*!
1002 * @brief Reads data from the data buffer.
1003 *
1004 * This function reads the data from the Receive Data Register (RDR).
1005 * This function can be used for either master or slave mode.
1006 *
1007 * @param base LPSPI peripheral address.
1008 * @return The data read from the data buffer.
1009 */
LPSPI_ReadData(LPSPI_Type * base)1010 static inline uint32_t LPSPI_ReadData(LPSPI_Type *base)
1011 {
1012 return (base->RDR);
1013 }
1014
1015 /*!
1016 * @brief Set up the dummy data.
1017 *
1018 * @param base LPSPI peripheral address.
1019 * @param dummyData Data to be transferred when tx buffer is NULL.
1020 * Note:
1021 * This API has no effect when LPSPI in slave interrupt mode, because driver
1022 * will set the TXMSK bit to 1 if txData is NULL, no data is loaded from transmit
1023 * FIFO and output pin is tristated.
1024 */
1025 void LPSPI_SetDummyData(LPSPI_Type *base, uint8_t dummyData);
1026
1027 /*!
1028 *@}
1029 */
1030
1031 /*!
1032 * @name Transactional
1033 * @{
1034 */
1035 /*Transactional APIs*/
1036
1037 /*!
1038 * @brief Initializes the LPSPI master handle.
1039 *
1040 * This function initializes the LPSPI handle, which can be used for other LPSPI transactional APIs. Usually, for a
1041 * specified LPSPI instance, call this API once to get the initialized handle.
1042
1043 * @param base LPSPI peripheral address.
1044 * @param handle LPSPI handle pointer to lpspi_master_handle_t.
1045 * @param callback DSPI callback.
1046 * @param userData callback function parameter.
1047 */
1048 void LPSPI_MasterTransferCreateHandle(LPSPI_Type *base,
1049 lpspi_master_handle_t *handle,
1050 lpspi_master_transfer_callback_t callback,
1051 void *userData);
1052
1053 /*!
1054 * @brief LPSPI master transfer data using a polling method.
1055 *
1056 * This function transfers data using a polling method. This is a blocking function, which does not return until all
1057 * transfers have been
1058 * completed.
1059 *
1060 * Note:
1061 * The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4.
1062 * For bytesPerFrame greater than 4:
1063 * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not integer multiples of 4.
1064 * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.
1065 *
1066 * @param base LPSPI peripheral address.
1067 * @param transfer pointer to lpspi_transfer_t structure.
1068 * @return status of status_t.
1069 */
1070 status_t LPSPI_MasterTransferBlocking(LPSPI_Type *base, lpspi_transfer_t *transfer);
1071
1072 /*!
1073 * @brief LPSPI master transfer data using an interrupt method.
1074 *
1075 * This function transfers data using an interrupt method. This is a non-blocking function, which returns right away.
1076 * When all data is transferred, the callback function is called.
1077 *
1078 * Note:
1079 * The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4.
1080 * For bytesPerFrame greater than 4:
1081 * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not integer multiples of 4.
1082 * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.
1083 *
1084 * @param base LPSPI peripheral address.
1085 * @param handle pointer to lpspi_master_handle_t structure which stores the transfer state.
1086 * @param transfer pointer to lpspi_transfer_t structure.
1087 * @return status of status_t.
1088 */
1089 status_t LPSPI_MasterTransferNonBlocking(LPSPI_Type *base, lpspi_master_handle_t *handle, lpspi_transfer_t *transfer);
1090
1091 /*!
1092 * @brief Gets the master transfer remaining bytes.
1093 *
1094 * This function gets the master transfer remaining bytes.
1095 *
1096 * @param base LPSPI peripheral address.
1097 * @param handle pointer to lpspi_master_handle_t structure which stores the transfer state.
1098 * @param count Number of bytes transferred so far by the non-blocking transaction.
1099 * @return status of status_t.
1100 */
1101 status_t LPSPI_MasterTransferGetCount(LPSPI_Type *base, lpspi_master_handle_t *handle, size_t *count);
1102
1103 /*!
1104 * @brief LPSPI master abort transfer which uses an interrupt method.
1105 *
1106 * This function aborts a transfer which uses an interrupt method.
1107 *
1108 * @param base LPSPI peripheral address.
1109 * @param handle pointer to lpspi_master_handle_t structure which stores the transfer state.
1110 */
1111 void LPSPI_MasterTransferAbort(LPSPI_Type *base, lpspi_master_handle_t *handle);
1112
1113 /*!
1114 * @brief LPSPI Master IRQ handler function.
1115 *
1116 * This function processes the LPSPI transmit and receive IRQ.
1117 *
1118 * @param base LPSPI peripheral address.
1119 * @param handle pointer to lpspi_master_handle_t structure which stores the transfer state.
1120 */
1121 void LPSPI_MasterTransferHandleIRQ(LPSPI_Type *base, lpspi_master_handle_t *handle);
1122
1123 /*!
1124 * @brief Initializes the LPSPI slave handle.
1125 *
1126 * This function initializes the LPSPI handle, which can be used for other LPSPI transactional APIs. Usually, for a
1127 * specified LPSPI instance, call this API once to get the initialized handle.
1128 *
1129 * @param base LPSPI peripheral address.
1130 * @param handle LPSPI handle pointer to lpspi_slave_handle_t.
1131 * @param callback DSPI callback.
1132 * @param userData callback function parameter.
1133 */
1134 void LPSPI_SlaveTransferCreateHandle(LPSPI_Type *base,
1135 lpspi_slave_handle_t *handle,
1136 lpspi_slave_transfer_callback_t callback,
1137 void *userData);
1138
1139 /*!
1140 * @brief LPSPI slave transfer data using an interrupt method.
1141 *
1142 * This function transfer data using an interrupt method. This is a non-blocking function, which returns right away.
1143 * When all data is transferred, the callback function is called.
1144 *
1145 * Note:
1146 * The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4.
1147 * For bytesPerFrame greater than 4:
1148 * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4.
1149 * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.
1150 *
1151 * @param base LPSPI peripheral address.
1152 * @param handle pointer to lpspi_slave_handle_t structure which stores the transfer state.
1153 * @param transfer pointer to lpspi_transfer_t structure.
1154 * @return status of status_t.
1155 */
1156 status_t LPSPI_SlaveTransferNonBlocking(LPSPI_Type *base, lpspi_slave_handle_t *handle, lpspi_transfer_t *transfer);
1157
1158 /*!
1159 * @brief Gets the slave transfer remaining bytes.
1160 *
1161 * This function gets the slave transfer remaining bytes.
1162 *
1163 * @param base LPSPI peripheral address.
1164 * @param handle pointer to lpspi_slave_handle_t structure which stores the transfer state.
1165 * @param count Number of bytes transferred so far by the non-blocking transaction.
1166 * @return status of status_t.
1167 */
1168 status_t LPSPI_SlaveTransferGetCount(LPSPI_Type *base, lpspi_slave_handle_t *handle, size_t *count);
1169
1170 /*!
1171 * @brief LPSPI slave aborts a transfer which uses an interrupt method.
1172 *
1173 * This function aborts a transfer which uses an interrupt method.
1174 *
1175 * @param base LPSPI peripheral address.
1176 * @param handle pointer to lpspi_slave_handle_t structure which stores the transfer state.
1177 */
1178 void LPSPI_SlaveTransferAbort(LPSPI_Type *base, lpspi_slave_handle_t *handle);
1179
1180 /*!
1181 * @brief LPSPI Slave IRQ handler function.
1182 *
1183 * This function processes the LPSPI transmit and receives an IRQ.
1184 *
1185 * @param base LPSPI peripheral address.
1186 * @param handle pointer to lpspi_slave_handle_t structure which stores the transfer state.
1187 */
1188 void LPSPI_SlaveTransferHandleIRQ(LPSPI_Type *base, lpspi_slave_handle_t *handle);
1189
1190 /*!
1191 *@}
1192 */
1193
1194 #if defined(__cplusplus)
1195 }
1196 #endif
1197
1198 /*! @}*/
1199
1200 #endif /*_FSL_LPSPI_H_*/
1201
