1 /*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016-2023 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8 #ifndef _FSL_FLEXCAN_H_
9 #define _FSL_FLEXCAN_H_
10
11 #include "fsl_common.h"
12
13 /*!
14 * @addtogroup flexcan_driver
15 * @{
16 */
17
18 /******************************************************************************
19 * Definitions
20 *****************************************************************************/
21
22 /*! @name Driver version */
23 /*@{*/
24 /*! @brief FlexCAN driver version. */
25 #define FSL_FLEXCAN_DRIVER_VERSION (MAKE_VERSION(2, 11, 1))
26 /*@}*/
27
28 #if !(defined(FLEXCAN_WAIT_TIMEOUT) && FLEXCAN_WAIT_TIMEOUT)
29 /* Define to 1000 means keep waiting 1000 times until the flag is assert/deassert. */
30 #define FLEXCAN_WAIT_TIMEOUT (1000U)
31 #endif
32
33 /*! @brief FlexCAN frame length helper macro. */
34 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
35 #define DLC_LENGTH_DECODE(dlc) (((dlc) <= 8U) ? (dlc) : (((dlc) <= 12U) ? (((dlc)-6U) * 4U) : (((dlc)-11U) * 16U)))
36 #endif
37
38 /*! @brief FlexCAN Frame ID helper macro. */
39 #define FLEXCAN_ID_STD(id) \
40 (((uint32_t)(((uint32_t)(id)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK) /*!< Standard Frame ID helper macro. */
41 #define FLEXCAN_ID_EXT(id) \
42 (((uint32_t)(((uint32_t)(id)) << CAN_ID_EXT_SHIFT)) & \
43 (CAN_ID_EXT_MASK | CAN_ID_STD_MASK)) /*!< Extend Frame ID helper macro. */
44
45 /*! @brief FlexCAN Rx Message Buffer Mask helper macro. */
46 #define FLEXCAN_RX_MB_STD_MASK(id, rtr, ide) \
47 (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \
48 FLEXCAN_ID_STD(id)) /*!< Standard Rx Message Buffer Mask helper macro. */
49 #define FLEXCAN_RX_MB_EXT_MASK(id, rtr, ide) \
50 (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \
51 FLEXCAN_ID_EXT(id)) /*!< Extend Rx Message Buffer Mask helper macro. */
52
53 /*! @brief FlexCAN Legacy Rx FIFO Mask helper macro. */
54 #define FLEXCAN_RX_FIFO_STD_MASK_TYPE_A(id, rtr, ide) \
55 (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \
56 (FLEXCAN_ID_STD(id) << 1)) /*!< Standard Rx FIFO Mask helper macro Type A helper macro. */
57 #define FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_HIGH(id, rtr, ide) \
58 (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \
59 (((uint32_t)(id)&0x7FF) << 19)) /*!< Standard Rx FIFO Mask helper macro Type B upper part helper macro. */
60 #define FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_LOW(id, rtr, ide) \
61 (((uint32_t)((uint32_t)(rtr) << 15) | (uint32_t)((uint32_t)(ide) << 14)) | \
62 (((uint32_t)(id)&0x7FF) << 3)) /*!< Standard Rx FIFO Mask helper macro Type B lower part helper macro. */
63 #define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_HIGH(id) \
64 (((uint32_t)(id)&0x7F8) << 21) /*!< Standard Rx FIFO Mask helper macro Type C upper part helper macro. */
65 #define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_HIGH(id) \
66 (((uint32_t)(id)&0x7F8) << 13) /*!< Standard Rx FIFO Mask helper macro Type C mid-upper part helper macro. */
67 #define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_LOW(id) \
68 (((uint32_t)(id)&0x7F8) << 5) /*!< Standard Rx FIFO Mask helper macro Type C mid-lower part helper macro. */
69 #define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_LOW(id) \
70 (((uint32_t)(id)&0x7F8) >> 3) /*!< Standard Rx FIFO Mask helper macro Type C lower part helper macro. */
71 #define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_A(id, rtr, ide) \
72 (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \
73 (FLEXCAN_ID_EXT(id) << 1)) /*!< Extend Rx FIFO Mask helper macro Type A helper macro. */
74 #define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_HIGH(id, rtr, ide) \
75 ( \
76 ((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \
77 ((FLEXCAN_ID_EXT(id) & 0x1FFF8000) \
78 << 1)) /*!< Extend Rx FIFO Mask helper macro Type B upper part helper macro. */
79 #define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_LOW(id, rtr, ide) \
80 (((uint32_t)((uint32_t)(rtr) << 15) | (uint32_t)((uint32_t)(ide) << 14)) | \
81 ((FLEXCAN_ID_EXT(id) & 0x1FFF8000) >> \
82 15)) /*!< Extend Rx FIFO Mask helper macro Type B lower part helper macro. */
83 #define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_HIGH(id) \
84 ((FLEXCAN_ID_EXT(id) & 0x1FE00000) << 3) /*!< Extend Rx FIFO Mask helper macro Type C upper part helper macro. */
85 #define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_HIGH(id) \
86 ((FLEXCAN_ID_EXT(id) & 0x1FE00000) >> \
87 5) /*!< Extend Rx FIFO Mask helper macro Type C mid-upper part helper macro. */
88 #define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_LOW(id) \
89 ((FLEXCAN_ID_EXT(id) & 0x1FE00000) >> \
90 13) /*!< Extend Rx FIFO Mask helper macro Type C mid-lower part helper macro. */
91 #define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_LOW(id) \
92 ((FLEXCAN_ID_EXT(id) & 0x1FE00000) >> 21) /*!< Extend Rx FIFO Mask helper macro Type C lower part helper macro. */
93
94 /*! @brief FlexCAN Rx FIFO Filter helper macro. */
95 #define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_A(id, rtr, ide) \
96 FLEXCAN_RX_FIFO_STD_MASK_TYPE_A(id, rtr, ide) /*!< Standard Rx FIFO Filter helper macro Type A helper macro. */
97 #define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_B_HIGH(id, rtr, ide) \
98 FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_HIGH( \
99 id, rtr, ide) /*!< Standard Rx FIFO Filter helper macro Type B upper part helper macro. */
100 #define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_B_LOW(id, rtr, ide) \
101 FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_LOW( \
102 id, rtr, ide) /*!< Standard Rx FIFO Filter helper macro Type B lower part helper macro. */
103 #define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_HIGH(id) \
104 FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_HIGH( \
105 id) /*!< Standard Rx FIFO Filter helper macro Type C upper part helper macro. */
106 #define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_MID_HIGH(id) \
107 FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_HIGH( \
108 id) /*!< Standard Rx FIFO Filter helper macro Type C mid-upper part helper macro. */
109 #define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_MID_LOW(id) \
110 FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_LOW( \
111 id) /*!< Standard Rx FIFO Filter helper macro Type C mid-lower part helper macro. */
112 #define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_LOW(id) \
113 FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_LOW( \
114 id) /*!< Standard Rx FIFO Filter helper macro Type C lower part helper macro. */
115 #define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_A(id, rtr, ide) \
116 FLEXCAN_RX_FIFO_EXT_MASK_TYPE_A(id, rtr, ide) /*!< Extend Rx FIFO Filter helper macro Type A helper macro. */
117 #define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_B_HIGH(id, rtr, ide) \
118 FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_HIGH( \
119 id, rtr, ide) /*!< Extend Rx FIFO Filter helper macro Type B upper part helper macro. */
120 #define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_B_LOW(id, rtr, ide) \
121 FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_LOW( \
122 id, rtr, ide) /*!< Extend Rx FIFO Filter helper macro Type B lower part helper macro. */
123 #define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_HIGH(id) \
124 FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_HIGH( \
125 id) /*!< Extend Rx FIFO Filter helper macro Type C upper part helper macro. */
126 #define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_MID_HIGH(id) \
127 FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_HIGH( \
128 id) /*!< Extend Rx FIFO Filter helper macro Type C mid-upper part helper macro. */
129 #define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_MID_LOW(id) \
130 FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_LOW( \
131 id) /*!< Extend Rx FIFO Filter helper macro Type C mid-lower part helper macro. */
132 #define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_LOW(id) \
133 FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_LOW(id) /*!< Extend Rx FIFO Filter helper macro Type C lower part helper macro. */
134
135 #if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
136 /*! @brief FlexCAN Enhanced Rx FIFO Filter and Mask helper macro. */
137 #define ENHANCED_RX_FIFO_FSCH(x) (((uint32_t)(((uint32_t)(x)) << 30)) & 0xC0000000U)
138 #define RTR_STD_HIGH(x) (((uint32_t)(((uint32_t)(x)) << 27)) & 0x08000000U)
139 #define RTR_STD_LOW(x) (((uint32_t)(((uint32_t)(x)) << 11)) & 0x00000800U)
140 #define RTR_EXT(x) (((uint32_t)(((uint32_t)(x)) << 29)) & 0x40000000U)
141 #define ID_STD_LOW(id) (((uint32_t)id) & 0x7FFU)
142 #define ID_STD_HIGH(id) (((uint32_t)(((uint32_t)(id)) << 16)) & 0x07FF0000U)
143 #define ID_EXT(id) (((uint32_t)id) & 0x1FFFFFFFU)
144
145 /*! Standard ID filter element with filter + mask scheme. */
146 #define FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(id, rtr, id_mask, rtr_mask) \
147 (ENHANCED_RX_FIFO_FSCH(0x0) | RTR_STD_HIGH(rtr) | ID_STD_HIGH(id) | RTR_STD_LOW(rtr_mask) | ID_STD_LOW(id_mask))
148 /*! Standard ID filter element with filter range. */
149 #define FLEXCAN_ENHANCED_RX_FIFO_STD_FILTER_WITH_RANGE(id_upper, rtr, id_lower, rtr_mask) \
150 (ENHANCED_RX_FIFO_FSCH(0x1) | RTR_STD_HIGH(rtr) | ID_STD_HIGH(id_upper) | RTR_STD_LOW(rtr_mask) | \
151 ID_STD_LOW(id_lower))
152 /*! Standard ID filter element with two filters without masks. */
153 #define FLEXCAN_ENHANCED_RX_FIFO_STD_TWO_FILTERS(id1, rtr1, id2, rtr2) \
154 (ENHANCED_RX_FIFO_FSCH(0x2) | RTR_STD_HIGH(rtr1) | ID_STD_HIGH(id1) | RTR_STD_LOW(rtr2) | ID_STD_LOW(id2))
155 /*! Extended ID filter element with filter + mask scheme low word. */
156 #define FLEXCAN_ENHANCED_RX_FIFO_EXT_MASK_AND_FILTER_LOW(id, rtr) \
157 (ENHANCED_RX_FIFO_FSCH(0x0) | RTR_EXT(rtr) | ID_EXT(id))
158 /*! Extended ID filter element with filter + mask scheme high word. */
159 #define FLEXCAN_ENHANCED_RX_FIFO_EXT_MASK_AND_FILTER_HIGH(id_mask, rtr_mask) \
160 (ENHANCED_RX_FIFO_FSCH(0x0) | RTR_EXT(rtr_mask) | ID_EXT(id_mask))
161 /*! Extended ID filter element with range scheme low word. */
162 #define FLEXCAN_ENHANCED_RX_FIFO_EXT_FILTER_WITH_RANGE_LOW(id_upper, rtr) \
163 (ENHANCED_RX_FIFO_FSCH(0x1) | RTR_EXT(rtr) | ID_EXT(id_upper))
164 /*! Extended ID filter element with range scheme high word. */
165 #define FLEXCAN_ENHANCED_RX_FIFO_EXT_FILTER_WITH_RANGE_HIGH(id_lower, rtr_mask) \
166 (ENHANCED_RX_FIFO_FSCH(0x1) | RTR_EXT(rtr_mask) | ID_EXT(id_lower))
167 /*! Extended ID filter element with two filters without masks low word. */
168 #define FLEXCAN_ENHANCED_RX_FIFO_EXT_TWO_FILTERS_LOW(id2, rtr2) \
169 (ENHANCED_RX_FIFO_FSCH(0x2) | RTR_EXT(rtr2) | ID_EXT(id2))
170 /*! Extended ID filter element with two filters without masks high word. */
171 #define FLEXCAN_ENHANCED_RX_FIFO_EXT_TWO_FILTERS_HIGH(id1, rtr1) \
172 (ENHANCED_RX_FIFO_FSCH(0x2) | RTR_EXT(rtr1) | ID_EXT(id1))
173 #endif
174
175 #if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE)
176 /*! @brief FlexCAN Pretended Networking ID Mask helper macro. */
177 #define FLEXCAN_PN_STD_MASK(id, rtr) \
178 ((uint32_t)((uint32_t)(rtr) << CAN_FLT_ID1_FLT_RTR_SHIFT) | \
179 FLEXCAN_ID_STD(id)) /*!< Standard Rx Message Buffer Mask helper macro. */
180 #define FLEXCAN_PN_EXT_MASK(id, rtr) \
181 ((uint32_t)CAN_FLT_ID1_FLT_IDE_MASK | (uint32_t)((uint32_t)(rtr) << CAN_FLT_ID1_FLT_RTR_SHIFT) | \
182 FLEXCAN_ID_EXT(id)) /*!< Extend Rx Message Buffer Mask helper macro. */
183 #endif
184
185 /*! @brief FlexCAN interrupt/status flag helper macro. */
186 #if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE)
187 #define FLEXCAN_PN_INT_MASK(x) (((uint64_t)(((uint64_t)(x)) << 32)) & 0x3000000000000U)
188 #define FLEXCAN_PN_INT_UNMASK(x) (((uint32_t)(((uint64_t)(x)) >> 32)) & 0x00030000U)
189 #define FLEXCAN_PN_STATUS_MASK(x) (((uint64_t)(((uint64_t)(x)) << 16)) & 0x300000000U)
190 #define FLEXCAN_PN_STATUS_UNMASK(x) (((uint32_t)(((uint64_t)(x)) >> 16)) & 0x00030000U)
191 #endif
192 #if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
193 #define FLEXCAN_EFIFO_INT_MASK(x) (((uint64_t)(((uint64_t)(x)) << 32)) & 0xF000000000000000U)
194 #define FLEXCAN_EFIFO_INT_UNMASK(x) (((uint32_t)(((uint64_t)(x)) >> 32)) & 0xF0000000U)
195 #define FLEXCAN_EFIFO_STATUS_MASK(x) (((uint64_t)(((uint64_t)(x)) << 32)) & 0xF003000000000000U)
196 #define FLEXCAN_EFIFO_STATUS_UNMASK(x) (((uint32_t)(((uint64_t)(x)) >> 32)) & 0xF0030000U)
197 #endif
198 #if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL)
199 #define FLEXCAN_MECR_INT_MASK(x) (((uint64_t)(((uint64_t)(x)) << 16)) & 0xD00000000U)
200 #define FLEXCAN_MECR_INT_UNMASK(x) (((uint32_t)(((uint64_t)(x)) >> 16)) & 0x000D0000U)
201 #define FLEXCAN_MECR_STATUS_MASK(x) (((uint64_t)(((uint64_t)(x)) << 34)) & 0x34003400000000U)
202 #define FLEXCAN_MECR_STATUS_UNMASK(x) (((uint32_t)(((uint64_t)(x)) >> 34)) & 0x000D000DU)
203 #endif
204
205 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
206 #define FLEXCAN_ERROR_AND_STATUS_INIT_FLAG \
207 ((uint32_t)kFLEXCAN_ErrorOverrunFlag | (uint32_t)kFLEXCAN_FDErrorIntFlag | (uint32_t)kFLEXCAN_BusoffDoneIntFlag | \
208 (uint32_t)kFLEXCAN_TxWarningIntFlag | (uint32_t)kFLEXCAN_RxWarningIntFlag | (uint32_t)kFLEXCAN_BusOffIntFlag | \
209 (uint32_t)kFLEXCAN_ErrorIntFlag | FLEXCAN_MEMORY_ERROR_INIT_FLAG)
210 #else
211 #define FLEXCAN_ERROR_AND_STATUS_INIT_FLAG \
212 ((uint32_t)kFLEXCAN_TxWarningIntFlag | (uint32_t)kFLEXCAN_RxWarningIntFlag | (uint32_t)kFLEXCAN_BusOffIntFlag | \
213 (uint32_t)kFLEXCAN_ErrorIntFlag | FLEXCAN_MEMORY_ERROR_INIT_FLAG)
214 #endif
215 #if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE)
216 #define FLEXCAN_WAKE_UP_FLAG \
217 ((uint32_t)kFLEXCAN_WakeUpIntFlag | (uint64_t)kFLEXCAN_PNMatchIntFlag | (uint64_t)kFLEXCAN_PNTimeoutIntFlag)
218 #else
219 #define FLEXCAN_WAKE_UP_FLAG ((uint32_t)kFLEXCAN_WakeUpIntFlag)
220 #endif
221 #if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL)
222 #define FLEXCAN_MEMORY_ERROR_INIT_FLAG ((uint64_t)kFLEXCAN_AllMemoryErrorFlag)
223 #else
224 #define FLEXCAN_MEMORY_ERROR_INIT_FLAG (0U)
225 #endif
226
227 #if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
228 #define FLEXCAN_MEMORY_ENHANCED_RX_FIFO_INIT_FLAG \
229 ((uint64_t)kFLEXCAN_ERxFifoUnderflowIntFlag | (uint64_t)kFLEXCAN_ERxFifoOverflowIntFlag | \
230 (uint64_t)kFLEXCAN_ERxFifoWatermarkIntFlag | (uint64_t)kFLEXCAN_ERxFifoDataAvlIntFlag)
231 #endif
232 /*! @brief FlexCAN Enhanced Rx FIFO base address helper macro. */
233 #if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
234 #define E_RX_FIFO(base) ((uint32_t)(base) + 0x2000U)
235 #else
236 #define FLEXCAN_MEMORY_ENHANCED_RX_FIFO_INIT_FLAG (0U)
237 #endif
238 /*! @brief FlexCAN transfer status. */
239 enum
240 {
241 kStatus_FLEXCAN_TxBusy = MAKE_STATUS(kStatusGroup_FLEXCAN, 0), /*!< Tx Message Buffer is Busy. */
242 kStatus_FLEXCAN_TxIdle = MAKE_STATUS(kStatusGroup_FLEXCAN, 1), /*!< Tx Message Buffer is Idle. */
243 kStatus_FLEXCAN_TxSwitchToRx = MAKE_STATUS(
244 kStatusGroup_FLEXCAN, 2), /*!< Remote Message is send out and Message buffer changed to Receive one. */
245 kStatus_FLEXCAN_RxBusy = MAKE_STATUS(kStatusGroup_FLEXCAN, 3), /*!< Rx Message Buffer is Busy. */
246 kStatus_FLEXCAN_RxIdle = MAKE_STATUS(kStatusGroup_FLEXCAN, 4), /*!< Rx Message Buffer is Idle. */
247 kStatus_FLEXCAN_RxOverflow = MAKE_STATUS(kStatusGroup_FLEXCAN, 5), /*!< Rx Message Buffer is Overflowed. */
248 kStatus_FLEXCAN_RxFifoBusy = MAKE_STATUS(kStatusGroup_FLEXCAN, 6), /*!< Rx Message FIFO is Busy. */
249 kStatus_FLEXCAN_RxFifoIdle = MAKE_STATUS(kStatusGroup_FLEXCAN, 7), /*!< Rx Message FIFO is Idle. */
250 kStatus_FLEXCAN_RxFifoOverflow = MAKE_STATUS(kStatusGroup_FLEXCAN, 8), /*!< Rx Message FIFO is overflowed. */
251 kStatus_FLEXCAN_RxFifoWarning = MAKE_STATUS(kStatusGroup_FLEXCAN, 9), /*!< Rx Message FIFO is almost overflowed. */
252 kStatus_FLEXCAN_RxFifoDisabled =
253 MAKE_STATUS(kStatusGroup_FLEXCAN, 10), /*!< Rx Message FIFO is disabled during reading. */
254 kStatus_FLEXCAN_ErrorStatus = MAKE_STATUS(kStatusGroup_FLEXCAN, 11), /*!< FlexCAN Module Error and Status. */
255 kStatus_FLEXCAN_WakeUp = MAKE_STATUS(kStatusGroup_FLEXCAN, 12), /*!< FlexCAN is waken up from STOP mode. */
256 kStatus_FLEXCAN_UnHandled = MAKE_STATUS(kStatusGroup_FLEXCAN, 13), /*!< UnHadled Interrupt asserted. */
257 kStatus_FLEXCAN_RxRemote = MAKE_STATUS(kStatusGroup_FLEXCAN, 14), /*!< Rx Remote Message Received in Mail box. */
258 #if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
259 kStatus_FLEXCAN_RxFifoUnderflow =
260 MAKE_STATUS(kStatusGroup_FLEXCAN, 15), /*!< Enhanced Rx Message FIFO is underflow. */
261 #endif
262 };
263
264 /*! @brief FlexCAN frame format. */
265 typedef enum _flexcan_frame_format
266 {
267 kFLEXCAN_FrameFormatStandard = 0x0U, /*!< Standard frame format attribute. */
268 kFLEXCAN_FrameFormatExtend = 0x1U, /*!< Extend frame format attribute. */
269 } flexcan_frame_format_t;
270
271 /*! @brief FlexCAN frame type. */
272 typedef enum _flexcan_frame_type
273 {
274 kFLEXCAN_FrameTypeData = 0x0U, /*!< Data frame type attribute. */
275 kFLEXCAN_FrameTypeRemote = 0x1U, /*!< Remote frame type attribute. */
276 } flexcan_frame_type_t;
277
278 /*! @brief FlexCAN clock source.
279 * @deprecated Do not use the kFLEXCAN_ClkSrcOs. It has been superceded kFLEXCAN_ClkSrc0
280 * @deprecated Do not use the kFLEXCAN_ClkSrcPeri. It has been superceded kFLEXCAN_ClkSrc1
281 */
282 typedef enum _flexcan_clock_source
283 {
284 kFLEXCAN_ClkSrcOsc = 0x0U, /*!< FlexCAN Protocol Engine clock from Oscillator. */
285 kFLEXCAN_ClkSrcPeri = 0x1U, /*!< FlexCAN Protocol Engine clock from Peripheral Clock. */
286 kFLEXCAN_ClkSrc0 = 0x0U, /*!< FlexCAN Protocol Engine clock selected by user as SRC == 0. */
287 kFLEXCAN_ClkSrc1 = 0x1U, /*!< FlexCAN Protocol Engine clock selected by user as SRC == 1. */
288 } flexcan_clock_source_t;
289
290 /*! @brief FlexCAN wake up source. */
291 typedef enum _flexcan_wake_up_source
292 {
293 kFLEXCAN_WakeupSrcUnfiltered = 0x0U, /*!< FlexCAN uses unfiltered Rx input to detect edge. */
294 kFLEXCAN_WakeupSrcFiltered = 0x1U, /*!< FlexCAN uses filtered Rx input to detect edge. */
295 } flexcan_wake_up_source_t;
296
297 /*! @brief FlexCAN Rx Fifo Filter type. */
298 typedef enum _flexcan_rx_fifo_filter_type
299 {
300 kFLEXCAN_RxFifoFilterTypeA = 0x0U, /*!< One full ID (standard and extended) per ID Filter element. */
301 kFLEXCAN_RxFifoFilterTypeB =
302 0x1U, /*!< Two full standard IDs or two partial 14-bit ID slices per ID Filter Table element. */
303 kFLEXCAN_RxFifoFilterTypeC =
304 0x2U, /*!< Four partial 8-bit Standard or extended ID slices per ID Filter Table element. */
305 kFLEXCAN_RxFifoFilterTypeD = 0x3U, /*!< All frames rejected. */
306 } flexcan_rx_fifo_filter_type_t;
307
308 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
309 /*!
310 * @brief FlexCAN Message Buffer Payload size.
311 */
312 typedef enum _flexcan_mb_size
313 {
314 kFLEXCAN_8BperMB = 0x0U, /*!< Selects 8 bytes per Message Buffer. */
315 kFLEXCAN_16BperMB = 0x1U, /*!< Selects 16 bytes per Message Buffer. */
316 kFLEXCAN_32BperMB = 0x2U, /*!< Selects 32 bytes per Message Buffer. */
317 kFLEXCAN_64BperMB = 0x3U, /*!< Selects 64 bytes per Message Buffer. */
318 } flexcan_mb_size_t;
319
320 /*!
321 * @brief FlexCAN CAN FD frame supporting data length (available DLC values).
322 *
323 * For Tx, when the Data size corresponding to DLC value stored in the MB selected for transmission is larger than the
324 * MB Payload size, FlexCAN adds the necessary number of bytes with constant 0xCC pattern to complete the expected DLC.
325 * For Rx, when the Data size corresponding to DLC value received from the CAN bus is larger than the MB Payload size,
326 * the high order bytes that do not fit the Payload size will lose.
327 */
328 enum _flexcan_fd_frame_length
329 {
330 kFLEXCAN_0BperFrame = 0x0U, /*!< Frame contains 0 valid data bytes. */
331 kFLEXCAN_1BperFrame, /*!< Frame contains 1 valid data bytes. */
332 kFLEXCAN_2BperFrame, /*!< Frame contains 2 valid data bytes. */
333 kFLEXCAN_3BperFrame, /*!< Frame contains 3 valid data bytes. */
334 kFLEXCAN_4BperFrame, /*!< Frame contains 4 valid data bytes. */
335 kFLEXCAN_5BperFrame, /*!< Frame contains 5 valid data bytes. */
336 kFLEXCAN_6BperFrame, /*!< Frame contains 6 valid data bytes. */
337 kFLEXCAN_7BperFrame, /*!< Frame contains 7 valid data bytes. */
338 kFLEXCAN_8BperFrame, /*!< Frame contains 8 valid data bytes. */
339 kFLEXCAN_12BperFrame, /*!< Frame contains 12 valid data bytes. */
340 kFLEXCAN_16BperFrame, /*!< Frame contains 16 valid data bytes. */
341 kFLEXCAN_20BperFrame, /*!< Frame contains 20 valid data bytes. */
342 kFLEXCAN_24BperFrame, /*!< Frame contains 24 valid data bytes. */
343 kFLEXCAN_32BperFrame, /*!< Frame contains 32 valid data bytes. */
344 kFLEXCAN_48BperFrame, /*!< Frame contains 48 valid data bytes. */
345 kFLEXCAN_64BperFrame, /*!< Frame contains 64 valid data bytes. */
346 };
347 #endif
348
349 #if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
350 /*! @brief FlexCAN Enhanced Rx Fifo DMA transfer per read length enumerations. */
351 typedef enum _flexcan_efifo_dma_per_read_length
352 {
353 kFLEXCAN_1WordPerRead = 0x0U, /*!< Transfer 1 32-bit words (CS).*/
354 kFLEXCAN_2WordPerRead, /*!< Transfer 2 32-bit words (CS + ID).*/
355 kFLEXCAN_3WordPerRead, /*!< Transfer 3 32-bit words (CS + ID + 1~4 bytes data).*/
356 kFLEXCAN_4WordPerRead, /*!< Transfer 4 32-bit words (CS + ID + 5~8 bytes data).*/
357 kFLEXCAN_5WordPerRead, /*!< Transfer 5 32-bit words (CS + ID + 9~12 bytes data).*/
358 kFLEXCAN_6WordPerRead, /*!< Transfer 6 32-bit words (CS + ID + 13~16 bytes data).*/
359 kFLEXCAN_7WordPerRead, /*!< Transfer 7 32-bit words (CS + ID + 17~20 bytes data).*/
360 kFLEXCAN_8WordPerRead, /*!< Transfer 8 32-bit words (CS + ID + 21~24 bytes data).*/
361 kFLEXCAN_9WordPerRead, /*!< Transfer 9 32-bit words (CS + ID + 25~28 bytes data).*/
362 kFLEXCAN_10WordPerRead, /*!< Transfer 10 32-bit words (CS + ID + 29~32 bytes data).*/
363 kFLEXCAN_11WordPerRead, /*!< Transfer 11 32-bit words (CS + ID + 33~36 bytes data).*/
364 kFLEXCAN_12WordPerRead, /*!< Transfer 12 32-bit words (CS + ID + 37~40 bytes data).*/
365 kFLEXCAN_13WordPerRead, /*!< Transfer 13 32-bit words (CS + ID + 41~44 bytes data).*/
366 kFLEXCAN_14WordPerRead, /*!< Transfer 14 32-bit words (CS + ID + 45~48 bytes data).*/
367 kFLEXCAN_15WordPerRead, /*!< Transfer 15 32-bit words (CS + ID + 49~52 bytes data).*/
368 kFLEXCAN_16WordPerRead, /*!< Transfer 16 32-bit words (CS + ID + 53~56 bytes data).*/
369 kFLEXCAN_17WordPerRead, /*!< Transfer 17 32-bit words (CS + ID + 57~60 bytes data).*/
370 kFLEXCAN_18WordPerRead, /*!< Transfer 18 32-bit words (CS + ID + 61~64 bytes data).*/
371 kFLEXCAN_19WordPerRead /*!< Transfer 19 32-bit words (CS + ID + 64 bytes data + ID HIT).*/
372 } flexcan_efifo_dma_per_read_length_t;
373 #endif
374
375 /*!
376 * @brief FlexCAN Enhanced/Legacy Rx FIFO priority.
377 *
378 * The matching process starts from the Rx MB(or Enhanced/Legacy Rx FIFO) with higher priority.
379 * If no MB(or Enhanced/Legacy Rx FIFO filter) is satisfied, the matching process goes on with
380 * the Enhanced/Legacy Rx FIFO(or Rx MB) with lower priority.
381 */
382 typedef enum _flexcan_rx_fifo_priority
383 {
384 kFLEXCAN_RxFifoPrioLow = 0x0U, /*!< Matching process start from Rx Message Buffer first. */
385 kFLEXCAN_RxFifoPrioHigh = 0x1U, /*!< Matching process start from Enhanced/Legacy Rx FIFO first. */
386 } flexcan_rx_fifo_priority_t;
387
388 /*!
389 * @brief FlexCAN interrupt enable enumerations.
390 *
391 * This provides constants for the FlexCAN interrupt enable enumerations for use in the FlexCAN functions.
392 * @note FlexCAN Message Buffers and Legacy Rx FIFO interrupts not included in.
393 */
394 enum _flexcan_interrupt_enable
395 {
396 kFLEXCAN_BusOffInterruptEnable = CAN_CTRL1_BOFFMSK_MASK, /*!< Bus Off interrupt, use bit 15. */
397 kFLEXCAN_ErrorInterruptEnable = CAN_CTRL1_ERRMSK_MASK, /*!< CAN Error interrupt, use bit 14. */
398 kFLEXCAN_TxWarningInterruptEnable = CAN_CTRL1_TWRNMSK_MASK, /*!< Tx Warning interrupt, use bit 11. */
399 kFLEXCAN_RxWarningInterruptEnable = CAN_CTRL1_RWRNMSK_MASK, /*!< Rx Warning interrupt, use bit 10. */
400 kFLEXCAN_WakeUpInterruptEnable = CAN_MCR_WAKMSK_MASK, /*!< Self Wake Up interrupt, use bit 26. */
401 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
402 kFLEXCAN_FDErrorInterruptEnable = CAN_CTRL2_ERRMSK_FAST_MASK, /*!< CAN FD Error interrupt, use bit 31. */
403 #endif
404 #if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE)
405 /*! PN Match Wake Up interrupt, use high word bit 17. */
406 kFLEXCAN_PNMatchWakeUpInterruptEnable = FLEXCAN_PN_INT_MASK(CAN_CTRL1_PN_WTOF_MSK_MASK),
407 /*! PN Timeout Wake Up interrupt, use high word bit 16. */
408 kFLEXCAN_PNTimeoutWakeUpInterruptEnable = FLEXCAN_PN_INT_MASK(CAN_CTRL1_PN_WUMF_MSK_MASK),
409 #endif
410 #if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
411 /*!< Enhanced Rx FIFO Underflow interrupt, use high word bit 31. */
412 kFLEXCAN_ERxFifoUnderflowInterruptEnable = FLEXCAN_EFIFO_INT_MASK(CAN_ERFIER_ERFUFWIE_MASK),
413 /*!< Enhanced Rx FIFO Overflow interrupt, use high word bit 30. */
414 kFLEXCAN_ERxFifoOverflowInterruptEnable = FLEXCAN_EFIFO_INT_MASK(CAN_ERFIER_ERFOVFIE_MASK),
415 /*!< Enhanced Rx FIFO Watermark interrupt, use high word bit 29. */
416 kFLEXCAN_ERxFifoWatermarkInterruptEnable = FLEXCAN_EFIFO_INT_MASK(CAN_ERFIER_ERFWMIIE_MASK),
417 /*!< Enhanced Rx FIFO Data Avilable interrupt, use high word bit 28. */
418 kFLEXCAN_ERxFifoDataAvlInterruptEnable = FLEXCAN_EFIFO_INT_MASK(CAN_ERFIER_ERFDAIE_MASK),
419 #endif
420 #if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL)
421 /*! Host Access With Non-Correctable Errors interrupt, use high word bit 0. */
422 kFLEXCAN_HostAccessNCErrorInterruptEnable = FLEXCAN_MECR_INT_MASK(CAN_MECR_HANCEI_MSK_MASK),
423 /*! FlexCAN Access With Non-Correctable Errors interrupt, use high word bit 2. */
424 kFLEXCAN_FlexCanAccessNCErrorInterruptEnable = FLEXCAN_MECR_INT_MASK(CAN_MECR_FANCEI_MSK_MASK),
425 /*! Host or FlexCAN Access With Correctable Errors interrupt, use high word bit 3. */
426 kFLEXCAN_HostOrFlexCanCErrorInterruptEnable = FLEXCAN_MECR_INT_MASK(CAN_MECR_CEI_MSK_MASK),
427 #endif
428 };
429
430 /*!
431 * @brief FlexCAN status flags.
432 *
433 * This provides constants for the FlexCAN status flags for use in the FlexCAN functions.
434 * @note The CPU read action clears the bits corresponding to the FlEXCAN_ErrorFlag macro, therefore user need to
435 * read status flags and distinguish which error is occur using @ref _flexcan_error_flags enumerations.
436 */
437 enum _flexcan_flags
438 {
439 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
440 kFLEXCAN_ErrorOverrunFlag = CAN_ESR1_ERROVR_MASK, /*!< Error Overrun Status. */
441 kFLEXCAN_FDErrorIntFlag = CAN_ESR1_ERRINT_FAST_MASK, /*!< CAN FD Error Interrupt Flag. */
442 kFLEXCAN_BusoffDoneIntFlag = CAN_ESR1_BOFFDONEINT_MASK, /*!< Bus Off process completed Interrupt Flag. */
443 #endif
444 kFLEXCAN_SynchFlag = CAN_ESR1_SYNCH_MASK, /*!< CAN Synchronization Status. */
445 kFLEXCAN_TxWarningIntFlag = CAN_ESR1_TWRNINT_MASK, /*!< Tx Warning Interrupt Flag. */
446 kFLEXCAN_RxWarningIntFlag = CAN_ESR1_RWRNINT_MASK, /*!< Rx Warning Interrupt Flag. */
447 kFLEXCAN_IdleFlag = CAN_ESR1_IDLE_MASK, /*!< FlexCAN In IDLE Status. */
448 kFLEXCAN_FaultConfinementFlag = CAN_ESR1_FLTCONF_MASK, /*!< FlexCAN Fault Confinement State. */
449 kFLEXCAN_TransmittingFlag = CAN_ESR1_TX_MASK, /*!< FlexCAN In Transmission Status. */
450 kFLEXCAN_ReceivingFlag = CAN_ESR1_RX_MASK, /*!< FlexCAN In Reception Status. */
451 kFLEXCAN_BusOffIntFlag = CAN_ESR1_BOFFINT_MASK, /*!< Bus Off Interrupt Flag. */
452 kFLEXCAN_ErrorIntFlag = CAN_ESR1_ERRINT_MASK, /*!< CAN Error Interrupt Flag. */
453 kFLEXCAN_WakeUpIntFlag = CAN_ESR1_WAKINT_MASK, /*!< Self Wake-Up Interrupt Flag. */
454 kFLEXCAN_ErrorFlag =
455 (uint32_t)(/*!< All FlexCAN Read Clear Error Status. */
456 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
457 CAN_ESR1_STFERR_FAST_MASK | CAN_ESR1_FRMERR_FAST_MASK | CAN_ESR1_CRCERR_FAST_MASK |
458 CAN_ESR1_BIT0ERR_FAST_MASK | CAN_ESR1_BIT1ERR_FAST_MASK | CAN_ESR1_ERROVR_MASK |
459 #endif
460 CAN_ESR1_TXWRN_MASK | CAN_ESR1_RXWRN_MASK | CAN_ESR1_BIT1ERR_MASK | CAN_ESR1_BIT0ERR_MASK |
461 CAN_ESR1_ACKERR_MASK | CAN_ESR1_CRCERR_MASK | CAN_ESR1_FRMERR_MASK | CAN_ESR1_STFERR_MASK),
462 #if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE)
463 kFLEXCAN_PNMatchIntFlag = FLEXCAN_PN_STATUS_MASK(CAN_WU_MTC_WUMF_MASK), /*!< PN Matching Event Interrupt Flag. */
464 kFLEXCAN_PNTimeoutIntFlag = FLEXCAN_PN_STATUS_MASK(CAN_WU_MTC_WTOF_MASK), /*!< PN Timeout Event Interrupt Flag. */
465 #endif
466 #if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
467 kFLEXCAN_ERxFifoUnderflowIntFlag =
468 FLEXCAN_EFIFO_STATUS_MASK(CAN_ERFSR_ERFUFW_MASK), /*!< Enhanced Rx FIFO underflow Interrupt Flag. */
469 kFLEXCAN_ERxFifoOverflowIntFlag =
470 FLEXCAN_EFIFO_STATUS_MASK(CAN_ERFSR_ERFOVF_MASK), /*!< Enhanced Rx FIFO overflow Interrupt Flag. */
471 kFLEXCAN_ERxFifoWatermarkIntFlag =
472 FLEXCAN_EFIFO_STATUS_MASK(CAN_ERFSR_ERFWMI_MASK), /*!< Enhanced Rx FIFO watermark Interrupt Flag. */
473 kFLEXCAN_ERxFifoDataAvlIntFlag =
474 FLEXCAN_EFIFO_STATUS_MASK(CAN_ERFSR_ERFDA_MASK), /*!< Enhanced Rx FIFO data available Interrupt Flag. */
475 kFLEXCAN_ERxFifoEmptyFlag = FLEXCAN_EFIFO_STATUS_MASK(CAN_ERFSR_ERFE_MASK), /*!< Enhanced Rx FIFO empty status. */
476 kFLEXCAN_ERxFifoFullFlag = FLEXCAN_EFIFO_STATUS_MASK(CAN_ERFSR_ERFF_MASK), /*!< Enhanced Rx FIFO full status. */
477 #endif
478 #if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL)
479 /*! Host Access With Non-Correctable Error Interrupt Flag. */
480 kFLEXCAN_HostAccessNonCorrectableErrorIntFlag = FLEXCAN_MECR_INT_MASK(CAN_ERRSR_HANCEIF_MASK),
481 /*! FlexCAN Access With Non-Correctable Error Interrupt Flag. */
482 kFLEXCAN_FlexCanAccessNonCorrectableErrorIntFlag = FLEXCAN_MECR_INT_MASK(CAN_ERRSR_FANCEIF_MASK),
483 /*! Correctable Error Interrupt Flag. */
484 kFLEXCAN_CorrectableErrorIntFlag = FLEXCAN_MECR_INT_MASK(CAN_ERRSR_CEIF_MASK),
485 /*! Host Access With Non-Correctable Error Interrupt Overrun Flag. */
486 kFLEXCAN_HostAccessNonCorrectableErrorOverrunFlag = FLEXCAN_MECR_INT_MASK(CAN_ERRSR_HANCEIOF_MASK),
487 /*! FlexCAN Access With Non-Correctable Error Interrupt Overrun Flag. */
488 kFLEXCAN_FlexCanAccessNonCorrectableErrorOverrunFlag = FLEXCAN_MECR_INT_MASK(CAN_ERRSR_FANCEIOF_MASK),
489 /*! Correctable Error Interrupt Overrun Flag. */
490 kFLEXCAN_CorrectableErrorOverrunFlag = FLEXCAN_MECR_INT_MASK(CAN_ERRSR_CEIOF_MASK),
491 /*! All Memory Error Flags. */
492 kFLEXCAN_AllMemoryErrorFlag =
493 (kFLEXCAN_HostAccessNonCorrectableErrorIntFlag | kFLEXCAN_FlexCanAccessNonCorrectableErrorIntFlag |
494 kFLEXCAN_CorrectableErrorIntFlag | kFLEXCAN_HostAccessNonCorrectableErrorOverrunFlag |
495 kFLEXCAN_FlexCanAccessNonCorrectableErrorOverrunFlag | kFLEXCAN_CorrectableErrorOverrunFlag)
496 #endif
497 };
498
499 /*!
500 * @brief FlexCAN error status flags.
501 *
502 * The FlexCAN Error Status enumerations is used to report current error of the FlexCAN bus.
503 * This enumerations should be used with KFLEXCAN_ErrorFlag in @ref _flexcan_flags enumerations
504 * to ditermine which error is generated.
505 */
506 enum _flexcan_error_flags
507 {
508 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
509 kFLEXCAN_FDStuffingError = CAN_ESR1_STFERR_FAST_MASK, /*!< Stuffing Error. */
510 kFLEXCAN_FDFormError = CAN_ESR1_FRMERR_FAST_MASK, /*!< Form Error. */
511 kFLEXCAN_FDCrcError = CAN_ESR1_CRCERR_FAST_MASK, /*!< Cyclic Redundancy Check Error. */
512 kFLEXCAN_FDBit0Error = CAN_ESR1_BIT0ERR_FAST_MASK, /*!< Unable to send dominant bit. */
513 kFLEXCAN_FDBit1Error = (int)CAN_ESR1_BIT1ERR_FAST_MASK, /*!< Unable to send recessive bit. */
514 #endif
515 kFLEXCAN_TxErrorWarningFlag = CAN_ESR1_TXWRN_MASK, /*!< Tx Error Warning Status. */
516 kFLEXCAN_RxErrorWarningFlag = CAN_ESR1_RXWRN_MASK, /*!< Rx Error Warning Status. */
517 kFLEXCAN_StuffingError = CAN_ESR1_STFERR_MASK, /*!< Stuffing Error. */
518 kFLEXCAN_FormError = CAN_ESR1_FRMERR_MASK, /*!< Form Error. */
519 kFLEXCAN_CrcError = CAN_ESR1_CRCERR_MASK, /*!< Cyclic Redundancy Check Error. */
520 kFLEXCAN_AckError = CAN_ESR1_ACKERR_MASK, /*!< Received no ACK on transmission. */
521 kFLEXCAN_Bit0Error = CAN_ESR1_BIT0ERR_MASK, /*!< Unable to send dominant bit. */
522 kFLEXCAN_Bit1Error = CAN_ESR1_BIT1ERR_MASK, /*!< Unable to send recessive bit. */
523 };
524
525 /*!
526 * @brief FlexCAN Legacy Rx FIFO status flags.
527 *
528 * The FlexCAN Legacy Rx FIFO Status enumerations are used to determine the status of the
529 * Rx FIFO. Because Rx FIFO occupy the MB0 ~ MB7 (Rx Fifo filter also occupies
530 * more Message Buffer space), Rx FIFO status flags are mapped to the corresponding
531 * Message Buffer status flags.
532 */
533 enum
534 {
535 kFLEXCAN_RxFifoOverflowFlag = CAN_IFLAG1_BUF7I_MASK, /*!< Rx FIFO overflow flag. */
536 kFLEXCAN_RxFifoWarningFlag = CAN_IFLAG1_BUF6I_MASK, /*!< Rx FIFO almost full flag. */
537 kFLEXCAN_RxFifoFrameAvlFlag = CAN_IFLAG1_BUF5I_MASK, /*!< Frames available in Rx FIFO flag. */
538 };
539
540 #if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL)
541 /*!
542 * @brief FlexCAN Memory Error Type.
543 */
544 typedef enum _flexcan_memory_error_type
545 {
546 kFLEXCAN_CorrectableError = 0U, /*!< The memory error is correctable which means on bit error. */
547 kFLEXCAN_NonCorrectableError /*!< The memory error is non-correctable which means two bit errors. */
548 } flexcan_memory_error_type_t;
549
550 /*!
551 * @brief FlexCAN Memory Access Type.
552 */
553 typedef enum _flexcan_memory_access_type
554 {
555 kFLEXCAN_MoveOutFlexCanAccess = 0U, /*!< The memory error was detected during move-out FlexCAN access. */
556 kFLEXCAN_MoveInAccess, /*!< The memory error was detected during move-in FlexCAN access. */
557 kFLEXCAN_TxArbitrationAccess, /*!< The memory error was detected during Tx Arbitration FlexCAN access. */
558 kFLEXCAN_RxMatchingAccess, /*!< The memory error was detected during Rx Matching FlexCAN access. */
559 kFLEXCAN_MoveOutHostAccess /*!< The memory error was detected during Rx Matching Host (CPU) access. */
560 } flexcan_memory_access_type_t;
561
562 /*!
563 * @brief FlexCAN Memory Error Byte Syndrome.
564 */
565 typedef enum _flexcan_byte_error_syndrome
566 {
567 kFLEXCAN_NoError = 0U, /*!< No bit error in this byte. */
568 kFLEXCAN_ParityBits0Error = 1U, /*!< Parity bit 0 error in this byte. */
569 kFLEXCAN_ParityBits1Error = 2U, /*!< Parity bit 1 error in this byte. */
570 kFLEXCAN_ParityBits2Error = 4U, /*!< Parity bit 2 error in this byte. */
571 kFLEXCAN_ParityBits3Error = 8U, /*!< Parity bit 3 error in this byte. */
572 kFLEXCAN_ParityBits4Error = 16U, /*!< Parity bit 4 error in this byte. */
573 kFLEXCAN_DataBits0Error = 28U, /*!< Data bit 0 error in this byte. */
574 kFLEXCAN_DataBits1Error = 22U, /*!< Data bit 1 error in this byte. */
575 kFLEXCAN_DataBits2Error = 19U, /*!< Data bit 2 error in this byte. */
576 kFLEXCAN_DataBits3Error = 25U, /*!< Data bit 3 error in this byte. */
577 kFLEXCAN_DataBits4Error = 26U, /*!< Data bit 4 error in this byte. */
578 kFLEXCAN_DataBits5Error = 7U, /*!< Data bit 5 error in this byte. */
579 kFLEXCAN_DataBits6Error = 21U, /*!< Data bit 6 error in this byte. */
580 kFLEXCAN_DataBits7Error = 14U, /*!< Data bit 7 error in this byte. */
581 kFLEXCAN_AllZeroError = 6U, /*!< All-zeros non-correctable error in this byte. */
582 kFLEXCAN_AllOneError = 31U, /*!< All-ones non-correctable error in this byte. */
583 kFLEXCAN_NonCorrectableErrors /*!< Non-correctable error in this byte. */
584 } flexcan_byte_error_syndrome_t;
585
586 /*!
587 * @brief FlexCAN memory error register status structure
588 *
589 * This structure contains the memory access properties that caused a memory error access.
590 * It is used as the parameter of FLEXCAN_GetMemoryErrorReportStatus() function. And user can
591 * use FLEXCAN_GetMemoryErrorReportStatus to get the status of the last memory error access.
592 */
593 typedef struct _flexcan_memory_error_report_status
594 {
595 flexcan_memory_error_type_t errorType; /*!< The type of memory error that giving rise to the report. */
596 flexcan_memory_access_type_t accessType; /*!< The type of memory access that giving rise to the memory error. */
597 uint16_t accessAddress; /*!< The address where memory error detected. */
598 uint32_t errorData; /*!< The raw data word read from memory with error. */
599 struct
600 {
601 bool byteIsRead; /*!< The byte n (0~3) was read or not. */
602 /*!< The type of error and which bit in byte (n) is affected by the error. */
603 flexcan_byte_error_syndrome_t bitAffected;
604 } byteStatus[4];
605 } flexcan_memory_error_report_status_t;
606 #endif
607
608 #if defined(__CC_ARM)
609 #pragma anon_unions
610 #endif
611 /*! @brief FlexCAN message frame structure. */
612 typedef struct _flexcan_frame
613 {
614 struct
615 {
616 uint32_t timestamp : 16; /*!< FlexCAN internal Free-Running Counter Time Stamp. */
617 uint32_t length : 4; /*!< CAN frame data length in bytes (Range: 0~8). */
618 uint32_t type : 1; /*!< CAN Frame Type(DATA or REMOTE). */
619 uint32_t format : 1; /*!< CAN Frame Identifier(STD or EXT format). */
620 uint32_t : 1; /*!< Reserved. */
621 uint32_t idhit : 9; /*!< CAN Rx FIFO filter hit id(This value is only used in Rx FIFO receive mode). */
622 };
623 struct
624 {
625 uint32_t id : 29; /*!< CAN Frame Identifier, should be set using FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro. */
626 uint32_t : 3; /*!< Reserved. */
627 };
628 union
629 {
630 struct
631 {
632 uint32_t dataWord0; /*!< CAN Frame payload word0. */
633 uint32_t dataWord1; /*!< CAN Frame payload word1. */
634 };
635 struct
636 {
637 uint8_t dataByte3; /*!< CAN Frame payload byte3. */
638 uint8_t dataByte2; /*!< CAN Frame payload byte2. */
639 uint8_t dataByte1; /*!< CAN Frame payload byte1. */
640 uint8_t dataByte0; /*!< CAN Frame payload byte0. */
641 uint8_t dataByte7; /*!< CAN Frame payload byte7. */
642 uint8_t dataByte6; /*!< CAN Frame payload byte6. */
643 uint8_t dataByte5; /*!< CAN Frame payload byte5. */
644 uint8_t dataByte4; /*!< CAN Frame payload byte4. */
645 };
646 };
647 } flexcan_frame_t;
648
649 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
650 /*! @brief CAN FD message frame structure.
651 *
652 * The CAN FD message supporting up to sixty four bytes can be used for a data frame, depending on the length
653 * selected for the message buffers. The length should be a enumeration member, see @ref _flexcan_fd_frame_length.
654 */
655 typedef struct _flexcan_fd_frame
656 {
657 struct
658 {
659 uint32_t timestamp : 16; /*!< FlexCAN internal Free-Running Counter Time Stamp. */
660 uint32_t length : 4; /*!< CAN FD frame data length code (DLC), range see @ref _flexcan_fd_frame_length, When the
661 length <= 8, it equal to the data length, otherwise the number of valid frame data is
662 not equal to the length value. user can
663 use DLC_LENGTH_DECODE(length) macro to get the number of valid data bytes. */
664 uint32_t type : 1; /*!< CAN Frame Type(DATA or REMOTE). */
665 uint32_t format : 1; /*!< CAN Frame Identifier(STD or EXT format). */
666 uint32_t srr : 1; /*!< Substitute Remote request. */
667 uint32_t : 6;
668 uint32_t esi : 1; /*!< Error State Indicator. */
669 uint32_t brs : 1; /*!< Bit Rate Switch. */
670 uint32_t edl : 1; /*!< Extended Data Length. */
671 };
672 struct
673 {
674 uint32_t id : 29; /*!< CAN Frame Identifier, should be set using FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro. */
675 uint32_t : 3; /*!< Reserved. */
676 };
677 union
678 {
679 struct
680 {
681 uint32_t dataWord[16]; /*!< CAN FD Frame payload, 16 double word maximum. */
682 };
683 /* Note: the maximum databyte* below is actually 64, user can add them if needed,
684 or just use dataWord[*] instead. */
685 struct
686 {
687 uint8_t dataByte3; /*!< CAN Frame payload byte3. */
688 uint8_t dataByte2; /*!< CAN Frame payload byte2. */
689 uint8_t dataByte1; /*!< CAN Frame payload byte1. */
690 uint8_t dataByte0; /*!< CAN Frame payload byte0. */
691 uint8_t dataByte7; /*!< CAN Frame payload byte7. */
692 uint8_t dataByte6; /*!< CAN Frame payload byte6. */
693 uint8_t dataByte5; /*!< CAN Frame payload byte5. */
694 uint8_t dataByte4; /*!< CAN Frame payload byte4. */
695 };
696 };
697 #if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
698 /*! @note ID HIT offset is changed dynamically according to data length code (DLC), when DLC is 15, they will be
699 * located below. Using FLEXCAN_FixEnhancedRxFifoFrameIdHit API is recommended to ensure this idhit value is
700 * correct.*/
701 uint32_t idhit; /*!< CAN Enhanced Rx FIFO filter hit id (This value is only used in Enhanced Rx FIFO receive
702 mode). */
703 #endif
704 } flexcan_fd_frame_t;
705 #endif
706
707 /*! @brief FlexCAN protocol timing characteristic configuration structure. */
708 typedef struct _flexcan_timing_config
709 {
710 uint16_t preDivider; /*!< Classic CAN or CAN FD nominal phase bit rate prescaler. */
711 uint8_t rJumpwidth; /*!< Classic CAN or CAN FD nominal phase Re-sync Jump Width. */
712 uint8_t phaseSeg1; /*!< Classic CAN or CAN FD nominal phase Segment 1. */
713 uint8_t phaseSeg2; /*!< Classic CAN or CAN FD nominal phase Segment 2. */
714 uint8_t propSeg; /*!< Classic CAN or CAN FD nominal phase Propagation Segment. */
715 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
716 uint16_t fpreDivider; /*!< CAN FD data phase bit rate prescaler. */
717 uint8_t frJumpwidth; /*!< CAN FD data phase Re-sync Jump Width. */
718 uint8_t fphaseSeg1; /*!< CAN FD data phase Phase Segment 1. */
719 uint8_t fphaseSeg2; /*!< CAN FD data phase Phase Segment 2. */
720 uint8_t fpropSeg; /*!< CAN FD data phase Propagation Segment. */
721 #endif
722 } flexcan_timing_config_t;
723
724 /*! @brief FlexCAN module configuration structure.
725 * @deprecated Do not use the baudRate. It has been superceded bitRate
726 * @deprecated Do not use the baudRateFD. It has been superceded bitRateFD
727 */
728 typedef struct _flexcan_config
729 {
730 union
731 {
732 struct
733 {
734 uint32_t baudRate; /*!< FlexCAN bit rate in bps, for classical CAN or CANFD nominal phase. */
735 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
736 uint32_t baudRateFD; /*!< FlexCAN FD bit rate in bps, for CANFD data phase. */
737 #endif
738 };
739 struct
740 {
741 uint32_t bitRate; /*!< FlexCAN bit rate in bps, for classical CAN or CANFD nominal phase. */
742 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
743 uint32_t bitRateFD; /*!< FlexCAN FD bit rate in bps, for CANFD data phase. */
744 #endif
745 };
746 };
747 flexcan_clock_source_t clkSrc; /*!< Clock source for FlexCAN Protocol Engine. */
748 flexcan_wake_up_source_t wakeupSrc; /*!< Wake up source selection. */
749 uint8_t maxMbNum; /*!< The maximum number of Message Buffers used by user. */
750 bool enableLoopBack; /*!< Enable or Disable Loop Back Self Test Mode. */
751 bool enableTimerSync; /*!< Enable or Disable Timer Synchronization. */
752 bool enableSelfWakeup; /*!< Enable or Disable Self Wakeup Mode. */
753 bool enableIndividMask; /*!< Enable or Disable Rx Individual Mask and Queue feature. */
754 bool disableSelfReception; /*!< Enable or Disable Self Reflection. */
755 bool enableListenOnlyMode; /*!< Enable or Disable Listen Only Mode. */
756 #if !(defined(FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT)
757 bool enableSupervisorMode; /*!< Enable or Disable Supervisor Mode, enable this mode will make registers allow only
758 Supervisor access. */
759 #endif
760 #if (defined(FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT)
761 bool enableDoze; /*!< Enable or Disable Doze Mode. */
762 #endif
763 #if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE)
764 bool enablePretendedeNetworking; /*!< Enable or Disable the Pretended Networking mode. */
765 #endif
766 #if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL)
767 bool enableMemoryErrorControl; /*!< Enable or Disable the memory errors detection and correction mechanism. */
768 bool enableNonCorrectableErrorEnterFreeze; /*!< Enable or Disable Non-Correctable Errors In FlexCAN Access Put
769 Device In Freeze Mode. */
770 #endif
771 #if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG)
772 bool enableTransceiverDelayMeasure; /*!< Enable or Disable the transceiver delay measurement, when it is enabled,
773 then the secondary sample point position is determined by the sum of the
774 transceiver delay measurement plus the enhanced TDC offset. */
775 #endif
776 flexcan_timing_config_t timingConfig; /* Protocol timing . */
777 } flexcan_config_t;
778
779 /*!
780 * @brief FlexCAN Receive Message Buffer configuration structure
781 *
782 * This structure is used as the parameter of FLEXCAN_SetRxMbConfig() function.
783 * The FLEXCAN_SetRxMbConfig() function is used to configure FlexCAN Receive
784 * Message Buffer. The function abort previous receiving process, clean the
785 * Message Buffer and activate the Rx Message Buffer using given Message Buffer
786 * setting.
787 */
788 typedef struct _flexcan_rx_mb_config
789 {
790 uint32_t id; /*!< CAN Message Buffer Frame Identifier, should be set using
791 FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro. */
792 flexcan_frame_format_t format; /*!< CAN Frame Identifier format(Standard of Extend). */
793 flexcan_frame_type_t type; /*!< CAN Frame Type(Data or Remote). */
794 } flexcan_rx_mb_config_t;
795
796 #if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE)
797 /*! @brief FlexCAN Pretended Networking match source selection. */
798 typedef enum _flexcan_pn_match_source
799 {
800 kFLEXCAN_PNMatSrcID = 0U, /*!< Message match with ID filtering. */
801 kFLEXCAN_PNMatSrcIDAndData, /*!< Message match with ID filtering and payload filtering. */
802 } flexcan_pn_match_source_t;
803
804 /*! @brief FlexCAN Pretended Networking mode match type. */
805 typedef enum _flexcan_pn_match_mode
806 {
807 kFLEXCAN_PNMatModeEqual = 0x0U, /*!< Match upon ID/Payload contents against an exact target value. */
808 kFLEXCAN_PNMatModeGreater, /*!< Match upon an ID/Payload value greater than or equal to a specified target value.
809 */
810 kFLEXCAN_PNMatModeSmaller, /*!< Match upon an ID/Payload value smaller than or equal to a specified target value.
811 */
812 kFLEXCAN_PNMatModeRange, /*!< Match upon an ID/Payload value inside a range, greater than or equal to a specified
813 lower limit, and smaller than or equal to a specified upper limit */
814 } flexcan_pn_match_mode_t;
815
816 /*!
817 * @brief FlexCAN Pretended Networking configuration structure
818 *
819 * This structure is used as the parameter of FLEXCAN_SetPNConfig() function.
820 * The FLEXCAN_SetPNConfig() function is used to configure FlexCAN Networking work mode.
821 */
822 typedef struct _flexcan_pn_config
823 {
824 bool enableTimeout; /*!< Enable or Disable timeout event trigger wakeup.*/
825 uint16_t timeoutValue; /*!< The timeout value that generates a wakeup event, the counter timer is incremented based
826 on 64 times the CAN Bit Time unit. */
827 bool enableMatch; /*!< Enable or Disable match event trigger wakeup.*/
828 flexcan_pn_match_source_t matchSrc; /*!< Selects the match source (ID and/or data match) to trigger wakeup. */
829 uint8_t matchNum; /*!< The number of times a given message must match the predefined ID and/or data before
830 generating a wakeup event, range in 0x1 ~ 0xFF. */
831 flexcan_pn_match_mode_t idMatchMode; /*!< The ID match type. */
832 flexcan_pn_match_mode_t dataMatchMode; /*!< The data match type. */
833 uint32_t idLower; /*!< The ID target values 1 which used either for ID match "equal to", "smaller than",
834 "greater than" comparisons, or as the lower limit value in ID match "range detection". */
835 uint32_t idUpper; /*!< The ID target values 2 which used only as the upper limit value in ID match "range
836 detection" or used to store the ID mask in "equal to". */
837 uint8_t lengthLower; /*!< The lower limit for length of data bytes which used only in data match "range
838 detection". Range in 0x0 ~ 0x8.*/
839 uint8_t lengthUpper; /*!< The upper limit for length of data bytes which used only in data match "range
840 detection". Range in 0x0 ~ 0x8.*/
841 union
842 {
843 /*!< The data target values 1 which used either for data match "equal to", "smaller than",
844 "greater than" comparisons, or as the lower limit value in data match "range
845 detection". */
846 struct
847 {
848 uint32_t lowerWord0; /*!< CAN Frame payload word0. */
849 uint32_t lowerWord1; /*!< CAN Frame payload word1. */
850 };
851 struct
852 {
853 uint8_t lowerByte3; /*!< CAN Frame payload byte3. */
854 uint8_t lowerByte2; /*!< CAN Frame payload byte2. */
855 uint8_t lowerByte1; /*!< CAN Frame payload byte1. */
856 uint8_t lowerByte0; /*!< CAN Frame payload byte0. */
857 uint8_t lowerByte7; /*!< CAN Frame payload byte7. */
858 uint8_t lowerByte6; /*!< CAN Frame payload byte6. */
859 uint8_t lowerByte5; /*!< CAN Frame payload byte5. */
860 uint8_t lowerByte4; /*!< CAN Frame payload byte4. */
861 };
862 };
863 union
864 {
865 /*!< The data target values 2 which used only as the upper limit value in data match "range
866 detection" or used to store the data mask in "equal to". */
867 struct
868 {
869 uint32_t upperWord0; /*!< CAN Frame payload word0. */
870 uint32_t upperWord1; /*!< CAN Frame payload word1. */
871 };
872 struct
873 {
874 uint8_t upperByte3; /*!< CAN Frame payload byte3. */
875 uint8_t upperByte2; /*!< CAN Frame payload byte2. */
876 uint8_t upperByte1; /*!< CAN Frame payload byte1. */
877 uint8_t upperByte0; /*!< CAN Frame payload byte0. */
878 uint8_t upperByte7; /*!< CAN Frame payload byte7. */
879 uint8_t upperByte6; /*!< CAN Frame payload byte6. */
880 uint8_t upperByte5; /*!< CAN Frame payload byte5. */
881 uint8_t upperByte4; /*!< CAN Frame payload byte4. */
882 };
883 };
884 } flexcan_pn_config_t;
885 #endif
886
887 /*! @brief FlexCAN Legacy Rx FIFO configuration structure. */
888 typedef struct _flexcan_rx_fifo_config
889 {
890 uint32_t *idFilterTable; /*!< Pointer to the FlexCAN Legacy Rx FIFO identifier filter table. */
891 uint8_t idFilterNum; /*!< The FlexCAN Legacy Rx FIFO Filter elements quantity. */
892 flexcan_rx_fifo_filter_type_t idFilterType; /*!< The FlexCAN Legacy Rx FIFO Filter type. */
893 flexcan_rx_fifo_priority_t priority; /*!< The FlexCAN Legacy Rx FIFO receive priority. */
894 } flexcan_rx_fifo_config_t;
895
896 #if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
897 /*! @brief FlexCAN Enhanced Rx FIFO Standard ID filter element structure. */
898 typedef struct _flexcan_enhanced_rx_fifo_std_id_filter
899 {
900 uint32_t filterType : 2; /*!< FlexCAN internal Free-Running Counter Time Stamp. */
901 uint32_t : 2;
902 uint32_t rtr1 : 1; /*!< CAN FD frame data length code (DLC), range see @ref _flexcan_fd_frame_length, When the
903 length <= 8, it equal to the data length, otherwise the number of valid frame data is
904 not equal to the length value. user can
905 use DLC_LENGTH_DECODE(length) macro to get the number of valid data bytes. */
906 uint32_t std1 : 11; /*!< CAN Frame Type(DATA or REMOTE). */
907 uint32_t : 4;
908 uint32_t rtr2 : 1; /*!< CAN Frame Identifier(STD or EXT format). */
909 uint32_t std2 : 11; /*!< Substitute Remote request. */
910 } flexcan_enhanced_rx_fifo_std_id_filter_t;
911
912 /*! @brief FlexCAN Enhanced Rx FIFO Extended ID filter element structure. */
913 typedef struct _flexcan_enhanced_rx_fifo_ext_id_filter
914 {
915 uint32_t filterType : 2; /*!< FlexCAN internal Free-Running Counter Time Stamp. */
916 uint32_t rtr1 : 1; /*!< CAN FD frame data length code (DLC), range see @ref _flexcan_fd_frame_length, When the
917 length <= 8, it equal to the data length, otherwise the number of valid frame data is
918 not equal to the length value. user can
919 use DLC_LENGTH_DECODE(length) macro to get the number of valid data bytes. */
920 uint32_t std1 : 29; /*!< CAN Frame Type(DATA or REMOTE). */
921 uint32_t : 2;
922 uint32_t rtr2 : 1; /*!< CAN Frame Identifier(STD or EXT format). */
923 uint32_t std2 : 29; /*!< Substitute Remote request. */
924 } flexcan_enhanced_rx_fifo_ext_id_filter_t;
925 /*! @brief FlexCAN Enhanced Rx FIFO configuration structure. */
926 typedef struct _flexcan_enhanced_rx_fifo_config
927 {
928 uint32_t *idFilterTable; /*!< Pointer to the FlexCAN Enhanced Rx FIFO identifier filter table, each table member
929 occupies 32 bit word, table size should be equal to idFilterNum. There are two types of
930 Enhanced Rx FIFO filter elements that can be stored in table : extended-ID filter element
931 (1 word, occupie 1 table members) and standard-ID filter element (2 words, occupies 2 table
932 members), the extended-ID filter element needs to be placed in front of the table. */
933 uint8_t idFilterPairNum; /*!< idFilterPairNum is the Enhanced Rx FIFO identifier filter element pair numbers,
934 each pair of filter elements occupies 2 words and can consist of one extended ID filter
935 element or two standard ID filter elements. */
936 uint8_t extendIdFilterNum; /*!< The number of extended ID filter element items in the FlexCAN enhanced Rx FIFO
937 identifier filter table, each extended-ID filter element occupies 2 words,
938 extendIdFilterNum need less than or equal to idFilterPairNum. */
939 uint8_t fifoWatermark; /*!< (fifoWatermark + 1) is the minimum number of CAN messages stored in the Enhanced RX FIFO
940 which can trigger FIFO watermark interrupt or a DMA request. */
941 flexcan_efifo_dma_per_read_length_t dmaPerReadLength; /*!< Define the length of each read of the Enhanced RX FIFO
942 element by the DAM, see @ref _flexcan_fd_frame_length. */
943 flexcan_rx_fifo_priority_t priority; /*!< The FlexCAN Enhanced Rx FIFO receive priority. */
944 } flexcan_enhanced_rx_fifo_config_t;
945 #endif
946
947 /*! @brief FlexCAN Message Buffer transfer. */
948 typedef struct _flexcan_mb_transfer
949 {
950 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
951 flexcan_fd_frame_t *framefd;
952 #endif
953 flexcan_frame_t *frame; /*!< The buffer of CAN Message to be transfer. */
954 uint8_t mbIdx; /*!< The index of Message buffer used to transfer Message. */
955 } flexcan_mb_transfer_t;
956
957 /*! @brief FlexCAN Rx FIFO transfer. */
958 typedef struct _flexcan_fifo_transfer
959 {
960 #if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
961 flexcan_fd_frame_t *framefd; /*!< The buffer of CAN Message to be received from Enhanced Rx FIFO. */
962 #endif
963 flexcan_frame_t *frame; /*!< The buffer of CAN Message to be received from Legacy Rx FIFO. */
964 size_t frameNum; /*!< Number of CAN Message need to be received from Legacy or Ehanced Rx FIFO. */
965 } flexcan_fifo_transfer_t;
966
967 /*! @brief FlexCAN handle structure definition. */
968 typedef struct _flexcan_handle flexcan_handle_t;
969
970 /*! @brief FlexCAN transfer callback function.
971 *
972 * The FlexCAN transfer callback returns a value from the underlying layer.
973 * If the status equals to kStatus_FLEXCAN_ErrorStatus, the result parameter is the Content of
974 * FlexCAN status register which can be used to get the working status(or error status) of FlexCAN module.
975 * If the status equals to other FlexCAN Message Buffer transfer status, the result is the index of
976 * Message Buffer that generate transfer event.
977 * If the status equals to other FlexCAN Message Buffer transfer status, the result is meaningless and should be
978 * Ignored.
979 */
980 #if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) || \
981 (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL)
982 #define FLEXCAN_CALLBACK(x) \
983 void(x)(CAN_Type * base, flexcan_handle_t * handle, status_t status, uint64_t result, void *userData)
984 typedef void (*flexcan_transfer_callback_t)(
985 CAN_Type *base, flexcan_handle_t *handle, status_t status, uint64_t result, void *userData);
986 #else
987 #define FLEXCAN_CALLBACK(x) \
988 void(x)(CAN_Type * base, flexcan_handle_t * handle, status_t status, uint32_t result, void *userData)
989 typedef void (*flexcan_transfer_callback_t)(
990 CAN_Type *base, flexcan_handle_t *handle, status_t status, uint32_t result, void *userData);
991 #endif
992
993 /*! @brief FlexCAN handle structure. */
994 struct _flexcan_handle
995 {
996 flexcan_transfer_callback_t callback; /*!< Callback function. */
997 void *userData; /*!< FlexCAN callback function parameter.*/
998 flexcan_frame_t
999 *volatile mbFrameBuf[CAN_WORD1_COUNT]; /*!< The buffer for received CAN data from Message Buffers. */
1000 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
1001 flexcan_fd_frame_t
1002 *volatile mbFDFrameBuf[CAN_WORD1_COUNT]; /*!< The buffer for received CAN FD data from Message Buffers. */
1003 #endif
1004 flexcan_frame_t *volatile rxFifoFrameBuf; /*!< The buffer for received CAN data from Legacy Rx FIFO. */
1005 #if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
1006 flexcan_fd_frame_t *volatile rxFifoFDFrameBuf; /*!< The buffer for received CAN FD data from Ehanced Rx FIFO. */
1007 #endif
1008 size_t rxFifoFrameNum; /*!< The number of CAN messages remaining to be received from Legacy or Ehanced Rx FIFO. */
1009 size_t rxFifoTransferTotalNum; /*!< Total CAN Message number need to be received from Legacy or Ehanced Rx FIFO. */
1010 volatile uint8_t mbState[CAN_WORD1_COUNT]; /*!< Message Buffer transfer state. */
1011 volatile uint8_t rxFifoState; /*!< Rx FIFO transfer state. */
1012 volatile uint32_t timestamp[CAN_WORD1_COUNT]; /*!< Mailbox transfer timestamp. */
1013 };
1014
1015 /******************************************************************************
1016 * API
1017 *****************************************************************************/
1018
1019 #if defined(__cplusplus)
1020 extern "C" {
1021 #endif
1022
1023 /*!
1024 * @name Initialization and deinitialization
1025 * @{
1026 */
1027
1028 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
1029 /*!
1030 * @brief Determine whether the FlexCAN instance support CAN FD mode at run time.
1031 *
1032 * @note Use this API only if different soc parts share the SOC part name macro define. Otherwise, a different SOC part
1033 * name can be used to determine at compile time whether the FlexCAN instance supports CAN FD mode or not.
1034 * If need use this API to determine if CAN FD mode is supported, the FLEXCAN_Init function needs to be
1035 * executed first, and then call this API and use the return to value determines whether to supports CAN FD mode,
1036 * if return true, continue calling FLEXCAN_FDInit to enable CAN FD mode.
1037 *
1038 * @param base FlexCAN peripheral base address.
1039 * @return return TRUE if instance support CAN FD mode, FALSE if instance only support classic CAN (2.0) mode.
1040 */
1041 bool FLEXCAN_IsInstanceHasFDMode(CAN_Type *base);
1042 #endif
1043
1044 /*!
1045 * @brief Enter FlexCAN Freeze Mode.
1046 *
1047 * This function makes the FlexCAN work under Freeze Mode.
1048 *
1049 * @param base FlexCAN peripheral base address.
1050 */
1051 void FLEXCAN_EnterFreezeMode(CAN_Type *base);
1052
1053 /*!
1054 * @brief Exit FlexCAN Freeze Mode.
1055 *
1056 * This function makes the FlexCAN leave Freeze Mode.
1057 *
1058 * @param base FlexCAN peripheral base address.
1059 */
1060 void FLEXCAN_ExitFreezeMode(CAN_Type *base);
1061
1062 /*!
1063 * @brief Get the FlexCAN instance from peripheral base address.
1064 *
1065 * @param base FlexCAN peripheral base address.
1066 * @return FlexCAN instance.
1067 */
1068 uint32_t FLEXCAN_GetInstance(CAN_Type *base);
1069
1070 /*!
1071 * @brief Calculates the improved timing values by specific bit Rates for classical CAN.
1072 *
1073 * This function use to calculates the Classical CAN timing values according to the given bit rate. The Calculated
1074 * timing values will be set in CTRL1/CBT/ENCBT register. The calculation is based on the recommendation of the CiA 301
1075 * v4.2.0 and previous version document.
1076 *
1077 * @param base FlexCAN peripheral base address.
1078 * @param bitRate The classical CAN speed in bps defined by user, should be less than or equal to 1Mbps.
1079 * @param sourceClock_Hz The Source clock frequency in Hz.
1080 * @param pTimingConfig Pointer to the FlexCAN timing configuration structure.
1081 *
1082 * @return TRUE if timing configuration found, FALSE if failed to find configuration.
1083 */
1084 bool FLEXCAN_CalculateImprovedTimingValues(CAN_Type *base,
1085 uint32_t bitRate,
1086 uint32_t sourceClock_Hz,
1087 flexcan_timing_config_t *pTimingConfig);
1088
1089 /*!
1090 * @brief Initializes a FlexCAN instance.
1091 *
1092 * This function initializes the FlexCAN module with user-defined settings.
1093 * This example shows how to set up the flexcan_config_t parameters and how
1094 * to call the FLEXCAN_Init function by passing in these parameters.
1095 * @code
1096 * flexcan_config_t flexcanConfig;
1097 * flexcanConfig.clkSrc = kFLEXCAN_ClkSrc0;
1098 * flexcanConfig.bitRate = 1000000U;
1099 * flexcanConfig.maxMbNum = 16;
1100 * flexcanConfig.enableLoopBack = false;
1101 * flexcanConfig.enableSelfWakeup = false;
1102 * flexcanConfig.enableIndividMask = false;
1103 * flexcanConfig.enableDoze = false;
1104 * flexcanConfig.disableSelfReception = false;
1105 * flexcanConfig.enableListenOnlyMode = false;
1106 * flexcanConfig.timingConfig = timingConfig;
1107 * FLEXCAN_Init(CAN0, &flexcanConfig, 40000000UL);
1108 * @endcode
1109 *
1110 * @param base FlexCAN peripheral base address.
1111 * @param pConfig Pointer to the user-defined configuration structure.
1112 * @param sourceClock_Hz FlexCAN Protocol Engine clock source frequency in Hz.
1113 */
1114 void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *pConfig, uint32_t sourceClock_Hz);
1115
1116 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
1117 /*!
1118 * @brief Calculates the improved timing values by specific bit rates for CANFD.
1119 *
1120 * This function use to calculates the CANFD timing values according to the given nominal phase bit rate and data phase
1121 * bit rate. The Calculated timing values will be set in CBT/ENCBT and FDCBT/EDCBT registers. The calculation is based
1122 * on the recommendation of the CiA 1301 v1.0.0 document.
1123 *
1124 * @param base FlexCAN peripheral base address.
1125 * @param bitRate The CANFD bus control speed in bps defined by user.
1126 * @param bitRateFD The CAN FD data phase speed in bps defined by user. Equal to bitRate means disable bit rate
1127 * switching.
1128 * @param sourceClock_Hz The Source clock frequency in Hz.
1129 * @param pTimingConfig Pointer to the FlexCAN timing configuration structure.
1130 *
1131 * @return TRUE if timing configuration found, FALSE if failed to find configuration
1132 */
1133 bool FLEXCAN_FDCalculateImprovedTimingValues(CAN_Type *base,
1134 uint32_t bitRate,
1135 uint32_t bitRateFD,
1136 uint32_t sourceClock_Hz,
1137 flexcan_timing_config_t *pTimingConfig);
1138 /*!
1139 * @brief Initializes a FlexCAN instance.
1140 *
1141 * This function initializes the FlexCAN module with user-defined settings.
1142 * This example shows how to set up the flexcan_config_t parameters and how
1143 * to call the FLEXCAN_FDInit function by passing in these parameters.
1144 * @code
1145 * flexcan_config_t flexcanConfig;
1146 * flexcanConfig.clkSrc = kFLEXCAN_ClkSrc0;
1147 * flexcanConfig.bitRate = 1000000U;
1148 * flexcanConfig.bitRateFD = 2000000U;
1149 * flexcanConfig.maxMbNum = 16;
1150 * flexcanConfig.enableLoopBack = false;
1151 * flexcanConfig.enableSelfWakeup = false;
1152 * flexcanConfig.enableIndividMask = false;
1153 * flexcanConfig.disableSelfReception = false;
1154 * flexcanConfig.enableListenOnlyMode = false;
1155 * flexcanConfig.enableDoze = false;
1156 * flexcanConfig.timingConfig = timingConfig;
1157 * FLEXCAN_FDInit(CAN0, &flexcanConfig, 80000000UL, kFLEXCAN_16BperMB, true);
1158 * @endcode
1159 *
1160 * @param base FlexCAN peripheral base address.
1161 * @param pConfig Pointer to the user-defined configuration structure.
1162 * @param sourceClock_Hz FlexCAN Protocol Engine clock source frequency in Hz.
1163 * @param dataSize FlexCAN Message Buffer payload size. The actual transmitted or received CAN FD frame data size needs
1164 * to be less than or equal to this value.
1165 * @param brs True if bit rate switch is enabled in FD mode.
1166 */
1167 void FLEXCAN_FDInit(
1168 CAN_Type *base, const flexcan_config_t *pConfig, uint32_t sourceClock_Hz, flexcan_mb_size_t dataSize, bool brs);
1169 #endif
1170
1171 /*!
1172 * @brief De-initializes a FlexCAN instance.
1173 *
1174 * This function disables the FlexCAN module clock and sets all register values
1175 * to the reset value.
1176 *
1177 * @param base FlexCAN peripheral base address.
1178 */
1179 void FLEXCAN_Deinit(CAN_Type *base);
1180
1181 /*!
1182 * @brief Gets the default configuration structure.
1183 *
1184 * This function initializes the FlexCAN configuration structure to default values. The default
1185 * values are as follows.
1186 * flexcanConfig->clkSrc = kFLEXCAN_ClkSrc0;
1187 * flexcanConfig->bitRate = 1000000U;
1188 * flexcanConfig->bitRateFD = 2000000U;
1189 * flexcanConfig->maxMbNum = 16;
1190 * flexcanConfig->enableLoopBack = false;
1191 * flexcanConfig->enableSelfWakeup = false;
1192 * flexcanConfig->enableIndividMask = false;
1193 * flexcanConfig->disableSelfReception = false;
1194 * flexcanConfig->enableListenOnlyMode = false;
1195 * flexcanConfig->enableDoze = false;
1196 * flexcanConfig->enableMemoryErrorControl = true;
1197 * flexcanConfig->enableNonCorrectableErrorEnterFreeze = true;
1198 * flexcanConfig.timingConfig = timingConfig;
1199 *
1200 * @param pConfig Pointer to the FlexCAN configuration structure.
1201 */
1202 void FLEXCAN_GetDefaultConfig(flexcan_config_t *pConfig);
1203
1204 /* @} */
1205
1206 /*!
1207 * @name Configuration.
1208 * @{
1209 */
1210
1211 /*!
1212 * @brief Sets the FlexCAN classical CAN protocol timing characteristic.
1213 *
1214 * This function gives user settings to classical CAN or CAN FD nominal phase timing characteristic.
1215 * The function is for an experienced user. For less experienced users, call the FLEXCAN_SetBitRate() instead.
1216 *
1217 * @note Calling FLEXCAN_SetTimingConfig() overrides the bit rate set in FLEXCAN_Init() or FLEXCAN_SetBitRate().
1218 *
1219 * @param base FlexCAN peripheral base address.
1220 * @param pConfig Pointer to the timing configuration structure.
1221 */
1222 void FLEXCAN_SetTimingConfig(CAN_Type *base, const flexcan_timing_config_t *pConfig);
1223
1224 /*!
1225 * @brief Set bit rate of FlexCAN classical CAN frame or CAN FD frame nominal phase.
1226 *
1227 * This function set the bit rate of classical CAN frame or CAN FD frame nominal phase base on
1228 * FLEXCAN_CalculateImprovedTimingValues() API calculated timing values.
1229 *
1230 * @note Calling FLEXCAN_SetBitRate() overrides the bit rate set in FLEXCAN_Init().
1231 *
1232 * @param base FlexCAN peripheral base address.
1233 * @param sourceClock_Hz Source Clock in Hz.
1234 * @param bitRate_Bps Bit rate in Bps.
1235 * @return kStatus_Success - Set CAN baud rate (only Nominal phase) successfully.
1236 */
1237 status_t FLEXCAN_SetBitRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t bitRate_Bps);
1238
1239 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
1240 /*!
1241 * @brief Sets the FlexCAN CANFD data phase timing characteristic.
1242 *
1243 * This function gives user settings to CANFD data phase timing characteristic.
1244 * The function is for an experienced user. For less experienced users, call the FLEXCAN_SetFDBitRate()
1245 * to set both Nominal/Data bit Rate instead.
1246 *
1247 * @note Calling FLEXCAN_SetFDTimingConfig() overrides the data phase bit rate set in
1248 * FLEXCAN_FDInit()/FLEXCAN_SetFDBitRate().
1249 *
1250 * @param base FlexCAN peripheral base address.
1251 * @param pConfig Pointer to the timing configuration structure.
1252 */
1253 void FLEXCAN_SetFDTimingConfig(CAN_Type *base, const flexcan_timing_config_t *pConfig);
1254
1255 /*!
1256 * @brief Set bit rate of FlexCAN FD frame.
1257 *
1258 * This function set the baud rate of FLEXCAN FD base on FLEXCAN_FDCalculateImprovedTimingValues() API calculated timing
1259 * values.
1260 *
1261 * @param base FlexCAN peripheral base address.
1262 * @param sourceClock_Hz Source Clock in Hz.
1263 * @param bitRateN_Bps Nominal bit Rate in Bps.
1264 * @param bitRateD_Bps Data bit Rate in Bps.
1265 * @return kStatus_Success - Set CAN FD bit rate (include Nominal and Data phase) successfully.
1266 */
1267 status_t FLEXCAN_SetFDBitRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t bitRateN_Bps, uint32_t bitRateD_Bps);
1268 #endif
1269
1270 /*!
1271 * @brief Sets the FlexCAN receive message buffer global mask.
1272 *
1273 * This function sets the global mask for the FlexCAN message buffer in a matching process.
1274 * The configuration is only effective when the Rx individual mask is disabled in the FLEXCAN_Init().
1275 *
1276 * @param base FlexCAN peripheral base address.
1277 * @param mask Rx Message Buffer Global Mask value.
1278 */
1279 void FLEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask);
1280
1281 /*!
1282 * @brief Sets the FlexCAN receive FIFO global mask.
1283 *
1284 * This function sets the global mask for FlexCAN FIFO in a matching process.
1285 *
1286 * @param base FlexCAN peripheral base address.
1287 * @param mask Rx Fifo Global Mask value.
1288 */
1289 void FLEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask);
1290
1291 /*!
1292 * @brief Sets the FlexCAN receive individual mask.
1293 *
1294 * This function sets the individual mask for the FlexCAN matching process.
1295 * The configuration is only effective when the Rx individual mask is enabled in the FLEXCAN_Init().
1296 * If the Rx FIFO is disabled, the individual mask is applied to the corresponding Message Buffer.
1297 * If the Rx FIFO is enabled, the individual mask for Rx FIFO occupied Message Buffer is applied to
1298 * the Rx Filter with the same index. Note that only the first 32
1299 * individual masks can be used as the Rx FIFO filter mask.
1300 *
1301 * @param base FlexCAN peripheral base address.
1302 * @param maskIdx The Index of individual Mask.
1303 * @param mask Rx Individual Mask value.
1304 */
1305 void FLEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask);
1306
1307 /*!
1308 * @brief Configures a FlexCAN transmit message buffer.
1309 *
1310 * This function aborts the previous transmission, cleans the Message Buffer, and
1311 * configures it as a Transmit Message Buffer.
1312 *
1313 * @param base FlexCAN peripheral base address.
1314 * @param mbIdx The Message Buffer index.
1315 * @param enable Enable/disable Tx Message Buffer.
1316 * - true: Enable Tx Message Buffer.
1317 * - false: Disable Tx Message Buffer.
1318 */
1319 void FLEXCAN_SetTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable);
1320
1321 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
1322 /*!
1323 * @brief Configures a FlexCAN transmit message buffer.
1324 *
1325 * This function aborts the previous transmission, cleans the Message Buffer, and
1326 * configures it as a Transmit Message Buffer.
1327 *
1328 * @param base FlexCAN peripheral base address.
1329 * @param mbIdx The Message Buffer index.
1330 * @param enable Enable/disable Tx Message Buffer.
1331 * - true: Enable Tx Message Buffer.
1332 * - false: Disable Tx Message Buffer.
1333 */
1334 void FLEXCAN_SetFDTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable);
1335 #endif
1336
1337 /*!
1338 * @brief Configures a FlexCAN Receive Message Buffer.
1339 *
1340 * This function cleans a FlexCAN build-in Message Buffer and configures it
1341 * as a Receive Message Buffer.
1342 *
1343 * @param base FlexCAN peripheral base address.
1344 * @param mbIdx The Message Buffer index.
1345 * @param pRxMbConfig Pointer to the FlexCAN Message Buffer configuration structure.
1346 * @param enable Enable/disable Rx Message Buffer.
1347 * - true: Enable Rx Message Buffer.
1348 * - false: Disable Rx Message Buffer.
1349 */
1350 void FLEXCAN_SetRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_config_t *pRxMbConfig, bool enable);
1351
1352 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
1353 /*!
1354 * @brief Configures a FlexCAN Receive Message Buffer.
1355 *
1356 * This function cleans a FlexCAN build-in Message Buffer and configures it
1357 * as a Receive Message Buffer.
1358 *
1359 * @param base FlexCAN peripheral base address.
1360 * @param mbIdx The Message Buffer index.
1361 * @param pRxMbConfig Pointer to the FlexCAN Message Buffer configuration structure.
1362 * @param enable Enable/disable Rx Message Buffer.
1363 * - true: Enable Rx Message Buffer.
1364 * - false: Disable Rx Message Buffer.
1365 */
1366 void FLEXCAN_SetFDRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_config_t *pRxMbConfig, bool enable);
1367 #endif
1368
1369 /*!
1370 * @brief Configures the FlexCAN Legacy Rx FIFO.
1371 *
1372 * This function configures the FlexCAN Rx FIFO with given configuration.
1373 * @note Legacy Rx FIFO only can receive classic CAN message.
1374 *
1375 * @param base FlexCAN peripheral base address.
1376 * @param pRxFifoConfig Pointer to the FlexCAN Legacy Rx FIFO configuration structure. Can be NULL when enable parameter
1377 * is false.
1378 * @param enable Enable/disable Legacy Rx FIFO.
1379 * - true: Enable Legacy Rx FIFO.
1380 * - false: Disable Legacy Rx FIFO.
1381 */
1382 void FLEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *pRxFifoConfig, bool enable);
1383
1384 #if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
1385 /*!
1386 * @brief Configures the FlexCAN Enhanced Rx FIFO.
1387 *
1388 * This function configures the Enhanced Rx FIFO with given configuration.
1389 * @note Enhanced Rx FIFO support receive classic CAN or CAN FD messages, Legacy Rx FIFO and Enhanced Rx FIFO
1390 * cannot be enabled at the same time.
1391 *
1392 * @param base FlexCAN peripheral base address.
1393 * @param pConfig Pointer to the FlexCAN Enhanced Rx FIFO configuration structure. Can be NULL when enable parameter
1394 * is false.
1395 * @param enable Enable/disable Enhanced Rx FIFO.
1396 * - true: Enable Enhanced Rx FIFO.
1397 * - false: Disable Enhanced Rx FIFO.
1398 */
1399 void FLEXCAN_SetEnhancedRxFifoConfig(CAN_Type *base, const flexcan_enhanced_rx_fifo_config_t *pConfig, bool enable);
1400 #endif
1401
1402 #if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE)
1403 /*!
1404 * @brief Configures the FlexCAN Pretended Networking mode.
1405 *
1406 * This function configures the FlexCAN Pretended Networking mode with given configuration.
1407 *
1408 * @param base FlexCAN peripheral base address.
1409 * @param pConfig Pointer to the FlexCAN Rx FIFO configuration structure.
1410 */
1411 void FLEXCAN_SetPNConfig(CAN_Type *base, const flexcan_pn_config_t *pConfig);
1412 #endif
1413 /* @} */
1414
1415 /*!
1416 * @name Status
1417 * @{
1418 */
1419
1420 /*!
1421 * @brief Gets the FlexCAN module interrupt flags.
1422 *
1423 * This function gets all FlexCAN status flags. The flags are returned as the logical
1424 * OR value of the enumerators @ref _flexcan_flags. To check the specific status,
1425 * compare the return value with enumerators in @ref _flexcan_flags.
1426 *
1427 * @param base FlexCAN peripheral base address.
1428 * @return FlexCAN status flags which are ORed by the enumerators in the _flexcan_flags.
1429 */
1430 #if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) || \
1431 (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) || \
1432 (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL)
FLEXCAN_GetStatusFlags(CAN_Type * base)1433 static inline uint64_t FLEXCAN_GetStatusFlags(CAN_Type *base)
1434 {
1435 uint64_t tempflag = (uint64_t)base->ESR1;
1436 #if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE)
1437 /* Get PN Wake Up status. */
1438 tempflag |= FLEXCAN_PN_STATUS_MASK(base->WU_MTC);
1439 #endif
1440 #if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
1441 /* Get Enhanced Rx FIFO status. */
1442 tempflag |= FLEXCAN_EFIFO_STATUS_MASK(base->ERFSR);
1443 #endif
1444 #if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL)
1445 /* Get Memory Error status. */
1446 tempflag |= FLEXCAN_MECR_STATUS_MASK(base->ERRSR);
1447 #endif
1448 return tempflag;
1449 }
1450 #else
FLEXCAN_GetStatusFlags(CAN_Type * base)1451 static inline uint32_t FLEXCAN_GetStatusFlags(CAN_Type *base)
1452 {
1453 return base->ESR1;
1454 }
1455 #endif
1456 /*!
1457 * @brief Clears status flags with the provided mask.
1458 *
1459 * This function clears the FlexCAN status flags with a provided mask. An automatically cleared flag
1460 * can't be cleared by this function.
1461 *
1462 * @param base FlexCAN peripheral base address.
1463 * @param mask The status flags to be cleared, it is logical OR value of @ref _flexcan_flags.
1464 */
1465 #if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) || \
1466 (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) || \
1467 (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL)
FLEXCAN_ClearStatusFlags(CAN_Type * base,uint64_t mask)1468 static inline void FLEXCAN_ClearStatusFlags(CAN_Type *base, uint64_t mask)
1469 {
1470 #if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE)
1471 /* Clear PN Wake Up status. */
1472 base->WU_MTC = FLEXCAN_PN_STATUS_UNMASK(mask);
1473 #endif
1474 #if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
1475 /* Clear Enhanced Rx FIFO status. */
1476 base->ERFSR = FLEXCAN_EFIFO_STATUS_UNMASK(mask);
1477 #endif
1478 #if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL)
1479 /* Clear Memory Error status. */
1480 base->ERRSR = FLEXCAN_MECR_STATUS_UNMASK(mask);
1481 #endif
1482 base->ESR1 = (uint32_t)(mask & 0xFFFFFFFFU);
1483 }
1484 #else
FLEXCAN_ClearStatusFlags(CAN_Type * base,uint32_t mask)1485 static inline void FLEXCAN_ClearStatusFlags(CAN_Type *base, uint32_t mask)
1486 {
1487 /* Write 1 to clear status flag. */
1488 base->ESR1 = mask;
1489 }
1490 #endif
1491 /*!
1492 * @brief Gets the FlexCAN Bus Error Counter value.
1493 *
1494 * This function gets the FlexCAN Bus Error Counter value for both Tx and
1495 * Rx direction. These values may be needed in the upper layer error handling.
1496 *
1497 * @param base FlexCAN peripheral base address.
1498 * @param txErrBuf Buffer to store Tx Error Counter value.
1499 * @param rxErrBuf Buffer to store Rx Error Counter value.
1500 */
FLEXCAN_GetBusErrCount(CAN_Type * base,uint8_t * txErrBuf,uint8_t * rxErrBuf)1501 static inline void FLEXCAN_GetBusErrCount(CAN_Type *base, uint8_t *txErrBuf, uint8_t *rxErrBuf)
1502 {
1503 if (NULL != txErrBuf)
1504 {
1505 *txErrBuf = (uint8_t)((base->ECR & CAN_ECR_TXERRCNT_MASK) >> CAN_ECR_TXERRCNT_SHIFT);
1506 }
1507
1508 if (NULL != rxErrBuf)
1509 {
1510 *rxErrBuf = (uint8_t)((base->ECR & CAN_ECR_RXERRCNT_MASK) >> CAN_ECR_RXERRCNT_SHIFT);
1511 }
1512 }
1513
1514 /*!
1515 * @brief Gets the FlexCAN Message Buffer interrupt flags.
1516 *
1517 * This function gets the interrupt flags of a given Message Buffers.
1518 *
1519 * @param base FlexCAN peripheral base address.
1520 * @param mask The ORed FlexCAN Message Buffer mask.
1521 * @return The status of given Message Buffers.
1522 */
1523 #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
FLEXCAN_GetMbStatusFlags(CAN_Type * base,uint64_t mask)1524 static inline uint64_t FLEXCAN_GetMbStatusFlags(CAN_Type *base, uint64_t mask)
1525 #else
1526 static inline uint32_t FLEXCAN_GetMbStatusFlags(CAN_Type *base, uint32_t mask)
1527 #endif
1528 {
1529 #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
1530 uint64_t tempflag = (uint64_t)base->IFLAG1;
1531 return (tempflag | (((uint64_t)base->IFLAG2) << 32)) & mask;
1532 #else
1533 return (base->IFLAG1 & mask);
1534 #endif
1535 }
1536
1537 #if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB)
1538 /*!
1539 * @brief Gets the FlexCAN High 64 Message Buffer interrupt flags.
1540 *
1541 * Valid only if the number of available MBs exceeds 64.
1542 *
1543 * @param base FlexCAN peripheral base address.
1544 * @param mask The ORed FlexCAN Message Buffer mask.
1545 * @return The status of given Message Buffers.
1546 */
FLEXCAN_GetHigh64MbStatusFlags(CAN_Type * base,uint64_t mask)1547 static inline uint64_t FLEXCAN_GetHigh64MbStatusFlags(CAN_Type *base, uint64_t mask)
1548 {
1549 uint64_t tempflag = 0U;
1550 #if defined(CAN_IFLAG3_BUF95TO64_MASK)
1551 tempflag |= (uint64_t)base->IFLAG3;
1552 #endif
1553 #if defined(CAN_IFLAG4_BUF127TO96_MASK)
1554 tempflag |= (uint64_t)base->IFLAG4;
1555 #endif
1556 return (tempflag & mask);
1557 }
1558 #endif
1559
1560 /*!
1561 * @brief Clears the FlexCAN Message Buffer interrupt flags.
1562 *
1563 * This function clears the interrupt flags of a given Message Buffers.
1564 *
1565 * @param base FlexCAN peripheral base address.
1566 * @param mask The ORed FlexCAN Message Buffer mask.
1567 */
1568 #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
FLEXCAN_ClearMbStatusFlags(CAN_Type * base,uint64_t mask)1569 static inline void FLEXCAN_ClearMbStatusFlags(CAN_Type *base, uint64_t mask)
1570 #else
1571 static inline void FLEXCAN_ClearMbStatusFlags(CAN_Type *base, uint32_t mask)
1572 #endif
1573 {
1574 #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
1575 base->IFLAG1 = (uint32_t)(mask & 0xFFFFFFFFU);
1576 base->IFLAG2 = (uint32_t)(mask >> 32);
1577 #else
1578 base->IFLAG1 = mask;
1579 #endif
1580 }
1581
1582 #if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB)
1583 /*!
1584 * @brief Clears the FlexCAN High 64 Message Buffer interrupt flags.
1585 *
1586 * Valid only if the number of available MBs exceeds 64.
1587 *
1588 * @param base FlexCAN peripheral base address.
1589 * @param mask The ORed FlexCAN Message Buffer mask.
1590 */
FLEXCAN_ClearHigh64MbStatusFlags(CAN_Type * base,uint64_t mask)1591 static inline void FLEXCAN_ClearHigh64MbStatusFlags(CAN_Type *base, uint64_t mask)
1592 {
1593 #if defined(CAN_IFLAG3_BUF95TO64_MASK)
1594 base->IFLAG3 = (uint32_t)(mask & 0xFFFFFFFFU);
1595 #endif
1596 #if defined(CAN_IFLAG4_BUF127TO96_MASK)
1597 base->IFLAG4 = (uint32_t)(mask >> 32U);
1598 #endif
1599 }
1600 #endif
1601
1602 #if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL)
1603 /*!
1604 * @brief Gets the FlexCAN Memory Error Report registers status.
1605 *
1606 * This function gets the FlexCAN Memory Error Report registers status.
1607 *
1608 * @param base FlexCAN peripheral base address.
1609 * @param errorStatus Pointer to FlexCAN Memory Error Report registers status structure.
1610 */
1611 void FLEXCAN_GetMemoryErrorReportStatus(CAN_Type *base, flexcan_memory_error_report_status_t *errorStatus);
1612 #endif
1613
1614 #if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE)
1615 /*!
1616 * @brief Gets the FlexCAN Number of Matches when in Pretended Networking.
1617 *
1618 * This function gets the number of times a given message has matched the predefined filtering criteria for ID and/or PL
1619 * before a wakeup event.
1620 *
1621 * @param base FlexCAN peripheral base address.
1622 * @return The number of received wake up msessages.
1623 */
FLEXCAN_GetPNMatchCount(CAN_Type * base)1624 static inline uint8_t FLEXCAN_GetPNMatchCount(CAN_Type *base)
1625 {
1626 return (uint8_t)((base->WU_MTC & CAN_WU_MTC_MCOUNTER_MASK) >> CAN_WU_MTC_MCOUNTER_SHIFT);
1627 }
1628 #endif
1629
1630 #if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
1631 /*!
1632 * @brief Gets the number of FlexCAN Enhanced Rx FIFO available frames.
1633 *
1634 * This function gets the number of CAN messages stored in the Enhanced Rx FIFO.
1635 *
1636 * @param base FlexCAN peripheral base address.
1637 * @return The number of available CAN messages stored in the Enhanced Rx FIFO.
1638 */
FLEXCAN_GetEnhancedFifoDataCount(CAN_Type * base)1639 static inline uint32_t FLEXCAN_GetEnhancedFifoDataCount(CAN_Type *base)
1640 {
1641 return (base->ERFSR & CAN_ERFSR_ERFEL_MASK);
1642 }
1643 #endif
1644 /* @} */
1645
1646 /*!
1647 * @name Interrupts
1648 * @{
1649 */
1650
1651 /*!
1652 * @brief Enables FlexCAN interrupts according to the provided mask.
1653 *
1654 * This function enables the FlexCAN interrupts according to the provided mask. The mask
1655 * is a logical OR of enumeration members, see @ref _flexcan_interrupt_enable.
1656 *
1657 * @param base FlexCAN peripheral base address.
1658 * @param mask The interrupts to enable. Logical OR of @ref _flexcan_interrupt_enable.
1659 */
1660 #if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) || \
1661 (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) || \
1662 (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL)
FLEXCAN_EnableInterrupts(CAN_Type * base,uint64_t mask)1663 static inline void FLEXCAN_EnableInterrupts(CAN_Type *base, uint64_t mask)
1664 #else
1665 static inline void FLEXCAN_EnableInterrupts(CAN_Type *base, uint32_t mask)
1666 #endif
1667 {
1668 uint32_t primask = DisableGlobalIRQ();
1669
1670 /* Solve Self Wake Up interrupt. */
1671 base->MCR |= (uint32_t)(mask & (uint32_t)kFLEXCAN_WakeUpInterruptEnable);
1672
1673 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
1674 if (0 != FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(base))
1675 {
1676 /* Solve CAN FD frames data phase error interrupt. */
1677 base->CTRL2 |= (uint32_t)(mask & (uint32_t)kFLEXCAN_FDErrorInterruptEnable);
1678 }
1679 #endif
1680
1681 #if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE)
1682 /* Solve PN Wake Up interrupt. */
1683 base->CTRL1_PN |= FLEXCAN_PN_INT_UNMASK(mask);
1684 #endif
1685
1686 #if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
1687 /* Solve Enhanced Rx FIFO interrupt. */
1688 base->ERFIER |= FLEXCAN_EFIFO_INT_UNMASK(mask);
1689 #endif
1690
1691 #if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL)
1692 /* Solve Memory Error interrupt. */
1693 base->MECR |= FLEXCAN_MECR_INT_UNMASK(mask);
1694 #endif
1695
1696 /* Solve interrupt enable bits in CTRL1 register. */
1697 base->CTRL1 |=
1698 (uint32_t)(mask & ((uint32_t)kFLEXCAN_BusOffInterruptEnable | (uint32_t)kFLEXCAN_ErrorInterruptEnable |
1699 (uint32_t)kFLEXCAN_RxWarningInterruptEnable | (uint32_t)kFLEXCAN_TxWarningInterruptEnable));
1700
1701 EnableGlobalIRQ(primask);
1702 }
1703
1704 /*!
1705 * @brief Disables FlexCAN interrupts according to the provided mask.
1706 *
1707 * This function disables the FlexCAN interrupts according to the provided mask. The mask
1708 * is a logical OR of enumeration members, see @ref _flexcan_interrupt_enable.
1709 *
1710 * @param base FlexCAN peripheral base address.
1711 * @param mask The interrupts to disable. Logical OR of @ref _flexcan_interrupt_enable.
1712 */
1713 #if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) || \
1714 (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL)
FLEXCAN_DisableInterrupts(CAN_Type * base,uint64_t mask)1715 static inline void FLEXCAN_DisableInterrupts(CAN_Type *base, uint64_t mask)
1716 #else
1717 static inline void FLEXCAN_DisableInterrupts(CAN_Type *base, uint32_t mask)
1718 #endif
1719 {
1720 uint32_t primask = DisableGlobalIRQ();
1721
1722 /* Solve Wake Up Interrupt. */
1723 base->MCR &= ~(uint32_t)(mask & (uint32_t)kFLEXCAN_WakeUpInterruptEnable);
1724
1725 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
1726 if (0 != FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(base))
1727 {
1728 /* Solve CAN FD frames data phase error interrupt. */
1729 base->CTRL2 &= ~(uint32_t)(mask & (uint32_t)kFLEXCAN_FDErrorInterruptEnable);
1730 }
1731 #endif
1732
1733 #if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE)
1734 /* Solve PN Wake Up Interrupt. */
1735 base->CTRL1_PN &= ~FLEXCAN_PN_STATUS_UNMASK(mask);
1736 #endif
1737
1738 #if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
1739 /* Solve Enhanced Rx FIFO interrupt. */
1740 base->ERFIER &= ~FLEXCAN_EFIFO_INT_UNMASK(mask);
1741 #endif
1742
1743 #if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL)
1744 /* Solve Memory Error Interrupt. */
1745 base->MECR &= ~FLEXCAN_MECR_STATUS_UNMASK(mask);
1746 #endif
1747
1748 /* Solve interrupt enable bits in CTRL1 register. */
1749 base->CTRL1 &=
1750 ~(uint32_t)(mask & ((uint32_t)kFLEXCAN_BusOffInterruptEnable | (uint32_t)kFLEXCAN_ErrorInterruptEnable |
1751 (uint32_t)kFLEXCAN_RxWarningInterruptEnable | (uint32_t)kFLEXCAN_TxWarningInterruptEnable));
1752
1753 EnableGlobalIRQ(primask);
1754 }
1755
1756 /*!
1757 * @brief Enables FlexCAN Message Buffer interrupts.
1758 *
1759 * This function enables the interrupts of given Message Buffers.
1760 *
1761 * @param base FlexCAN peripheral base address.
1762 * @param mask The ORed FlexCAN Message Buffer mask.
1763 */
1764 #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
FLEXCAN_EnableMbInterrupts(CAN_Type * base,uint64_t mask)1765 static inline void FLEXCAN_EnableMbInterrupts(CAN_Type *base, uint64_t mask)
1766 #else
1767 static inline void FLEXCAN_EnableMbInterrupts(CAN_Type *base, uint32_t mask)
1768 #endif
1769 {
1770 uint32_t primask = DisableGlobalIRQ();
1771
1772 #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
1773 base->IMASK1 |= (uint32_t)(mask & 0xFFFFFFFFU);
1774 base->IMASK2 |= (uint32_t)(mask >> 32);
1775 #else
1776 base->IMASK1 |= mask;
1777 #endif
1778 EnableGlobalIRQ(primask);
1779 }
1780
1781 #if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB)
1782 /*!
1783 * @brief Enables FlexCAN high 64 Message Buffer interrupts.
1784 *
1785 * Valid only if the number of available MBs exceeds 64.
1786 *
1787 * @param base FlexCAN peripheral base address.
1788 * @param mask The ORed FlexCAN Message Buffer mask.
1789 */
FLEXCAN_EnableHigh64MbInterrupts(CAN_Type * base,uint64_t mask)1790 static inline void FLEXCAN_EnableHigh64MbInterrupts(CAN_Type *base, uint64_t mask)
1791 {
1792 uint32_t primask = DisableGlobalIRQ();
1793
1794 #if defined(CAN_IMASK3_BUF95TO64M_MASK)
1795 base->IMASK3 |= (uint32_t)(mask & 0xFFFFFFFFU);
1796 #endif
1797 #if defined(CAN_IMASK4_BUF127TO96_MASK)
1798 base->IMASK4 |= (uint32_t)(mask >> 32U);
1799 #endif
1800 EnableGlobalIRQ(primask);
1801 }
1802 #endif
1803
1804 /*!
1805 * @brief Disables FlexCAN Message Buffer interrupts.
1806 *
1807 * This function disables the interrupts of given Message Buffers.
1808 *
1809 * @param base FlexCAN peripheral base address.
1810 * @param mask The ORed FlexCAN Message Buffer mask.
1811 */
1812 #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
FLEXCAN_DisableMbInterrupts(CAN_Type * base,uint64_t mask)1813 static inline void FLEXCAN_DisableMbInterrupts(CAN_Type *base, uint64_t mask)
1814 #else
1815 static inline void FLEXCAN_DisableMbInterrupts(CAN_Type *base, uint32_t mask)
1816 #endif
1817 {
1818 uint32_t primask = DisableGlobalIRQ();
1819
1820 #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
1821 base->IMASK1 &= ~((uint32_t)(mask & 0xFFFFFFFFU));
1822 base->IMASK2 &= ~((uint32_t)(mask >> 32));
1823 #else
1824 base->IMASK1 &= ~mask;
1825 #endif
1826 EnableGlobalIRQ(primask);
1827 }
1828
1829 #if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB)
1830 /*!
1831 * @brief Disables FlexCAN high 64 Message Buffer interrupts.
1832 *
1833 * Valid only if the number of available MBs exceeds 64.
1834 *
1835 * @param base FlexCAN peripheral base address.
1836 * @param mask The ORed FlexCAN Message Buffer mask.
1837 */
FLEXCAN_DisableHigh64MbInterrupts(CAN_Type * base,uint64_t mask)1838 static inline void FLEXCAN_DisableHigh64MbInterrupts(CAN_Type *base, uint64_t mask)
1839 {
1840 uint32_t primask = DisableGlobalIRQ();
1841
1842 #if defined(CAN_IMASK3_BUF95TO64M_MASK)
1843 base->IMASK3 &= ~((uint32_t)(mask & 0xFFFFFFFFU));
1844 #endif
1845 #if defined(CAN_IMASK4_BUF127TO96_MASK)
1846 base->IMASK4 &= ~((uint32_t)(mask >> 32U));
1847 #endif
1848 EnableGlobalIRQ(primask);
1849 }
1850 #endif
1851
1852 /* @} */
1853
1854 #if (defined(FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA) && FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA)
1855 /*!
1856 * @name DMA Control
1857 * @{
1858 */
1859
1860 /*!
1861 * @brief Enables or disables the FlexCAN Rx FIFO DMA request.
1862 *
1863 * This function enables or disables the DMA feature of FlexCAN build-in Rx FIFO.
1864 *
1865 * @param base FlexCAN peripheral base address.
1866 * @param enable true to enable, false to disable.
1867 */
1868 void FLEXCAN_EnableRxFifoDMA(CAN_Type *base, bool enable);
1869
1870 /*!
1871 * @brief Gets the Rx FIFO Head address.
1872 *
1873 * This function returns the FlexCAN Rx FIFO Head address, which is mainly used for the DMA/eDMA use case.
1874 *
1875 * @param base FlexCAN peripheral base address.
1876 * @return FlexCAN Rx FIFO Head address.
1877 */
FLEXCAN_GetRxFifoHeadAddr(CAN_Type * base)1878 static inline uintptr_t FLEXCAN_GetRxFifoHeadAddr(CAN_Type *base)
1879 {
1880 return (uintptr_t) & (base->MB[0].CS);
1881 }
1882
1883 /* @} */
1884 #endif /* FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA */
1885
1886 /*!
1887 * @name Bus Operations
1888 * @{
1889 */
1890
1891 /*!
1892 * @brief Enables or disables the FlexCAN module operation.
1893 *
1894 * This function enables or disables the FlexCAN module.
1895 *
1896 * @param base FlexCAN base pointer.
1897 * @param enable true to enable, false to disable.
1898 */
FLEXCAN_Enable(CAN_Type * base,bool enable)1899 static inline void FLEXCAN_Enable(CAN_Type *base, bool enable)
1900 {
1901 if (enable)
1902 {
1903 base->MCR &= ~CAN_MCR_MDIS_MASK;
1904
1905 /* Wait FlexCAN exit from low-power mode. */
1906 while (0U != (base->MCR & CAN_MCR_LPMACK_MASK))
1907 {
1908 }
1909 }
1910 else
1911 {
1912 base->MCR |= CAN_MCR_MDIS_MASK;
1913
1914 /* Wait FlexCAN enter low-power mode. */
1915 while (0U == (base->MCR & CAN_MCR_LPMACK_MASK))
1916 {
1917 }
1918 }
1919 }
1920
1921 /*!
1922 * @brief Writes a FlexCAN Message to the Transmit Message Buffer.
1923 *
1924 * This function writes a CAN Message to the specified Transmit Message Buffer
1925 * and changes the Message Buffer state to start CAN Message transmit. After
1926 * that the function returns immediately.
1927 *
1928 * @param base FlexCAN peripheral base address.
1929 * @param mbIdx The FlexCAN Message Buffer index.
1930 * @param pTxFrame Pointer to CAN message frame to be sent.
1931 * @retval kStatus_Success - Write Tx Message Buffer Successfully.
1932 * @retval kStatus_Fail - Tx Message Buffer is currently in use.
1933 */
1934 status_t FLEXCAN_WriteTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_frame_t *pTxFrame);
1935
1936 /*!
1937 * @brief Reads a FlexCAN Message from Receive Message Buffer.
1938 *
1939 * This function reads a CAN message from a specified Receive Message Buffer.
1940 * The function fills a receive CAN message frame structure with
1941 * just received data and activates the Message Buffer again.
1942 * The function returns immediately.
1943 *
1944 * @param base FlexCAN peripheral base address.
1945 * @param mbIdx The FlexCAN Message Buffer index.
1946 * @param pRxFrame Pointer to CAN message frame structure for reception.
1947 * @retval kStatus_Success - Rx Message Buffer is full and has been read successfully.
1948 * @retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully.
1949 * @retval kStatus_Fail - Rx Message Buffer is empty.
1950 */
1951 status_t FLEXCAN_ReadRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pRxFrame);
1952
1953 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
1954 /*!
1955 * @brief Writes a FlexCAN FD Message to the Transmit Message Buffer.
1956 *
1957 * This function writes a CAN FD Message to the specified Transmit Message Buffer
1958 * and changes the Message Buffer state to start CAN FD Message transmit. After
1959 * that the function returns immediately.
1960 *
1961 * @param base FlexCAN peripheral base address.
1962 * @param mbIdx The FlexCAN FD Message Buffer index.
1963 * @param pTxFrame Pointer to CAN FD message frame to be sent.
1964 * @retval kStatus_Success - Write Tx Message Buffer Successfully.
1965 * @retval kStatus_Fail - Tx Message Buffer is currently in use.
1966 */
1967 status_t FLEXCAN_WriteFDTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_fd_frame_t *pTxFrame);
1968
1969 /*!
1970 * @brief Reads a FlexCAN FD Message from Receive Message Buffer.
1971 *
1972 * This function reads a CAN FD message from a specified Receive Message Buffer.
1973 * The function fills a receive CAN FD message frame structure with
1974 * just received data and activates the Message Buffer again.
1975 * The function returns immediately.
1976 *
1977 * @param base FlexCAN peripheral base address.
1978 * @param mbIdx The FlexCAN FD Message Buffer index.
1979 * @param pRxFrame Pointer to CAN FD message frame structure for reception.
1980 * @retval kStatus_Success - Rx Message Buffer is full and has been read successfully.
1981 * @retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully.
1982 * @retval kStatus_Fail - Rx Message Buffer is empty.
1983 */
1984 status_t FLEXCAN_ReadFDRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *pRxFrame);
1985 #endif
1986
1987 /*!
1988 * @brief Reads a FlexCAN Message from Legacy Rx FIFO.
1989 *
1990 * This function reads a CAN message from the FlexCAN Legacy Rx FIFO.
1991 *
1992 * @param base FlexCAN peripheral base address.
1993 * @param pRxFrame Pointer to CAN message frame structure for reception.
1994 * @retval kStatus_Success - Read Message from Rx FIFO successfully.
1995 * @retval kStatus_Fail - Rx FIFO is not enabled.
1996 */
1997 status_t FLEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *pRxFrame);
1998
1999 #if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
2000 /*!
2001 * @brief Reads a FlexCAN Message from Enhanced Rx FIFO.
2002 *
2003 * This function reads a CAN or CAN FD message from the FlexCAN Enhanced Rx FIFO.
2004 *
2005 * @param base FlexCAN peripheral base address.
2006 * @param pRxFrame Pointer to CAN FD message frame structure for reception.
2007 * @retval kStatus_Success - Read Message from Rx FIFO successfully.
2008 * @retval kStatus_Fail - Rx FIFO is not enabled.
2009 */
2010 status_t FLEXCAN_ReadEnhancedRxFifo(CAN_Type *base, flexcan_fd_frame_t *pRxFrame);
2011 #endif
2012
2013 #if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE)
2014 /*!
2015 * @brief Reads a FlexCAN Message from Wake Up MB.
2016 *
2017 * This function reads a CAN message from the FlexCAN Wake up Message Buffers. There are four Wake up Message Buffers
2018 * (WMBs) used to store incoming messages in Pretended Networking mode. The WMB index indicates the arrival order. The
2019 * last message is stored in WMB3.
2020 *
2021 * @param base FlexCAN peripheral base address.
2022 * @param pRxFrame Pointer to CAN message frame structure for reception.
2023 * @param mbIdx The FlexCAN Wake up Message Buffer index. Range in 0x0 ~ 0x3.
2024 * @retval kStatus_Success - Read Message from Wake up Message Buffer successfully.
2025 * @retval kStatus_Fail - Wake up Message Buffer has no valid content.
2026 */
2027 status_t FLEXCAN_ReadPNWakeUpMB(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pRxFrame);
2028 #endif
2029 /* @} */
2030
2031 /*!
2032 * @name Transactional
2033 * @{
2034 */
2035
2036 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
2037 /*!
2038 * @brief Performs a polling send transaction on the CAN bus.
2039 *
2040 * @note A transfer handle does not need to be created before calling this API.
2041 *
2042 * @param base FlexCAN peripheral base pointer.
2043 * @param mbIdx The FlexCAN FD Message Buffer index.
2044 * @param pTxFrame Pointer to CAN FD message frame to be sent.
2045 * @retval kStatus_Success - Write Tx Message Buffer Successfully.
2046 * @retval kStatus_Fail - Tx Message Buffer is currently in use.
2047 */
2048 status_t FLEXCAN_TransferFDSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *pTxFrame);
2049
2050 /*!
2051 * @brief Performs a polling receive transaction on the CAN bus.
2052 *
2053 * @note A transfer handle does not need to be created before calling this API.
2054 *
2055 * @param base FlexCAN peripheral base pointer.
2056 * @param mbIdx The FlexCAN FD Message Buffer index.
2057 * @param pRxFrame Pointer to CAN FD message frame structure for reception.
2058 * @retval kStatus_Success - Rx Message Buffer is full and has been read successfully.
2059 * @retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully.
2060 * @retval kStatus_Fail - Rx Message Buffer is empty.
2061 */
2062 status_t FLEXCAN_TransferFDReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *pRxFrame);
2063
2064 /*!
2065 * @brief Sends a message using IRQ.
2066 *
2067 * This function sends a message using IRQ. This is a non-blocking function, which returns
2068 * right away. When messages have been sent out, the send callback function is called.
2069 *
2070 * @param base FlexCAN peripheral base address.
2071 * @param handle FlexCAN handle pointer.
2072 * @param pMbXfer FlexCAN FD Message Buffer transfer structure. See the #flexcan_mb_transfer_t.
2073 * @retval kStatus_Success Start Tx Message Buffer sending process successfully.
2074 * @retval kStatus_Fail Write Tx Message Buffer failed.
2075 * @retval kStatus_FLEXCAN_TxBusy Tx Message Buffer is in use.
2076 */
2077 status_t FLEXCAN_TransferFDSendNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer);
2078
2079 /*!
2080 * @brief Receives a message using IRQ.
2081 *
2082 * This function receives a message using IRQ. This is non-blocking function, which returns
2083 * right away. When the message has been received, the receive callback function is called.
2084 *
2085 * @param base FlexCAN peripheral base address.
2086 * @param handle FlexCAN handle pointer.
2087 * @param pMbXfer FlexCAN FD Message Buffer transfer structure. See the #flexcan_mb_transfer_t.
2088 * @retval kStatus_Success - Start Rx Message Buffer receiving process successfully.
2089 * @retval kStatus_FLEXCAN_RxBusy - Rx Message Buffer is in use.
2090 */
2091 status_t FLEXCAN_TransferFDReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer);
2092
2093 /*!
2094 * @brief Aborts the interrupt driven message send process.
2095 *
2096 * This function aborts the interrupt driven message send process.
2097 *
2098 * @param base FlexCAN peripheral base address.
2099 * @param handle FlexCAN handle pointer.
2100 * @param mbIdx The FlexCAN FD Message Buffer index.
2101 */
2102 void FLEXCAN_TransferFDAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx);
2103
2104 /*!
2105 * @brief Aborts the interrupt driven message receive process.
2106 *
2107 * This function aborts the interrupt driven message receive process.
2108 *
2109 * @param base FlexCAN peripheral base address.
2110 * @param handle FlexCAN handle pointer.
2111 * @param mbIdx The FlexCAN FD Message Buffer index.
2112 */
2113 void FLEXCAN_TransferFDAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx);
2114 #endif
2115
2116 /*!
2117 * @brief Performs a polling send transaction on the CAN bus.
2118 *
2119 * @note A transfer handle does not need to be created before calling this API.
2120 *
2121 * @param base FlexCAN peripheral base pointer.
2122 * @param mbIdx The FlexCAN Message Buffer index.
2123 * @param pTxFrame Pointer to CAN message frame to be sent.
2124 * @retval kStatus_Success - Write Tx Message Buffer Successfully.
2125 * @retval kStatus_Fail - Tx Message Buffer is currently in use.
2126 */
2127 status_t FLEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pTxFrame);
2128
2129 /*!
2130 * @brief Performs a polling receive transaction on the CAN bus.
2131 *
2132 * @note A transfer handle does not need to be created before calling this API.
2133 *
2134 * @param base FlexCAN peripheral base pointer.
2135 * @param mbIdx The FlexCAN Message Buffer index.
2136 * @param pRxFrame Pointer to CAN message frame structure for reception.
2137 * @retval kStatus_Success - Rx Message Buffer is full and has been read successfully.
2138 * @retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully.
2139 * @retval kStatus_Fail - Rx Message Buffer is empty.
2140 */
2141 status_t FLEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pRxFrame);
2142
2143 /*!
2144 * @brief Performs a polling receive transaction from Legacy Rx FIFO on the CAN bus.
2145 *
2146 * @note A transfer handle does not need to be created before calling this API.
2147 *
2148 * @param base FlexCAN peripheral base pointer.
2149 * @param pRxFrame Pointer to CAN message frame structure for reception.
2150 * @retval kStatus_Success - Read Message from Rx FIFO successfully.
2151 * @retval kStatus_Fail - Rx FIFO is not enabled.
2152 */
2153 status_t FLEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *pRxFrame);
2154
2155 #if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
2156 /*!
2157 * @brief Performs a polling receive transaction from Enhanced Rx FIFO on the CAN bus.
2158 *
2159 * @note A transfer handle does not need to be created before calling this API.
2160 *
2161 * @param base FlexCAN peripheral base pointer.
2162 * @param pRxFrame Pointer to CAN FD message frame structure for reception.
2163 * @retval kStatus_Success - Read Message from Rx FIFO successfully.
2164 * @retval kStatus_Fail - Rx FIFO is not enabled.
2165 */
2166 status_t FLEXCAN_TransferReceiveEnhancedFifoBlocking(CAN_Type *base, flexcan_fd_frame_t *pRxFrame);
2167 #endif
2168
2169 /*!
2170 * @brief Initializes the FlexCAN handle.
2171 *
2172 * This function initializes the FlexCAN handle, which can be used for other FlexCAN
2173 * transactional APIs. Usually, for a specified FlexCAN instance,
2174 * call this API once to get the initialized handle.
2175 *
2176 * @param base FlexCAN peripheral base address.
2177 * @param handle FlexCAN handle pointer.
2178 * @param callback The callback function.
2179 * @param userData The parameter of the callback function.
2180 */
2181 void FLEXCAN_TransferCreateHandle(CAN_Type *base,
2182 flexcan_handle_t *handle,
2183 flexcan_transfer_callback_t callback,
2184 void *userData);
2185
2186 /*!
2187 * @brief Sends a message using IRQ.
2188 *
2189 * This function sends a message using IRQ. This is a non-blocking function, which returns
2190 * right away. When messages have been sent out, the send callback function is called.
2191 *
2192 * @param base FlexCAN peripheral base address.
2193 * @param handle FlexCAN handle pointer.
2194 * @param pMbXfer FlexCAN Message Buffer transfer structure. See the #flexcan_mb_transfer_t.
2195 * @retval kStatus_Success Start Tx Message Buffer sending process successfully.
2196 * @retval kStatus_Fail Write Tx Message Buffer failed.
2197 * @retval kStatus_FLEXCAN_TxBusy Tx Message Buffer is in use.
2198 */
2199 status_t FLEXCAN_TransferSendNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer);
2200
2201 /*!
2202 * @brief Receives a message using IRQ.
2203 *
2204 * This function receives a message using IRQ. This is non-blocking function, which returns
2205 * right away. When the message has been received, the receive callback function is called.
2206 *
2207 * @param base FlexCAN peripheral base address.
2208 * @param handle FlexCAN handle pointer.
2209 * @param pMbXfer FlexCAN Message Buffer transfer structure. See the #flexcan_mb_transfer_t.
2210 * @retval kStatus_Success - Start Rx Message Buffer receiving process successfully.
2211 * @retval kStatus_FLEXCAN_RxBusy - Rx Message Buffer is in use.
2212 */
2213 status_t FLEXCAN_TransferReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer);
2214
2215 /*!
2216 * @brief Receives a message from Rx FIFO using IRQ.
2217 *
2218 * This function receives a message using IRQ. This is a non-blocking function, which returns
2219 * right away. When all messages have been received, the receive callback function is called.
2220 *
2221 * @param base FlexCAN peripheral base address.
2222 * @param handle FlexCAN handle pointer.
2223 * @param pFifoXfer FlexCAN Rx FIFO transfer structure. See the @ref flexcan_fifo_transfer_t.
2224 * @retval kStatus_Success - Start Rx FIFO receiving process successfully.
2225 * @retval kStatus_FLEXCAN_RxFifoBusy - Rx FIFO is currently in use.
2226 */
2227 status_t FLEXCAN_TransferReceiveFifoNonBlocking(CAN_Type *base,
2228 flexcan_handle_t *handle,
2229 flexcan_fifo_transfer_t *pFifoXfer);
2230
2231 /*!
2232 * @brief Gets the Legacy Rx Fifo transfer status during a interrupt non-blocking receive.
2233 *
2234 * @param base FlexCAN peripheral base address.
2235 * @param handle FlexCAN handle pointer.
2236 * @param count Number of CAN messages receive so far by the non-blocking transaction.
2237 * @retval kStatus_InvalidArgument count is Invalid.
2238 * @retval kStatus_Success Successfully return the count.
2239 */
2240
2241 status_t FLEXCAN_TransferGetReceiveFifoCount(CAN_Type *base, flexcan_handle_t *handle, size_t *count);
2242
2243 #if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
2244 /*!
2245 * @brief Receives a message from Enhanced Rx FIFO using IRQ.
2246 *
2247 * This function receives a message using IRQ. This is a non-blocking function, which returns
2248 * right away. When all messages have been received, the receive callback function is called.
2249 *
2250 * @param base FlexCAN peripheral base address.
2251 * @param handle FlexCAN handle pointer.
2252 * @param pFifoXfer FlexCAN Rx FIFO transfer structure. See the ref flexcan_fifo_transfer_t.@
2253 * @retval kStatus_Success - Start Rx FIFO receiving process successfully.
2254 * @retval kStatus_FLEXCAN_RxFifoBusy - Rx FIFO is currently in use.
2255 */
2256 status_t FLEXCAN_TransferReceiveEnhancedFifoNonBlocking(CAN_Type *base,
2257 flexcan_handle_t *handle,
2258 flexcan_fifo_transfer_t *pFifoXfer);
2259
2260 /*!
2261 * @brief Gets the Enhanced Rx Fifo transfer status during a interrupt non-blocking receive.
2262 *
2263 * @param base FlexCAN peripheral base address.
2264 * @param handle FlexCAN handle pointer.
2265 * @param count Number of CAN messages receive so far by the non-blocking transaction.
2266 * @retval kStatus_InvalidArgument count is Invalid.
2267 * @retval kStatus_Success Successfully return the count.
2268 */
2269
FLEXCAN_TransferGetReceiveEnhancedFifoCount(CAN_Type * base,flexcan_handle_t * handle,size_t * count)2270 static inline status_t FLEXCAN_TransferGetReceiveEnhancedFifoCount(CAN_Type *base,
2271 flexcan_handle_t *handle,
2272 size_t *count)
2273 {
2274 return FLEXCAN_TransferGetReceiveFifoCount(base, handle, count);
2275 }
2276 #endif
2277
2278 /*!
2279 * @brief Gets the detail index of Mailbox's Timestamp by handle.
2280 *
2281 * Then function can only be used when calling non-blocking Data transfer (TX/RX) API,
2282 * After TX/RX data transfer done (User can get the status by handler's callback function),
2283 * we can get the detail index of Mailbox's timestamp by handle,
2284 * Detail non-blocking data transfer API (TX/RX) contain.
2285 * -FLEXCAN_TransferSendNonBlocking
2286 * -FLEXCAN_TransferFDSendNonBlocking
2287 * -FLEXCAN_TransferReceiveNonBlocking
2288 * -FLEXCAN_TransferFDReceiveNonBlocking
2289 * -FLEXCAN_TransferReceiveFifoNonBlocking
2290 *
2291 * @param handle FlexCAN handle pointer.
2292 * @param mbIdx The FlexCAN Message Buffer index.
2293 * @retval the index of mailbox 's timestamp stored in the handle.
2294 *
2295 */
2296 uint32_t FLEXCAN_GetTimeStamp(flexcan_handle_t *handle, uint8_t mbIdx);
2297
2298 /*!
2299 * @brief Aborts the interrupt driven message send process.
2300 *
2301 * This function aborts the interrupt driven message send process.
2302 *
2303 * @param base FlexCAN peripheral base address.
2304 * @param handle FlexCAN handle pointer.
2305 * @param mbIdx The FlexCAN Message Buffer index.
2306 */
2307 void FLEXCAN_TransferAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx);
2308
2309 /*!
2310 * @brief Aborts the interrupt driven message receive process.
2311 *
2312 * This function aborts the interrupt driven message receive process.
2313 *
2314 * @param base FlexCAN peripheral base address.
2315 * @param handle FlexCAN handle pointer.
2316 * @param mbIdx The FlexCAN Message Buffer index.
2317 */
2318 void FLEXCAN_TransferAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx);
2319
2320 /*!
2321 * @brief Aborts the interrupt driven message receive from Rx FIFO process.
2322 *
2323 * This function aborts the interrupt driven message receive from Rx FIFO process.
2324 *
2325 * @param base FlexCAN peripheral base address.
2326 * @param handle FlexCAN handle pointer.
2327 */
2328 void FLEXCAN_TransferAbortReceiveFifo(CAN_Type *base, flexcan_handle_t *handle);
2329
2330 #if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
2331 /*!
2332 * @brief Aborts the interrupt driven message receive from Enhanced Rx FIFO process.
2333 *
2334 * This function aborts the interrupt driven message receive from Enhanced Rx FIFO process.
2335 *
2336 * @param base FlexCAN peripheral base address.
2337 * @param handle FlexCAN handle pointer.
2338 */
2339 void FLEXCAN_TransferAbortReceiveEnhancedFifo(CAN_Type *base, flexcan_handle_t *handle);
2340 #endif
2341
2342 /*!
2343 * @brief FlexCAN IRQ handle function.
2344 *
2345 * This function handles the FlexCAN Error, the Message Buffer, and the Rx FIFO IRQ request.
2346 *
2347 * @param base FlexCAN peripheral base address.
2348 * @param handle FlexCAN handle pointer.
2349 */
2350 void FLEXCAN_TransferHandleIRQ(CAN_Type *base, flexcan_handle_t *handle);
2351
2352 /* @} */
2353
2354 #if defined(__cplusplus)
2355 }
2356 #endif
2357
2358 /*! @}*/
2359
2360 #endif /* _FSL_FLEXCAN_H_ */
2361
