1 /* This linker script generated from xt-genldscripts.tpp for LSP c:\_ddm\audio\devices\MIMXRT685S\xtensa\gdbio */ 2 /* Linker Script for default link */ 3 MEMORY 4 { 5 dsp_core_seg : org = 0x00200000, len = 0x280000 6 dsp_uncached_seg : org = 0x20060000, len = 0x10000 7 dram0_0_seg : org = 0x24000000, len = 0x10000 8 iram0_0_seg : org = 0x24020000, len = 0x400 9 iram0_1_seg : org = 0x24020400, len = 0x17C 10 iram0_2_seg : org = 0x2402057C, len = 0x20 11 iram0_3_seg : org = 0x2402059C, len = 0x20 12 iram0_4_seg : org = 0x240205BC, len = 0x20 13 iram0_5_seg : org = 0x240205DC, len = 0x20 14 iram0_6_seg : org = 0x240205FC, len = 0x20 15 iram0_7_seg : org = 0x2402061C, len = 0x20 16 iram0_8_seg : org = 0x2402063C, len = 0xF9C4 17 } 18 19 PHDRS 20 { 21 dsp_core_phdr PT_LOAD; 22 dsp_core_bss_phdr PT_LOAD; 23 dsp_uncached_phdr PT_LOAD; 24 dram0_0_phdr PT_LOAD; 25 dram0_0_bss_phdr PT_LOAD; 26 iram0_0_phdr PT_LOAD; 27 iram0_1_phdr PT_LOAD; 28 iram0_2_phdr PT_LOAD; 29 iram0_3_phdr PT_LOAD; 30 iram0_4_phdr PT_LOAD; 31 iram0_5_phdr PT_LOAD; 32 iram0_6_phdr PT_LOAD; 33 iram0_7_phdr PT_LOAD; 34 iram0_8_phdr PT_LOAD; 35 } 36 37 38 /* Default entry point: */ 39 ENTRY(_ResetVector) 40 41 42 /* Memory boundary addresses: */ 43 _memmap_mem_dsp_core_start = 0x200000; 44 _memmap_mem_dsp_core_end = 0x480000; 45 _memmap_mem_dsp_uncached_start = 0x20000000; 46 _memmap_mem_dsp_uncached_end = 0x20480000; 47 _memmap_mem_dram0_start = 0x24000000; 48 _memmap_mem_dram0_end = 0x24010000; 49 _memmap_mem_iram0_start = 0x24020000; 50 _memmap_mem_iram0_end = 0x24030000; 51 52 /* Memory segment boundary addresses: */ 53 _memmap_seg_dsp_core_start = 0x200000; 54 _memmap_seg_dsp_core_max = 0x480000; 55 _memmap_seg_dsp_uncached_start = 0x20060000; 56 _memmap_seg_dsp_uncached_max = 0x20070000; 57 _memmap_seg_dram0_0_start = 0x24000000; 58 _memmap_seg_dram0_0_max = 0x24010000; 59 _memmap_seg_iram0_0_start = 0x24020000; 60 _memmap_seg_iram0_0_max = 0x24020400; 61 _memmap_seg_iram0_1_start = 0x24020400; 62 _memmap_seg_iram0_1_max = 0x2402057c; 63 _memmap_seg_iram0_2_start = 0x2402057c; 64 _memmap_seg_iram0_2_max = 0x2402059c; 65 _memmap_seg_iram0_3_start = 0x2402059c; 66 _memmap_seg_iram0_3_max = 0x240205bc; 67 _memmap_seg_iram0_4_start = 0x240205bc; 68 _memmap_seg_iram0_4_max = 0x240205dc; 69 _memmap_seg_iram0_5_start = 0x240205dc; 70 _memmap_seg_iram0_5_max = 0x240205fc; 71 _memmap_seg_iram0_6_start = 0x240205fc; 72 _memmap_seg_iram0_6_max = 0x2402061c; 73 _memmap_seg_iram0_7_start = 0x2402061c; 74 _memmap_seg_iram0_7_max = 0x2402063c; 75 _memmap_seg_iram0_8_start = 0x2402063c; 76 _memmap_seg_iram0_8_max = 0x24030000; 77 78 _rom_store_table = 0; 79 PROVIDE(_memmap_reset_vector = 0x24020000); 80 PROVIDE(_memmap_vecbase_reset = 0x24020400); 81 /* Various memory-map dependent cache attribute settings: */ 82 _memmap_cacheattr_wb_base = 0x00000024; 83 _memmap_cacheattr_wt_base = 0x00000021; 84 _memmap_cacheattr_bp_base = 0x00000022; 85 _memmap_cacheattr_unused_mask = 0xFFFFFF00; 86 _memmap_cacheattr_wb_trapnull = 0x22222224; 87 _memmap_cacheattr_wba_trapnull = 0x22222224; 88 _memmap_cacheattr_wbna_trapnull = 0x22222225; 89 _memmap_cacheattr_wt_trapnull = 0x22222221; 90 _memmap_cacheattr_bp_trapnull = 0x22222222; 91 _memmap_cacheattr_wb_strict = 0xFFFFFF24; 92 _memmap_cacheattr_wt_strict = 0xFFFFFF21; 93 _memmap_cacheattr_bp_strict = 0xFFFFFF22; 94 _memmap_cacheattr_wb_allvalid = 0x22222224; 95 _memmap_cacheattr_wt_allvalid = 0x22222221; 96 _memmap_cacheattr_bp_allvalid = 0x22222222; 97 _memmap_region_map = 0x00000003; 98 PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull); 99 100 SECTIONS 101 { 102 103 NonCacheable.init : ALIGN(4) 104 { 105 NonCacheable_init_start = ABSOLUTE(.); 106 *(NonCacheable.init) 107 . = ALIGN (4); 108 NonCacheable_init_end = ABSOLUTE(.); 109 } >dsp_uncached_seg :dsp_uncached_phdr 110 111 NonCacheable : ALIGN(4) 112 { 113 NonCacheable_start = ABSOLUTE(.); 114 *(NonCacheable) 115 . = ALIGN (4); 116 NonCacheable_end = ABSOLUTE(.); 117 _memmap_seg_dsp_uncached_end = ALIGN(0x8); 118 } >dsp_uncached_seg :dsp_uncached_phdr 119 120 _memmap_mem_dsp_uncached_max = ABSOLUTE(.); 121 122 .dram0.rodata : ALIGN(4) 123 { 124 _dram0_rodata_start = ABSOLUTE(.); 125 *(.dram0.rodata) 126 *(.dram.rodata) 127 . = ALIGN (4); 128 _dram0_rodata_end = ABSOLUTE(.); 129 } >dram0_0_seg :dram0_0_phdr 130 131 .ResetVector.literal : ALIGN(4) 132 { 133 _ResetVector_literal_start = ABSOLUTE(.); 134 *(.ResetVector.literal) 135 . = ALIGN (4); 136 _ResetVector_literal_end = ABSOLUTE(.); 137 } >dram0_0_seg :dram0_0_phdr 138 139 .Level2InterruptVector.literal : ALIGN(4) 140 { 141 _Level2InterruptVector_literal_start = ABSOLUTE(.); 142 *(.Level2InterruptVector.literal) 143 . = ALIGN (4); 144 _Level2InterruptVector_literal_end = ABSOLUTE(.); 145 } >dram0_0_seg :dram0_0_phdr 146 147 .Level3InterruptVector.literal : ALIGN(4) 148 { 149 _Level3InterruptVector_literal_start = ABSOLUTE(.); 150 *(.Level3InterruptVector.literal) 151 . = ALIGN (4); 152 _Level3InterruptVector_literal_end = ABSOLUTE(.); 153 } >dram0_0_seg :dram0_0_phdr 154 155 .DebugExceptionVector.literal : ALIGN(4) 156 { 157 _DebugExceptionVector_literal_start = ABSOLUTE(.); 158 *(.DebugExceptionVector.literal) 159 . = ALIGN (4); 160 _DebugExceptionVector_literal_end = ABSOLUTE(.); 161 } >dram0_0_seg :dram0_0_phdr 162 163 .NMIExceptionVector.literal : ALIGN(4) 164 { 165 _NMIExceptionVector_literal_start = ABSOLUTE(.); 166 *(.NMIExceptionVector.literal) 167 . = ALIGN (4); 168 _NMIExceptionVector_literal_end = ABSOLUTE(.); 169 } >dram0_0_seg :dram0_0_phdr 170 171 .KernelExceptionVector.literal : ALIGN(4) 172 { 173 _KernelExceptionVector_literal_start = ABSOLUTE(.); 174 *(.KernelExceptionVector.literal) 175 . = ALIGN (4); 176 _KernelExceptionVector_literal_end = ABSOLUTE(.); 177 } >dram0_0_seg :dram0_0_phdr 178 179 .UserExceptionVector.literal : ALIGN(4) 180 { 181 _UserExceptionVector_literal_start = ABSOLUTE(.); 182 *(.UserExceptionVector.literal) 183 . = ALIGN (4); 184 _UserExceptionVector_literal_end = ABSOLUTE(.); 185 } >dram0_0_seg :dram0_0_phdr 186 187 .DoubleExceptionVector.literal : ALIGN(4) 188 { 189 _DoubleExceptionVector_literal_start = ABSOLUTE(.); 190 *(.DoubleExceptionVector.literal) 191 . = ALIGN (4); 192 _DoubleExceptionVector_literal_end = ABSOLUTE(.); 193 } >dram0_0_seg :dram0_0_phdr 194 195 .iram0.literal : ALIGN(4) 196 { 197 _iram0_literal_start = ABSOLUTE(.); 198 *(.iram0.literal) 199 *(.iram.literal) 200 *(.iram.text.literal) 201 . = ALIGN (4); 202 _iram0_literal_end = ABSOLUTE(.); 203 } >dram0_0_seg :dram0_0_phdr 204 205 .dram0.data : ALIGN(4) 206 { 207 _dram0_data_start = ABSOLUTE(.); 208 *(.dram0.data) 209 *(.dram.data) 210 . = ALIGN (4); 211 _dram0_data_end = ABSOLUTE(.); 212 } >dram0_0_seg :dram0_0_phdr 213 bss(NOLOAD)214 .dram0.bss (NOLOAD) : ALIGN(8) 215 { 216 . = ALIGN (8); 217 _dram0_bss_start = ABSOLUTE(.); 218 *(.dram0.bss) 219 . = ALIGN (8); 220 _dram0_bss_end = ABSOLUTE(.); 221 _memmap_seg_dram0_0_end = ALIGN(0x8); 222 } >dram0_0_seg :dram0_0_bss_phdr 223 224 _memmap_mem_dram0_max = ABSOLUTE(.); 225 226 .ResetVector.text : ALIGN(4) 227 { 228 _ResetVector_text_start = ABSOLUTE(.); 229 KEEP (*(.ResetVector.text)) 230 . = ALIGN (4); 231 _ResetVector_text_end = ABSOLUTE(.); 232 } >iram0_0_seg :iram0_0_phdr 233 234 .ResetHandler.text : ALIGN(4) 235 { 236 _ResetHandler_text_start = ABSOLUTE(.); 237 *(.ResetHandler.literal .ResetHandler.text) 238 . = ALIGN (4); 239 _ResetHandler_text_end = ABSOLUTE(.); 240 _memmap_seg_iram0_0_end = ALIGN(0x8); 241 } >iram0_0_seg :iram0_0_phdr 242 243 244 .WindowVectors.text : ALIGN(4) 245 { 246 _WindowVectors_text_start = ABSOLUTE(.); 247 KEEP (*(.WindowVectors.text)) 248 . = ALIGN (4); 249 _WindowVectors_text_end = ABSOLUTE(.); 250 _memmap_seg_iram0_1_end = ALIGN(0x8); 251 } >iram0_1_seg :iram0_1_phdr 252 253 254 .Level2InterruptVector.text : ALIGN(4) 255 { 256 _Level2InterruptVector_text_start = ABSOLUTE(.); 257 KEEP (*(.Level2InterruptVector.text)) 258 . = ALIGN (4); 259 _Level2InterruptVector_text_end = ABSOLUTE(.); 260 _memmap_seg_iram0_2_end = ALIGN(0x8); 261 } >iram0_2_seg :iram0_2_phdr 262 263 264 .Level3InterruptVector.text : ALIGN(4) 265 { 266 _Level3InterruptVector_text_start = ABSOLUTE(.); 267 KEEP (*(.Level3InterruptVector.text)) 268 . = ALIGN (4); 269 _Level3InterruptVector_text_end = ABSOLUTE(.); 270 _memmap_seg_iram0_3_end = ALIGN(0x8); 271 } >iram0_3_seg :iram0_3_phdr 272 273 274 .DebugExceptionVector.text : ALIGN(4) 275 { 276 _DebugExceptionVector_text_start = ABSOLUTE(.); 277 KEEP (*(.DebugExceptionVector.text)) 278 . = ALIGN (4); 279 _DebugExceptionVector_text_end = ABSOLUTE(.); 280 _memmap_seg_iram0_4_end = ALIGN(0x8); 281 } >iram0_4_seg :iram0_4_phdr 282 283 284 .NMIExceptionVector.text : ALIGN(4) 285 { 286 _NMIExceptionVector_text_start = ABSOLUTE(.); 287 KEEP (*(.NMIExceptionVector.text)) 288 . = ALIGN (4); 289 _NMIExceptionVector_text_end = ABSOLUTE(.); 290 _memmap_seg_iram0_5_end = ALIGN(0x8); 291 } >iram0_5_seg :iram0_5_phdr 292 293 294 .KernelExceptionVector.text : ALIGN(4) 295 { 296 _KernelExceptionVector_text_start = ABSOLUTE(.); 297 KEEP (*(.KernelExceptionVector.text)) 298 . = ALIGN (4); 299 _KernelExceptionVector_text_end = ABSOLUTE(.); 300 _memmap_seg_iram0_6_end = ALIGN(0x8); 301 } >iram0_6_seg :iram0_6_phdr 302 303 304 .UserExceptionVector.text : ALIGN(4) 305 { 306 _UserExceptionVector_text_start = ABSOLUTE(.); 307 KEEP (*(.UserExceptionVector.text)) 308 . = ALIGN (4); 309 _UserExceptionVector_text_end = ABSOLUTE(.); 310 _memmap_seg_iram0_7_end = ALIGN(0x8); 311 } >iram0_7_seg :iram0_7_phdr 312 313 314 .DoubleExceptionVector.text : ALIGN(4) 315 { 316 _DoubleExceptionVector_text_start = ABSOLUTE(.); 317 KEEP (*(.DoubleExceptionVector.text)) 318 . = ALIGN (4); 319 _DoubleExceptionVector_text_end = ABSOLUTE(.); 320 } >iram0_8_seg :iram0_8_phdr 321 322 .iram0.text : ALIGN(4) 323 { 324 _iram0_text_start = ABSOLUTE(.); 325 *(.iram0.text) 326 *(.iram.text) 327 . = ALIGN (4); 328 _iram0_text_end = ABSOLUTE(.); 329 _memmap_seg_iram0_8_end = ALIGN(0x8); 330 } >iram0_8_seg :iram0_8_phdr 331 332 _memmap_mem_iram0_max = ABSOLUTE(.); 333 334 .clib.rodata : ALIGN(4) 335 { 336 _clib_rodata_start = ABSOLUTE(.); 337 *(.clib.rodata) 338 . = ALIGN (4); 339 _clib_rodata_end = ABSOLUTE(.); 340 } >dsp_core_seg :dsp_core_phdr 341 342 .rtos.rodata : ALIGN(4) 343 { 344 _rtos_rodata_start = ABSOLUTE(.); 345 *(.rtos.rodata) 346 . = ALIGN (4); 347 _rtos_rodata_end = ABSOLUTE(.); 348 } >dsp_core_seg :dsp_core_phdr 349 350 .rodata : ALIGN(4) 351 { 352 _rodata_start = ABSOLUTE(.); 353 *(.rodata) 354 *(SORT(.rodata.sort.*)) 355 KEEP (*(SORT(.rodata.keepsort.*) .rodata.keep.*)) 356 *(.rodata.*) 357 *(.gnu.linkonce.r.*) 358 *(.rodata1) 359 __XT_EXCEPTION_TABLE__ = ABSOLUTE(.); 360 KEEP (*(.xt_except_table)) 361 KEEP (*(.gcc_except_table)) 362 *(.gnu.linkonce.e.*) 363 *(.gnu.version_r) 364 KEEP (*(.eh_frame)) 365 /* C++ constructor and destructor tables, properly ordered: */ 366 KEEP (*crtbegin.o(.ctors)) 367 KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) 368 KEEP (*(SORT(.ctors.*))) 369 KEEP (*(.ctors)) 370 KEEP (*crtbegin.o(.dtors)) 371 KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) 372 KEEP (*(SORT(.dtors.*))) 373 KEEP (*(.dtors)) 374 /* C++ exception handlers table: */ 375 __XT_EXCEPTION_DESCS__ = ABSOLUTE(.); 376 *(.xt_except_desc) 377 *(.gnu.linkonce.h.*) 378 __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); 379 *(.xt_except_desc_end) 380 *(.dynamic) 381 *(.gnu.version_d) 382 . = ALIGN(4); /* this table MUST be 4-byte aligned */ 383 _bss_table_start = ABSOLUTE(.); 384 LONG(_dram0_bss_start) 385 LONG(_dram0_bss_end) 386 LONG(_bss_start) 387 LONG(_bss_end) 388 _bss_table_end = ABSOLUTE(.); 389 . = ALIGN (4); 390 _rodata_end = ABSOLUTE(.); 391 } >dsp_core_seg :dsp_core_phdr 392 393 .text : ALIGN(4) 394 { 395 _stext = .; 396 _text_start = ABSOLUTE(.); 397 *(.entry.text) 398 *(.init.literal) 399 KEEP(*(.init)) 400 *(.literal.sort.* SORT(.text.sort.*)) 401 KEEP (*(.literal.keepsort.* SORT(.text.keepsort.*) .literal.keep.* .text.keep.* .literal.*personality* .text.*personality*)) 402 *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) 403 *(.fini.literal) 404 KEEP(*(.fini)) 405 *(.gnu.version) 406 . = ALIGN (4); 407 _text_end = ABSOLUTE(.); 408 _etext = .; 409 } >dsp_core_seg :dsp_core_phdr 410 411 .clib.text : ALIGN(4) 412 { 413 _clib_text_start = ABSOLUTE(.); 414 *(.clib.literal .clib.text) 415 . = ALIGN (4); 416 _clib_text_end = ABSOLUTE(.); 417 } >dsp_core_seg :dsp_core_phdr 418 419 .rtos.text : ALIGN(4) 420 { 421 _rtos_text_start = ABSOLUTE(.); 422 *(.rtos.literal .rtos.text) 423 . = ALIGN (4); 424 _rtos_text_end = ABSOLUTE(.); 425 } >dsp_core_seg :dsp_core_phdr 426 427 .clib.data : ALIGN(4) 428 { 429 _clib_data_start = ABSOLUTE(.); 430 *(.clib.data) 431 . = ALIGN (4); 432 _clib_data_end = ABSOLUTE(.); 433 } >dsp_core_seg :dsp_core_phdr 434 435 .clib.percpu.data : ALIGN(4) 436 { 437 _clib_percpu_data_start = ABSOLUTE(.); 438 *(.clib.percpu.data) 439 . = ALIGN (4); 440 _clib_percpu_data_end = ABSOLUTE(.); 441 } >dsp_core_seg :dsp_core_phdr 442 443 .rtos.percpu.data : ALIGN(4) 444 { 445 _rtos_percpu_data_start = ABSOLUTE(.); 446 *(.rtos.percpu.data) 447 . = ALIGN (4); 448 _rtos_percpu_data_end = ABSOLUTE(.); 449 } >dsp_core_seg :dsp_core_phdr 450 451 .rtos.data : ALIGN(4) 452 { 453 _rtos_data_start = ABSOLUTE(.); 454 *(.rtos.data) 455 . = ALIGN (4); 456 _rtos_data_end = ABSOLUTE(.); 457 } >dsp_core_seg :dsp_core_phdr 458 459 .data : ALIGN(4) 460 { 461 _data_start = ABSOLUTE(.); 462 *(.data) 463 *(SORT(.data.sort.*)) 464 KEEP (*(SORT(.data.keepsort.*) .data.keep.*)) 465 *(.data.*) 466 *(.gnu.linkonce.d.*) 467 KEEP(*(.gnu.linkonce.d.*personality*)) 468 *(.data1) 469 *(.sdata) 470 *(.sdata.*) 471 *(.gnu.linkonce.s.*) 472 *(.sdata2) 473 *(.sdata2.*) 474 *(.gnu.linkonce.s2.*) 475 KEEP(*(.jcr)) 476 *(__llvm_prf_cnts) 477 *(__llvm_prf_data) 478 *(__llvm_prf_vnds) 479 . = ALIGN (4); 480 _data_end = ABSOLUTE(.); 481 } >dsp_core_seg :dsp_core_phdr 482 483 __llvm_prf_names : ALIGN(4) 484 { 485 __llvm_prf_names_start = ABSOLUTE(.); 486 *(__llvm_prf_names) 487 . = ALIGN (4); 488 __llvm_prf_names_end = ABSOLUTE(.); 489 } >dsp_core_seg :dsp_core_phdr 490 bss(NOLOAD)491 .bss (NOLOAD) : ALIGN(8) 492 { 493 . = ALIGN (8); 494 _bss_start = ABSOLUTE(.); 495 *(.dynsbss) 496 *(.sbss) 497 *(.sbss.*) 498 *(.gnu.linkonce.sb.*) 499 *(.scommon) 500 *(.sbss2) 501 *(.sbss2.*) 502 *(.gnu.linkonce.sb2.*) 503 *(.dynbss) 504 *(.bss) 505 *(SORT(.bss.sort.*)) 506 KEEP (*(SORT(.bss.keepsort.*) .bss.keep.*)) 507 *(.bss.*) 508 *(.gnu.linkonce.b.*) 509 *(COMMON) 510 *(.clib.bss) 511 *(.clib.percpu.bss) 512 *(.rtos.percpu.bss) 513 *(.rtos.bss) 514 . = ALIGN (8); 515 _bss_end = ABSOLUTE(.); 516 _end = ALIGN(0x8); 517 PROVIDE(end = ALIGN(0x8)); 518 _stack_sentry = ALIGN(0x8); 519 _memmap_seg_dsp_core_end = ALIGN(0x8); 520 } >dsp_core_seg :dsp_core_bss_phdr 521 522 PROVIDE(__stack = 0x480000); 523 _heap_sentry = 0x480000; 524 525 _memmap_mem_dsp_core_max = ABSOLUTE(.); 526 527 .debug 0 : { *(.debug) } 528 .line 0 : { *(.line) } 529 .debug_srcinfo 0 : { *(.debug_srcinfo) } 530 .debug_sfnames 0 : { *(.debug_sfnames) } 531 .debug_aranges 0 : { *(.debug_aranges) } 532 .debug_pubnames 0 : { *(.debug_pubnames) } 533 .debug_info 0 : { *(.debug_info) } 534 .debug_abbrev 0 : { *(.debug_abbrev) } 535 .debug_line 0 : { *(.debug_line) } 536 .debug_frame 0 : { *(.debug_frame) } 537 .debug_str 0 : { *(.debug_str) } 538 .debug_loc 0 : { *(.debug_loc) } 539 .debug_macinfo 0 : { *(.debug_macinfo) } 540 .debug_weaknames 0 : { *(.debug_weaknames) } 541 .debug_funcnames 0 : { *(.debug_funcnames) } 542 .debug_typenames 0 : { *(.debug_typenames) } 543 .debug_varnames 0 : { *(.debug_varnames) } 544 .xt.insn 0 : 545 { 546 KEEP (*(.xt.insn)) 547 KEEP (*(.gnu.linkonce.x.*)) 548 } 549 .xt.prop 0 : 550 { 551 KEEP (*(.xt.prop)) 552 KEEP (*(.xt.prop.*)) 553 KEEP (*(.gnu.linkonce.prop.*)) 554 } 555 .xt.lit 0 : 556 { 557 KEEP (*(.xt.lit)) 558 KEEP (*(.xt.lit.*)) 559 KEEP (*(.gnu.linkonce.p.*)) 560 } 561 .debug.xt.callgraph 0 : 562 { 563 KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*)) 564 } 565 .note.gnu.build-id 0 : 566 { 567 KEEP(*(.note.gnu.build-id)) 568 } 569 } 570 571
