1 /*
2 * Copyright 2018-2023, NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7 #ifndef _FSL_POWER_H_
8 #define _FSL_POWER_H_
9
10 #include "fsl_common.h"
11
12 /*!
13 * @addtogroup power
14 * @{
15 */
16 /*******************************************************************************
17 * Definitions
18 ******************************************************************************/
19
20 /*! @name Driver version */
21 /*@{*/
22 /*! @brief power driver version 2.5.0. */
23 #define FSL_POWER_DRIVER_VERSION (MAKE_VERSION(2, 5, 0))
24 /*@}*/
25
26 #define MAKE_PD_BITS(reg, slot) (((reg) << 8) | (slot))
27 #define SYSCTL0_PDRCFGSET_REG(x) (*((volatile uint32_t *)((uint32_t)(&(SYSCTL0->PDRUNCFG0_SET)) + ((x) << 2U))))
28 #define SYSCTL0_PDRCFGCLR_REG(x) (*((volatile uint32_t *)((uint32_t)(&(SYSCTL0->PDRUNCFG0_CLR)) + ((x) << 2U))))
29 #define PDRCFG0 0x0U
30 #define PDRCFG1 0x1U
31 #define PDRCFG2 0x2U
32 #define PDRCFG3 0x3U
33
34 /*! PMIC is used but vddcore supply is always above LVD threshold. */
35 #define PMIC_VDDCORE_RECOVERY_TIME_IGNORE (0xFFFFFFFFU)
36
37 /**
38 * @brief PMC event flags.
39 *
40 * @note These enums are meant to be OR'd together to form a bit mask.
41 */
42 enum _pmc_interrupt
43 {
44 kPMC_INT_LVDCORE = PMC_CTRL_LVDCOREIE_MASK, /*!< Vddcore Low-Voltage Detector Interrupt Enable. */
45 kPMC_INT_HVDCORE = PMC_CTRL_HVDCOREIE_MASK, /*!< Vddcore High-Voltage Detector Interrupt Enable. */
46 kPMC_INT_HVD1V8 = PMC_CTRL_HVD1V8IE_MASK, /*!< Vdd1v8 High-Voltage Detector Interrupt Enable. */
47 kPMC_INT_AUTOWK = PMC_CTRL_AUTOWKEN_MASK, /*!< PMC automatic wakeup enable and interrupt enable. */
48 kPMC_INT_INTRPAD =
49 PMC_CTRL_INTRPADEN_MASK /*!< Interrupt pad deep powerdown and deep sleep wake up & interrupt enable. */
50 };
51
52 /**
53 * @brief PMC event flags.
54 *
55 * @note These enums are meant to be OR'd together to form a bit mask.
56 */
57 enum _pmc_event_flags
58 {
59 kPMC_FLAGS_PORCORE = PMC_FLAGS_PORCOREF_MASK, /*!< POR triggered by the vddcore POR monitor (0 = no, 1 = yes). */
60 kPMC_FLAGS_POR1V8 =
61 PMC_FLAGS_POR1V8F_MASK, /*!< vdd1v8 power on event detected since last cleared(0 = no, 1 = yes). */
62 kPMC_FLAGS_PORAO18 =
63 PMC_FLAGS_PORAO18F_MASK, /*!< vdd_ao18 power on event detected since last cleared (0 = no, 1 = yes). */
64 kPMC_FLAGS_LVDCORE =
65 PMC_FLAGS_LVDCOREF_MASK, /*!< LVD tripped since last time this bit was cleared (0 = no, 1 = yes). */
66 kPMC_FLAGS_HVDCORE =
67 PMC_FLAGS_HVDCOREF_MASK, /*!< HVD tripped since last time this bit was cleared (0 = no, 1 = yes). */
68 kPMC_FLAGS_HVD1V8 =
69 PMC_FLAGS_HVD1V8F_MASK, /*!< vdd1v8 HVD tripped since last time this bit was cleared (0 = no, 1 = yes). */
70 kPMC_FLAGS_RTC =
71 PMC_FLAGS_RTCF_MASK, /*!< RTC wakeup detected since last time flag was cleared (0 = no, 1 = yes). */
72 kPMC_FLAGS_AUTOWK =
73 PMC_FLAGS_AUTOWKF_MASK, /*!< PMC Auto wakeup caused a deep sleep wakeup and interrupt (0 = no, 1 = yes). */
74 kPMC_FLAGS_INTNPADF = PMC_FLAGS_INTNPADF_MASK, /*!< Pad interrupt caused a wakeup or interrupt event since the last
75 time this flag was cleared (0 = no, 1 = yes). */
76 kPMC_FLAGS_RESETNPAD = PMC_FLAGS_RESETNPADF_MASK, /*!< Reset pad wakeup caused a wakeup or reset event since the
77 last time this bit was cleared. (0 = no, 1 = yes). */
78 kPMC_FLAGS_DEEPPD = PMC_FLAGS_DEEPPDF_MASK /*!< Deep powerdown was entered since the last time this flag was cleared
79 (0 = no, 1 = yes). */
80 };
81
82 typedef enum pd_bits
83 {
84 kPDRUNCFG_PMC_MODE0 = MAKE_PD_BITS(PDRCFG0, 1U),
85 kPDRUNCFG_PMC_MODE1 = MAKE_PD_BITS(PDRCFG0, 2U),
86 kPDRUNCFG_LP_VDD_COREREG = MAKE_PD_BITS(PDRCFG0, 4U),
87 kPDRUNCFG_LP_PMCREF = MAKE_PD_BITS(PDRCFG0, 6U),
88 kPDRUNCFG_PD_HVD1V8 = MAKE_PD_BITS(PDRCFG0, 7U),
89 kPDRUNCFG_LP_PORCORE = MAKE_PD_BITS(PDRCFG0, 8U),
90 kPDRUNCFG_LP_LVDCORE = MAKE_PD_BITS(PDRCFG0, 9U),
91 kPDRUNCFG_PD_HVDCORE = MAKE_PD_BITS(PDRCFG0, 10U),
92 kPDRUNCFG_PD_SYSXTAL = MAKE_PD_BITS(PDRCFG0, 13U),
93 kPDRUNCFG_PD_LPOSC = MAKE_PD_BITS(PDRCFG0, 14U),
94 kPDRUNCFG_PD_SFRO = MAKE_PD_BITS(PDRCFG0, 15U),
95 kPDRUNCFG_PD_FFRO = MAKE_PD_BITS(PDRCFG0, 16U),
96 kPDRUNCFG_PD_SYSPLL_LDO = MAKE_PD_BITS(PDRCFG0, 17U),
97 kPDRUNCFG_PD_SYSPLL_ANA = MAKE_PD_BITS(PDRCFG0, 18U),
98 kPDRUNCFG_PD_AUDPLL_LDO = MAKE_PD_BITS(PDRCFG0, 19U),
99 kPDRUNCFG_PD_AUDPLL_ANA = MAKE_PD_BITS(PDRCFG0, 20U),
100 kPDRUNCFG_PD_ADC = MAKE_PD_BITS(PDRCFG0, 21U),
101 kPDRUNCFG_LP_ADC = MAKE_PD_BITS(PDRCFG0, 22U),
102 kPDRUNCFG_PD_ADC_TEMPSNS = MAKE_PD_BITS(PDRCFG0, 23U),
103 kPDRUNCFG_PD_ACMP = MAKE_PD_BITS(PDRCFG0, 25U),
104 kPDRUNCFG_LP_HSPAD_VDET = MAKE_PD_BITS(PDRCFG0, 28U),
105 kPDRUNCFG_PD_HSPAD_REF = MAKE_PD_BITS(PDRCFG0, 29U),
106
107 kPDRUNCFG_APD_PQ_SRAM = MAKE_PD_BITS(PDRCFG1, 0U),
108 kPDRUNCFG_PPD_PQ_SRAM = MAKE_PD_BITS(PDRCFG1, 1U),
109 kPDRUNCFG_APD_FLEXSPI_SRAM = MAKE_PD_BITS(PDRCFG1, 2U),
110 kPDRUNCFG_PPD_FLEXSPI_SRAM = MAKE_PD_BITS(PDRCFG1, 3U),
111 kPDRUNCFG_APD_USBHS_SRAM = MAKE_PD_BITS(PDRCFG1, 4U),
112 kPDRUNCFG_PPD_USBHS_SRAM = MAKE_PD_BITS(PDRCFG1, 5U),
113 kPDRUNCFG_APD_USDHC0_SRAM = MAKE_PD_BITS(PDRCFG1, 6U),
114 kPDRUNCFG_PPD_USDHC0_SRAM = MAKE_PD_BITS(PDRCFG1, 7U),
115 kPDRUNCFG_APD_USDHC1_SRAM = MAKE_PD_BITS(PDRCFG1, 8U),
116 kPDRUNCFG_PPD_USDHC1_SRAM = MAKE_PD_BITS(PDRCFG1, 9U),
117 kPDRUNCFG_APD_CASPER_SRAM = MAKE_PD_BITS(PDRCFG1, 10U),
118 kPDRUNCFG_PPD_CASPER_SRAM = MAKE_PD_BITS(PDRCFG1, 11U),
119 kPDRUNCFG_APD_DSP_CACHE_REGF = MAKE_PD_BITS(PDRCFG1, 24U),
120 kPDRUNCFG_PPD_DSP_CACHE_REGF = MAKE_PD_BITS(PDRCFG1, 25U),
121 kPDRUNCFG_APD_DSP_TCM_REGF = MAKE_PD_BITS(PDRCFG1, 26U),
122 kPDRUNCFG_PPD_DSP_TCM_REGF = MAKE_PD_BITS(PDRCFG1, 27U),
123 kPDRUNCFG_PD_ROM = MAKE_PD_BITS(PDRCFG1, 28U),
124 kPDRUNCFG_SRAM_SLEEP = MAKE_PD_BITS(PDRCFG1, 31U),
125
126 kPDRUNCFG_APD_SRAM_IF0 = MAKE_PD_BITS(PDRCFG2, 0U),
127 kPDRUNCFG_APD_SRAM_IF1 = MAKE_PD_BITS(PDRCFG2, 1U),
128 kPDRUNCFG_APD_SRAM_IF2 = MAKE_PD_BITS(PDRCFG2, 2U),
129 kPDRUNCFG_APD_SRAM_IF3 = MAKE_PD_BITS(PDRCFG2, 3U),
130 kPDRUNCFG_APD_SRAM_IF4 = MAKE_PD_BITS(PDRCFG2, 4U),
131 kPDRUNCFG_APD_SRAM_IF5 = MAKE_PD_BITS(PDRCFG2, 5U),
132 kPDRUNCFG_APD_SRAM_IF6 = MAKE_PD_BITS(PDRCFG2, 6U),
133 kPDRUNCFG_APD_SRAM_IF7 = MAKE_PD_BITS(PDRCFG2, 7U),
134 kPDRUNCFG_APD_SRAM_IF8 = MAKE_PD_BITS(PDRCFG2, 8U),
135 kPDRUNCFG_APD_SRAM_IF9 = MAKE_PD_BITS(PDRCFG2, 9U),
136 kPDRUNCFG_APD_SRAM_IF10 = MAKE_PD_BITS(PDRCFG2, 10U),
137 kPDRUNCFG_APD_SRAM_IF11 = MAKE_PD_BITS(PDRCFG2, 11U),
138 kPDRUNCFG_APD_SRAM_IF12 = MAKE_PD_BITS(PDRCFG2, 12U),
139 kPDRUNCFG_APD_SRAM_IF13 = MAKE_PD_BITS(PDRCFG2, 13U),
140 kPDRUNCFG_APD_SRAM_IF14 = MAKE_PD_BITS(PDRCFG2, 14U),
141 kPDRUNCFG_APD_SRAM_IF15 = MAKE_PD_BITS(PDRCFG2, 15U),
142 kPDRUNCFG_APD_SRAM_IF16 = MAKE_PD_BITS(PDRCFG2, 16U),
143 kPDRUNCFG_APD_SRAM_IF17 = MAKE_PD_BITS(PDRCFG2, 17U),
144 kPDRUNCFG_APD_SRAM_IF18 = MAKE_PD_BITS(PDRCFG2, 18U),
145 kPDRUNCFG_APD_SRAM_IF19 = MAKE_PD_BITS(PDRCFG2, 19U),
146 kPDRUNCFG_APD_SRAM_IF20 = MAKE_PD_BITS(PDRCFG2, 20U),
147 kPDRUNCFG_APD_SRAM_IF21 = MAKE_PD_BITS(PDRCFG2, 21U),
148 kPDRUNCFG_APD_SRAM_IF22 = MAKE_PD_BITS(PDRCFG2, 22U),
149 kPDRUNCFG_APD_SRAM_IF23 = MAKE_PD_BITS(PDRCFG2, 23U),
150 kPDRUNCFG_APD_SRAM_IF24 = MAKE_PD_BITS(PDRCFG2, 24U),
151 kPDRUNCFG_APD_SRAM_IF25 = MAKE_PD_BITS(PDRCFG2, 25U),
152 kPDRUNCFG_APD_SRAM_IF26 = MAKE_PD_BITS(PDRCFG2, 26U),
153 kPDRUNCFG_APD_SRAM_IF27 = MAKE_PD_BITS(PDRCFG2, 27U),
154 kPDRUNCFG_APD_SRAM_IF28 = MAKE_PD_BITS(PDRCFG2, 28U),
155 kPDRUNCFG_APD_SRAM_IF29 = MAKE_PD_BITS(PDRCFG2, 29U),
156
157 kPDRUNCFG_PPD_SRAM_IF0 = MAKE_PD_BITS(PDRCFG3, 0U),
158 kPDRUNCFG_PPD_SRAM_IF1 = MAKE_PD_BITS(PDRCFG3, 1U),
159 kPDRUNCFG_PPD_SRAM_IF2 = MAKE_PD_BITS(PDRCFG3, 2U),
160 kPDRUNCFG_PPD_SRAM_IF3 = MAKE_PD_BITS(PDRCFG3, 3U),
161 kPDRUNCFG_PPD_SRAM_IF4 = MAKE_PD_BITS(PDRCFG3, 4U),
162 kPDRUNCFG_PPD_SRAM_IF5 = MAKE_PD_BITS(PDRCFG3, 5U),
163 kPDRUNCFG_PPD_SRAM_IF6 = MAKE_PD_BITS(PDRCFG3, 6U),
164 kPDRUNCFG_PPD_SRAM_IF7 = MAKE_PD_BITS(PDRCFG3, 7U),
165 kPDRUNCFG_PPD_SRAM_IF8 = MAKE_PD_BITS(PDRCFG3, 8U),
166 kPDRUNCFG_PPD_SRAM_IF9 = MAKE_PD_BITS(PDRCFG3, 9U),
167 kPDRUNCFG_PPD_SRAM_IF10 = MAKE_PD_BITS(PDRCFG3, 10U),
168 kPDRUNCFG_PPD_SRAM_IF11 = MAKE_PD_BITS(PDRCFG3, 11U),
169 kPDRUNCFG_PPD_SRAM_IF12 = MAKE_PD_BITS(PDRCFG3, 12U),
170 kPDRUNCFG_PPD_SRAM_IF13 = MAKE_PD_BITS(PDRCFG3, 13U),
171 kPDRUNCFG_PPD_SRAM_IF14 = MAKE_PD_BITS(PDRCFG3, 14U),
172 kPDRUNCFG_PPD_SRAM_IF15 = MAKE_PD_BITS(PDRCFG3, 15U),
173 kPDRUNCFG_PPD_SRAM_IF16 = MAKE_PD_BITS(PDRCFG3, 16U),
174 kPDRUNCFG_PPD_SRAM_IF17 = MAKE_PD_BITS(PDRCFG3, 17U),
175 kPDRUNCFG_PPD_SRAM_IF18 = MAKE_PD_BITS(PDRCFG3, 18U),
176 kPDRUNCFG_PPD_SRAM_IF19 = MAKE_PD_BITS(PDRCFG3, 19U),
177 kPDRUNCFG_PPD_SRAM_IF20 = MAKE_PD_BITS(PDRCFG3, 20U),
178 kPDRUNCFG_PPD_SRAM_IF21 = MAKE_PD_BITS(PDRCFG3, 21U),
179 kPDRUNCFG_PPD_SRAM_IF22 = MAKE_PD_BITS(PDRCFG3, 22U),
180 kPDRUNCFG_PPD_SRAM_IF23 = MAKE_PD_BITS(PDRCFG3, 23U),
181 kPDRUNCFG_PPD_SRAM_IF24 = MAKE_PD_BITS(PDRCFG3, 24U),
182 kPDRUNCFG_PPD_SRAM_IF25 = MAKE_PD_BITS(PDRCFG3, 25U),
183 kPDRUNCFG_PPD_SRAM_IF26 = MAKE_PD_BITS(PDRCFG3, 26U),
184 kPDRUNCFG_PPD_SRAM_IF27 = MAKE_PD_BITS(PDRCFG3, 27U),
185 kPDRUNCFG_PPD_SRAM_IF28 = MAKE_PD_BITS(PDRCFG3, 28U),
186 kPDRUNCFG_PPD_SRAM_IF29 = MAKE_PD_BITS(PDRCFG3, 29U),
187 /*
188 This enum member has no practical meaning,it is used to avoid MISRA issue,
189 user should not trying to use it.
190 */
191 kPDRUNCFG_ForceUnsigned = (int)0x80000000U,
192 } pd_bit_t;
193
194 /*! @brief Power mode configuration API parameter */
195 typedef enum _power_mode_config
196 {
197 kPmu_Sleep = 0U,
198 kPmu_Deep_Sleep = 1U,
199 kPmu_Deep_PowerDown = 2U,
200 kPmu_Full_Deep_PowerDown = 3U,
201 } power_mode_cfg_t;
202
203 /*! @brief Body Bias mode definition */
204 typedef enum _body_bias_mode
205 {
206 kPmu_Fbb = 0x01U, /* Forward Body Bias Mode. */
207 kPmu_Rbb = 0x02U, /* Reverse Body Bias Mode. */
208 kPmu_Nbb = 0x03U, /* Normal Body Bias Mode. */
209 } body_bias_mode_t;
210
211 /*! @brief PMIC mode pin configuration API parameter */
212 #define SYSCTL0_TUPLE_REG(reg) (*((volatile uint32_t *)(((uint32_t)(SYSCTL0)) + (((uint32_t)(reg)) & 0xFFFU))))
213 typedef enum _pmic_mode_reg
214 {
215 kCfg_Run = 0x610,
216 kCfg_Sleep = 0x600,
217 } pmic_mode_reg_t;
218
219 /*!
220 * @brief pad voltage range value.
221 */
222 typedef enum _power_pad_vrange_val
223 {
224 kPadVol_171_360 = 0U, /*!< Voltage from 1.71V to 3.60V. */
225 kPadVol_171_198 = 1U, /*!< Voltage from 1.71V to 1.98V. */
226 kPadVol_300_360 = 2U, /*!< Voltage from 3.00V to 3.60V. */
227 } power_pad_vrange_val_t;
228
229 /*!
230 * @brief pad voltage range configuration.
231 */
232 typedef struct _power_pad_vrange
233 {
234 uint32_t Vdde0Range : 2; /*!< VDDE0 voltage range for VDDIO_0. @ref power_pad_vrange_val_t */
235 uint32_t Vdde1Range : 2; /*!< VDDE1 voltage range for VDDIO_1. @ref power_pad_vrange_val_t */
236 uint32_t Vdde2Range : 2; /*!< VDDE2 voltage range for VDDIO_2. @ref power_pad_vrange_val_t */
237 uint32_t : 26; /*!< Reserved. */
238 } power_pad_vrange_t;
239
240 /*!
241 * @brief LVD falling trip voltage value.
242 */
243 typedef enum _power_lvd_falling_trip_vol_val
244 {
245 kLvdFallingTripVol_720 = 0U, /*!< Voltage 720mV. */
246 kLvdFallingTripVol_735 = 1U, /*!< Voltage 735mV. */
247 kLvdFallingTripVol_750 = 2U, /*!< Voltage 750mV. */
248 kLvdFallingTripVol_765 = 3U, /*!< Voltage 765mV. */
249 kLvdFallingTripVol_780 = 4U, /*!< Voltage 780mV. */
250 kLvdFallingTripVol_795 = 5U, /*!< Voltage 795mV. */
251 kLvdFallingTripVol_810 = 6U, /*!< Voltage 810mV. */
252 kLvdFallingTripVol_825 = 7U, /*!< Voltage 825mV. */
253 kLvdFallingTripVol_840 = 8U, /*!< Voltage 840mV. */
254 kLvdFallingTripVol_855 = 9U, /*!< Voltage 855mV. */
255 kLvdFallingTripVol_870 = 10U, /*!< Voltage 870mV. */
256 kLvdFallingTripVol_885 = 11U, /*!< Voltage 885mV. */
257 kLvdFallingTripVol_900 = 12U, /*!< Voltage 900mV. */
258 kLvdFallingTripVol_915 = 13U, /*!< Voltage 915mV. */
259 kLvdFallingTripVol_930 = 14U, /*!< Voltage 930mV. */
260 kLvdFallingTripVol_945 = 15U, /*!< Voltage 945mV. */
261 } power_lvd_falling_trip_vol_val_t;
262
263 /*!
264 * @brief Part temperature range.
265 */
266 typedef enum _power_part_temp_range
267 {
268 kPartTemp_0C_P85C = 0U, /*!< Part temp range 0C - 85C. */
269 kPartTemp_N20C_P85C = 1U, /*!< Part temp range -20C - 85C. */
270 } power_part_temp_range_t;
271
272 /*!
273 * @brief Voltage operation range.
274 */
275 typedef enum _power_volt_op_range
276 {
277 kVoltOpLowRange = 0U, /*!< Voltage operation range is (0.7V, 0.8V, 0.9V).
278 Maximum supported CM33 frequency is 220MHz for 0C-85C part and 215MHz for -20C-85C part.
279 Maximum supported DSP frequency is 375MHz for 0C-85C part and 355MHz for -20C-85C part. */
280 kVoltOpFullRange = 1U, /*!< Voltage operation range is (0.7V, 0.8V, 0.9V, 1.0V, 1.13V). This range can support full
281 CM33/DSP speed clarified in Data Sheet. */
282 } power_volt_op_range_t;
283
284 /*! @brief VDDCORE supply source. */
285 typedef enum _power_vddcore_src
286 {
287 kVddCoreSrc_LDO = 0U, /*!< VDDCORE is supplied by onchip regulator. */
288 kVddCoreSrc_PMIC = 1U, /*!< VDDCORE is supplied by external PMIC. */
289 } power_vddcore_src_t;
290
291 /*!
292 * @brief vddcore or vdd1v8 power on selection for different PMIC mode.
293 * vddcore and vdd1v8 are always on in mode0. Refer to PMC->PMICCFG.
294 */
295 typedef enum _power_control_for_pmic_mode
296 {
297 kVddCoreOnMode1 = 0x2U, /*!< VDDCORE is powered in PMIC mode1. */
298 kVddCoreOnMode2 = 0x4U, /*!< VDDCORE is powered in PMIC mode2. */
299 kVddCoreOnMode3 = 0x8U, /*!< VDDCORE is powered in PMIC mode3. */
300 kVdd1v8OnMode1 = 0x20U, /*!< VDD1V8 is powered in PMIC mode1. */
301 kVdd1v8OnMode2 = 0x40U, /*!< VDD1V8 is powered in PMIC mode2. */
302 kVdd1v8OnMode3 = 0x80U, /*!< VDD1V8 is powered in PMIC mode3. */
303 } power_control_for_pmic_mode;
304
305 /*! Callback function used to change VDDCORE when the VDDCORE is supplied by external PMIC. Refer to
306 * #POWER_SetVddCoreSupplySrc() */
307 typedef void (*power_vddcore_set_func_t)(uint32_t millivolt);
308
309 /*******************************************************************************
310 * API
311 ******************************************************************************/
312
313 #ifdef __cplusplus
314 extern "C" {
315 #endif
316
317 /*!
318 * @brief API to set vddcore or vdd1v8 power on for PMIC modes which is responded to PDRUNCFG0[PMIC_MODE] or
319 * PDSLEEPCFG0[PMIC_MODE] select pin values. If not set, the driver will use default configurations for different PMIC
320 * mode.
321 * The default configuration is as below.
322 * PMIC_MODE: power mode select
323 * 0b00 run mode, all supplies on.
324 * 0b01 deep sleep mode, all supplies on.
325 * 0b10 deep powerdown mode, vddcore off.
326 * 0b11 full deep powerdown mode vdd1v8 and vddcore off.
327 *
328 * Note, be cautious to modify the VDD state in different PMIC mode. When the default configuration is changed, use
329 * exclude_from_pd[0] to configure the PMIC mode for deep sleep and power down mode.
330 *
331 * @param vddSelect the ORd value of @ref power_control_for_pmic_mode. Defines run (all supplies on), deep power-down
332 * (VDDCORE off), and true deep power-down (VDD1V8 and VDDCORE off).
333 */
334 void POWER_PmicPowerModeSelectControl(uint32_t vddSelect);
335
336 /*!
337 * @brief API to enable PDRUNCFG bit in the Sysctl0. Note that enabling the bit powers down the peripheral
338 *
339 * @param en peripheral for which to enable the PDRUNCFG bit
340 */
POWER_EnablePD(pd_bit_t en)341 static inline void POWER_EnablePD(pd_bit_t en)
342 {
343 /* PDRUNCFGSET */
344 SYSCTL0_PDRCFGSET_REG(((uint32_t)en) >> 8UL) = (1UL << (((uint32_t)en) & 0xFFU));
345 }
346
347 /*!
348 * @brief API to disable PDRUNCFG bit in the Sysctl0. Note that disabling the bit powers up the peripheral
349 *
350 * @param en peripheral for which to disable the PDRUNCFG bit
351 */
POWER_DisablePD(pd_bit_t en)352 static inline void POWER_DisablePD(pd_bit_t en)
353 {
354 /* PDRUNCFGCLR */
355 SYSCTL0_PDRCFGCLR_REG(((uint32_t)en) >> 8UL) = (1UL << (((uint32_t)en) & 0xFFU));
356 }
357
358 /*!
359 * @brief API to enable deep sleep bit in the ARM Core.
360 */
POWER_EnableDeepSleep(void)361 static inline void POWER_EnableDeepSleep(void)
362 {
363 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
364 }
365
366 /*!
367 * @brief API to disable deep sleep bit in the ARM Core.
368 */
POWER_DisableDeepSleep(void)369 static inline void POWER_DisableDeepSleep(void)
370 {
371 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
372 }
373
374 /**
375 * @brief API to update XTAL oscillator settling time .
376 * @param osc_delay : OSC stabilization time in unit of microsecond
377 */
378 void POWER_UpdateOscSettlingTime(uint32_t osc_delay);
379
380 /**
381 * @brief API to update on-board PMIC vddcore recovery time.
382 *
383 * NOTE: If LDO is used instead of PMIC, don't call it. Otherwise it must be called to allow power library to well
384 * handle the deep sleep process.
385 *
386 * @param pmic_delay : PMIC stabilization time in unit of microsecond, or PMIC_VDDCORE_RECOVERY_TIME_IGNORE if not
387 * care.
388 */
389 void POWER_UpdatePmicRecoveryTime(uint32_t pmic_delay);
390
391 /*!
392 * @brief API to apply updated PMC PDRUNCFG bits in the Sysctl0.
393 */
394 void POWER_ApplyPD(void);
395
396 /**
397 * @brief Clears the PMC event flags state.
398 * @param statusMask : A bitmask of event flags that are to be cleared.
399 */
400 void POWER_ClearEventFlags(uint32_t statusMask);
401
402 /**
403 * @brief Get the PMC event flags state.
404 * @return PMC FLAGS register value
405 */
406 uint32_t POWER_GetEventFlags(void);
407
408 /**
409 * @brief Enable the PMC interrupt requests.
410 * @param interruptMask : A bitmask of of interrupts to enable.
411 */
412 void POWER_EnableInterrupts(uint32_t interruptMask);
413
414 /**
415 * @brief Disable the PMC interrupt requests.
416 * @param interruptMask : A bitmask of of interrupts to disable.
417 */
418 void POWER_DisableInterrupts(uint32_t interruptMask);
419
420 /**
421 * @brief Set the PMC analog buffer for references or ATX2.
422 * @param enable : Set to true to enable analog buffer for references or ATX2, false to disable.
423 */
424 void POWER_SetAnalogBuffer(bool enable);
425
426 /**
427 * @brief Get PMIC_MODE pins configure value.
428 * @param reg : PDSLEEPCFG0 or PDRUNCFG0 register offset
429 * @return PMIC_MODE pins value in PDSLEEPCFG0
430 */
POWER_GetPmicMode(pmic_mode_reg_t reg)431 static inline uint32_t POWER_GetPmicMode(pmic_mode_reg_t reg)
432 {
433 uint32_t mode = (uint32_t)reg;
434
435 return ((SYSCTL0_TUPLE_REG(mode) & (SYSCTL0_PDSLEEPCFG0_PMIC_MODE0_MASK | SYSCTL0_PDSLEEPCFG0_PMIC_MODE1_MASK)) >>
436 SYSCTL0_PDSLEEPCFG0_PMIC_MODE0_SHIFT);
437 }
438
439 /**
440 * @brief Get RBB/FBB bit value.
441 * @param reg : PDSLEEPCFG0 or PDRUNCFG0 register offset
442 * @return Current body bias mode
443 */
POWER_GetBodyBiasMode(pmic_mode_reg_t reg)444 static inline body_bias_mode_t POWER_GetBodyBiasMode(pmic_mode_reg_t reg)
445 {
446 uint32_t mode = (uint32_t)reg;
447 uint32_t bbMode = (SYSCTL0_TUPLE_REG(mode) & (SYSCTL0_PDSLEEPCFG0_RBB_PD_MASK | SYSCTL0_PDSLEEPCFG0_FBB_PD_MASK)) >>
448 SYSCTL0_PDSLEEPCFG0_RBB_PD_SHIFT;
449
450 return (body_bias_mode_t)bbMode;
451 }
452
453 /*!
454 * @brief Configure pad voltage level. Wide voltage range cost more power due to enabled voltage detector.
455 *
456 * NOTE: BE CAUTIOUS TO CALL THIS API. IF THE PAD SUPPLY IS BEYOND THE SET RANGE, SILICON MIGHT BE DAMAGED.
457 *
458 * @param config pad voltage range configuration.
459 */
460 void POWER_SetPadVolRange(const power_pad_vrange_t *config);
461
462 /**
463 * @brief PMC Enter Rbb mode function call
464 */
465 #if defined(DOXYGEN_OUTPUT) && DOXYGEN_OUTPUT
466 void POWER_EnterRbb(void);
467 #else
468 AT_QUICKACCESS_SECTION_CODE(void POWER_EnterRbb(void));
469 #endif
470
471 /**
472 * @brief PMC Enter Fbb mode function call
473 */
474 #if defined(DOXYGEN_OUTPUT) && DOXYGEN_OUTPUT
475 void POWER_EnterFbb(void);
476 #else
477 AT_QUICKACCESS_SECTION_CODE(void POWER_EnterFbb(void));
478 #endif
479
480 /**
481 * @brief PMC exit Rbb & Fbb mode function call
482 */
483 #if defined(DOXYGEN_OUTPUT) && DOXYGEN_OUTPUT
484 void POWER_EnterNbb(void);
485 #else
486 AT_QUICKACCESS_SECTION_CODE(void POWER_EnterNbb(void));
487 #endif
488
489 /**
490 * @brief Deprecated and replaced by #POWER_SetVoltageForFreq()! PMC Set Ldo volatage for particular frequency.
491 * NOTE: The API is only valid when MAINPLLCLKDIV[7:0] and DSPPLLCLKDIV[7:0] are 0.
492 * If LVD falling trip voltage is higher than the required core voltage for particular frequency,
493 * LVD voltage will be decreased to safe level to avoid unexpected LVD reset or interrupt event.
494 * @param tempRange : part temperature range
495 * @param voltOpRange : voltage operation range.
496 * @param cm33Freq : CM33 CPU clock frequency value
497 * @param dspFreq : DSP CPU clock frequency value
498 * @return true for success and false for CPU frequency out of specified voltOpRange.
499 */
500 bool POWER_SetLdoVoltageForFreq(power_part_temp_range_t tempRange,
501 power_volt_op_range_t voltOpRange,
502 uint32_t cm33Freq,
503 uint32_t dspFreq);
504
505 /**
506 * @brief Set VDDCORE supply source, PMIC or on-chip regulator.
507 * @param src : #power_vddcore_src_t, VDDCore supply source
508 */
509 void POWER_SetVddCoreSupplySrc(power_vddcore_src_t src);
510
511 /**
512 * @brief Set the core supply setting function if PMIC is used. The function is not needed and ignored when
513 * using the onchip regulator to supply VDDCORE.
514 * @param func : #power_vddcore_set_func_t, the PMIC core supply voltage set function.
515 */
516 void POWER_SetPmicCoreSupplyFunc(power_vddcore_set_func_t func);
517
518 /**
519 * @brief PMC Set volatage for particular frequency with given minimum value. #POWER_SetVddCoreSupplySrc should be
520 * called in advance to tell power driver the supply source. If PMIC is used, the VDDCORE setting function
521 * should be set by #POWER_SetPmicCoreSupplyFunc before this API is called.
522 * NOTE: The API is only valid when MAINPLLCLKDIV[7:0] and DSPPLLCLKDIV[7:0] are 0.
523 * If LVD falling trip voltage is higher than therequired core voltage for particular frequency,
524 * LVD voltage will be decreased to safe level to avoid unexpected LVD reset or interrupt event.
525 * @param tempRange : part temperature range
526 * @param voltOpRange : voltage operation range.
527 * @param cm33Freq : CM33 CPU clock frequency value
528 * @param dspFreq : DSP CPU clock frequency value
529 * @param mini_volt : minimum voltage in millivolt(mV) for VDDCORE. Should <= 1130mV, 0 means use the core frequency
530 * to calculate voltage.
531 * @return true for success and false for CPU frequency out of specified voltOpRange or failed to set voltage.
532 */
533 bool POWER_SetVoltageForFreq(power_part_temp_range_t tempRange,
534 power_volt_op_range_t voltOpRange,
535 uint32_t cm33Freq,
536 uint32_t dspFreq,
537 uint32_t mini_volt);
538
539 /*!
540 * @brief Set vddcore low voltage detection falling trip voltage.
541 * @param volt target LVD voltage to set.
542 */
543 void POWER_SetLvdFallingTripVoltage(power_lvd_falling_trip_vol_val_t volt);
544
545 /**
546 * @brief Get current vddcore low voltage detection falling trip voltage.
547 * @return Current LVD voltage.
548 */
549 power_lvd_falling_trip_vol_val_t POWER_GetLvdFallingTripVoltage(void);
550
551 /**
552 * @brief Disable low voltage detection, no reset or interrupt is triggered when vddcore voltage drops below
553 * threshold.
554 * NOTE: This API is for internal use only. Application should not touch it.
555 */
556 void POWER_DisableLVD(void);
557
558 /**
559 * @brief Restore low voltage detection setting.
560 * NOTE: This API is for internal use only. Application should not touch it.
561 */
562 void POWER_RestoreLVD(void);
563
564 /**
565 * @brief Set PMIC_MODE pins configure value.
566 * @param mode : PMIC MODE pin value
567 * @param reg : PDSLEEPCFG0 or PDRUNCFG0 register offset
568 * @return PMIC_MODE pins value in PDSLEEPCFG0
569 */
570 void POWER_SetPmicMode(uint32_t mode, pmic_mode_reg_t reg);
571
572 /**
573 * @brief Configures and enters in SLEEP low power mode
574 */
575 void POWER_EnterSleep(void);
576
577 /**
578 * @brief PMC Deep Sleep function call
579 * @param exclude_from_pd Bit mask of the PDRUNCFG0 ~ PDRUNCFG3 that needs to be powered on during Deep Sleep mode
580 * selected.
581 */
582 #if defined(DOXYGEN_OUTPUT) && DOXYGEN_OUTPUT
583 void POWER_EnterDeepSleep(const uint32_t exclude_from_pd[4]);
584 #else
585 AT_QUICKACCESS_SECTION_CODE(void POWER_EnterDeepSleep(const uint32_t exclude_from_pd[4]));
586 #endif
587
588 /**
589 * @brief PMC Deep Power Down function call
590 * @param exclude_from_pd Bit mask of the PDRUNCFG0 ~ PDRUNCFG3 that needs to be powered on during Deep Power Down
591 * mode selected.
592 */
593 void POWER_EnterDeepPowerDown(const uint32_t exclude_from_pd[4]);
594
595 /**
596 * @brief PMC Full Deep Power Down function call
597 * @param exclude_from_pd Bit mask of the PDRUNCFG0 ~ PDRUNCFG3 that needs to be powered on during Full Deep Power
598 * Down mode selected.
599 */
600 void POWER_EnterFullDeepPowerDown(const uint32_t exclude_from_pd[4]);
601
602 /*!
603 * @brief Power Library API to enter different power mode.
604 *
605 * @param mode Power mode to enter.
606 * @param exclude_from_pd Bit mask of the PDRUNCFG0 ~ PDRUNCFG3 that needs to be powered on during power mode selected.
607 */
608 void POWER_EnterPowerMode(power_mode_cfg_t mode, const uint32_t exclude_from_pd[4]);
609
610 /*!
611 * @brief Enable specific interrupt for wake-up from deep-sleep mode.
612 * Enable the interrupt for wake-up from deep sleep mode.
613 * Some interrupts are typically used in sleep mode only and will not occur during
614 * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
615 * those clocks (significantly increasing power consumption in the reduced power mode),
616 * making these wake-ups possible.
617 * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internally).
618 * @param interrupt The IRQ number.
619 */
620 void EnableDeepSleepIRQ(IRQn_Type interrupt);
621
622 /*!
623 * @brief Disable specific interrupt for wake-up from deep-sleep mode.
624 * Disable the interrupt for wake-up from deep sleep mode.
625 * Some interrupts are typically used in sleep mode only and will not occur during
626 * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
627 * those clocks (significantly increasing power consumption in the reduced power mode),
628 * making these wake-ups possible.
629 * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internally).
630 * @param interrupt The IRQ number.
631 */
632 void DisableDeepSleepIRQ(IRQn_Type interrupt);
633
634 /*!
635 * @brief Power Library API to return the library version.
636 *
637 * @return version number of the power library
638 */
639 uint32_t POWER_GetLibVersion(void);
640
641 #ifdef __cplusplus
642 }
643 #endif
644
645 /**
646 * @}
647 */
648
649 #endif /* _FSL_POWER_H_ */
650
