1 /*
2 ** ###################################################################
3 ** Processors: MIMXRT595SFAWC_cm33
4 ** MIMXRT595SFFOC_cm33
5 **
6 ** Compilers: GNU C Compiler
7 ** IAR ANSI C/C++ Compiler for ARM
8 ** Keil ARM C/C++ Compiler
9 ** MCUXpresso Compiler
10 **
11 ** Reference manual: iMXRT500RM Rev.0, 01/2021
12 ** Version: rev. 5.0, 2020-08-27
13 ** Build: b220711
14 **
15 ** Abstract:
16 ** Provides a system configuration function and a global variable that
17 ** contains the system frequency. It configures the device and initializes
18 ** the oscillator (PLL) that is part of the microcontroller device.
19 **
20 ** Copyright 2016 Freescale Semiconductor, Inc.
21 ** Copyright 2016-2022 NXP
22 ** All rights reserved.
23 **
24 ** SPDX-License-Identifier: BSD-3-Clause
25 **
26 ** http: www.nxp.com
27 ** mail: support@nxp.com
28 **
29 ** Revisions:
30 ** - rev. 1.0 (2019-04-19)
31 ** Initial version.
32 ** - rev. 2.0 (2019-07-22)
33 ** Base on rev 0.7 RM.
34 ** - rev. 3.0 (2020-03-16)
35 ** Base on Rev.A RM.
36 ** - rev. 4.0 (2020-05-18)
37 ** Base on Rev.B RM.
38 ** - rev. 5.0 (2020-08-27)
39 ** Base on Rev.C RM.
40 **
41 ** ###################################################################
42 */
43
44 /*!
45 * @file MIMXRT595S_cm33
46 * @version 5.0
47 * @date 2020-08-27
48 * @brief Device specific configuration file for MIMXRT595S_cm33 (implementation
49 * file)
50 *
51 * Provides a system configuration function and a global variable that contains
52 * the system frequency. It configures the device and initializes the oscillator
53 * (PLL) that is part of the microcontroller device.
54 */
55
56 #include <stdint.h>
57 #include "fsl_device_registers.h"
58
59 #define SYSTEM_IS_XIP_FLEXSPI() \
60 ((((uint32_t)SystemCoreClockUpdate >= 0x08000000U) && ((uint32_t)SystemCoreClockUpdate < 0x10000000U)) || \
61 (((uint32_t)SystemCoreClockUpdate >= 0x18000000U) && ((uint32_t)SystemCoreClockUpdate < 0x20000000U)))
62
63 /* Get FRO DIV clock from FRODIVSEL */
getFroDivClk(void)64 static uint32_t getFroDivClk(void)
65 {
66 uint32_t freq = 0U;
67
68 switch ((CLKCTL0->FRODIVSEL) & CLKCTL0_FRODIVSEL_SEL_MASK)
69 {
70 case CLKCTL0_FRODIVSEL_SEL(0):
71 freq = CLK_FRO_DIV2_CLK;
72 break;
73 case CLKCTL0_FRODIVSEL_SEL(1):
74 freq = CLK_FRO_DIV4_CLK;
75 break;
76 case CLKCTL0_FRODIVSEL_SEL(2):
77 freq = CLK_FRO_DIV8_CLK;
78 break;
79 case CLKCTL0_FRODIVSEL_SEL(3):
80 freq = CLK_FRO_DIV16_CLK;
81 break;
82 default:
83 freq = 0U;
84 break;
85 }
86
87 return freq;
88 }
89
90 /* ----------------------------------------------------------------------------
91 -- Core clock
92 ---------------------------------------------------------------------------- */
93
94 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
95
96 /* ----------------------------------------------------------------------------
97 -- SystemInit()
98 ---------------------------------------------------------------------------- */
99
SystemInit(void)100 __attribute__((weak)) void SystemInit(void)
101 {
102 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
103 SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access in Secure mode */
104 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
105 SCB_NS->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access in Non-secure mode */
106 #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
107 #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
108
109 SCB->CPACR |= ((3UL << 0 * 2) | (3UL << 1 * 2)); /* set CP0, CP1 Full Access in Secure mode (enable PowerQuad) */
110
111 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
112 SCB_NS->CPACR |=
113 ((3UL << 0 * 2) | (3UL << 1 * 2)); /* set CP0, CP1 Full Access in Non-secure mode (enable PowerQuad) */
114 #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
115
116 SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */
117
118 SYSCTL0->DSPSTALL = SYSCTL0_DSPSTALL_DSPSTALL_MASK;
119
120 PMC->CTRL |= PMC_CTRL_CLKDIVEN_MASK; /* enable the internal clock divider for power saving */
121
122 if (SYSTEM_IS_XIP_FLEXSPI() && (CACHE64_POLSEL0->POLSEL == 0U)) /* set CAHCHE64 if not configured */
123 {
124 /* set command to invalidate all ways and write GO bit to initiate command */
125 CACHE64_CTRL0->CCR = CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR_INVW0_MASK;
126 CACHE64_CTRL0->CCR |= CACHE64_CTRL_CCR_GO_MASK;
127 /* Wait until the command completes */
128 while ((CACHE64_CTRL0->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0U)
129 {
130 }
131 /* Enable cache, enable write buffer */
132 CACHE64_CTRL0->CCR = (CACHE64_CTRL_CCR_ENWRBUF_MASK | CACHE64_CTRL_CCR_ENCACHE_MASK);
133
134 /* Set whole FlexSPI0 space to write through. */
135 CACHE64_POLSEL0->REG0_TOP = 0x07FFFC00U;
136 CACHE64_POLSEL0->REG1_TOP = 0x0U;
137 CACHE64_POLSEL0->POLSEL = 0x1U;
138
139 __ISB();
140 __DSB();
141 }
142
143 SystemInitHook();
144 }
145
146 /* ----------------------------------------------------------------------------
147 -- SystemCoreClockUpdate()
148 ---------------------------------------------------------------------------- */
149
SystemCoreClockUpdate(void)150 void SystemCoreClockUpdate(void)
151 {
152 /* iMXRT5xx systemCoreClockUpdate */
153 uint32_t freq = 0U;
154 uint64_t freqTmp = 0U;
155
156 switch ((CLKCTL0->MAINCLKSELB) & CLKCTL0_MAINCLKSELB_SEL_MASK)
157 {
158 case CLKCTL0_MAINCLKSELB_SEL(0): /* MAINCLKSELA clock */
159 switch ((CLKCTL0->MAINCLKSELA) & CLKCTL0_MAINCLKSELA_SEL_MASK)
160 {
161 case CLKCTL0_MAINCLKSELA_SEL(0): /* Low Power Oscillator Clock (1m_lposc) */
162 freq = CLK_LPOSC_1MHZ;
163 break;
164 case CLKCTL0_MAINCLKSELA_SEL(1): /* FRO DIV clock */
165 freq = getFroDivClk();
166 break;
167 case CLKCTL0_MAINCLKSELA_SEL(2): /* OSC clock */
168 freq = CLK_OSC_CLK;
169 break;
170 case CLKCTL0_MAINCLKSELA_SEL(3): /* FRO clock */
171 freq = CLK_FRO_CLK;
172 break;
173 default:
174 freq = 0U;
175 break;
176 }
177 break;
178
179 case CLKCTL0_MAINCLKSELB_SEL(1): /* Main System PLL clock */
180 switch ((CLKCTL0->SYSPLL0CLKSEL) & CLKCTL0_SYSPLL0CLKSEL_SEL_MASK)
181 {
182 case CLKCTL0_SYSPLL0CLKSEL_SEL(0): /* FRO_DIV8 clock */
183 freq = CLK_FRO_DIV8_CLK;
184 break;
185 case CLKCTL0_SYSPLL0CLKSEL_SEL(1): /* OSC clock */
186 freq = CLK_OSC_CLK;
187 break;
188 default:
189 freq = 0U;
190 break;
191 }
192
193 if (((CLKCTL0->SYSPLL0CTL0) & CLKCTL0_SYSPLL0CTL0_BYPASS_MASK) == 0U)
194 {
195 /* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */
196 freqTmp = ((uint64_t)freq * ((uint64_t)(CLKCTL0->SYSPLL0NUM))) / ((uint64_t)(CLKCTL0->SYSPLL0DENOM));
197 freq *= ((CLKCTL0->SYSPLL0CTL0) & CLKCTL0_SYSPLL0CTL0_MULT_MASK) >> CLKCTL0_SYSPLL0CTL0_MULT_SHIFT;
198 freq += (uint32_t)freqTmp;
199 freq =
200 (uint32_t)((uint64_t)freq * 18U /
201 ((CLKCTL0->SYSPLL0PFD & CLKCTL0_SYSPLL0PFD_PFD0_MASK) >> CLKCTL0_SYSPLL0PFD_PFD0_SHIFT));
202 }
203
204 freq = freq / ((CLKCTL0->MAINPLLCLKDIV & CLKCTL0_MAINPLLCLKDIV_DIV_MASK) + 1U);
205 break;
206
207 case CLKCTL0_MAINCLKSELB_SEL(2): /* RTC 32KHz clock */
208 freq = CLK_RTC_32K_CLK;
209 break;
210
211 default:
212 freq = 0U;
213 break;
214 }
215
216 SystemCoreClock = freq / ((CLKCTL0->SYSCPUAHBCLKDIV & CLKCTL0_SYSCPUAHBCLKDIV_DIV_MASK) + 1U);
217 }
218
219 /* ----------------------------------------------------------------------------
220 -- SystemInitHook()
221 ---------------------------------------------------------------------------- */
222
SystemInitHook(void)223 __attribute__((weak)) void SystemInitHook(void)
224 {
225 /* Void implementation of the weak function. */
226 }
227
