1 /* 2 * Copyright 2019 NXP 3 * All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef _RTE_DEVICE_H 9 #define _RTE_DEVICE_H 10 11 #include "pin_mux.h" 12 13 /* UART Select, UART0-UART13. */ 14 /* User needs to provide the implementation of USARTX_GetFreq/USARTX_InitPins/USARTX_DeinitPins for the enabled USART 15 * instance. */ 16 #define RTE_USART0 0 17 #define RTE_USART0_DMA_EN 0 18 #define RTE_USART1 0 19 #define RTE_USART1_DMA_EN 0 20 #define RTE_USART2 0 21 #define RTE_USART2_DMA_EN 0 22 #define RTE_USART3 0 23 #define RTE_USART3_DMA_EN 0 24 #define RTE_USART4 0 25 #define RTE_USART4_DMA_EN 0 26 #define RTE_USART5 0 27 #define RTE_USART5_DMA_EN 0 28 #define RTE_USART6 0 29 #define RTE_USART6_DMA_EN 0 30 #define RTE_USART7 0 31 #define RTE_USART7_DMA_EN 0 32 #define RTE_USART8 0 33 #define RTE_USART8_DMA_EN 0 34 #define RTE_USART9 0 35 #define RTE_USART9_DMA_EN 0 36 #define RTE_USART10 0 37 #define RTE_USART10_DMA_EN 0 38 #define RTE_USART11 0 39 #define RTE_USART11_DMA_EN 0 40 #define RTE_USART12 0 41 #define RTE_USART12_DMA_EN 0 42 #define RTE_USART13 0 43 #define RTE_USART13_DMA_EN 0 44 45 /* USART configuration. */ 46 #define USART_RX_BUFFER_LEN 64 47 #define USART0_RX_BUFFER_ENABLE 0 48 #define USART1_RX_BUFFER_ENABLE 0 49 #define USART2_RX_BUFFER_ENABLE 0 50 #define USART3_RX_BUFFER_ENABLE 0 51 #define USART4_RX_BUFFER_ENABLE 0 52 #define USART5_RX_BUFFER_ENABLE 0 53 #define USART6_RX_BUFFER_ENABLE 0 54 #define USART7_RX_BUFFER_ENABLE 0 55 #define USART8_RX_BUFFER_ENABLE 0 56 #define USART9_RX_BUFFER_ENABLE 0 57 #define USART10_RX_BUFFER_ENABLE 0 58 #define USART11_RX_BUFFER_ENABLE 0 59 #define USART12_RX_BUFFER_ENABLE 0 60 #define USART13_RX_BUFFER_ENABLE 0 61 62 #define RTE_USART0_PIN_INIT USART0_InitPins 63 #define RTE_USART0_PIN_DEINIT USART0_DeinitPins 64 #define RTE_USART0_DMA_TX_CH 1 65 #define RTE_USART0_DMA_TX_DMA_BASE DMA0 66 #define RTE_USART0_DMA_RX_CH 0 67 #define RTE_USART0_DMA_RX_DMA_BASE DMA0 68 69 #define RTE_USART1_PIN_INIT USART1_InitPins 70 #define RTE_USART1_PIN_DEINIT USART1_DeinitPins 71 #define RTE_USART1_DMA_TX_CH 3 72 #define RTE_USART1_DMA_TX_DMA_BASE DMA0 73 #define RTE_USART1_DMA_RX_CH 2 74 #define RTE_USART1_DMA_RX_DMA_BASE DMA0 75 76 #define RTE_USART2_PIN_INIT USART2_InitPins 77 #define RTE_USART2_PIN_DEINIT USART2_DeinitPins 78 #define RTE_USART2_DMA_TX_CH 5 79 #define RTE_USART2_DMA_TX_DMA_BASE DMA0 80 #define RTE_USART2_DMA_RX_CH 4 81 #define RTE_USART2_DMA_RX_DMA_BASE DMA0 82 83 #define RTE_USART3_PIN_INIT USART3_InitPins 84 #define RTE_USART3_PIN_DEINIT USART3_DeinitPins 85 #define RTE_USART3_DMA_TX_CH 7 86 #define RTE_USART3_DMA_TX_DMA_BASE DMA0 87 #define RTE_USART3_DMA_RX_CH 6 88 #define RTE_USART3_DMA_RX_DMA_BASE DMA0 89 90 #define RTE_USART4_PIN_INIT USART4_InitPins 91 #define RTE_USART4_PIN_DEINIT USART4_DeinitPins 92 #define RTE_USART4_DMA_TX_CH 9 93 #define RTE_USART4_DMA_TX_DMA_BASE DMA0 94 #define RTE_USART4_DMA_RX_CH 8 95 #define RTE_USART4_DMA_RX_DMA_BASE DMA0 96 97 #define RTE_USART5_PIN_INIT USART5_InitPins 98 #define RTE_USART5_PIN_DEINIT USART5_DeinitPins 99 #define RTE_USART5_DMA_TX_CH 11 100 #define RTE_USART5_DMA_TX_DMA_BASE DMA0 101 #define RTE_USART5_DMA_RX_CH 10 102 #define RTE_USART5_DMA_RX_DMA_BASE DMA0 103 104 #define RTE_USART6_PIN_INIT USART6_InitPins 105 #define RTE_USART6_PIN_DEINIT USART6_DeinitPins 106 #define RTE_USART6_DMA_TX_CH 13 107 #define RTE_USART6_DMA_TX_DMA_BASE DMA0 108 #define RTE_USART6_DMA_RX_CH 12 109 #define RTE_USART6_DMA_RX_DMA_BASE DMA0 110 111 #define RTE_USART7_PIN_INIT USART7_InitPins 112 #define RTE_USART7_PIN_DEINIT USART7_DeinitPins 113 #define RTE_USART7_DMA_TX_CH 15 114 #define RTE_USART7_DMA_TX_DMA_BASE DMA0 115 #define RTE_USART7_DMA_RX_CH 14 116 #define RTE_USART7_DMA_RX_DMA_BASE DMA0 117 118 #define RTE_USART8_PIN_INIT USART8_InitPins 119 #define RTE_USART8_PIN_DEINIT USART8_DeinitPins 120 #define RTE_USART8_DMA_TX_CH 17 121 #define RTE_USART8_DMA_TX_DMA_BASE DMA0 122 #define RTE_USART8_DMA_RX_CH 16 123 #define RTE_USART8_DMA_RX_DMA_BASE DMA0 124 125 #define RTE_USART9_PIN_INIT USART9_InitPins 126 #define RTE_USART9_PIN_DEINIT USART9_DeinitPins 127 #define RTE_USART9_DMA_TX_CH 19 128 #define RTE_USART9_DMA_TX_DMA_BASE DMA0 129 #define RTE_USART9_DMA_RX_CH 18 130 #define RTE_USART9_DMA_RX_DMA_BASE DMA0 131 132 #define RTE_USART10_PIN_INIT USART10_InitPins 133 #define RTE_USART10_PIN_DEINIT USART10_DeinitPins 134 #define RTE_USART10_DMA_TX_CH 21 135 #define RTE_USART10_DMA_TX_DMA_BASE DMA0 136 #define RTE_USART10_DMA_RX_CH 20 137 #define RTE_USART10_DMA_RX_DMA_BASE DMA0 138 139 #define RTE_USART11_PIN_INIT USART11_InitPins 140 #define RTE_USART11_PIN_DEINIT USART11_DeinitPins 141 #define RTE_USART11_DMA_TX_CH 33 142 #define RTE_USART11_DMA_TX_DMA_BASE DMA0 143 #define RTE_USART11_DMA_RX_CH 32 144 #define RTE_USART11_DMA_RX_DMA_BASE DMA0 145 146 #define RTE_USART12_PIN_INIT USART12_InitPins 147 #define RTE_USART12_PIN_DEINIT USART12_DeinitPins 148 #define RTE_USART12_DMA_TX_CH 35 149 #define RTE_USART12_DMA_TX_DMA_BASE DMA0 150 #define RTE_USART12_DMA_RX_CH 34 151 #define RTE_USART12_DMA_RX_DMA_BASE DMA0 152 153 #define RTE_USART13_PIN_INIT USART13_InitPins 154 #define RTE_USART13_PIN_DEINIT USART13_DeinitPins 155 #define RTE_USART13_DMA_TX_CH 23 156 #define RTE_USART13_DMA_TX_DMA_BASE DMA0 157 #define RTE_USART13_DMA_RX_CH 22 158 #define RTE_USART13_DMA_RX_DMA_BASE DMA0 159 160 /* I2C Select, I2C0-I2C13,I2C15*/ 161 /* User needs to provide the implementation of I2CX_GetFreq/I2CX_InitPins/I2CX_DeinitPins for the enabled I2C instance. 162 */ 163 #define RTE_I2C0 0 164 #define RTE_I2C0_DMA_EN 0 165 #define RTE_I2C1 0 166 #define RTE_I2C1_DMA_EN 0 167 #define RTE_I2C2 0 168 #define RTE_I2C2_DMA_EN 0 169 #define RTE_I2C3 0 170 #define RTE_I2C3_DMA_EN 0 171 #define RTE_I2C4 0 172 #define RTE_I2C4_DMA_EN 0 173 #define RTE_I2C5 0 174 #define RTE_I2C5_DMA_EN 0 175 #define RTE_I2C6 0 176 #define RTE_I2C6_DMA_EN 0 177 #define RTE_I2C7 0 178 #define RTE_I2C7_DMA_EN 0 179 #define RTE_I2C8 0 180 #define RTE_I2C8_DMA_EN 0 181 #define RTE_I2C9 0 182 #define RTE_I2C9_DMA_EN 0 183 #define RTE_I2C10 0 184 #define RTE_I2C10_DMA_EN 0 185 #define RTE_I2C11 0 186 #define RTE_I2C11_DMA_EN 0 187 #define RTE_I2C12 0 188 #define RTE_I2C12_DMA_EN 0 189 #define RTE_I2C13 0 190 #define RTE_I2C13_DMA_EN 0 191 #define RTE_I2C15 0 192 #define RTE_I2C15_DMA_EN 0 193 194 /*I2C configuration*/ 195 #define RTE_I2C0_Master_DMA_BASE DMA0 196 #define RTE_I2C0_Master_DMA_CH 1 197 198 #define RTE_I2C1_Master_DMA_BASE DMA0 199 #define RTE_I2C1_Master_DMA_CH 3 200 201 #define RTE_I2C2_Master_DMA_BASE DMA0 202 #define RTE_I2C2_Master_DMA_CH 5 203 204 #define RTE_I2C3_Master_DMA_BASE DMA0 205 #define RTE_I2C3_Master_DMA_CH 7 206 207 #define RTE_I2C4_Master_DMA_BASE DMA0 208 #define RTE_I2C4_Master_DMA_CH 9 209 210 #define RTE_I2C5_Master_DMA_BASE DMA0 211 #define RTE_I2C5_Master_DMA_CH 11 212 213 #define RTE_I2C6_Master_DMA_BASE DMA0 214 #define RTE_I2C6_Master_DMA_CH 13 215 216 #define RTE_I2C7_Master_DMA_BASE DMA0 217 #define RTE_I2C7_Master_DMA_CH 15 218 219 #define RTE_I2C8_Master_DMA_BASE DMA0 220 #define RTE_I2C8_Master_DMA_CH 17 221 222 #define RTE_I2C9_Master_DMA_BASE DMA0 223 #define RTE_I2C9_Master_DMA_CH 19 224 225 #define RTE_I2C10_Master_DMA_BASE DMA0 226 #define RTE_I2C10_Master_DMA_CH 21 227 228 #define RTE_I2C11_Master_DMA_BASE DMA0 229 #define RTE_I2C11_Master_DMA_CH 33 230 231 #define RTE_I2C12_Master_DMA_BASE DMA0 232 #define RTE_I2C12_Master_DMA_CH 35 233 234 #define RTE_I2C13_Master_DMA_BASE DMA0 235 #define RTE_I2C13_Master_DMA_CH 23 236 237 /* SPI select, SPI0-SPI14, SPI16.*/ 238 /* User needs to provide the implementation of SPIX_GetFreq/SPIX_InitPins/SPIX_DeinitPins for the enabled SPI instance. 239 */ 240 #define RTE_SPI0 0 241 #define RTE_SPI0_DMA_EN 0 242 #define RTE_SPI1 0 243 #define RTE_SPI1_DMA_EN 0 244 #define RTE_SPI2 0 245 #define RTE_SPI2_DMA_EN 0 246 #define RTE_SPI3 0 247 #define RTE_SPI3_DMA_EN 0 248 #define RTE_SPI4 0 249 #define RTE_SPI4_DMA_EN 0 250 #define RTE_SPI5 0 251 #define RTE_SPI5_DMA_EN 0 252 #define RTE_SPI6 0 253 #define RTE_SPI6_DMA_EN 0 254 #define RTE_SPI7 0 255 #define RTE_SPI7_DMA_EN 0 256 #define RTE_SPI8 0 257 #define RTE_SPI8_DMA_EN 0 258 #define RTE_SPI9 0 259 #define RTE_SPI9_DMA_EN 0 260 #define RTE_SPI10 0 261 #define RTE_SPI10_DMA_EN 0 262 #define RTE_SPI11 0 263 #define RTE_SPI11_DMA_EN 0 264 #define RTE_SPI12 0 265 #define RTE_SPI12_DMA_EN 0 266 #define RTE_SPI13 0 267 #define RTE_SPI13_DMA_EN 0 268 #define RTE_SPI14 0 269 #define RTE_SPI14_DMA_EN 0 270 #define RTE_SPI16 0 271 #define RTE_SPI16_DMA_EN 0 272 273 /* SPI configuration. */ 274 #define RTE_SPI0_SSEL_NUM kSPI_Ssel0 275 #define RTE_SPI0_PIN_INIT SPI0_InitPins 276 #define RTE_SPI0_PIN_DEINIT SPI0_DeinitPins 277 #define RTE_SPI0_DMA_TX_CH 1 278 #define RTE_SPI0_DMA_TX_DMA_BASE DMA0 279 #define RTE_SPI0_DMA_RX_CH 0 280 #define RTE_SPI0_DMA_RX_DMA_BASE DMA0 281 282 #define RTE_SPI1_SSEL_NUM kSPI_Ssel0 283 #define RTE_SPI1_PIN_INIT SPI1_InitPins 284 #define RTE_SPI1_PIN_DEINIT SPI1_DeinitPins 285 #define RTE_SPI1_DMA_TX_CH 3 286 #define RTE_SPI1_DMA_TX_DMA_BASE DMA0 287 #define RTE_SPI1_DMA_RX_CH 2 288 #define RTE_SPI1_DMA_RX_DMA_BASE DMA0 289 290 #define RTE_SPI2_SSEL_NUM kSPI_Ssel0 291 #define RTE_SPI2_PIN_INIT SPI2_InitPins 292 #define RTE_SPI2_PIN_DEINIT SPI2_DeinitPins 293 #define RTE_SPI2_DMA_TX_CH 5 294 #define RTE_SPI2_DMA_TX_DMA_BASE DMA0 295 #define RTE_SPI2_DMA_RX_CH 4 296 #define RTE_SPI2_DMA_RX_DMA_BASE DMA0 297 298 #define RTE_SPI3_SSEL_NUM kSPI_Ssel0 299 #define RTE_SPI3_PIN_INIT SPI3_InitPins 300 #define RTE_SPI3_PIN_DEINIT SPI3_DeinitPins 301 #define RTE_SPI3_DMA_TX_CH 7 302 #define RTE_SPI3_DMA_TX_DMA_BASE DMA0 303 #define RTE_SPI3_DMA_RX_CH 6 304 #define RTE_SPI3_DMA_RX_DMA_BASE DMA0 305 306 #define RTE_SPI4_SSEL_NUM kSPI_Ssel0 307 #define RTE_SPI4_PIN_INIT SPI4_InitPins 308 #define RTE_SPI4_PIN_DEINIT SPI4_DeinitPins 309 #define RTE_SPI4_DMA_TX_CH 9 310 #define RTE_SPI4_DMA_TX_DMA_BASE DMA0 311 #define RTE_SPI4_DMA_RX_CH 8 312 #define RTE_SPI4_DMA_RX_DMA_BASE DMA0 313 314 #define RTE_SPI5_SSEL_NUM kSPI_Ssel0 315 #define RTE_SPI5_PIN_INIT SPI5_InitPins 316 #define RTE_SPI5_PIN_DEINIT SPI5_DeinitPins 317 #define RTE_SPI5_DMA_TX_CH 11 318 #define RTE_SPI5_DMA_TX_DMA_BASE DMA0 319 #define RTE_SPI5_DMA_RX_CH 10 320 #define RTE_SPI5_DMA_RX_DMA_BASE DMA0 321 322 #define RTE_SPI6_SSEL_NUM kSPI_Ssel0 323 #define RTE_SPI6_PIN_INIT SPI6_InitPins 324 #define RTE_SPI6_PIN_DEINIT SPI6_DeinitPins 325 #define RTE_SPI6_DMA_TX_CH 13 326 #define RTE_SPI6_DMA_TX_DMA_BASE DMA0 327 #define RTE_SPI6_DMA_RX_CH 12 328 #define RTE_SPI6_DMA_RX_DMA_BASE DMA0 329 330 #define RTE_SPI7_SSEL_NUM kSPI_Ssel0 331 #define RTE_SPI7_PIN_INIT SPI7_InitPins 332 #define RTE_SPI7_PIN_DEINIT SPI7_DeinitPins 333 #define RTE_SPI7_DMA_TX_CH 15 334 #define RTE_SPI7_DMA_TX_DMA_BASE DMA0 335 #define RTE_SPI7_DMA_RX_CH 14 336 #define RTE_SPI7_DMA_RX_DMA_BASE DMA0 337 338 #define RTE_SPI8_SSEL_NUM kSPI_Ssel0 339 #define RTE_SPI8_PIN_INIT SPI8_InitPins 340 #define RTE_SPI8_PIN_DEINIT SPI8_DeinitPins 341 #define RTE_SPI8_DMA_TX_CH 17 342 #define RTE_SPI8_DMA_TX_DMA_BASE DMA0 343 #define RTE_SPI8_DMA_RX_CH 16 344 #define RTE_SPI8_DMA_RX_DMA_BASE DMA0 345 346 #define RTE_SPI9_SSEL_NUM kSPI_Ssel0 347 #define RTE_SPI9_PIN_INIT SPI9_InitPins 348 #define RTE_SPI9_PIN_DEINIT SPI9_DeinitPins 349 #define RTE_SPI9_DMA_TX_CH 19 350 #define RTE_SPI9_DMA_TX_DMA_BASE DMA0 351 #define RTE_SPI9_DMA_RX_CH 18 352 #define RTE_SPI9_DMA_RX_DMA_BASE DMA0 353 354 #define RTE_SPI10_SSEL_NUM kSPI_Ssel0 355 #define RTE_SPI10_PIN_INIT SPI10_InitPins 356 #define RTE_SPI10_PIN_DEINIT SPI10_DeinitPins 357 #define RTE_SPI10_DMA_TX_CH 21 358 #define RTE_SPI10_DMA_TX_DMA_BASE DMA0 359 #define RTE_SPI10_DMA_RX_CH 20 360 #define RTE_SPI10_DMA_RX_DMA_BASE DMA0 361 362 #define RTE_SPI11_SSEL_NUM kSPI_Ssel0 363 #define RTE_SPI11_PIN_INIT SPI11_InitPins 364 #define RTE_SPI11_PIN_DEINIT SPI11_DeinitPins 365 #define RTE_SPI11_DMA_TX_CH 33 366 #define RTE_SPI11_DMA_TX_DMA_BASE DMA0 367 #define RTE_SPI11_DMA_RX_CH 32 368 #define RTE_SPI11_DMA_RX_DMA_BASE DMA0 369 370 #define RTE_SPI12_SSEL_NUM kSPI_Ssel0 371 #define RTE_SPI12_PIN_INIT SPI12_InitPins 372 #define RTE_SPI12_PIN_DEINIT SPI12_DeinitPins 373 #define RTE_SPI12_DMA_TX_CH 35 374 #define RTE_SPI12_DMA_TX_DMA_BASE DMA0 375 #define RTE_SPI12_DMA_RX_CH 34 376 #define RTE_SPI12_DMA_RX_DMA_BASE DMA0 377 378 #define RTE_SPI13_SSEL_NUM kSPI_Ssel0 379 #define RTE_SPI13_PIN_INIT SPI13_InitPins 380 #define RTE_SPI13_PIN_DEINIT SPI13_DeinitPins 381 #define RTE_SPI13_DMA_TX_CH 23 382 #define RTE_SPI13_DMA_TX_DMA_BASE DMA0 383 #define RTE_SPI13_DMA_RX_CH 22 384 #define RTE_SPI13_DMA_RX_DMA_BASE DMA0 385 386 #define RTE_SPI14_SSEL_NUM kSPI_Ssel0 387 #define RTE_SPI14_PIN_INIT SPI14_InitPins 388 #define RTE_SPI14_PIN_DEINIT SPI14_DeinitPins 389 #define RTE_SPI14_DMA_TX_CH 27 390 #define RTE_SPI14_DMA_TX_DMA_BASE DMA0 391 #define RTE_SPI14_DMA_RX_CH 26 392 #define RTE_SPI14_DMA_RX_DMA_BASE DMA0 393 394 #define RTE_SPI16_SSEL_NUM kSPI_Ssel0 395 #define RTE_SPI16_PIN_INIT SPI16_InitPins 396 #define RTE_SPI16_PIN_DEINIT SPI16_DeinitPins 397 #define RTE_SPI16_DMA_TX_CH 29 398 #define RTE_SPI16_DMA_TX_DMA_BASE DMA0 399 #define RTE_SPI16_DMA_RX_CH 28 400 #define RTE_SPI16_DMA_RX_DMA_BASE DMA0 401 #endif /* _RTE_DEVICE_H */ 402
