1 /*
2 * Copyright 2018-2023 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7 #ifndef _FSL_POWER_H_
8 #define _FSL_POWER_H_
9
10 #include "fsl_common.h"
11
12 /*!
13 * @addtogroup power
14 * @{
15 */
16
17 /*******************************************************************************
18 * Definitions
19 ******************************************************************************/
20
21 /*! @name Driver version */
22 /*@{*/
23 /*! @brief power driver version 2.6.0. */
24 #define FSL_POWER_DRIVER_VERSION (MAKE_VERSION(2, 6, 0))
25 /*@}*/
26
27 #define MAKE_PD_BITS(reg, slot) (((reg) << 8) | (slot))
28 #define SYSCTL0_PDRCFGSET_REG(x) (*((volatile uint32_t *)((uint32_t)(&(SYSCTL0->PDRUNCFG0_SET)) + ((x) << 2U))))
29 #define SYSCTL0_PDRCFGCLR_REG(x) (*((volatile uint32_t *)((uint32_t)(&(SYSCTL0->PDRUNCFG0_CLR)) + ((x) << 2U))))
30 #define PDRCFG0 0x0U
31 #define PDRCFG1 0x1U
32 #define PDRCFG2 0x2U
33 #define PDRCFG3 0x3U
34
35 /* PMC FLAGS register bitfield MASK. */
36 #define PMC_FLAGS_PORCOREF_MASK (0x10000U)
37 #define PMC_FLAGS_POR1V8F_MASK (0x20000U)
38 #define PMC_FLAGS_PORAO18F_MASK (0x40000U)
39 #define PMC_FLAGS_LVDCOREF_MASK (0x100000U)
40 #define PMC_FLAGS_HVDCOREF_MASK (0x400000U)
41 #define PMC_FLAGS_HVD1V8F_MASK (0x1000000U)
42 #define PMC_FLAGS_RTCF_MASK (0x8000000U)
43 #define PMC_FLAGS_AUTOWKF_MASK (0x10000000U)
44 #define PMC_FLAGS_INTNPADF_MASK (0x20000000U)
45 #define PMC_FLAGS_RESETNPADF_MASK (0x40000000U)
46 #define PMC_FLAGS_DEEPPDF_MASK (0x80000000U)
47
48 #define PMC_CTRL_LVDCOREIE_MASK (0x100000U)
49 #define PMC_CTRL_HVDCOREIE_MASK (0x400000U)
50 #define PMC_CTRL_HVD1V8IE_MASK (0x1000000U)
51 #define PMC_CTRL_AUTOWKEN_MASK (0x10000000U)
52 #define PMC_CTRL_INTRPADEN_MASK (0x20000000U)
53
54 /*! PMIC is used but vddcore supply is always above LVD threshold. */
55 #define PMIC_VDDCORE_RECOVERY_TIME_IGNORE (0xFFFFFFFFU)
56
57 /**
58 * @brief PMC event flags.
59 *
60 * @note These enums are meant to be OR'd together to form a bit mask.
61 */
62 enum _pmc_interrupt
63 {
64 kPMC_INT_LVDCORE = PMC_CTRL_LVDCOREIE_MASK, /*!< Vddcore Low-Voltage Detector Interrupt Enable. */
65 kPMC_INT_HVDCORE = PMC_CTRL_HVDCOREIE_MASK, /*!< Vddcore High-Voltage Detector Interrupt Enable. */
66 kPMC_INT_HVD1V8 = PMC_CTRL_HVD1V8IE_MASK, /*!< Vdd1v8 High-Voltage Detector Interrupt Enable. */
67 kPMC_INT_AUTOWK = PMC_CTRL_AUTOWKEN_MASK, /*!< PMC automatic wakeup enable and interrupt enable. */
68 kPMC_INT_INTRPAD =
69 PMC_CTRL_INTRPADEN_MASK /*!< Interrupt pad deep powerdown and deep sleep wake up & interrupt enable. */
70 };
71
72 /**
73 * @brief PMC event flags.
74 *
75 * @note These enums are meant to be OR'd together to form a bit mask.
76 */
77 enum _pmc_event_flags
78 {
79 kPMC_FLAGS_PORCORE = PMC_FLAGS_PORCOREF_MASK, /*!< POR triggered by the vddcore POR monitor (0 = no, 1 = yes). */
80 kPMC_FLAGS_POR1V8 =
81 PMC_FLAGS_POR1V8F_MASK, /*!< vdd1v8 power on event detected since last cleared(0 = no, 1 = yes). */
82 kPMC_FLAGS_PORAO18 =
83 PMC_FLAGS_PORAO18F_MASK, /*!< vdd_ao18 power on event detected since last cleared (0 = no, 1 = yes). */
84 kPMC_FLAGS_LVDCORE =
85 PMC_FLAGS_LVDCOREF_MASK, /*!< LVD tripped since last time this bit was cleared (0 = no, 1 = yes). */
86 kPMC_FLAGS_HVDCORE =
87 PMC_FLAGS_HVDCOREF_MASK, /*!< HVD tripped since last time this bit was cleared (0 = no, 1 = yes). */
88 kPMC_FLAGS_HVD1V8 =
89 PMC_FLAGS_HVD1V8F_MASK, /*!< vdd1v8 HVD tripped since last time this bit was cleared (0 = no, 1 = yes). */
90 kPMC_FLAGS_RTC =
91 PMC_FLAGS_RTCF_MASK, /*!< RTC wakeup detected since last time flag was cleared (0 = no, 1 = yes). */
92 kPMC_FLAGS_AUTOWK =
93 PMC_FLAGS_AUTOWKF_MASK, /*!< PMC Auto wakeup caused a deep sleep wakeup and interrupt (0 = no, 1 = yes). */
94 kPMC_FLAGS_INTNPADF = PMC_FLAGS_INTNPADF_MASK, /*!< Pad interrupt caused a wakeup or interrupt event since the last
95 time this flag was cleared (0 = no, 1 = yes). */
96 kPMC_FLAGS_RESETNPAD = PMC_FLAGS_RESETNPADF_MASK, /*!< Reset pad wakeup caused a wakeup or reset event since the
97 last time this bit was cleared. (0 = no, 1 = yes). */
98 kPMC_FLAGS_DEEPPD = PMC_FLAGS_DEEPPDF_MASK /*!< Deep powerdown was entered since the last time this flag was cleared
99 (0 = no, 1 = yes). */
100 };
101
102 typedef enum pd_bits
103 {
104 kPDRUNCFG_PMC_MODE0 = MAKE_PD_BITS(PDRCFG0, 1U),
105 kPDRUNCFG_PMC_MODE1 = MAKE_PD_BITS(PDRCFG0, 2U),
106 kPDRUNCFG_LP_VDD_COREREG = MAKE_PD_BITS(PDRCFG0, 4U),
107 kPDRUNCFG_LP_PMCREF = MAKE_PD_BITS(PDRCFG0, 6U),
108 kPDRUNCFG_PD_HVD1V8 = MAKE_PD_BITS(PDRCFG0, 7U),
109 kPDRUNCFG_LP_LVDCORE = MAKE_PD_BITS(PDRCFG0, 9U),
110 kPDRUNCFG_PD_HVDCORE = MAKE_PD_BITS(PDRCFG0, 10U),
111 kPDRUNCFG_PD_RBB = MAKE_PD_BITS(PDRCFG0, 11U),
112 kPDRUNCFG_PD_FBB = MAKE_PD_BITS(PDRCFG0, 12U),
113 kPDRUNCFG_PD_SYSXTAL = MAKE_PD_BITS(PDRCFG0, 13U),
114 kPDRUNCFG_PD_LPOSC = MAKE_PD_BITS(PDRCFG0, 14U),
115 kPDRUNCFG_PD_RBBSRAM = MAKE_PD_BITS(PDRCFG0, 15U),
116 kPDRUNCFG_PD_FFRO = MAKE_PD_BITS(PDRCFG0, 16U),
117 kPDRUNCFG_PD_SYSPLL_LDO = MAKE_PD_BITS(PDRCFG0, 17U),
118 kPDRUNCFG_PD_SYSPLL_ANA = MAKE_PD_BITS(PDRCFG0, 18U),
119 kPDRUNCFG_PD_AUDPLL_LDO = MAKE_PD_BITS(PDRCFG0, 19U),
120 kPDRUNCFG_PD_AUDPLL_ANA = MAKE_PD_BITS(PDRCFG0, 20U),
121 kPDRUNCFG_PD_ADC = MAKE_PD_BITS(PDRCFG0, 21U),
122 kPDRUNCFG_LP_ADC = MAKE_PD_BITS(PDRCFG0, 22U),
123 kPDRUNCFG_PD_ADC_TEMPSNS = MAKE_PD_BITS(PDRCFG0, 23U),
124 kPDRUNCFG_PD_PMC_TEMPSNS = MAKE_PD_BITS(PDRCFG0, 24U),
125 kPDRUNCFG_PD_ACMP = MAKE_PD_BITS(PDRCFG0, 25U),
126
127 kPDRUNCFG_PPD_PQ_SRAM = MAKE_PD_BITS(PDRCFG1, 1U),
128 kPDRUNCFG_APD_FLEXSPI0_SRAM = MAKE_PD_BITS(PDRCFG1, 2U),
129 kPDRUNCFG_PPD_FLEXSPI0_SRAM = MAKE_PD_BITS(PDRCFG1, 3U),
130 kPDRUNCFG_APD_FLEXSPI1_SRAM = MAKE_PD_BITS(PDRCFG1, 4U),
131 kPDRUNCFG_PPD_FLEXSPI1_SRAM = MAKE_PD_BITS(PDRCFG1, 5U),
132 kPDRUNCFG_APD_USBHS_SRAM = MAKE_PD_BITS(PDRCFG1, 6U),
133 kPDRUNCFG_PPD_USBHS_SRAM = MAKE_PD_BITS(PDRCFG1, 7U),
134 kPDRUNCFG_APD_USDHC0_SRAM = MAKE_PD_BITS(PDRCFG1, 8U),
135 kPDRUNCFG_PPD_USDHC0_SRAM = MAKE_PD_BITS(PDRCFG1, 9U),
136 kPDRUNCFG_APD_USDHC1_SRAM = MAKE_PD_BITS(PDRCFG1, 10U),
137 kPDRUNCFG_PPD_USDHC1_SRAM = MAKE_PD_BITS(PDRCFG1, 11U),
138 kPDRUNCFG_PPD_CASPER_SRAM = MAKE_PD_BITS(PDRCFG1, 13U),
139 kPDRUNCFG_APD_GPU_SRAM = MAKE_PD_BITS(PDRCFG1, 14U),
140 kPDRUNCFG_PPD_GPU_SRAM = MAKE_PD_BITS(PDRCFG1, 15U),
141 kPDRUNCFG_APD_SMARTDMA_SRAM = MAKE_PD_BITS(PDRCFG1, 16U),
142 kPDRUNCFG_PPD_SMARTDMA_SRAM = MAKE_PD_BITS(PDRCFG1, 17U),
143 kPDRUNCFG_APD_MIPIDSI_SRAM = MAKE_PD_BITS(PDRCFG1, 18U),
144 kPDRUNCFG_PPD_MIPIDSI_SRAM = MAKE_PD_BITS(PDRCFG1, 19U),
145 kPDRUNCFG_APD_DCNANO_SRAM = MAKE_PD_BITS(PDRCFG1, 20U),
146 kPDRUNCFG_PPD_DCNANO_SRAM = MAKE_PD_BITS(PDRCFG1, 21U),
147 kPDRUNCFG_PD_DSP = MAKE_PD_BITS(PDRCFG1, 25U),
148 kPDRUNCFG_PD_MIPIDSI = MAKE_PD_BITS(PDRCFG1, 26U),
149 kPDRUNCFG_PD_OTP = MAKE_PD_BITS(PDRCFG1, 27U),
150 kPDRUNCFG_PD_ROM = MAKE_PD_BITS(PDRCFG1, 28U),
151 kPDRUNCFG_SRAM_SLEEP = MAKE_PD_BITS(PDRCFG1, 31U),
152
153 kPDRUNCFG_APD_SRAM_IF0 = MAKE_PD_BITS(PDRCFG2, 0U),
154 kPDRUNCFG_APD_SRAM_IF1 = MAKE_PD_BITS(PDRCFG2, 1U),
155 kPDRUNCFG_APD_SRAM_IF2 = MAKE_PD_BITS(PDRCFG2, 2U),
156 kPDRUNCFG_APD_SRAM_IF3 = MAKE_PD_BITS(PDRCFG2, 3U),
157 kPDRUNCFG_APD_SRAM_IF4 = MAKE_PD_BITS(PDRCFG2, 4U),
158 kPDRUNCFG_APD_SRAM_IF5 = MAKE_PD_BITS(PDRCFG2, 5U),
159 kPDRUNCFG_APD_SRAM_IF6 = MAKE_PD_BITS(PDRCFG2, 6U),
160 kPDRUNCFG_APD_SRAM_IF7 = MAKE_PD_BITS(PDRCFG2, 7U),
161 kPDRUNCFG_APD_SRAM_IF8 = MAKE_PD_BITS(PDRCFG2, 8U),
162 kPDRUNCFG_APD_SRAM_IF9 = MAKE_PD_BITS(PDRCFG2, 9U),
163 kPDRUNCFG_APD_SRAM_IF10 = MAKE_PD_BITS(PDRCFG2, 10U),
164 kPDRUNCFG_APD_SRAM_IF11 = MAKE_PD_BITS(PDRCFG2, 11U),
165 kPDRUNCFG_APD_SRAM_IF12 = MAKE_PD_BITS(PDRCFG2, 12U),
166 kPDRUNCFG_APD_SRAM_IF13 = MAKE_PD_BITS(PDRCFG2, 13U),
167 kPDRUNCFG_APD_SRAM_IF14 = MAKE_PD_BITS(PDRCFG2, 14U),
168 kPDRUNCFG_APD_SRAM_IF15 = MAKE_PD_BITS(PDRCFG2, 15U),
169 kPDRUNCFG_APD_SRAM_IF16 = MAKE_PD_BITS(PDRCFG2, 16U),
170 kPDRUNCFG_APD_SRAM_IF17 = MAKE_PD_BITS(PDRCFG2, 17U),
171 kPDRUNCFG_APD_SRAM_IF18 = MAKE_PD_BITS(PDRCFG2, 18U),
172 kPDRUNCFG_APD_SRAM_IF19 = MAKE_PD_BITS(PDRCFG2, 19U),
173 kPDRUNCFG_APD_SRAM_IF20 = MAKE_PD_BITS(PDRCFG2, 20U),
174 kPDRUNCFG_APD_SRAM_IF21 = MAKE_PD_BITS(PDRCFG2, 21U),
175 kPDRUNCFG_APD_SRAM_IF22 = MAKE_PD_BITS(PDRCFG2, 22U),
176 kPDRUNCFG_APD_SRAM_IF23 = MAKE_PD_BITS(PDRCFG2, 23U),
177 kPDRUNCFG_APD_SRAM_IF24 = MAKE_PD_BITS(PDRCFG2, 24U),
178 kPDRUNCFG_APD_SRAM_IF25 = MAKE_PD_BITS(PDRCFG2, 25U),
179 kPDRUNCFG_APD_SRAM_IF26 = MAKE_PD_BITS(PDRCFG2, 26U),
180 kPDRUNCFG_APD_SRAM_IF27 = MAKE_PD_BITS(PDRCFG2, 27U),
181 kPDRUNCFG_APD_SRAM_IF28 = MAKE_PD_BITS(PDRCFG2, 28U),
182 kPDRUNCFG_APD_SRAM_IF29 = MAKE_PD_BITS(PDRCFG2, 29U),
183 kPDRUNCFG_APD_SRAM_IF30 = MAKE_PD_BITS(PDRCFG2, 30U),
184 kPDRUNCFG_APD_SRAM_IF31 = MAKE_PD_BITS(PDRCFG2, 31U),
185
186 kPDRUNCFG_PPD_SRAM_IF0 = MAKE_PD_BITS(PDRCFG3, 0U),
187 kPDRUNCFG_PPD_SRAM_IF1 = MAKE_PD_BITS(PDRCFG3, 1U),
188 kPDRUNCFG_PPD_SRAM_IF2 = MAKE_PD_BITS(PDRCFG3, 2U),
189 kPDRUNCFG_PPD_SRAM_IF3 = MAKE_PD_BITS(PDRCFG3, 3U),
190 kPDRUNCFG_PPD_SRAM_IF4 = MAKE_PD_BITS(PDRCFG3, 4U),
191 kPDRUNCFG_PPD_SRAM_IF5 = MAKE_PD_BITS(PDRCFG3, 5U),
192 kPDRUNCFG_PPD_SRAM_IF6 = MAKE_PD_BITS(PDRCFG3, 6U),
193 kPDRUNCFG_PPD_SRAM_IF7 = MAKE_PD_BITS(PDRCFG3, 7U),
194 kPDRUNCFG_PPD_SRAM_IF8 = MAKE_PD_BITS(PDRCFG3, 8U),
195 kPDRUNCFG_PPD_SRAM_IF9 = MAKE_PD_BITS(PDRCFG3, 9U),
196 kPDRUNCFG_PPD_SRAM_IF10 = MAKE_PD_BITS(PDRCFG3, 10U),
197 kPDRUNCFG_PPD_SRAM_IF11 = MAKE_PD_BITS(PDRCFG3, 11U),
198 kPDRUNCFG_PPD_SRAM_IF12 = MAKE_PD_BITS(PDRCFG3, 12U),
199 kPDRUNCFG_PPD_SRAM_IF13 = MAKE_PD_BITS(PDRCFG3, 13U),
200 kPDRUNCFG_PPD_SRAM_IF14 = MAKE_PD_BITS(PDRCFG3, 14U),
201 kPDRUNCFG_PPD_SRAM_IF15 = MAKE_PD_BITS(PDRCFG3, 15U),
202 kPDRUNCFG_PPD_SRAM_IF16 = MAKE_PD_BITS(PDRCFG3, 16U),
203 kPDRUNCFG_PPD_SRAM_IF17 = MAKE_PD_BITS(PDRCFG3, 17U),
204 kPDRUNCFG_PPD_SRAM_IF18 = MAKE_PD_BITS(PDRCFG3, 18U),
205 kPDRUNCFG_PPD_SRAM_IF19 = MAKE_PD_BITS(PDRCFG3, 19U),
206 kPDRUNCFG_PPD_SRAM_IF20 = MAKE_PD_BITS(PDRCFG3, 20U),
207 kPDRUNCFG_PPD_SRAM_IF21 = MAKE_PD_BITS(PDRCFG3, 21U),
208 kPDRUNCFG_PPD_SRAM_IF22 = MAKE_PD_BITS(PDRCFG3, 22U),
209 kPDRUNCFG_PPD_SRAM_IF23 = MAKE_PD_BITS(PDRCFG3, 23U),
210 kPDRUNCFG_PPD_SRAM_IF24 = MAKE_PD_BITS(PDRCFG3, 24U),
211 kPDRUNCFG_PPD_SRAM_IF25 = MAKE_PD_BITS(PDRCFG3, 25U),
212 kPDRUNCFG_PPD_SRAM_IF26 = MAKE_PD_BITS(PDRCFG3, 26U),
213 kPDRUNCFG_PPD_SRAM_IF27 = MAKE_PD_BITS(PDRCFG3, 27U),
214 kPDRUNCFG_PPD_SRAM_IF28 = MAKE_PD_BITS(PDRCFG3, 28U),
215 kPDRUNCFG_PPD_SRAM_IF29 = MAKE_PD_BITS(PDRCFG3, 29U),
216 kPDRUNCFG_PPD_SRAM_IF30 = MAKE_PD_BITS(PDRCFG3, 30U),
217 kPDRUNCFG_PPD_SRAM_IF31 = MAKE_PD_BITS(PDRCFG3, 31U),
218 /*
219 This enum member has no practical meaning,it is used to avoid MISRA issue,
220 user should not trying to use it.
221 */
222 kPDRUNCFG_ForceUnsigned = (int)0x80000000U,
223 } pd_bit_t;
224
225 /*! @brief Power mode configuration API parameter */
226 typedef enum _power_mode_config
227 {
228 kPmu_Sleep = 0U,
229 kPmu_Deep_Sleep = 1U,
230 kPmu_Deep_PowerDown = 2U,
231 kPmu_Full_Deep_PowerDown = 3U,
232 } power_mode_cfg_t;
233
234 /*! @brief Body Bias mode definition */
235 typedef enum _body_bias_mode
236 {
237 kPmu_Fbb = 0x01U, /* Forward Body Bias Mode. */
238 kPmu_Rbb = 0x02U, /* Reverse Body Bias Mode. */
239 kPmu_Nbb = 0x03U, /* Normal Body Bias Mode. */
240 } body_bias_mode_t;
241
242 /*! @brief PMIC mode pin configuration API parameter */
243 #define SYSCTL0_TUPLE_REG(reg) (*((volatile uint32_t *)(((uint32_t)(SYSCTL0)) + (((uint32_t)(reg)) & 0xFFFU))))
244 typedef enum _pmic_mode_reg
245 {
246 kCfg_Run = 0x610,
247 kCfg_Sleep = 0x600,
248 } pmic_mode_reg_t;
249
250 /*! @brief Clock source of main clock before entering deep sleep. */
251 typedef enum _power_deep_sleep_clk
252 {
253 kDeepSleepClk_LpOsc = 0U,
254 kDeepSleepClk_Fro = 1U,
255 } power_deep_sleep_clk_t;
256
257 /*! @brief VDDCORE supply source. */
258 typedef enum _power_vddcore_src
259 {
260 kVddCoreSrc_LDO = 0U, /*!< VDDCORE is supplied by onchip regulator. */
261 kVddCoreSrc_PMIC = 1U, /*!< VDDCORE is supplied by external PMIC. */
262 } power_vddcore_src_t;
263
264 /*!
265 * @brief pad voltage range value. Note, refer to Reference Manual PMC GPIO VDDIO Range Selection Control (PADVRANGE)
266 * register's description for the supported voltage by different VDDDIO.
267 */
268 typedef enum _power_pad_vrange_val
269 {
270 kPadVol_171_360 = 0U, /*!< Deprecated! Voltage from 1.71V to 3.60V. */
271 kPadVol_Continuous = 0U, /*!< Continuous mode, VDDE detector on. */
272 kPadVol_171_198 = 1U, /*!< Voltage from 1.71V to 1.98V. VDDE detector off. */
273 kPadVol_300_360 = 2U, /*!< Voltage from 3.00V to 3.60V. VDDE detector off. */
274 } power_pad_vrange_val_t;
275
276 /*!
277 * @brief pad voltage range configuration.
278 */
279 typedef struct _power_pad_vrange
280 {
281 uint32_t Vdde0Range : 2; /*!< VDDE0 voltage range for VDDIO_0. @ref power_pad_vrange_val_t */
282 uint32_t Vdde1Range : 2; /*!< VDDE1 voltage range for VDDIO_1. @ref power_pad_vrange_val_t */
283 uint32_t Vdde2Range : 2; /*!< VDDE2 voltage range for VDDIO_2. @ref power_pad_vrange_val_t */
284 uint32_t Vdde3Range : 2; /*!< VDDE3 voltage range for VDDIO_3. @ref power_pad_vrange_val_t */
285 uint32_t Vdde4Range : 2; /*!< VDDE4 voltage range for VDDIO_4. @ref power_pad_vrange_val_t */
286 uint32_t : 22; /*!< Reserved. */
287 } power_pad_vrange_t;
288
289 /*!
290 * @brief LVD falling trip voltage value.
291 */
292 typedef enum _power_lvd_falling_trip_vol_val
293 {
294 kLvdFallingTripVol_720 = 0U, /*!< Voltage 720mV. */
295 kLvdFallingTripVol_735 = 1U, /*!< Voltage 735mV. */
296 kLvdFallingTripVol_750 = 2U, /*!< Voltage 750mV. */
297 kLvdFallingTripVol_765 = 3U, /*!< Voltage 765mV. */
298 kLvdFallingTripVol_780 = 4U, /*!< Voltage 780mV. */
299 kLvdFallingTripVol_795 = 5U, /*!< Voltage 795mV. */
300 kLvdFallingTripVol_810 = 6U, /*!< Voltage 810mV. */
301 kLvdFallingTripVol_825 = 7U, /*!< Voltage 825mV. */
302 kLvdFallingTripVol_840 = 8U, /*!< Voltage 840mV. */
303 kLvdFallingTripVol_855 = 9U, /*!< Voltage 855mV. */
304 kLvdFallingTripVol_870 = 10U, /*!< Voltage 870mV. */
305 kLvdFallingTripVol_885 = 11U, /*!< Voltage 885mV. */
306 kLvdFallingTripVol_900 = 12U, /*!< Voltage 900mV. */
307 kLvdFallingTripVol_915 = 13U, /*!< Voltage 915mV. */
308 kLvdFallingTripVol_930 = 14U, /*!< Voltage 930mV. */
309 kLvdFallingTripVol_945 = 15U, /*!< Voltage 945mV. */
310 } power_lvd_falling_trip_vol_val_t;
311
312 /*!
313 * @brief vddcore or vdd1v8 power on selection for different PMIC mode.
314 * vddcore and vdd1v8 are always on in mode0. Refer to PMC->PMICCFG.
315 */
316 typedef enum _power_control_for_pmic_mode
317 {
318 kVddCoreOnMode1 = 0x2U, /*!< VDDCORE is powered in PMIC mode1. */
319 kVddCoreOnMode2 = 0x4U, /*!< VDDCORE is powered in PMIC mode2. */
320 kVddCoreOnMode3 = 0x8U, /*!< VDDCORE is powered in PMIC mode3. */
321 kVdd1v8OnMode1 = 0x20U, /*!< VDD1V8 is powered in PMIC mode1. */
322 kVdd1v8OnMode2 = 0x40U, /*!< VDD1V8 is powered in PMIC mode2. */
323 kVdd1v8OnMode3 = 0x80U, /*!< VDD1V8 is powered in PMIC mode3. */
324 } power_control_for_pmic_mode;
325
326 /*! Callback function used to change VDDCORE when the VDDCORE is supplied by external PMIC. Refer to
327 * #POWER_SetVddCoreSupplySrc() */
328 typedef void (*power_vddcore_set_func_t)(uint32_t millivolt);
329
330 /*******************************************************************************
331 * API
332 ******************************************************************************/
333
334 #ifdef __cplusplus
335 extern "C" {
336 #endif
337
338 /*!
339 * @brief API to set vddcore or vdd1v8 power on for PMIC modes which is responded to PDRUNCFG0[PMIC_MODE] or
340 * PDSLEEPCFG0[PMIC_MODE] select pin values. If not set, the driver will use default configurations for different PMIC
341 * mode.
342 * The default configuration is as below.
343 * PMIC_MODE: power mode select
344 * 0b00 run mode, all supplies on.
345 * 0b01 deep sleep mode, all supplies on.
346 * 0b10 deep powerdown mode, vddcore off.
347 * 0b11 full deep powerdown mode vdd1v8 and vddcore off.
348 *
349 * Note, be cautious to modify the VDD state in different PMIC mode. When the default configuration is changed, use
350 * exclude_from_pd[0] to configure the PMIC mode for deep sleep and power down mode.
351 *
352 * @param vddSelect the ORd value of @ref power_control_for_pmic_mode. Defines run (all supplies on), deep power-down
353 * (VDDCORE off), and true deep power-down (VDD1V8 and VDDCORE off).
354 */
355 void POWER_PmicPowerModeSelectControl(uint32_t vddSelect);
356
357 /*!
358 * @brief API to enable PDRUNCFG bit in the Sysctl0. Note that enabling the bit powers down the peripheral
359 *
360 * @param en peripheral for which to enable the PDRUNCFG bit
361 */
362 void POWER_EnablePD(pd_bit_t en);
363
364 /*!
365 * @brief API to disable PDRUNCFG bit in the Sysctl0. Note that disabling the bit powers up the peripheral
366 *
367 * @param en peripheral for which to disable the PDRUNCFG bit
368 */
369 void POWER_DisablePD(pd_bit_t en);
370
371 /*!
372 * @brief API to enable deep sleep bit in the ARM Core.
373 */
POWER_EnableDeepSleep(void)374 static inline void POWER_EnableDeepSleep(void)
375 {
376 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
377 }
378
379 /*!
380 * @brief API to disable deep sleep bit in the ARM Core.
381 */
POWER_DisableDeepSleep(void)382 static inline void POWER_DisableDeepSleep(void)
383 {
384 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
385 }
386
387 /**
388 * @brief API to update XTAL oscillator settling time .
389 * @param osc_delay : OSC stabilization time in unit of microsecond
390 */
391 void POWER_UpdateOscSettlingTime(uint32_t osc_delay);
392
393 /**
394 * @brief API to update on-board PMIC vddcore recovery time.
395 *
396 * NOTE: If LDO is used instead of PMIC, don't call it. Otherwise it must be called to allow power library to well
397 * handle the deep sleep process.
398 *
399 * @param pmic_delay : PMIC stabilization time in unit of microsecond, or PMIC_VDDCORE_RECOVERY_TIME_IGNORE if not
400 * care.
401 */
402 void POWER_UpdatePmicRecoveryTime(uint32_t pmic_delay);
403
404 /*!
405 * @brief API to apply updated PMC PDRUNCFG bits in the Sysctl0.
406 */
407 void POWER_ApplyPD(void);
408
409 /**
410 * @brief Clears the PMC event flags state.
411 * @param statusMask : A bitmask of event flags that are to be cleared.
412 */
413 void POWER_ClearEventFlags(uint32_t statusMask);
414
415 /**
416 * @brief Get the PMC event flags state.
417 * @return PMC FLAGS register value
418 */
419 uint32_t POWER_GetEventFlags(void);
420
421 /**
422 * @brief Enable the PMC interrupt requests.
423 * @param interruptMask : A bitmask of of interrupts to enable.
424 */
425 void POWER_EnableInterrupts(uint32_t interruptMask);
426
427 /**
428 * @brief Disable the PMC interrupt requests.
429 * @param interruptMask : A bitmask of of interrupts to disable.
430 */
431 void POWER_DisableInterrupts(uint32_t interruptMask);
432
433 /**
434 * @brief Set the PMC analog buffer for references or ATX2.
435 * @param enable : Set to true to enable analog buffer for references or ATX2, false to disable.
436 */
437 void POWER_SetAnalogBuffer(bool enable);
438
439 /**
440 * @brief Get PMIC_MODE pins configure value.
441 * @param reg : PDSLEEPCFG0 or PDRUNCFG0 register offset
442 * @return PMIC_MODE pins value in PDSLEEPCFG0
443 */
POWER_GetPmicMode(pmic_mode_reg_t reg)444 static inline uint32_t POWER_GetPmicMode(pmic_mode_reg_t reg)
445 {
446 uint32_t mode = (uint32_t)reg;
447
448 return ((SYSCTL0_TUPLE_REG(mode) & (SYSCTL0_PDSLEEPCFG0_PMIC_MODE0_MASK | SYSCTL0_PDSLEEPCFG0_PMIC_MODE1_MASK)) >>
449 SYSCTL0_PDSLEEPCFG0_PMIC_MODE0_SHIFT);
450 }
451
452 /**
453 * @brief Get RBB/FBB bit value.
454 * @param reg : PDSLEEPCFG0 or PDRUNCFG0 register offset
455 * @return Current body bias mode
456 */
POWER_GetBodyBiasMode(pmic_mode_reg_t reg)457 static inline body_bias_mode_t POWER_GetBodyBiasMode(pmic_mode_reg_t reg)
458 {
459 uint32_t mode = (uint32_t)reg;
460 uint32_t bbMode = (SYSCTL0_TUPLE_REG(mode) & (SYSCTL0_PDRUNCFG0_RBB_PD_MASK | SYSCTL0_PDRUNCFG0_FBB_PD_MASK)) >>
461 SYSCTL0_PDRUNCFG0_RBB_PD_SHIFT;
462
463 return (body_bias_mode_t)bbMode;
464 }
465
466 /*!
467 * @brief Configure pad voltage level. Wide voltage range cost more power due to enabled voltage detector.
468 *
469 * NOTE: BE CAUTIOUS TO CALL THIS API. IF THE PAD SUPPLY IS BEYOND THE SET RANGE, SILICON MIGHT BE DAMAGED.
470 *
471 * @param config pad voltage range configuration.
472 */
473 void POWER_SetPadVolRange(const power_pad_vrange_t *config);
474
475 /**
476 * @brief PMC Enter Rbb mode function call
477 */
478 void POWER_EnterRbb(void);
479
480 /**
481 * @brief PMC Enter Fbb mode function call
482 */
483 void POWER_EnterFbb(void);
484
485 /**
486 * @brief PMC exit Rbb & Fbb mode function call
487 */
488 void POWER_EnterNbb(void);
489
490 /**
491 * @brief Deprecated and replaced by #POWER_SetVoltageForFreq()! PMC Set Ldo volatage for particular frequency.
492 * NOTE: If LVD falling trip voltage is higher than the required core voltage for particular frequency,
493 * LVD voltage will be decreased to safe level to avoid unexpected LVD reset or interrupt event.
494 * @param cm33_clk_freq : CM33 core frequency value
495 * @param dsp_clk_freq : dsp core frequency value
496 * @return true for success and false for CPU frequency out of available frequency range.
497 */
498 bool POWER_SetLdoVoltageForFreq(uint32_t cm33_clk_freq, uint32_t dsp_clk_freq);
499
500 /**
501 * @brief Set VDDCORE supply source, PMIC or on-chip regulator.
502 * @param src : #power_vddcore_src_t, VDDCore supply source
503 */
504 void POWER_SetVddCoreSupplySrc(power_vddcore_src_t src);
505
506 /**
507 * @brief Set the core supply setting function if PMIC is used. The function is not needed and ignored when
508 * using the onchip regulator to supply VDDCORE.
509 * @param func : #power_vddcore_set_func_t, the PMIC core supply voltage set function.
510 */
511 void POWER_SetPmicCoreSupplyFunc(power_vddcore_set_func_t func);
512
513 /**
514 * @brief PMC Set volatage for particular frequency with given minimum value. #POWER_SetVddCoreSupplySrc should be
515 * called in advance to tell power driver the supply source. If PMIC is used, the VDDCORE setting function
516 * should be set by #POWER_SetPmicCoreSupplyFunc before this API is called.
517 * NOTE: If LVD falling trip voltage is higher than the required core voltage for particular frequency,
518 * LVD voltage will be decreased to safe level to avoid unexpected LVD reset or interrupt event.
519 * @param cm33_clk_freq : CM33 core frequency value
520 * @param dsp_clk_freq : dsp core frequency value
521 * @param mini_volt : minimum voltage in millivolt(mV) for VDDCORE. Should <= 1100mV, 0 means use the core frequency
522 * to calculate voltage.
523 * @return true for success and false for CPU frequency out of available frequency range or failed to set voltage.
524 */
525 bool POWER_SetVoltageForFreq(uint32_t cm33_clk_freq, uint32_t dsp_clk_freq, uint32_t mini_volt);
526
527 /*!
528 * @brief Set vddcore low voltage detection falling trip voltage.
529 * @param volt target LVD voltage to set.
530 */
531 void POWER_SetLvdFallingTripVoltage(power_lvd_falling_trip_vol_val_t volt);
532
533 /**
534 * @brief Get current vddcore low voltage detection falling trip voltage.
535 * @return Current LVD voltage.
536 */
537 power_lvd_falling_trip_vol_val_t POWER_GetLvdFallingTripVoltage(void);
538
539 /**
540 * @brief Disable low voltage detection, no reset or interrupt is triggered when vddcore voltage drops below
541 * threshold.
542 * NOTE: This API is for internal use only. Application should not touch it.
543 */
544 void POWER_DisableLVD(void);
545
546 /**
547 * @brief Restore low voltage detection setting.
548 * NOTE: This API is for internal use only. Application should not touch it.
549 */
550 void POWER_RestoreLVD(void);
551
552 /**
553 * @brief Set PMIC_MODE pins configure value.
554 * @param mode : PMIC MODE pin value
555 * @param reg : PDSLEEPCFG0 or PDRUNCFG0 register offset
556 * @return PMIC_MODE pins value in PDSLEEPCFG0
557 */
558 void POWER_SetPmicMode(uint32_t mode, pmic_mode_reg_t reg);
559
560 /**
561 * @brief Set deep sleep clock source of main clock.
562 * @param clk : clock source of main clock.
563 */
564 void POWER_SetDeepSleepClock(power_deep_sleep_clk_t clk);
565
566 /**
567 * @brief Configures and enters in SLEEP low power mode
568 */
569 void POWER_EnterSleep(void);
570
571 /**
572 * @brief PMC Deep Sleep function call
573 * @param exclude_from_pd Bit mask of the PDRUNCFG0 ~ PDRUNCFG3 that needs to be powered on during Deep Sleep mode
574 * selected.
575 */
576 void POWER_EnterDeepSleep(const uint32_t exclude_from_pd[4]);
577
578 /**
579 * @brief PMC Deep Power Down function call
580 * @param exclude_from_pd Bit mask of the PDRUNCFG0 ~ PDRUNCFG3 that needs to be powered on during Deep Power Down
581 * mode selected.
582 */
583 void POWER_EnterDeepPowerDown(const uint32_t exclude_from_pd[4]);
584
585 /**
586 * @brief PMC Full Deep Power Down function call
587 * @param exclude_from_pd Bit mask of the PDRUNCFG0 ~ PDRUNCFG3 that needs to be powered on during Full Deep Power
588 * Down mode selected.
589 */
590 void POWER_EnterFullDeepPowerDown(const uint32_t exclude_from_pd[4]);
591
592 /*!
593 * @brief Power Library API to enter different power mode.
594 *
595 * @param mode Power mode to enter.
596 * @param exclude_from_pd Bit mask of the PDRUNCFG0 ~ PDRUNCFG3 that needs to be powered on during power mode selected.
597 */
598 void POWER_EnterPowerMode(power_mode_cfg_t mode, const uint32_t exclude_from_pd[4]);
599
600 /*!
601 * @brief Enable specific interrupt for wake-up from deep-sleep mode.
602 * Enable the interrupt for wake-up from deep sleep mode.
603 * Some interrupts are typically used in sleep mode only and will not occur during
604 * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
605 * those clocks (significantly increasing power consumption in the reduced power mode),
606 * making these wake-ups possible.
607 * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internally).
608 * @param interrupt The IRQ number.
609 */
610 void EnableDeepSleepIRQ(IRQn_Type interrupt);
611
612 /*!
613 * @brief Disable specific interrupt for wake-up from deep-sleep mode.
614 * Disable the interrupt for wake-up from deep sleep mode.
615 * Some interrupts are typically used in sleep mode only and will not occur during
616 * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
617 * those clocks (significantly increasing power consumption in the reduced power mode),
618 * making these wake-ups possible.
619 * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internally).
620 * @param interrupt The IRQ number.
621 */
622 void DisableDeepSleepIRQ(IRQn_Type interrupt);
623
624 /*!
625 * @brief Power Library API to return the library version.
626 *
627 * @return version number of the power library
628 */
629 uint32_t POWER_GetLibVersion(void);
630
631 #ifdef __cplusplus
632 }
633 #endif
634
635 /*!
636 * @}
637 */
638
639 #endif /* _FSL_POWER_H_ */
640
