1 /*
2 * Copyright 2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 /*
9 * How to setup clock using clock driver functions:
10 *
11 * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
12 *
13 * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
14 *
15 * 3. Call CLOCK_SetRootClock() to configure corresponding module clock source and divider.
16 *
17 */
18
19 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
20 !!GlobalInfo
21 product: Clocks v7.0
22 processor: MIMXRT1175xxxxx
23 mcu_data: ksdk2_0
24 processor_version: 0.10.8
25 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
26
27 #include "clock_config.h"
28 #include "fsl_iomuxc.h"
29 #include "fsl_dcdc.h"
30 #include "fsl_pmu.h"
31 #include "fsl_clock.h"
32
33 /*******************************************************************************
34 * Definitions
35 ******************************************************************************/
36
37 /*******************************************************************************
38 * Variables
39 ******************************************************************************/
40
41 /*******************************************************************************
42 ************************ BOARD_InitBootClocks function ************************
43 ******************************************************************************/
BOARD_InitBootClocks(void)44 void BOARD_InitBootClocks(void)
45 {
46 BOARD_BootClockRUN();
47 }
48
49 #if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
50 #if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
51 /* This function should not run from SDRAM since it will change SEMC configuration. */
52 AT_QUICKACCESS_SECTION_CODE(void UpdateSemcClock(void));
UpdateSemcClock(void)53 void UpdateSemcClock(void)
54 {
55 /* Enable self-refresh mode and update semc clock root to 200MHz. */
56 SEMC->IPCMD = 0xA55A000D;
57 while ((SEMC->INTR & 0x3) == 0)
58 ;
59 SEMC->INTR = 0x3;
60 SEMC->DCCR = 0x0B;
61 /*
62 * Currently we are using SEMC parameter which fit both 166MHz and 200MHz, only
63 * need to change the SEMC clock root here. If customer is using their own DCD and
64 * want to switch from 166MHz to 200MHz, extra SEMC configuration might need to be
65 * adjusted here to fine tune the SDRAM performance
66 */
67 CCM->CLOCK_ROOT[kCLOCK_Root_Semc].CONTROL = 0x602;
68 }
69 #endif
70 #endif
71
72 /*******************************************************************************
73 ********************** Configuration BOARD_BootClockRUN ***********************
74 ******************************************************************************/
75 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
76 !!Configuration
77 name: BOARD_BootClockRUN
78 called_from_default_init: true
79 outputs:
80 - {id: ACMP_CLK_ROOT.outFreq, value: 24 MHz}
81 - {id: ADC1_CLK_ROOT.outFreq, value: 24 MHz}
82 - {id: ADC2_CLK_ROOT.outFreq, value: 24 MHz}
83 - {id: ARM_PLL_CLK.outFreq, value: 996 MHz}
84 - {id: ASRC_CLK_ROOT.outFreq, value: 24 MHz}
85 - {id: AXI_CLK_ROOT.outFreq, value: 24 MHz}
86 - {id: BUS_CLK_ROOT.outFreq, value: 24 MHz}
87 - {id: BUS_LPSR_CLK_ROOT.outFreq, value: 24 MHz}
88 - {id: CAN1_CLK_ROOT.outFreq, value: 24 MHz}
89 - {id: CAN2_CLK_ROOT.outFreq, value: 24 MHz}
90 - {id: CAN3_CLK_ROOT.outFreq, value: 24 MHz}
91 - {id: CCM_CLKO1_CLK_ROOT.outFreq, value: 24 MHz}
92 - {id: CCM_CLKO2_CLK_ROOT.outFreq, value: 24 MHz}
93 - {id: CLK_1M.outFreq, value: 1 MHz}
94 - {id: CSI2_CLK_ROOT.outFreq, value: 24 MHz}
95 - {id: CSI2_ESC_CLK_ROOT.outFreq, value: 24 MHz}
96 - {id: CSI2_UI_CLK_ROOT.outFreq, value: 24 MHz}
97 - {id: CSI_CLK_ROOT.outFreq, value: 24 MHz}
98 - {id: CSSYS_CLK_ROOT.outFreq, value: 24 MHz}
99 - {id: CSTRACE_CLK_ROOT.outFreq, value: 24 MHz}
100 - {id: ELCDIF_CLK_ROOT.outFreq, value: 24 MHz}
101 - {id: EMV1_CLK_ROOT.outFreq, value: 24 MHz}
102 - {id: EMV2_CLK_ROOT.outFreq, value: 24 MHz}
103 - {id: ENET1_CLK_ROOT.outFreq, value: 24 MHz}
104 - {id: ENET2_CLK_ROOT.outFreq, value: 24 MHz}
105 - {id: ENET_1G_TX_CLK.outFreq, value: 24 MHz}
106 - {id: ENET_25M_CLK_ROOT.outFreq, value: 24 MHz}
107 - {id: ENET_QOS_CLK_ROOT.outFreq, value: 24 MHz}
108 - {id: ENET_TIMER1_CLK_ROOT.outFreq, value: 24 MHz}
109 - {id: ENET_TIMER2_CLK_ROOT.outFreq, value: 24 MHz}
110 - {id: ENET_TIMER3_CLK_ROOT.outFreq, value: 24 MHz}
111 - {id: FLEXIO1_CLK_ROOT.outFreq, value: 24 MHz}
112 - {id: FLEXIO2_CLK_ROOT.outFreq, value: 24 MHz}
113 - {id: FLEXSPI1_CLK_ROOT.outFreq, value: 24 MHz}
114 - {id: FLEXSPI2_CLK_ROOT.outFreq, value: 24 MHz}
115 - {id: GC355_CLK_ROOT.outFreq, value: 24 MHz}
116 - {id: GPT1_CLK_ROOT.outFreq, value: 24 MHz}
117 - {id: GPT1_ipg_clk_highfreq.outFreq, value: 24 MHz}
118 - {id: GPT2_CLK_ROOT.outFreq, value: 24 MHz}
119 - {id: GPT2_ipg_clk_highfreq.outFreq, value: 24 MHz}
120 - {id: GPT3_CLK_ROOT.outFreq, value: 24 MHz}
121 - {id: GPT3_ipg_clk_highfreq.outFreq, value: 24 MHz}
122 - {id: GPT4_CLK_ROOT.outFreq, value: 24 MHz}
123 - {id: GPT4_ipg_clk_highfreq.outFreq, value: 24 MHz}
124 - {id: GPT5_CLK_ROOT.outFreq, value: 24 MHz}
125 - {id: GPT5_ipg_clk_highfreq.outFreq, value: 24 MHz}
126 - {id: GPT6_CLK_ROOT.outFreq, value: 24 MHz}
127 - {id: GPT6_ipg_clk_highfreq.outFreq, value: 24 MHz}
128 - {id: LCDIFV2_CLK_ROOT.outFreq, value: 24 MHz}
129 - {id: LPI2C1_CLK_ROOT.outFreq, value: 24 MHz}
130 - {id: LPI2C2_CLK_ROOT.outFreq, value: 24 MHz}
131 - {id: LPI2C3_CLK_ROOT.outFreq, value: 24 MHz}
132 - {id: LPI2C4_CLK_ROOT.outFreq, value: 24 MHz}
133 - {id: LPI2C5_CLK_ROOT.outFreq, value: 24 MHz}
134 - {id: LPI2C6_CLK_ROOT.outFreq, value: 24 MHz}
135 - {id: LPSPI1_CLK_ROOT.outFreq, value: 24 MHz}
136 - {id: LPSPI2_CLK_ROOT.outFreq, value: 24 MHz}
137 - {id: LPSPI3_CLK_ROOT.outFreq, value: 24 MHz}
138 - {id: LPSPI4_CLK_ROOT.outFreq, value: 24 MHz}
139 - {id: LPSPI5_CLK_ROOT.outFreq, value: 24 MHz}
140 - {id: LPSPI6_CLK_ROOT.outFreq, value: 24 MHz}
141 - {id: LPUART10_CLK_ROOT.outFreq, value: 24 MHz}
142 - {id: LPUART11_CLK_ROOT.outFreq, value: 24 MHz}
143 - {id: LPUART12_CLK_ROOT.outFreq, value: 24 MHz}
144 - {id: LPUART1_CLK_ROOT.outFreq, value: 24 MHz}
145 - {id: LPUART2_CLK_ROOT.outFreq, value: 24 MHz}
146 - {id: LPUART3_CLK_ROOT.outFreq, value: 24 MHz}
147 - {id: LPUART4_CLK_ROOT.outFreq, value: 24 MHz}
148 - {id: LPUART5_CLK_ROOT.outFreq, value: 24 MHz}
149 - {id: LPUART6_CLK_ROOT.outFreq, value: 24 MHz}
150 - {id: LPUART7_CLK_ROOT.outFreq, value: 24 MHz}
151 - {id: LPUART8_CLK_ROOT.outFreq, value: 24 MHz}
152 - {id: LPUART9_CLK_ROOT.outFreq, value: 24 MHz}
153 - {id: M4_CLK_ROOT.outFreq, value: 24 MHz}
154 - {id: M4_SYSTICK_CLK_ROOT.outFreq, value: 24 MHz}
155 - {id: M7_CLK_ROOT.outFreq, value: 24 MHz}
156 - {id: M7_SYSTICK_CLK_ROOT.outFreq, value: 24 MHz}
157 - {id: MIC_CLK_ROOT.outFreq, value: 24 MHz}
158 - {id: MIPI_DSI_TX_CLK_ESC_ROOT.outFreq, value: 24 MHz}
159 - {id: MIPI_ESC_CLK_ROOT.outFreq, value: 24 MHz}
160 - {id: MIPI_REF_CLK_ROOT.outFreq, value: 24 MHz}
161 - {id: MQS_CLK_ROOT.outFreq, value: 24 MHz}
162 - {id: MQS_MCLK.outFreq, value: 24 MHz}
163 - {id: OSC_24M.outFreq, value: 24 MHz}
164 - {id: OSC_32K.outFreq, value: 32.768 kHz}
165 - {id: OSC_RC_16M.outFreq, value: 16 MHz}
166 - {id: OSC_RC_400M.outFreq, value: 400 MHz}
167 - {id: OSC_RC_48M.outFreq, value: 48 MHz}
168 - {id: OSC_RC_48M_DIV2.outFreq, value: 24 MHz}
169 - {id: PLL_AUDIO_CLK.outFreq, value: 672.000025 MHz}
170 - {id: PLL_VIDEO_CLK.outFreq, value: 672.000025 MHz}
171 - {id: SAI1_CLK_ROOT.outFreq, value: 24 MHz}
172 - {id: SAI1_MCLK1.outFreq, value: 24 MHz}
173 - {id: SAI1_MCLK3.outFreq, value: 24 MHz}
174 - {id: SAI2_CLK_ROOT.outFreq, value: 24 MHz}
175 - {id: SAI2_MCLK1.outFreq, value: 24 MHz}
176 - {id: SAI2_MCLK3.outFreq, value: 24 MHz}
177 - {id: SAI3_CLK_ROOT.outFreq, value: 24 MHz}
178 - {id: SAI3_MCLK1.outFreq, value: 24 MHz}
179 - {id: SAI3_MCLK3.outFreq, value: 24 MHz}
180 - {id: SAI4_CLK_ROOT.outFreq, value: 24 MHz}
181 - {id: SAI4_MCLK1.outFreq, value: 24 MHz}
182 - {id: SEMC_CLK_ROOT.outFreq, value: 198 MHz}
183 - {id: SPDIF_CLK_ROOT.outFreq, value: 24 MHz}
184 - {id: SYS_PLL1_CLK.outFreq, value: 1 GHz}
185 - {id: SYS_PLL2_CLK.outFreq, value: 528 MHz}
186 - {id: SYS_PLL2_PFD0_CLK.outFreq, value: 352 MHz}
187 - {id: SYS_PLL2_PFD1_CLK.outFreq, value: 594 MHz}
188 - {id: SYS_PLL2_PFD2_CLK.outFreq, value: 396 MHz}
189 - {id: SYS_PLL2_PFD3_CLK.outFreq, value: 297 MHz}
190 - {id: SYS_PLL3_CLK.outFreq, value: 480 MHz}
191 - {id: SYS_PLL3_PFD0_CLK.outFreq, value: 8640/13 MHz}
192 - {id: SYS_PLL3_PFD1_CLK.outFreq, value: 8640/17 MHz}
193 - {id: SYS_PLL3_PFD2_CLK.outFreq, value: 270 MHz}
194 - {id: SYS_PLL3_PFD3_CLK.outFreq, value: 8640/13 MHz}
195 - {id: USDHC1_CLK_ROOT.outFreq, value: 24 MHz}
196 - {id: USDHC2_CLK_ROOT.outFreq, value: 24 MHz}
197 settings:
198 - {id: ANADIG_PLL.PLL_AUDIO.denom, value: '960000'}
199 - {id: ANADIG_PLL.PLL_AUDIO.div, value: '28'}
200 - {id: ANADIG_PLL.PLL_AUDIO.num, value: '1'}
201 - {id: ANADIG_PLL.PLL_VIDEO.denom, value: '960000'}
202 - {id: ANADIG_PLL.PLL_VIDEO.div, value: '28'}
203 - {id: ANADIG_PLL.PLL_VIDEO.num, value: '1'}
204 - {id: ANADIG_PLL.SYS_PLL2.denom, value: '60000'}
205 - {id: ANADIG_PLL.SYS_PLL2.div, value: '22'}
206 - {id: ANADIG_PLL.SYS_PLL2.num, value: '0'}
207 - {id: ANADIG_PLL.SYS_PLL3_PFD3_DIV.scale, value: '13'}
208 - {id: ANADIG_PLL_ARM_PLL_CTRL_POWERUP_CFG, value: Enabled}
209 - {id: ANADIG_PLL_PLL_AUDIO_CTRL0_POWERUP_CFG, value: Enabled}
210 - {id: ANADIG_PLL_PLL_VIDEO_CTRL0_POWERUP_CFG, value: Enabled}
211 - {id: ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_CFG, value: Enabled}
212 - {id: ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_CFG, value: Enabled}
213 - {id: CCM.CLOCK_ROOT4.DIV.scale, value: '3'}
214 - {id: CCM.CLOCK_ROOT4.MUX.sel, value: ANADIG_PLL.SYS_PLL2_PFD1_CLK}
215 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
216
217 /*******************************************************************************
218 * Variables for BOARD_BootClockRUN configuration
219 ******************************************************************************/
220
221 #ifndef SKIP_POWER_ADJUSTMENT
222 #if __CORTEX_M == 7
223 #define BYPASS_LDO_LPSR 1
224 #define SKIP_LDO_ADJUSTMENT 1
225 #elif __CORTEX_M == 4
226 #define SKIP_DCDC_ADJUSTMENT 1
227 #define SKIP_FBB_ENABLE 1
228 #endif
229 #endif
230
231 const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN =
232 {
233 .postDivider = kCLOCK_PllPostDiv2, /* Post divider, 0 - DIV by 2, 1 - DIV by 4, 2 - DIV by 8, 3 - DIV by 1 */
234 .loopDivider = 166, /* PLL Loop divider, Fout = Fin * ( loopDivider / ( 2 * postDivider ) ) */
235 };
236
237 const clock_sys_pll1_config_t sysPll1Config_BOARD_BootClockRUN =
238 {
239 .pllDiv2En = 0, /* Enable Sys Pll1 divide-by-2 clock or not */
240 .pllDiv5En = 0, /* Enable Sys Pll1 divide-by-5 clock or not */
241 .ss = NULL, /* Spread spectrum parameter */
242 .ssEnable = false, /* Enable spread spectrum or not */
243 };
244
245 const clock_sys_pll2_config_t sysPll2Config_BOARD_BootClockRUN =
246 {
247 .mfd = 60000, /* Denominator of spread spectrum */
248 .ss = NULL, /* Spread spectrum parameter */
249 .ssEnable = false, /* Enable spread spectrum or not */
250 };
251
252 const clock_audio_pll_config_t audioPllConfig_BOARD_BootClockRUN =
253 {
254 .loopDivider = 28, /* PLL Loop divider, valid range for DIV_SELECT divider value: 27 ~ 54. */
255 .postDivider = 0, /* Divider after PLL, should only be 1, 2, 4, 8, 16, 32 */
256 .numerator = 1, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
257 .denominator = 960000, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
258 .ss = NULL, /* Spread spectrum parameter */
259 .ssEnable = false, /* Enable spread spectrum or not */
260 };
261
262 const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN =
263 {
264 .loopDivider = 28, /* PLL Loop divider, valid range for DIV_SELECT divider value: 27 ~ 54. */
265 .postDivider = 0, /* Divider after PLL, should only be 1, 2, 4, 8, 16, 32 */
266 .numerator = 1, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
267 .denominator = 960000, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
268 .ss = NULL, /* Spread spectrum parameter */
269 .ssEnable = false, /* Enable spread spectrum or not */
270 };
271
272 /*******************************************************************************
273 * Code for BOARD_BootClockRUN configuration
274 ******************************************************************************/
BOARD_BootClockRUN(void)275 void BOARD_BootClockRUN(void)
276 {
277 clock_root_config_t rootCfg = {0};
278
279 /* Set DCDC to DCM mode to improve the efficiency for light loading in run mode and transient performance with a big loading step. */
280 DCDC_BootIntoDCM(DCDC);
281
282 #if !defined(SKIP_DCDC_ADJUSTMENT) || (!SKIP_DCDC_ADJUSTMENT)
283 if((OCOTP->FUSEN[16].FUSE == 0x57AC5969U) && ((OCOTP->FUSEN[17].FUSE & 0xFFU) == 0x0BU))
284 {
285 DCDC_SetVDD1P0BuckModeTargetVoltage(DCDC, kDCDC_1P0BuckTarget1P15V);
286 }
287 else
288 {
289 /* Set 1.125V for production samples to align with data sheet requirement */
290 DCDC_SetVDD1P0BuckModeTargetVoltage(DCDC, kDCDC_1P0BuckTarget1P125V);
291 }
292 #endif
293
294 #if !defined(SKIP_FBB_ENABLE) || (!SKIP_FBB_ENABLE)
295 /* Check if FBB need to be enabled in OverDrive(OD) mode */
296 if(((OCOTP->FUSEN[7].FUSE & 0x10U) >> 4U) != 1)
297 {
298 PMU_EnableBodyBias(ANADIG_PMU, kPMU_FBB_CM7, true);
299 }
300 else
301 {
302 PMU_EnableBodyBias(ANADIG_PMU, kPMU_FBB_CM7, false);
303 }
304 #endif
305
306 #if defined(BYPASS_LDO_LPSR) && BYPASS_LDO_LPSR
307 PMU_StaticEnableLpsrAnaLdoBypassMode(ANADIG_LDO_SNVS, true);
308 PMU_StaticEnableLpsrDigLdoBypassMode(ANADIG_LDO_SNVS, true);
309 #endif
310
311 #if !defined(SKIP_LDO_ADJUSTMENT) || (!SKIP_LDO_ADJUSTMENT)
312 pmu_static_lpsr_ana_ldo_config_t lpsrAnaConfig;
313 pmu_static_lpsr_dig_config_t lpsrDigConfig;
314
315 if((ANADIG_LDO_SNVS->PMU_LDO_LPSR_ANA & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_MASK) == 0UL)
316 {
317 PMU_StaticGetLpsrAnaLdoDefaultConfig(&lpsrAnaConfig);
318 PMU_StaticLpsrAnaLdoInit(ANADIG_LDO_SNVS, &lpsrAnaConfig);
319 }
320
321 if((ANADIG_LDO_SNVS->PMU_LDO_LPSR_DIG & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_MASK) == 0UL)
322 {
323 PMU_StaticGetLpsrDigLdoDefaultConfig(&lpsrDigConfig);
324 lpsrDigConfig.targetVoltage = kPMU_LpsrDigTargetStableVoltage1P117V;
325 PMU_StaticLpsrDigLdoInit(ANADIG_LDO_SNVS, &lpsrDigConfig);
326 }
327 #endif
328
329 /* Config CLK_1M */
330 CLOCK_OSC_Set1MHzOutputBehavior(kCLOCK_1MHzOutEnableFreeRunning1Mhz);
331
332 /* Init OSC RC 16M */
333 ANADIG_OSC->OSC_16M_CTRL |= ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_MASK;
334
335 /* Init OSC RC 400M */
336 CLOCK_OSC_EnableOscRc400M();
337 CLOCK_OSC_GateOscRc400M(true);
338
339 /* Init OSC RC 48M */
340 CLOCK_OSC_EnableOsc48M(true);
341 CLOCK_OSC_EnableOsc48MDiv2(true);
342
343 /* Config OSC 24M */
344 ANADIG_OSC->OSC_24M_CTRL |= ANADIG_OSC_OSC_24M_CTRL_OSC_EN(0) | ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN(0) | ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK(0) | ANADIG_OSC_OSC_24M_CTRL_LP_EN(0) | ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE(0);
345 /* Wait for 24M OSC to be stable. */
346 while (ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK !=
347 (ANADIG_OSC->OSC_24M_CTRL & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK))
348 {
349 }
350
351 /* Swicth both core, M7 Systick and Bus_Lpsr to OscRC48MDiv2 first */
352 rootCfg.mux = kCLOCK_M7_ClockRoot_MuxOscRc48MDiv2;
353 rootCfg.div = 1;
354 CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg);
355
356 rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc48MDiv2;
357 rootCfg.div = 1;
358 CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg);
359
360 rootCfg.mux = kCLOCK_M4_ClockRoot_MuxOscRc48MDiv2;
361 rootCfg.div = 1;
362 CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg);
363
364 rootCfg.mux = kCLOCK_BUS_LPSR_ClockRoot_MuxOscRc48MDiv2;
365 rootCfg.div = 1;
366 CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg);
367
368 /*
369 * if DCD is used, please make sure the clock source of SEMC is not changed in the following PLL/PFD configuration code.
370 */
371 /* Init Arm Pll. */
372 CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
373
374 /* Init Sys Pll1. */
375 CLOCK_InitSysPll1(&sysPll1Config_BOARD_BootClockRUN);
376
377 /* Init Sys Pll2. */
378 CLOCK_InitSysPll2(&sysPll2Config_BOARD_BootClockRUN);
379
380 /* Init System Pll2 pfd0. */
381 CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd0, 27);
382
383 /* Init System Pll2 pfd1. */
384 CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd1, 16);
385
386 /* Init System Pll2 pfd2. */
387 CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd2, 24);
388
389 /* Init System Pll2 pfd3. */
390 CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd3, 32);
391
392 /* Init Sys Pll3. */
393 CLOCK_InitSysPll3();
394
395 /* Init System Pll3 pfd0. */
396 CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd0, 13);
397
398 /* Init System Pll3 pfd1. */
399 CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd1, 17);
400
401 /* Init System Pll3 pfd2. */
402 CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd2, 32);
403
404 /* Init System Pll3 pfd3. */
405 CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd3, 13);
406
407 /* Disable Sys Pll3 Div2 output. */
408 ANADIG_PLL->SYS_PLL3_CTRL &= ~ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_MASK;
409
410 /* Init Audio Pll. */
411 CLOCK_InitAudioPll(&audioPllConfig_BOARD_BootClockRUN);
412
413 /* Init Video Pll. */
414 CLOCK_InitVideoPll(&videoPllConfig_BOARD_BootClockRUN);
415
416 /* Module clock root configurations. */
417 /* Configure M7 using OSC_RC_48M_DIV2 */
418 rootCfg.mux = kCLOCK_M7_ClockRoot_MuxOscRc48MDiv2;
419 rootCfg.div = 1;
420 CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg);
421
422 /* Configure M4 using OSC_RC_48M_DIV2 */
423 rootCfg.mux = kCLOCK_M4_ClockRoot_MuxOscRc48MDiv2;
424 rootCfg.div = 1;
425 CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg);
426
427 /* Configure BUS using OSC_RC_48M_DIV2 */
428 rootCfg.mux = kCLOCK_BUS_ClockRoot_MuxOscRc48MDiv2;
429 rootCfg.div = 1;
430 CLOCK_SetRootClock(kCLOCK_Root_Bus, &rootCfg);
431
432 /* Configure BUS_LPSR using OSC_RC_48M_DIV2 */
433 rootCfg.mux = kCLOCK_BUS_LPSR_ClockRoot_MuxOscRc48MDiv2;
434 rootCfg.div = 1;
435 CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg);
436
437 /* Configure SEMC using SYS_PLL2_PFD1_CLK */
438 #ifndef SKIP_SEMC_INIT
439 rootCfg.mux = kCLOCK_SEMC_ClockRoot_MuxSysPll2Pfd1;
440 rootCfg.div = 3;
441 CLOCK_SetRootClock(kCLOCK_Root_Semc, &rootCfg);
442 #endif
443
444 #if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
445 #if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
446 UpdateSemcClock();
447 #endif
448 #endif
449
450 /* Configure CSSYS using OSC_RC_48M_DIV2 */
451 rootCfg.mux = kCLOCK_CSSYS_ClockRoot_MuxOscRc48MDiv2;
452 rootCfg.div = 1;
453 CLOCK_SetRootClock(kCLOCK_Root_Cssys, &rootCfg);
454
455 /* Configure CSTRACE using OSC_RC_48M_DIV2 */
456 rootCfg.mux = kCLOCK_CSTRACE_ClockRoot_MuxOscRc48MDiv2;
457 rootCfg.div = 1;
458 CLOCK_SetRootClock(kCLOCK_Root_Cstrace, &rootCfg);
459
460 /* Configure M4_SYSTICK using OSC_RC_48M_DIV2 */
461 rootCfg.mux = kCLOCK_M4_SYSTICK_ClockRoot_MuxOscRc48MDiv2;
462 rootCfg.div = 1;
463 CLOCK_SetRootClock(kCLOCK_Root_M4_Systick, &rootCfg);
464
465 /* Configure M7_SYSTICK using OSC_RC_48M_DIV2 */
466 rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc48MDiv2;
467 rootCfg.div = 1;
468 CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg);
469
470 /* Configure ADC1 using OSC_RC_48M_DIV2 */
471 rootCfg.mux = kCLOCK_ADC1_ClockRoot_MuxOscRc48MDiv2;
472 rootCfg.div = 1;
473 CLOCK_SetRootClock(kCLOCK_Root_Adc1, &rootCfg);
474
475 /* Configure ADC2 using OSC_RC_48M_DIV2 */
476 rootCfg.mux = kCLOCK_ADC2_ClockRoot_MuxOscRc48MDiv2;
477 rootCfg.div = 1;
478 CLOCK_SetRootClock(kCLOCK_Root_Adc2, &rootCfg);
479
480 /* Configure ACMP using OSC_RC_48M_DIV2 */
481 rootCfg.mux = kCLOCK_ACMP_ClockRoot_MuxOscRc48MDiv2;
482 rootCfg.div = 1;
483 CLOCK_SetRootClock(kCLOCK_Root_Acmp, &rootCfg);
484
485 /* Configure FLEXIO1 using OSC_RC_48M_DIV2 */
486 rootCfg.mux = kCLOCK_FLEXIO1_ClockRoot_MuxOscRc48MDiv2;
487 rootCfg.div = 1;
488 CLOCK_SetRootClock(kCLOCK_Root_Flexio1, &rootCfg);
489
490 /* Configure FLEXIO2 using OSC_RC_48M_DIV2 */
491 rootCfg.mux = kCLOCK_FLEXIO2_ClockRoot_MuxOscRc48MDiv2;
492 rootCfg.div = 1;
493 CLOCK_SetRootClock(kCLOCK_Root_Flexio2, &rootCfg);
494
495 /* Configure GPT1 using OSC_RC_48M_DIV2 */
496 rootCfg.mux = kCLOCK_GPT1_ClockRoot_MuxOscRc48MDiv2;
497 rootCfg.div = 1;
498 CLOCK_SetRootClock(kCLOCK_Root_Gpt1, &rootCfg);
499
500 /* Configure GPT2 using OSC_RC_48M_DIV2 */
501 rootCfg.mux = kCLOCK_GPT2_ClockRoot_MuxOscRc48MDiv2;
502 rootCfg.div = 1;
503 CLOCK_SetRootClock(kCLOCK_Root_Gpt2, &rootCfg);
504
505 /* Configure GPT3 using OSC_RC_48M_DIV2 */
506 rootCfg.mux = kCLOCK_GPT3_ClockRoot_MuxOscRc48MDiv2;
507 rootCfg.div = 1;
508 CLOCK_SetRootClock(kCLOCK_Root_Gpt3, &rootCfg);
509
510 /* Configure GPT4 using OSC_RC_48M_DIV2 */
511 rootCfg.mux = kCLOCK_GPT4_ClockRoot_MuxOscRc48MDiv2;
512 rootCfg.div = 1;
513 CLOCK_SetRootClock(kCLOCK_Root_Gpt4, &rootCfg);
514
515 /* Configure GPT5 using OSC_RC_48M_DIV2 */
516 rootCfg.mux = kCLOCK_GPT5_ClockRoot_MuxOscRc48MDiv2;
517 rootCfg.div = 1;
518 CLOCK_SetRootClock(kCLOCK_Root_Gpt5, &rootCfg);
519
520 /* Configure GPT6 using OSC_RC_48M_DIV2 */
521 rootCfg.mux = kCLOCK_GPT6_ClockRoot_MuxOscRc48MDiv2;
522 rootCfg.div = 1;
523 CLOCK_SetRootClock(kCLOCK_Root_Gpt6, &rootCfg);
524
525 /* Configure FLEXSPI1 using OSC_RC_48M_DIV2 */
526 #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1) || defined(FLEXSPI_IN_USE))
527 rootCfg.mux = kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc48MDiv2;
528 rootCfg.div = 1;
529 CLOCK_SetRootClock(kCLOCK_Root_Flexspi1, &rootCfg);
530 #endif
531
532 /* Configure FLEXSPI2 using OSC_RC_48M_DIV2 */
533 rootCfg.mux = kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc48MDiv2;
534 rootCfg.div = 1;
535 CLOCK_SetRootClock(kCLOCK_Root_Flexspi2, &rootCfg);
536
537 /* Configure CAN1 using OSC_RC_48M_DIV2 */
538 rootCfg.mux = kCLOCK_CAN1_ClockRoot_MuxOscRc48MDiv2;
539 rootCfg.div = 1;
540 CLOCK_SetRootClock(kCLOCK_Root_Can1, &rootCfg);
541
542 /* Configure CAN2 using OSC_RC_48M_DIV2 */
543 rootCfg.mux = kCLOCK_CAN2_ClockRoot_MuxOscRc48MDiv2;
544 rootCfg.div = 1;
545 CLOCK_SetRootClock(kCLOCK_Root_Can2, &rootCfg);
546
547 /* Configure CAN3 using OSC_RC_48M_DIV2 */
548 rootCfg.mux = kCLOCK_CAN3_ClockRoot_MuxOscRc48MDiv2;
549 rootCfg.div = 1;
550 CLOCK_SetRootClock(kCLOCK_Root_Can3, &rootCfg);
551
552 /* Configure LPUART1 using OSC_RC_48M_DIV2 */
553 rootCfg.mux = kCLOCK_LPUART1_ClockRoot_MuxOscRc48MDiv2;
554 rootCfg.div = 1;
555 CLOCK_SetRootClock(kCLOCK_Root_Lpuart1, &rootCfg);
556
557 /* Configure LPUART2 using OSC_RC_48M_DIV2 */
558 rootCfg.mux = kCLOCK_LPUART2_ClockRoot_MuxOscRc48MDiv2;
559 rootCfg.div = 1;
560 CLOCK_SetRootClock(kCLOCK_Root_Lpuart2, &rootCfg);
561
562 /* Configure LPUART3 using OSC_RC_48M_DIV2 */
563 rootCfg.mux = kCLOCK_LPUART3_ClockRoot_MuxOscRc48MDiv2;
564 rootCfg.div = 1;
565 CLOCK_SetRootClock(kCLOCK_Root_Lpuart3, &rootCfg);
566
567 /* Configure LPUART4 using OSC_RC_48M_DIV2 */
568 rootCfg.mux = kCLOCK_LPUART4_ClockRoot_MuxOscRc48MDiv2;
569 rootCfg.div = 1;
570 CLOCK_SetRootClock(kCLOCK_Root_Lpuart4, &rootCfg);
571
572 /* Configure LPUART5 using OSC_RC_48M_DIV2 */
573 rootCfg.mux = kCLOCK_LPUART5_ClockRoot_MuxOscRc48MDiv2;
574 rootCfg.div = 1;
575 CLOCK_SetRootClock(kCLOCK_Root_Lpuart5, &rootCfg);
576
577 /* Configure LPUART6 using OSC_RC_48M_DIV2 */
578 rootCfg.mux = kCLOCK_LPUART6_ClockRoot_MuxOscRc48MDiv2;
579 rootCfg.div = 1;
580 CLOCK_SetRootClock(kCLOCK_Root_Lpuart6, &rootCfg);
581
582 /* Configure LPUART7 using OSC_RC_48M_DIV2 */
583 rootCfg.mux = kCLOCK_LPUART7_ClockRoot_MuxOscRc48MDiv2;
584 rootCfg.div = 1;
585 CLOCK_SetRootClock(kCLOCK_Root_Lpuart7, &rootCfg);
586
587 /* Configure LPUART8 using OSC_RC_48M_DIV2 */
588 rootCfg.mux = kCLOCK_LPUART8_ClockRoot_MuxOscRc48MDiv2;
589 rootCfg.div = 1;
590 CLOCK_SetRootClock(kCLOCK_Root_Lpuart8, &rootCfg);
591
592 /* Configure LPUART9 using OSC_RC_48M_DIV2 */
593 rootCfg.mux = kCLOCK_LPUART9_ClockRoot_MuxOscRc48MDiv2;
594 rootCfg.div = 1;
595 CLOCK_SetRootClock(kCLOCK_Root_Lpuart9, &rootCfg);
596
597 /* Configure LPUART10 using OSC_RC_48M_DIV2 */
598 rootCfg.mux = kCLOCK_LPUART10_ClockRoot_MuxOscRc48MDiv2;
599 rootCfg.div = 1;
600 CLOCK_SetRootClock(kCLOCK_Root_Lpuart10, &rootCfg);
601
602 /* Configure LPUART11 using OSC_RC_48M_DIV2 */
603 rootCfg.mux = kCLOCK_LPUART11_ClockRoot_MuxOscRc48MDiv2;
604 rootCfg.div = 1;
605 CLOCK_SetRootClock(kCLOCK_Root_Lpuart11, &rootCfg);
606
607 /* Configure LPUART12 using OSC_RC_48M_DIV2 */
608 rootCfg.mux = kCLOCK_LPUART12_ClockRoot_MuxOscRc48MDiv2;
609 rootCfg.div = 1;
610 CLOCK_SetRootClock(kCLOCK_Root_Lpuart12, &rootCfg);
611
612 /* Configure LPI2C1 using OSC_RC_48M_DIV2 */
613 rootCfg.mux = kCLOCK_LPI2C1_ClockRoot_MuxOscRc48MDiv2;
614 rootCfg.div = 1;
615 CLOCK_SetRootClock(kCLOCK_Root_Lpi2c1, &rootCfg);
616
617 /* Configure LPI2C2 using OSC_RC_48M_DIV2 */
618 rootCfg.mux = kCLOCK_LPI2C2_ClockRoot_MuxOscRc48MDiv2;
619 rootCfg.div = 1;
620 CLOCK_SetRootClock(kCLOCK_Root_Lpi2c2, &rootCfg);
621
622 /* Configure LPI2C3 using OSC_RC_48M_DIV2 */
623 rootCfg.mux = kCLOCK_LPI2C3_ClockRoot_MuxOscRc48MDiv2;
624 rootCfg.div = 1;
625 CLOCK_SetRootClock(kCLOCK_Root_Lpi2c3, &rootCfg);
626
627 /* Configure LPI2C4 using OSC_RC_48M_DIV2 */
628 rootCfg.mux = kCLOCK_LPI2C4_ClockRoot_MuxOscRc48MDiv2;
629 rootCfg.div = 1;
630 CLOCK_SetRootClock(kCLOCK_Root_Lpi2c4, &rootCfg);
631
632 /* Configure LPI2C5 using OSC_RC_48M_DIV2 */
633 rootCfg.mux = kCLOCK_LPI2C5_ClockRoot_MuxOscRc48MDiv2;
634 rootCfg.div = 1;
635 CLOCK_SetRootClock(kCLOCK_Root_Lpi2c5, &rootCfg);
636
637 /* Configure LPI2C6 using OSC_RC_48M_DIV2 */
638 rootCfg.mux = kCLOCK_LPI2C6_ClockRoot_MuxOscRc48MDiv2;
639 rootCfg.div = 1;
640 CLOCK_SetRootClock(kCLOCK_Root_Lpi2c6, &rootCfg);
641
642 /* Configure LPSPI1 using OSC_RC_48M_DIV2 */
643 rootCfg.mux = kCLOCK_LPSPI1_ClockRoot_MuxOscRc48MDiv2;
644 rootCfg.div = 1;
645 CLOCK_SetRootClock(kCLOCK_Root_Lpspi1, &rootCfg);
646
647 /* Configure LPSPI2 using OSC_RC_48M_DIV2 */
648 rootCfg.mux = kCLOCK_LPSPI2_ClockRoot_MuxOscRc48MDiv2;
649 rootCfg.div = 1;
650 CLOCK_SetRootClock(kCLOCK_Root_Lpspi2, &rootCfg);
651
652 /* Configure LPSPI3 using OSC_RC_48M_DIV2 */
653 rootCfg.mux = kCLOCK_LPSPI3_ClockRoot_MuxOscRc48MDiv2;
654 rootCfg.div = 1;
655 CLOCK_SetRootClock(kCLOCK_Root_Lpspi3, &rootCfg);
656
657 /* Configure LPSPI4 using OSC_RC_48M_DIV2 */
658 rootCfg.mux = kCLOCK_LPSPI4_ClockRoot_MuxOscRc48MDiv2;
659 rootCfg.div = 1;
660 CLOCK_SetRootClock(kCLOCK_Root_Lpspi4, &rootCfg);
661
662 /* Configure LPSPI5 using OSC_RC_48M_DIV2 */
663 rootCfg.mux = kCLOCK_LPSPI5_ClockRoot_MuxOscRc48MDiv2;
664 rootCfg.div = 1;
665 CLOCK_SetRootClock(kCLOCK_Root_Lpspi5, &rootCfg);
666
667 /* Configure LPSPI6 using OSC_RC_48M_DIV2 */
668 rootCfg.mux = kCLOCK_LPSPI6_ClockRoot_MuxOscRc48MDiv2;
669 rootCfg.div = 1;
670 CLOCK_SetRootClock(kCLOCK_Root_Lpspi6, &rootCfg);
671
672 /* Configure EMV1 using OSC_RC_48M_DIV2 */
673 rootCfg.mux = kCLOCK_EMV1_ClockRoot_MuxOscRc48MDiv2;
674 rootCfg.div = 1;
675 CLOCK_SetRootClock(kCLOCK_Root_Emv1, &rootCfg);
676
677 /* Configure EMV2 using OSC_RC_48M_DIV2 */
678 rootCfg.mux = kCLOCK_EMV2_ClockRoot_MuxOscRc48MDiv2;
679 rootCfg.div = 1;
680 CLOCK_SetRootClock(kCLOCK_Root_Emv2, &rootCfg);
681
682 /* Configure ENET1 using OSC_RC_48M_DIV2 */
683 rootCfg.mux = kCLOCK_ENET1_ClockRoot_MuxOscRc48MDiv2;
684 rootCfg.div = 1;
685 CLOCK_SetRootClock(kCLOCK_Root_Enet1, &rootCfg);
686
687 /* Configure ENET2 using OSC_RC_48M_DIV2 */
688 rootCfg.mux = kCLOCK_ENET2_ClockRoot_MuxOscRc48MDiv2;
689 rootCfg.div = 1;
690 CLOCK_SetRootClock(kCLOCK_Root_Enet2, &rootCfg);
691
692 /* Configure ENET_QOS using OSC_RC_48M_DIV2 */
693 rootCfg.mux = kCLOCK_ENET_QOS_ClockRoot_MuxOscRc48MDiv2;
694 rootCfg.div = 1;
695 CLOCK_SetRootClock(kCLOCK_Root_Enet_Qos, &rootCfg);
696
697 /* Configure ENET_25M using OSC_RC_48M_DIV2 */
698 rootCfg.mux = kCLOCK_ENET_25M_ClockRoot_MuxOscRc48MDiv2;
699 rootCfg.div = 1;
700 CLOCK_SetRootClock(kCLOCK_Root_Enet_25m, &rootCfg);
701
702 /* Configure ENET_TIMER1 using OSC_RC_48M_DIV2 */
703 rootCfg.mux = kCLOCK_ENET_TIMER1_ClockRoot_MuxOscRc48MDiv2;
704 rootCfg.div = 1;
705 CLOCK_SetRootClock(kCLOCK_Root_Enet_Timer1, &rootCfg);
706
707 /* Configure ENET_TIMER2 using OSC_RC_48M_DIV2 */
708 rootCfg.mux = kCLOCK_ENET_TIMER2_ClockRoot_MuxOscRc48MDiv2;
709 rootCfg.div = 1;
710 CLOCK_SetRootClock(kCLOCK_Root_Enet_Timer2, &rootCfg);
711
712 /* Configure ENET_TIMER3 using OSC_RC_48M_DIV2 */
713 rootCfg.mux = kCLOCK_ENET_TIMER3_ClockRoot_MuxOscRc48MDiv2;
714 rootCfg.div = 1;
715 CLOCK_SetRootClock(kCLOCK_Root_Enet_Timer3, &rootCfg);
716
717 /* Configure USDHC1 using OSC_RC_48M_DIV2 */
718 rootCfg.mux = kCLOCK_USDHC1_ClockRoot_MuxOscRc48MDiv2;
719 rootCfg.div = 1;
720 CLOCK_SetRootClock(kCLOCK_Root_Usdhc1, &rootCfg);
721
722 /* Configure USDHC2 using OSC_RC_48M_DIV2 */
723 rootCfg.mux = kCLOCK_USDHC2_ClockRoot_MuxOscRc48MDiv2;
724 rootCfg.div = 1;
725 CLOCK_SetRootClock(kCLOCK_Root_Usdhc2, &rootCfg);
726
727 /* Configure ASRC using OSC_RC_48M_DIV2 */
728 rootCfg.mux = kCLOCK_ASRC_ClockRoot_MuxOscRc48MDiv2;
729 rootCfg.div = 1;
730 CLOCK_SetRootClock(kCLOCK_Root_Asrc, &rootCfg);
731
732 /* Configure MQS using OSC_RC_48M_DIV2 */
733 rootCfg.mux = kCLOCK_MQS_ClockRoot_MuxOscRc48MDiv2;
734 rootCfg.div = 1;
735 CLOCK_SetRootClock(kCLOCK_Root_Mqs, &rootCfg);
736
737 /* Configure MIC using OSC_RC_48M_DIV2 */
738 rootCfg.mux = kCLOCK_MIC_ClockRoot_MuxOscRc48MDiv2;
739 rootCfg.div = 1;
740 CLOCK_SetRootClock(kCLOCK_Root_Mic, &rootCfg);
741
742 /* Configure SPDIF using OSC_RC_48M_DIV2 */
743 rootCfg.mux = kCLOCK_SPDIF_ClockRoot_MuxOscRc48MDiv2;
744 rootCfg.div = 1;
745 CLOCK_SetRootClock(kCLOCK_Root_Spdif, &rootCfg);
746
747 /* Configure SAI1 using OSC_RC_48M_DIV2 */
748 rootCfg.mux = kCLOCK_SAI1_ClockRoot_MuxOscRc48MDiv2;
749 rootCfg.div = 1;
750 CLOCK_SetRootClock(kCLOCK_Root_Sai1, &rootCfg);
751
752 /* Configure SAI2 using OSC_RC_48M_DIV2 */
753 rootCfg.mux = kCLOCK_SAI2_ClockRoot_MuxOscRc48MDiv2;
754 rootCfg.div = 1;
755 CLOCK_SetRootClock(kCLOCK_Root_Sai2, &rootCfg);
756
757 /* Configure SAI3 using OSC_RC_48M_DIV2 */
758 rootCfg.mux = kCLOCK_SAI3_ClockRoot_MuxOscRc48MDiv2;
759 rootCfg.div = 1;
760 CLOCK_SetRootClock(kCLOCK_Root_Sai3, &rootCfg);
761
762 /* Configure SAI4 using OSC_RC_48M_DIV2 */
763 rootCfg.mux = kCLOCK_SAI4_ClockRoot_MuxOscRc48MDiv2;
764 rootCfg.div = 1;
765 CLOCK_SetRootClock(kCLOCK_Root_Sai4, &rootCfg);
766
767 /* Configure GC355 using OSC_RC_48M_DIV2 */
768 rootCfg.mux = kCLOCK_GC355_ClockRoot_MuxOscRc48MDiv2;
769 rootCfg.div = 1;
770 CLOCK_SetRootClock(kCLOCK_Root_Gc355, &rootCfg);
771
772 /* Configure LCDIF using OSC_RC_48M_DIV2 */
773 rootCfg.mux = kCLOCK_LCDIF_ClockRoot_MuxOscRc48MDiv2;
774 rootCfg.div = 1;
775 CLOCK_SetRootClock(kCLOCK_Root_Lcdif, &rootCfg);
776
777 /* Configure LCDIFV2 using OSC_RC_48M_DIV2 */
778 rootCfg.mux = kCLOCK_LCDIFV2_ClockRoot_MuxOscRc48MDiv2;
779 rootCfg.div = 1;
780 CLOCK_SetRootClock(kCLOCK_Root_Lcdifv2, &rootCfg);
781
782 /* Configure MIPI_REF using OSC_RC_48M_DIV2 */
783 rootCfg.mux = kCLOCK_MIPI_REF_ClockRoot_MuxOscRc48MDiv2;
784 rootCfg.div = 1;
785 CLOCK_SetRootClock(kCLOCK_Root_Mipi_Ref, &rootCfg);
786
787 /* Configure MIPI_ESC using OSC_RC_48M_DIV2 */
788 rootCfg.mux = kCLOCK_MIPI_ESC_ClockRoot_MuxOscRc48MDiv2;
789 rootCfg.div = 1;
790 CLOCK_SetRootClock(kCLOCK_Root_Mipi_Esc, &rootCfg);
791
792 /* Configure CSI2 using OSC_RC_48M_DIV2 */
793 rootCfg.mux = kCLOCK_CSI2_ClockRoot_MuxOscRc48MDiv2;
794 rootCfg.div = 1;
795 CLOCK_SetRootClock(kCLOCK_Root_Csi2, &rootCfg);
796
797 /* Configure CSI2_ESC using OSC_RC_48M_DIV2 */
798 rootCfg.mux = kCLOCK_CSI2_ESC_ClockRoot_MuxOscRc48MDiv2;
799 rootCfg.div = 1;
800 CLOCK_SetRootClock(kCLOCK_Root_Csi2_Esc, &rootCfg);
801
802 /* Configure CSI2_UI using OSC_RC_48M_DIV2 */
803 rootCfg.mux = kCLOCK_CSI2_UI_ClockRoot_MuxOscRc48MDiv2;
804 rootCfg.div = 1;
805 CLOCK_SetRootClock(kCLOCK_Root_Csi2_Ui, &rootCfg);
806
807 /* Configure CSI using OSC_RC_48M_DIV2 */
808 rootCfg.mux = kCLOCK_CSI_ClockRoot_MuxOscRc48MDiv2;
809 rootCfg.div = 1;
810 CLOCK_SetRootClock(kCLOCK_Root_Csi, &rootCfg);
811
812 /* Configure CKO1 using OSC_RC_48M_DIV2 */
813 rootCfg.mux = kCLOCK_CKO1_ClockRoot_MuxOscRc48MDiv2;
814 rootCfg.div = 1;
815 CLOCK_SetRootClock(kCLOCK_Root_Cko1, &rootCfg);
816
817 /* Configure CKO2 using OSC_RC_48M_DIV2 */
818 rootCfg.mux = kCLOCK_CKO2_ClockRoot_MuxOscRc48MDiv2;
819 rootCfg.div = 1;
820 CLOCK_SetRootClock(kCLOCK_Root_Cko2, &rootCfg);
821
822 /* Set SAI1 MCLK1 clock source. */
823 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
824 /* Set SAI1 MCLK2 clock source. */
825 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 3);
826 /* Set SAI1 MCLK3 clock source. */
827 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
828 /* Set SAI2 MCLK3 clock source. */
829 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
830 /* Set SAI3 MCLK3 clock source. */
831 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
832
833 /* Set MQS configuration. */
834 IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
835 /* Set ENET Ref clock source. */
836 IOMUXC_GPR->GPR4 &= ~IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_MASK;
837 /* Set ENET_1G Tx clock source. */
838 IOMUXC_GPR->GPR5 = ((IOMUXC_GPR->GPR5 & ~IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_MASK) | IOMUXC_GPR_GPR5_ENET1G_RGMII_EN_MASK);
839 /* Set ENET_1G Ref clock source. */
840 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_MASK;
841 /* Set ENET_QOS Tx clock source. */
842 IOMUXC_GPR->GPR6 &= ~IOMUXC_GPR_GPR6_ENET_QOS_RGMII_EN_MASK;
843 /* Set ENET_QOS Ref clock source. */
844 IOMUXC_GPR->GPR6 &= ~IOMUXC_GPR_GPR6_ENET_QOS_REF_CLK_DIR_MASK;
845 /* Set GPT1 High frequency reference clock source. */
846 IOMUXC_GPR->GPR22 &= ~IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1_MASK;
847 /* Set GPT2 High frequency reference clock source. */
848 IOMUXC_GPR->GPR23 &= ~IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2_MASK;
849 /* Set GPT3 High frequency reference clock source. */
850 IOMUXC_GPR->GPR24 &= ~IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3_MASK;
851 /* Set GPT4 High frequency reference clock source. */
852 IOMUXC_GPR->GPR25 &= ~IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4_MASK;
853 /* Set GPT5 High frequency reference clock source. */
854 IOMUXC_GPR->GPR26 &= ~IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5_MASK;
855 /* Set GPT6 High frequency reference clock source. */
856 IOMUXC_GPR->GPR27 &= ~IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6_MASK;
857
858 #if __CORTEX_M == 7
859 SystemCoreClock = CLOCK_GetRootClockFreq(kCLOCK_Root_M7);
860 #else
861 SystemCoreClock = CLOCK_GetRootClockFreq(kCLOCK_Root_M4);
862 #endif
863 }
864
