1 /*
2 * Copyright 2018-2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include "fsl_common.h"
9 #include "fsl_debug_console.h"
10 #include "board.h"
11 #if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
12 #include "fsl_lpi2c.h"
13 #endif /* SDK_I2C_BASED_COMPONENT_USED */
14 #include "fsl_iomuxc.h"
15
16 /*******************************************************************************
17 * Variables
18 ******************************************************************************/
19 /*******************************************************************************
20 * Code
21 ******************************************************************************/
22
23 /* Get debug console frequency. */
BOARD_DebugConsoleSrcFreq(void)24 uint32_t BOARD_DebugConsoleSrcFreq(void)
25 {
26 #if DEBUG_CONSOLE_UART_INDEX == 1
27 return CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart1);
28 #elif DEBUG_CONSOLE_UART_INDEX == 12
29 return CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart12);
30 #else
31 return CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart2);
32 #endif
33 }
34
35 /* Initialize debug console. */
BOARD_InitDebugConsole(void)36 void BOARD_InitDebugConsole(void)
37 {
38 uint32_t uartClkSrcFreq = BOARD_DebugConsoleSrcFreq();
39 DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
40 }
41
42 #if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
BOARD_LPI2C_Init(LPI2C_Type * base,uint32_t clkSrc_Hz)43 void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz)
44 {
45 lpi2c_master_config_t lpi2cConfig = {0};
46
47 /*
48 * lpi2cConfig.debugEnable = false;
49 * lpi2cConfig.ignoreAck = false;
50 * lpi2cConfig.pinConfig = kLPI2C_2PinOpenDrain;
51 * lpi2cConfig.baudRate_Hz = 100000U;
52 * lpi2cConfig.busIdleTimeout_ns = 0;
53 * lpi2cConfig.pinLowTimeout_ns = 0;
54 * lpi2cConfig.sdaGlitchFilterWidth_ns = 0;
55 * lpi2cConfig.sclGlitchFilterWidth_ns = 0;
56 */
57 LPI2C_MasterGetDefaultConfig(&lpi2cConfig);
58 LPI2C_MasterInit(base, &lpi2cConfig, clkSrc_Hz);
59 }
60
BOARD_LPI2C_Send(LPI2C_Type * base,uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,uint8_t * txBuff,uint8_t txBuffSize)61 status_t BOARD_LPI2C_Send(LPI2C_Type *base,
62 uint8_t deviceAddress,
63 uint32_t subAddress,
64 uint8_t subAddressSize,
65 uint8_t *txBuff,
66 uint8_t txBuffSize)
67 {
68 lpi2c_master_transfer_t xfer;
69
70 xfer.flags = kLPI2C_TransferDefaultFlag;
71 xfer.slaveAddress = deviceAddress;
72 xfer.direction = kLPI2C_Write;
73 xfer.subaddress = subAddress;
74 xfer.subaddressSize = subAddressSize;
75 xfer.data = txBuff;
76 xfer.dataSize = txBuffSize;
77
78 return LPI2C_MasterTransferBlocking(base, &xfer);
79 }
80
BOARD_LPI2C_Receive(LPI2C_Type * base,uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,uint8_t * rxBuff,uint8_t rxBuffSize)81 status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
82 uint8_t deviceAddress,
83 uint32_t subAddress,
84 uint8_t subAddressSize,
85 uint8_t *rxBuff,
86 uint8_t rxBuffSize)
87 {
88 lpi2c_master_transfer_t xfer;
89
90 xfer.flags = kLPI2C_TransferDefaultFlag;
91 xfer.slaveAddress = deviceAddress;
92 xfer.direction = kLPI2C_Read;
93 xfer.subaddress = subAddress;
94 xfer.subaddressSize = subAddressSize;
95 xfer.data = rxBuff;
96 xfer.dataSize = rxBuffSize;
97
98 return LPI2C_MasterTransferBlocking(base, &xfer);
99 }
100
BOARD_LPI2C_SendSCCB(LPI2C_Type * base,uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,uint8_t * txBuff,uint8_t txBuffSize)101 status_t BOARD_LPI2C_SendSCCB(LPI2C_Type *base,
102 uint8_t deviceAddress,
103 uint32_t subAddress,
104 uint8_t subAddressSize,
105 uint8_t *txBuff,
106 uint8_t txBuffSize)
107 {
108 lpi2c_master_transfer_t xfer;
109
110 xfer.flags = kLPI2C_TransferDefaultFlag;
111 xfer.slaveAddress = deviceAddress;
112 xfer.direction = kLPI2C_Write;
113 xfer.subaddress = subAddress;
114 xfer.subaddressSize = subAddressSize;
115 xfer.data = txBuff;
116 xfer.dataSize = txBuffSize;
117
118 return LPI2C_MasterTransferBlocking(base, &xfer);
119 }
120
BOARD_LPI2C_ReceiveSCCB(LPI2C_Type * base,uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,uint8_t * rxBuff,uint8_t rxBuffSize)121 status_t BOARD_LPI2C_ReceiveSCCB(LPI2C_Type *base,
122 uint8_t deviceAddress,
123 uint32_t subAddress,
124 uint8_t subAddressSize,
125 uint8_t *rxBuff,
126 uint8_t rxBuffSize)
127 {
128 status_t status;
129 lpi2c_master_transfer_t xfer;
130
131 xfer.flags = kLPI2C_TransferDefaultFlag;
132 xfer.slaveAddress = deviceAddress;
133 xfer.direction = kLPI2C_Write;
134 xfer.subaddress = subAddress;
135 xfer.subaddressSize = subAddressSize;
136 xfer.data = NULL;
137 xfer.dataSize = 0;
138
139 status = LPI2C_MasterTransferBlocking(base, &xfer);
140
141 if (kStatus_Success == status)
142 {
143 xfer.subaddressSize = 0;
144 xfer.direction = kLPI2C_Read;
145 xfer.data = rxBuff;
146 xfer.dataSize = rxBuffSize;
147
148 status = LPI2C_MasterTransferBlocking(base, &xfer);
149 }
150
151 return status;
152 }
153
BOARD_Accel_I2C_Init(void)154 void BOARD_Accel_I2C_Init(void)
155 {
156 BOARD_LPI2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
157 }
158
BOARD_Accel_I2C_Send(uint8_t deviceAddress,uint32_t subAddress,uint8_t subaddressSize,uint32_t txBuff)159 status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)
160 {
161 uint8_t data = (uint8_t)txBuff;
162
163 return BOARD_LPI2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);
164 }
165
BOARD_Accel_I2C_Receive(uint8_t deviceAddress,uint32_t subAddress,uint8_t subaddressSize,uint8_t * rxBuff,uint8_t rxBuffSize)166 status_t BOARD_Accel_I2C_Receive(
167 uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
168 {
169 return BOARD_LPI2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);
170 }
171
BOARD_Codec_I2C_Init(void)172 void BOARD_Codec_I2C_Init(void)
173 {
174 BOARD_LPI2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
175 }
176
BOARD_Codec_I2C_Send(uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,const uint8_t * txBuff,uint8_t txBuffSize)177 status_t BOARD_Codec_I2C_Send(
178 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
179 {
180 return BOARD_LPI2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
181 txBuffSize);
182 }
183
BOARD_Codec_I2C_Receive(uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,uint8_t * rxBuff,uint8_t rxBuffSize)184 status_t BOARD_Codec_I2C_Receive(
185 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
186 {
187 return BOARD_LPI2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
188 }
189
BOARD_Camera_I2C_Init(void)190 void BOARD_Camera_I2C_Init(void)
191 {
192 const clock_root_config_t lpi2cClockConfig = {
193 .clockOff = false,
194 .mux = BOARD_CAMERA_I2C_CLOCK_SOURCE,
195 .div = BOARD_CAMERA_I2C_CLOCK_DIVIDER,
196 };
197
198 CLOCK_SetRootClock(BOARD_CAMERA_I2C_CLOCK_ROOT, &lpi2cClockConfig);
199
200 BOARD_LPI2C_Init(BOARD_CAMERA_I2C_BASEADDR, CLOCK_GetRootClockFreq(BOARD_CAMERA_I2C_CLOCK_ROOT));
201 }
202
BOARD_Camera_I2C_Send(uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,const uint8_t * txBuff,uint8_t txBuffSize)203 status_t BOARD_Camera_I2C_Send(
204 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
205 {
206 return BOARD_LPI2C_Send(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
207 txBuffSize);
208 }
209
BOARD_Camera_I2C_Receive(uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,uint8_t * rxBuff,uint8_t rxBuffSize)210 status_t BOARD_Camera_I2C_Receive(
211 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
212 {
213 return BOARD_LPI2C_Receive(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff,
214 rxBuffSize);
215 }
216
BOARD_Camera_I2C_SendSCCB(uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,const uint8_t * txBuff,uint8_t txBuffSize)217 status_t BOARD_Camera_I2C_SendSCCB(
218 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
219 {
220 return BOARD_LPI2C_SendSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
221 txBuffSize);
222 }
223
BOARD_Camera_I2C_ReceiveSCCB(uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,uint8_t * rxBuff,uint8_t rxBuffSize)224 status_t BOARD_Camera_I2C_ReceiveSCCB(
225 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
226 {
227 return BOARD_LPI2C_ReceiveSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff,
228 rxBuffSize);
229 }
230
BOARD_MIPIPanelTouch_I2C_Init(void)231 void BOARD_MIPIPanelTouch_I2C_Init(void)
232 {
233 const clock_root_config_t lpi2cClockConfig = {
234 .clockOff = false,
235 .mux = BOARD_MIPI_PANEL_TOUCH_I2C_CLOCK_SOURCE,
236 .div = BOARD_MIPI_PANEL_TOUCH_I2C_CLOCK_DIVIDER,
237 };
238
239 CLOCK_SetRootClock(BOARD_MIPI_PANEL_TOUCH_I2C_CLOCK_ROOT, &lpi2cClockConfig);
240
241 BOARD_LPI2C_Init(BOARD_MIPI_PANEL_TOUCH_I2C_BASEADDR,
242 CLOCK_GetRootClockFreq(BOARD_MIPI_PANEL_TOUCH_I2C_CLOCK_ROOT));
243 }
244
BOARD_MIPIPanelTouch_I2C_Send(uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,const uint8_t * txBuff,uint8_t txBuffSize)245 status_t BOARD_MIPIPanelTouch_I2C_Send(
246 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
247 {
248 return BOARD_LPI2C_Send(BOARD_MIPI_PANEL_TOUCH_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize,
249 (uint8_t *)txBuff, txBuffSize);
250 }
251
BOARD_MIPIPanelTouch_I2C_Receive(uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,uint8_t * rxBuff,uint8_t rxBuffSize)252 status_t BOARD_MIPIPanelTouch_I2C_Receive(
253 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
254 {
255 return BOARD_LPI2C_Receive(BOARD_MIPI_PANEL_TOUCH_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff,
256 rxBuffSize);
257 }
258 #endif /* SDK_I2C_BASED_COMPONENT_USED */
259
260 /* MPU configuration. */
261 #if __CORTEX_M == 7
BOARD_ConfigMPU(void)262 void BOARD_ConfigMPU(void)
263 {
264 #if defined(__ICACHE_PRESENT) && __ICACHE_PRESENT
265 /* Disable I cache and D cache */
266 if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR))
267 {
268 SCB_DisableICache();
269 }
270 #endif
271 #if defined(__DCACHE_PRESENT) && __DCACHE_PRESENT
272 if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR))
273 {
274 SCB_DisableDCache();
275 }
276 #endif
277
278 /* Disable MPU */
279 ARM_MPU_Disable();
280
281 /* MPU configure:
282 * Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable,
283 * SubRegionDisable, Size)
284 * API in mpu_armv7.h.
285 * param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches
286 * disabled.
287 * param AccessPermission Data access permissions, allows you to configure read/write access for User and
288 * Privileged mode.
289 * Use MACROS defined in mpu_armv7.h:
290 * ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
291 * Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes.
292 * TypeExtField IsShareable IsCacheable IsBufferable Memory Attribute Shareability Cache
293 * 0 x 0 0 Strongly Ordered shareable
294 * 0 x 0 1 Device shareable
295 * 0 0 1 0 Normal not shareable Outer and inner write
296 * through no write allocate
297 * 0 0 1 1 Normal not shareable Outer and inner write
298 * back no write allocate
299 * 0 1 1 0 Normal shareable Outer and inner write
300 * through no write allocate
301 * 0 1 1 1 Normal shareable Outer and inner write
302 * back no write allocate
303 * 1 0 0 0 Normal not shareable outer and inner
304 * noncache
305 * 1 1 0 0 Normal shareable outer and inner
306 * noncache
307 * 1 0 1 1 Normal not shareable outer and inner write
308 * back write/read acllocate
309 * 1 1 1 1 Normal shareable outer and inner write
310 * back write/read acllocate
311 * 2 x 0 0 Device not shareable
312 * Above are normal use settings, if your want to see more details or want to config different inner/outter cache
313 * policy.
314 * please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide <dui0646b_cortex_m7_dgug.pdf>
315 * param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled.
316 * param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in
317 * mpu_armv7.h.
318 */
319
320 /*
321 * Add default region to deny access to whole address space to workaround speculative prefetch.
322 * Refer to Arm errata 1013783-B for more details.
323 *
324 */
325 /* Region 0 setting: Instruction access disabled, No data access permission. */
326 MPU->RBAR = ARM_MPU_RBAR(0, 0x00000000U);
327 MPU->RASR = ARM_MPU_RASR(1, ARM_MPU_AP_NONE, 0, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4GB);
328
329 /* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */
330 MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
331 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
332
333 /* Region 2 setting: Memory with Device type, not shareable, non-cacheable. */
334 MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
335 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
336
337 /* Region 3 setting: Memory with Device type, not shareable, non-cacheable. */
338 MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U);
339 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
340
341 /* Region 4 setting: Memory with Normal type, not shareable, outer/inner write back */
342 MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
343 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
344
345 /* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */
346 MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U);
347 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
348
349 /* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */
350 MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U);
351 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_1MB);
352
353 /* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */
354 MPU->RBAR = ARM_MPU_RBAR(7, 0x20300000U);
355 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_512KB);
356
357 #if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
358 /* Region 8 setting: Memory with Normal type, not shareable, outer/inner write back. */
359 MPU->RBAR = ARM_MPU_RBAR(8, 0x30000000U);
360 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_16MB);
361 #endif
362
363 #ifdef USE_SDRAM
364 /* Region 9 setting: Memory with Normal type, not shareable, outer/inner write back */
365 MPU->RBAR = ARM_MPU_RBAR(9, 0x80000000U);
366 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64MB);
367 #endif
368
369 /* Region 11 setting: Memory with Device type, not shareable, non-cacheable */
370 MPU->RBAR = ARM_MPU_RBAR(11, 0x40000000);
371 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_16MB);
372
373 /* Region 12 setting: Memory with Device type, not shareable, non-cacheable */
374 MPU->RBAR = ARM_MPU_RBAR(12, 0x41000000);
375 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB);
376
377 /* Region 13 setting: Memory with Device type, not shareable, non-cacheable */
378 MPU->RBAR = ARM_MPU_RBAR(13, 0x41400000);
379 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1MB);
380
381 /* Region 14 setting: Memory with Device type, not shareable, non-cacheable */
382 MPU->RBAR = ARM_MPU_RBAR(14, 0x41800000);
383 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB);
384
385 /* Region 15 setting: Memory with Device type, not shareable, non-cacheable */
386 MPU->RBAR = ARM_MPU_RBAR(15, 0x42000000);
387 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1MB);
388
389 /* Enable MPU */
390 ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
391
392 /* Enable I cache and D cache */
393 #if defined(__DCACHE_PRESENT) && __DCACHE_PRESENT
394 SCB_EnableDCache();
395 #endif
396 #if defined(__ICACHE_PRESENT) && __ICACHE_PRESENT
397 SCB_EnableICache();
398 #endif
399 }
400 #elif __CORTEX_M == 4
BOARD_ConfigMPU(void)401 void BOARD_ConfigMPU(void)
402 {
403 }
404 #endif
405
BOARD_SD_Pin_Config(uint32_t speed,uint32_t strength)406 void BOARD_SD_Pin_Config(uint32_t speed, uint32_t strength)
407 {
408 }
409
BOARD_MMC_Pin_Config(uint32_t speed,uint32_t strength)410 void BOARD_MMC_Pin_Config(uint32_t speed, uint32_t strength)
411 {
412 }
413
