1 /*
2  * Copyright 2020-2023 NXP
3  * All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 #ifndef _FSL_PMU_H_
9 #define _FSL_PMU_H_
10 
11 #include "fsl_common.h"
12 
13 /*!
14  * @addtogroup pmu
15  * @{
16  */
17 
18 /*******************************************************************************
19  * Definitions
20  ******************************************************************************/
21 
22 /*! @name Driver version
23  * @{
24  */
25 
26 /*! @brief PMU driver version */
27 #define FSL_PMU_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) /*!< Version 2.1.1. */
28 
29 /*!
30  * @}
31  */
32 
33 #if defined(ANADIG_PMU_PMU_BIAS_CTRL2_FBB_M7_CONTROL_MODE_MASK)
34 #define PMU_HAS_FBB (1U)
35 #else
36 #define PMU_HAS_FBB (0U)
37 #endif /* ANADIG_PMU_PMU_BIAS_CTRL2_FBB_M7_CONTROL_MODE_MASK */
38 
39 /*!
40  * @brief System setpoints enumeration.
41  */
42 enum _pmu_setpoint_map
43 {
44     kPMU_SetPoint0  = 1UL << 0UL,  /*!< Set point 0. */
45     kPMU_SetPoint1  = 1UL << 1UL,  /*!< Set point 1. */
46     kPMU_SetPoint2  = 1UL << 2UL,  /*!< Set point 2. */
47     kPMU_SetPoint3  = 1UL << 3UL,  /*!< Set point 3. */
48     kPMU_SetPoint4  = 1UL << 4UL,  /*!< Set point 4. */
49     kPMU_SetPoint5  = 1UL << 5UL,  /*!< Set point 5. */
50     kPMU_SetPoint6  = 1UL << 6UL,  /*!< Set point 6. */
51     kPMU_SetPoint7  = 1UL << 7UL,  /*!< Set point 7. */
52     kPMU_SetPoint8  = 1UL << 8UL,  /*!< Set point 8. */
53     kPMU_SetPoint9  = 1UL << 9UL,  /*!< Set point 9. */
54     kPMU_SetPoint10 = 1UL << 10UL, /*!< Set point 10. */
55     kPMU_SetPoint11 = 1UL << 11UL, /*!< Set point 11. */
56     kPMU_SetPoint12 = 1UL << 12UL, /*!< Set point 12. */
57     kPMU_SetPoint13 = 1UL << 13UL, /*!< Set point 13. */
58     kPMU_SetPoint14 = 1UL << 14UL, /*!< Set point 14. */
59     kPMU_SetPoint15 = 1UL << 15UL  /*!< Set point 15. */
60 };
61 
62 /*!
63  * @brief The name of LDOs
64  */
65 typedef enum _pmu_ldo_name
66 {
67     kPMU_PllLdo     = 0U, /*!< The PLL LDO in SOC domain. */
68     kPMU_LpsrAnaLdo = 1U, /*!< The LPSR ANA LDO in LPSR domain. */
69     kPMU_LpsrDigLdo = 2U, /*!< The LPSR DIG LDO in LPSR domain. */
70     kPMU_SnvsDigLdo = 3U  /*!< The SNVS DIG LDO in SNVS domain. */
71 } pmu_ldo_name_t;
72 
73 /*!
74  * @brief The name of body bias.
75  */
76 typedef enum _pmu_body_bias_name
77 {
78 #if (defined(PMU_HAS_FBB) && PMU_HAS_FBB)
79     kPMU_FBB_CM7  = 0x0U, /*!< The FBB implemented in Cortex-M7 Platform. */
80     kPMU_RBB_SOC  = 0x1U, /*!< The RBB implemented in SOC. */
81     kPMU_RBB_LPSR = 0x2U, /*!< The RBB implemented in LPSRMIX. */
82 #else
83     kPMU_RBB_SOC  = 0x0U, /*!< The RBB implemented in SOC. */
84     kPMU_RBB_LPSR = 0x1U, /*!< The RBB implemented in LPSRMIX. */
85 #endif /* PMU_HAS_FBB */
86 } pmu_body_bias_name_t;
87 
88 /*!
89  * @brief The control mode of LDOs/Bandgaps/Body Bias.
90  */
91 typedef enum _pmu_control_mode
92 {
93     kPMU_StaticMode = 0U, /*!< Static/Software Control mode. */
94     kPMU_GPCMode    = 1U, /*!< GPC/Hardware Control mode. */
95 } pmu_control_mode_t;
96 
97 /*!
98  * @brief The operation mode for the LDOs.
99  */
100 typedef enum _pmu_ldo_operate_mode
101 {
102     kPMU_LowPowerMode  = 0x0U, /*!< LDOs operate in Low power mode. */
103     kPMU_HighPowerMode = 0x1U, /*!< LDOs operate in High power mode. */
104 } pmu_ldo_operate_mode_t;
105 
106 /*!
107  * @brief The enumeration of LPSR ANA LDO's charge pump current.
108  */
109 typedef enum _pmu_lpsr_ana_ldo_charge_pump_current
110 {
111     kPMU_LpsrAnaChargePump300nA = 0U, /*!< The current of the charge pump is selected as 300nA. */
112     kPMU_LpsrAnaChargePump400nA = 1U, /*!< The current of the charge pump is selected as 400nA. */
113     kPMU_LpsrAnaChargePump500nA = 2U, /*!< The current of the charge pump is selected as 500nA. */
114     kPMU_LpsrAnaChargePump600nA = 3U, /*!< The current of the charge pump is selected as 600nA. */
115 } pmu_lpsr_ana_ldo_charge_pump_current_t;
116 
117 /*!
118  * @brief The enumeration of LPSR ANA LDO's output range.
119  */
120 typedef enum _pmu_lpsr_ana_ldo_output_range
121 {
122     kPMU_LpsrAnaLdoOutputFrom1P77To1P83 = 0U, /*!< The output voltage varies from 1.77V to 1.83V. */
123     kPMU_LpsrAnaLdoOutputFrom1P72To1P77 = 1U, /*!< The output voltage varies from 1.72V to 1.77V. */
124     kPMU_LpsrAnaLdoOutputFrom1P82To1P88 = 2U, /*!< The output voltage varies from 1.82V to 1.88V. */
125 } pmu_lpsr_ana_ldo_output_range_t;
126 
127 /*!
128  * @brief The enumeration of voltage step time for LPSR DIG LDO.
129  */
130 typedef enum _pmu_lpsr_dig_voltage_step_time
131 {
132     kPMU_LpsrDigVoltageStepInc15us  = 0x0U, /*!< LPSR DIG LDO voltage step time selected as 15us. */
133     kPMU_LpsrDigVoltageStepInc25us  = 0x1U, /*!< LPSR DIG LDO voltage step time selected as 25us. */
134     kPMU_LpsrDigVoltageStepInc50us  = 0x2U, /*!< LPSR DIG LDO voltage step time selected as 50us. */
135     kPMU_LpsrDigVoltageStepInc100us = 0x3U, /*!< LPSR DIG LDO voltage step time selected as 100us. */
136 } pmu_lpsr_dig_voltage_step_time_t;
137 
138 /*!
139  * @brief The target output voltage of LPSR DIG LDO.
140  */
141 typedef enum _pmu_lpsr_dig_target_output_voltage
142 {
143     kPMU_LpsrDigTargetStableVoltage0P631V = 0x0U,  /*!< The target voltage selected as 0.631V */
144     kPMU_LpsrDigTargetStableVoltage0P65V  = 0x1U,  /*!< The target voltage selected as 0.65V */
145     kPMU_LpsrDigTargetStableVoltage0P67V  = 0x2U,  /*!< The target voltage selected as 0.67V */
146     kPMU_LpsrDigTargetStableVoltage0P689V = 0x3U,  /*!< The target voltage selected as 0.689V */
147     kPMU_LpsrDigTargetStableVoltage0P709V = 0x4U,  /*!< The target voltage selected as 0.709V */
148     kPMU_LpsrDigTargetStableVoltage0P728V = 0x5U,  /*!< The target voltage selected as 0.728V */
149     kPMU_LpsrDigTargetStableVoltage0P748V = 0x6U,  /*!< The target voltage selected as 0.748V */
150     kPMU_LpsrDigTargetStableVoltage0P767V = 0x7U,  /*!< The target voltage selected as 0.767V */
151     kPMU_LpsrDigTargetStableVoltage0P786V = 0x8U,  /*!< The target voltage selected as 0.786V */
152     kPMU_LpsrDigTargetStableVoltage0P806V = 0x9U,  /*!< The target voltage selected as 0.806V */
153     kPMU_LpsrDigTargetStableVoltage0P825V = 0xAU,  /*!< The target voltage selected as 0.825V */
154     kPMU_LpsrDigTargetStableVoltage0P845V = 0xBU,  /*!< The target voltage selected as 0.845V */
155     kPMU_LpsrDigTargetStableVoltage0P864V = 0xCU,  /*!< The target voltage selected as 0.864V */
156     kPMU_LpsrDigTargetStableVoltage0P883V = 0xDU,  /*!< The target voltage selected as 0.883V */
157     kPMU_LpsrDigTargetStableVoltage0P903V = 0xEU,  /*!< The target voltage selected as 0.903V */
158     kPMU_LpsrDigTargetStableVoltage0P922V = 0xFU,  /*!< The target voltage selected as 0.922V */
159     kPMU_LpsrDigTargetStableVoltage0P942V = 0x10U, /*!< The target voltage selected as 0.942V */
160     kPMU_LpsrDigTargetStableVoltage0P961V = 0x11U, /*!< The target voltage selected as 0.961V */
161     kPMU_LpsrDigTargetStableVoltage0P981V = 0x12U, /*!< The target voltage selected as 0.981V */
162     kPMU_LpsrDigTargetStableVoltage1P0V   = 0x13U, /*!< The target voltage selected as 1.0V */
163     kPMU_LpsrDigTargetStableVoltage1P019V = 0x14U, /*!< The target voltage selected as 1.019V */
164     kPMU_LpsrDigTargetStableVoltage1P039V = 0x15U, /*!< The target voltage selected as 1.039V */
165     kPMU_LpsrDigTargetStableVoltage1P058V = 0x16U, /*!< The target voltage selected as 1.058V */
166     kPMU_LpsrDigTargetStableVoltage1P078V = 0x17U, /*!< The target voltage selected as 1.078V */
167     kPMU_LpsrDigTargetStableVoltage1P097V = 0x18U, /*!< The target voltage selected as 1.097V */
168     kPMU_LpsrDigTargetStableVoltage1P117V = 0x19U, /*!< The target voltage selected as 1.117V */
169     kPMU_LpsrDigTargetStableVoltage1P136V = 0x1AU, /*!< The target voltage selected as 1.136V */
170     kPMU_LpsrDigTargetStableVoltage1P155V = 0x1BU, /*!< The target voltage selected as 1.155V */
171     kPMU_LpsrDigTargetStableVoltage1P175V = 0x1CU, /*!< The target voltage selected as 1.175V */
172     kPMU_LpsrDigTargetStableVoltage1P194V = 0x1DU, /*!< The target voltage selected as 1.194V */
173     kPMU_LpsrDigTargetStableVoltage1P214V = 0x1EU, /*!< The target voltage selected as 1.214V */
174     kPMU_LpsrDigTargetStableVoltage1P233V = 0x1FU, /*!< The target voltage selected as 1.233V */
175 } pmu_lpsr_dig_target_output_voltage_t;
176 
177 /*!
178  * @brief The enumeration of the SNVS DIG LDO's charge pump current.
179  */
180 typedef enum _pmu_snvs_dig_charge_pump_current
181 {
182     kPMU_SnvsDigChargePump12P5nA  = 0U, /*!< The current of SNVS DIG LDO's charge pump is selected as 12.5nA. */
183     kPMU_SnvsDigChargePump6P25nA  = 1U, /*!< The current of SNVS DIG LDO's charge pump is selected as 6.25nA. */
184     kPMU_SnvsDigChargePump18P75nA = 2U, /*!< The current of SNVS DIG LDO's charge pump is selected as 18.75nA. */
185 } pmu_snvs_dig_charge_pump_current_t;
186 
187 /*!
188  * @brief The enumeration of the SNVS DIG LDO's discharge resistor.
189  */
190 typedef enum _pmu_snvs_dig_discharge_resistor_value
191 {
192     kPMU_SnvsDigDischargeResistor15K = 0U, /*!< The Discharge Resistor is selected as 15K ohm */
193     kPMU_SnvsDigDischargeResistor30K = 1U, /*!< The Discharge Resistor is selected as 30K ohm */
194     kPMU_SnvsDigDischargeResistor9K  = 2U, /*!< The Discharge Resistor is selected as 9K ohm */
195 } pmu_snvs_dig_discharge_resistor_value_t;
196 
197 /*!
198  * @brief The enumeration of bandgap power down option.
199  */
200 enum _pmu_static_bandgap_power_down_option
201 {
202     kPMU_PowerDownBandgapFully               = 1U << 0U, /*!< Fully power down the bandgap module. */
203     kPMU_PowerDownVoltageReferenceOutputOnly = 1U << 1U, /*!< Power down only the reference output
204                                                                 section of the bandgap */
205     kPMU_PowerDownBandgapVBGUPDetector = 1U << 2U,       /*!< Power down the VBGUP detector of the bandgap without
206                                                               affecting any additional functionality. */
207 };
208 
209 /*!
210  * @brief The enumeration of output VBG voltage.
211  */
212 typedef enum _pmu_bandgap_output_VBG_voltage_value
213 {
214     kPMU_BandgapOutputVBGVoltageNominal   = 0x0U, /*!< Output nominal voltage. */
215     kPMU_BandgapOutputVBGVoltagePlus10mV  = 0x1U, /*!< Output VBG voltage Plus 10mV. */
216     kPMU_BandgapOutputVBGVoltagePlus20mV  = 0x2U, /*!< Output VBG voltage Plus 20mV. */
217     kPMU_BandgapOutputVBGVoltagePlus30mV  = 0x3U, /*!< Output VBG voltage Plus 30mV. */
218     kPMU_BandgapOutputVBGVoltageMinus10mV = 0x4U, /*!< Output VBG voltage Minus 10mV. */
219     kPMU_BandgapOutputVBGVoltageMinus20mV = 0x5U, /*!< Output VBG voltage Minus 20mV. */
220     kPMU_BandgapOutputVBGVoltageMinus30mV = 0x6U, /*!< Output VBG voltage Minus 30mV. */
221     kPMU_BandgapOutputVBGVoltageMinus40mV = 0x7U, /*!< Output VBG voltage Minus 40mV. */
222 } pmu_bandgap_output_VBG_voltage_value_t;
223 
224 /*!
225  * @brief The enumeration of output current.
226  */
227 typedef enum _pmu_bandgap_output_current_value
228 {
229     kPMU_OutputCurrent11P5uA = 0x0U, /*!< Output 11.5uA current from the bandgap. */
230     kPMU_OutputCurrent11P8uA = 0x1U, /*!< Output 11.8uA current from the bandgap. */
231     kPMU_OutputCurrent12P1uA = 0x2U, /*!< Output 12.1uA current from the bandgap. */
232     kPMU_OutputCurrent12P4uA = 0x4U, /*!< Output 12.4uA current from the bandgap. */
233     kPMU_OutputCurrent12P7uA = 0x5U, /*!< Output 12.7uA current from the bandgap. */
234     kPMU_OutputCurrent13P0uA = 0x6U, /*!< Output 13.0uA current from the bandgap. */
235     kPMU_OutputCurrent13P3uA = 0x7U, /*!< Output 13.3uA current from the bandgap. */
236 } pmu_bandgap_output_current_value_t;
237 
238 /*!
239  * @brief The enumerator of well bias power source.
240  */
241 typedef enum _pmu_well_bias_power_source
242 {
243     kPMU_WellBiasPowerFromLpsrDigLdo = 0U, /*!< LPSR Dig LDO supplies the power stage and NWELL sampler. */
244     kPMU_WellBiasPowerFromDCDC,            /*!< DCDC supplies the power stage and NWELL sampler. */
245 } pmu_well_bias_power_source_t;
246 
247 /*!
248  * @brief The enumerator of bias area size.
249  */
250 typedef enum _pmu_bias_area_size
251 {
252     kPMU_180uA_6mm2At125C = 0U, /*!< Imax = 180uA; Areamax-RVT = 6.00mm2 at 125C */
253     kPMU_150uA_5mm2At125C,      /*!< Imax = 150uA; Areamax-RVT = 5.00mm2 at 125C */
254     kPMU_120uA_4mm2At125C,      /*!< Imax = 120uA; Areamax-RVT = 4.00mm2 at 125C */
255     kPMU_90uA_3mm2At125C,       /*!< Imax = 90uA; Areamax-RVT = 3.00mm2 at 125C */
256     kPMU_60uA_2mm2At125C,       /*!< Imax = 60uA; Areamax-RVT = 2.00mm2 at 125C */
257     kPMU_45uA_1P5mm2At125C,     /*!< Imax = 45uA; Areamax-RVT = 1P5mm2 at 125C */
258     kPMU_30uA_1mm2At125C,       /*!< Imax = 30uA; Areamax-RVT = 1.00mm2 at 125C */
259     kPMU_15uA_0P5mm2At125C,     /*!< Imax = 15uA; Areamax-RVT = 0.50mm2 at 125C */
260 } pmu_bias_area_size_t;
261 
262 /*!
263  * @brief The enumerator of well bias typical frequency.
264  */
265 typedef enum _pmu_well_bias_typical_freq
266 {
267     kPMU_OscFreqDiv128 = 0U, /*!< Typical frequency = osc_freq / 128. */
268     kPMU_OscFreqDiv64  = 1U, /*!< Typical frequency = osc_freq / 64. */
269     kPMU_OscFreqDiv32  = 2U, /*!< Typical frequency = osc_freq / 32. */
270     kPMU_OscFreqDiv16  = 3U, /*!< Typical frequency = osc_freq / 16. */
271     kPMU_OscFreqDiv8   = 4U, /*!< Typical frequency = osc_freq / 8. */
272     kPMU_OscFreqDiv2   = 6U, /*!< Typical frequency = osc_freq / 2. */
273     kPMU_OscFreq       = 7U, /*!< Typical frequency = oscillator frequency. */
274 } pmu_well_bias_typical_freq_t;
275 
276 /*!
277  * @brief The enumerator of well bias adaptive clock source.
278  */
279 typedef enum _pmu_adaptive_clock_source
280 {
281     kPMU_AdaptiveClkSourceOscClk = 0U,   /*!< The adaptive clock source is oscillator clock. */
282     kPMU_AdaptiveClkSourceChargePumpClk, /*!< The adaptive clock source is charge pump clock. */
283 } pmu_adaptive_clock_source_t;
284 
285 /*!
286  * @brief The enumerator of frequency reduction due to cap increment.
287  */
288 typedef enum _pmu_freq_reduction
289 {
290     kPMU_FreqReductionNone = 0U, /*!< No frequency reduction. */
291     kPMU_FreqReduction30PCT,     /*!< 30% frequency reduction due to cap increment. */
292     kPMU_FreqReduction40PCT,     /*!< 40% frequency reduction due to cap increment. */
293     kPMU_FreqReduction50PCT,     /*!< 50% frequency reduction due to cap increment. */
294 } pmu_freq_reduction_t;
295 
296 /*!
297  * @brief The enumerator of well bias 1P8 adjustment.
298  */
299 typedef enum _pmu_well_bias_1P8_adjustment
300 {
301     kPMU_Cref0fFCspl0fFDeltaC0fF = 0U, /*!< Cref = 0fF, Cspl = 0fF, DeltaC = 0fF. */
302     kPMU_Cref0fFCspl30fFDeltaCN30fF,   /*!< Cref = 0fF, Cspl = 30fF, DeltaC = -30fF. */
303     kPMU_Cref0fFCspl43fFDeltaCN43fF,   /*!< Cref = 0fF, Cspl = 43fF, DeltaC = -43fF. */
304     kPMU_Cref0fFCspl62fFDeltaCN62fF,   /*!< Cref = 0fF, Cspl = 62fF, DeltaC = -62fF. */
305     kPMU_Cref0fFCspl105fFDeltaCN105fF, /*!< Cref = 0fF, Cspl = 105fF, DeltaC = -105fF. */
306     kPMU_Cref30fFCspl0fFDeltaC30fF,    /*!< Cref = 30fF, Cspl = 0fF, DeltaC = 30fF. */
307     kPMU_Cref30fFCspl43fFDeltaCN12fF,  /*!< Cref = 30fF, Cspl = 43fF, DeltaC = -12fF. */
308     kPMU_Cref30fFCspl105fFDeltaCN75fF, /*!< Cref = 30fF, Cspl = 105fF, DeltaC = -75fF. */
309     kPMU_Cref43fFCspl0fFDeltaC43fF,    /*!< Cref = 43fF, Cspl = 0fF, DeltaC = 43fF. */
310     kPMU_Cref43fFCspl30fFDeltaC13fF,   /*!< Cref = 43fF, Cspl = 30fF, DeltaC = 13fF. */
311     kPMU_Cref43fFCspl62fFDeltaCN19fF,  /*!< Cref = 43fF, Cspl = 62fF, DeltaC = -19fF. */
312     kPMU_Cref62fFCspl0fFDeltaC62fF,    /*!< Cref = 62fF, Cspl = 0fF, DeltaC = 62fF. */
313     kPMU_Cref62fFCspl43fFDeltaC19fF,   /*!< Cref = 62fF, Cspl = 43fF, DeltaC = 19fF. */
314     kPMU_Cref105fFCspl0fFDeltaC105fF,  /*!< Cref = 105fF, Cspl = 0fF, DeltaC = 105fF. */
315     kPMU_Cref105fFCspl30fFDeltaC75fF,  /*!< Cref = 105fF, Cspl = 30fF, DeltaC = 75fF. */
316 } pmu_well_bias_1P8_adjustment_t;
317 
318 /*!
319  * @brief LPSR ANA LDO config.
320  */
321 typedef struct _pmu_static_lpsr_ana_ldo_config
322 {
323     pmu_ldo_operate_mode_t mode; /*!< The operate mode of LPSR ANA LDO. */
324     bool enable2mALoad;          /*!< Enable/Disable 2mA load.
325                                       - \b true Enables 2mA loading to prevent overshoot;
326                                       - \b false Disables 2mA loading.*/
327     bool enable4mALoad;          /*!< Enable/Disable 4mA load.
328                                       - \b true Enables 4mA loading to prevent dramatic voltage drop;
329                                       - \b false Disables 4mA load. */
330     bool enable20uALoad;         /*!< Enable/Disable 20uA load.
331                                       - \b true Enables 20uA loading to prevent overshoot;
332                                       - \b false Disables 20uA load. */
333     bool enableStandbyMode;      /*!< Enable/Disable Standby Mode.
334                                       - \b true Enables Standby mode, if the STBY assert, the LPSR ANA LDO enter LP mode
335                                       - \b false Disables Standby mode. */
336 } pmu_static_lpsr_ana_ldo_config_t;
337 
338 /*!
339  * @brief LPSR DIG LDO Config in Static/Software Mode.
340  */
341 typedef struct _pmu_static_lpsr_dig_config
342 {
343     bool enableStableDetect;                            /*!< Enable/Disable Stable Detect.
344                                                                 - \b true   Enables Stable Detect.
345                                                                 - \b false  Disables Stable Detect. */
346     pmu_lpsr_dig_voltage_step_time_t voltageStepTime;   /*!< Step time. */
347     pmu_lpsr_dig_target_output_voltage_t targetVoltage; /*!< The target output voltage. */
348 } pmu_static_lpsr_dig_config_t;
349 
350 /*!
351  * @brief SNVS DIG LDO config.
352  */
353 typedef struct _pmu_snvs_dig_config
354 {
355     pmu_ldo_operate_mode_t mode;                          /*!< The operate mode the SNVS DIG LDO. */
356     pmu_snvs_dig_charge_pump_current_t chargePumpCurrent; /*!< The current of SNVS DIG LDO's charge pump current. */
357     pmu_snvs_dig_discharge_resistor_value_t dischargeResistorValue; /*!< The value of SNVS DIG LDO's
358                                                                         Discharge Resistor. */
359     uint8_t trimValue;                                              /*!< The trim value. */
360     bool enablePullDown;                                            /*!< Enable/Disable Pull down.
361                                                                       - \b true Enables the feature of using 1M ohm resistor to discharge the LDO output.
362                                                                       - \b false Disables the feature of using 1M ohm resistor to discharge the LDO output. */
363     bool enableLdoStable;                                           /*!< Enable/Disable SNVS DIG LDO Stable. */
364 } pmu_snvs_dig_config_t;
365 
366 /*!
367  * @brief Bandgap config in static mode.
368  */
369 typedef struct _pmu_static_bandgap_config
370 {
371     uint8_t powerDownOption; /*!< The OR'ed value of @ref _pmu_static_bandgap_power_down_option. Please refer to @ref
372                                 _pmu_static_bandgap_power_down_option.  */
373     bool enableLowPowerMode; /*!< Turn on/off the Low power mode.
374                                   - \b true Turns on the low power operation of the bandgap.
375                                   - \b false Turns off the low power operation of the bandgap. */
376     pmu_bandgap_output_VBG_voltage_value_t outputVoltage; /*!< The output VBG voltage of Bandgap. */
377     pmu_bandgap_output_current_value_t outputCurrent;     /*!< The output current from the bandgap to
378                                                                 the temperature sensors. */
379 } pmu_static_bandgap_config_t;
380 
381 /*!
382  * @brief The union of well bias basic options, such as clock source, power source and so on.
383  */
384 typedef union _pmu_well_bias_option
385 {
386     uint16_t wellBiasData; /*!< well bias configuration data. */
387     struct
388     {
389         uint16_t enablePWellOnly : 1U;     /*!< Turn on both PWELL and NWELL, or only trun on PWELL.
390                                                 - \b 1b0  PWELL and NEWLL are both turned on.
391                                                 - \b 1b1  PWELL is turned on only. */
392         uint16_t reserved1 : 1U;           /*!< Reserved. */
393         uint16_t biasAreaSize : 3U;        /*!< Select size of bias area, please refer to @ref pmu_bias_area_size_t */
394         uint16_t disableAdaptiveFreq : 1U; /*!< Enable/Disable adaptive frequency.
395                                                 - \b 1b0 Frequency change after each half cycle minimum frequency
396                                                         determined by typical frequency.
397                                                 - \b 1b1 Adaptive frequency disabled. Frequency determined by typical
398                                                        frequency. */
399         uint16_t wellBiasFreq : 3U;        /*!< Set well bias typical frequency, please refer to @ref
400                                               pmu_well_bias_typical_freq_t. */
401         uint16_t clkSource : 1U;     /*!< Config the adaptive clock source, please @ref pmu_adaptive_clock_source_t. */
402         uint16_t freqReduction : 2U; /*!< Config the percent of frequency reduction due to cap increment,
403                                          please refer to @ref pmu_freq_reduction_t.  */
404         uint16_t enablePowerDownOption : 1U; /*!< Enable/Disable pull down option.
405                                                  - \b false Pull down option is disabled.
406                                                  - \b true  Pull down option is enabled. */
407         uint16_t reserved2 : 1U;             /*!< Reserved. */
408         uint16_t powerSource : 1U; /*!< Set power source, please refer to @ref pmu_well_bias_power_source_t. */
409         uint16_t reserved3 : 1U;   /*!< Reserved. */
410     } wellBiasStruct;
411 } pmu_well_bias_option_t;
412 
413 /*!
414  * @brief The structure of well bias configuration.
415  */
416 typedef struct _pmu_well_bias_config
417 {
418     pmu_well_bias_option_t wellBiasOption;     /*!< Well bias basic function, please
419                                                     refer to @ref pmu_well_bias_option_t. */
420     pmu_well_bias_1P8_adjustment_t adjustment; /*!< Well bias adjustment 1P8, please
421                                                     refer to @ref pmu_well_bias_1P8_adjustment_t. */
422 } pmu_well_bias_config_t;
423 
424 /*!
425  * @brief The stucture of body bias config in GPC mode.
426  */
427 typedef struct _pmu_gpc_body_bias_config
428 {
429     uint8_t PWELLRegulatorSize; /*!< The size of the PWELL Regulator. */
430     uint8_t NWELLRegulatorSize; /*!< The size of the NWELL Regulator. */
431     uint8_t oscillatorSize;     /*!< The size of the oscillator bits. */
432     uint8_t regulatorStrength;  /*!< The strength of the selected regulator. */
433 } pmu_gpc_body_bias_config_t;
434 
435 /*******************************************************************************
436  * API
437  ******************************************************************************/
438 #if defined(__cplusplus)
439 extern "C" {
440 #endif
441 
442 /*!
443  * @name LDOs Control APIs
444  * @{
445  */
446 
447 /*!
448  * @brief Selects the control mode of the PLL LDO.
449  *
450  * @param base PMU peripheral base address.
451  * @param mode The control mode of the PLL LDO. Please refer to @ref pmu_control_mode_t.
452  */
453 void PMU_SetPllLdoControlMode(ANADIG_PMU_Type *base, pmu_control_mode_t mode);
454 
455 /*!
456  * @brief Switches the PLL LDO from Static/Software Mode to GPC/Hardware Mode.
457  *
458  * @param base PMU peripheral base address.
459  */
460 void PMU_SwitchPllLdoToGPCMode(ANADIG_PMU_Type *base);
461 
462 /*!
463  * @brief Enables PLL LDO via AI interface in Static/Software mode.
464  *
465  * @param base PMU peripheral base address.
466  */
467 void PMU_StaticEnablePllLdo(ANADIG_PMU_Type *base);
468 
469 /*!
470  * @brief Disables PLL LDO via AI interface in Static/Software mode.
471  */
472 void PMU_StaticDisablePllLdo(void);
473 
474 /*!
475  * @brief Selects the control mode of the LPSR ANA LDO.
476  *
477  * @param base PMU peripheral base address.
478  * @param mode The control mode of the LPSR ANA LDO. Please refer to @ref pmu_control_mode_t.
479  */
480 void PMU_SetLpsrAnaLdoControlMode(ANADIG_LDO_SNVS_Type *base, pmu_control_mode_t mode);
481 
482 /*!
483  * @brief Sets the Bypass mode of the LPSR ANA LDO.
484  *
485  * @param base ANADIG_LDO_SNVS peripheral base address.
486  * @param enable Enable/Disable bypass mode.
487  *          - \b true Enable LPSR ANA Bypass mode.
488  *          - \b false Disable LPSR ANA Bypass mode.
489  */
490 void PMU_StaticEnableLpsrAnaLdoBypassMode(ANADIG_LDO_SNVS_Type *base, bool enable);
491 
492 /*!
493  * @brief Checks whether the LPSR ANA LDO is in bypass mode.
494  *
495  * @param base ANADIG_LDO_SNVS peripheral base address.
496  * @return The result used to indicates whether the LPSR ANA LDO is in bypass mode.
497  *              - \b true   The LPSR ANA LDO is in bypass mode.
498  *              - \b false  The LPSR ANA LDO not in bypass mode.
499  */
PMU_StaticCheckLpsrAnaLdoBypassMode(ANADIG_LDO_SNVS_Type * base)500 static inline bool PMU_StaticCheckLpsrAnaLdoBypassMode(ANADIG_LDO_SNVS_Type *base)
501 {
502     return ((ANADIG_LDO_SNVS->PMU_LDO_LPSR_ANA & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_MASK) != 0UL);
503 }
504 
505 /*!
506  * @brief Fill the LPSR ANA LDO configuration structure with default settings.
507  *
508  * The default values are:
509  * @code
510  *      config->mode                   = kPMU_HighPowerMode;
511         config->enable2mALoad          = true;
512         config->enable20uALoad         = false;
513         config->enable4mALoad          = true;
514         config->enableStandbyMode      = false;
515         config->driverStrength         = kPMU_LpsrAnaLdoDriverStrength0;
516         config->brownOutDetectorConfig = kPMU_LpsrAnaLdoBrownOutDetectorDisable;
517         config->chargePumpCurrent      = kPMU_LpsrAnaChargePump300nA;
518         config->outputRange            = kPMU_LpsrAnaLdoOutputFrom1P77To1P83;
519  * @endcode
520  *
521  * @param config Pointer to the structure @ref pmu_static_lpsr_ana_ldo_config_t.
522  */
523 void PMU_StaticGetLpsrAnaLdoDefaultConfig(pmu_static_lpsr_ana_ldo_config_t *config);
524 
525 /*!
526  * @brief Initialize the LPSR ANA LDO in Static/Sofware Mode.
527  *
528  * @param base ANADIG_LDO_SNVS peripheral base address.
529  * @param config Pointer to the structure @ref pmu_static_lpsr_ana_ldo_config_t.
530  */
531 void PMU_StaticLpsrAnaLdoInit(ANADIG_LDO_SNVS_Type *base, const pmu_static_lpsr_ana_ldo_config_t *config);
532 
533 /*!
534  * @brief Disable the output of LPSR ANA LDO.
535  *
536  * @param base ANADIG_LDO_SNVS peripheral base address.
537  */
538 void PMU_StaticLpsrAnaLdoDeinit(ANADIG_LDO_SNVS_Type *base);
539 
540 /*!
541  * @brief Selects the control mode of the LPSR DIG LDO.
542  *
543  * @param base PMU peripheral base address.
544  * @param mode The control mode of the LPSR DIG LDO. Please refer to @ref pmu_control_mode_t.
545  */
546 void PMU_SetLpsrDigLdoControlMode(ANADIG_LDO_SNVS_Type *base, pmu_control_mode_t mode);
547 
548 /*!
549  * @brief Turn on/off Bypass mode of the LPSR DIG LDO in Static/Software mode.
550  *
551  * @param base ANADIG_LDO_SNVS peripheral base address.
552  * @param enable
553  *               - \b true Turns on Bypass mode of the LPSR DIG LDO.
554  *               - \b false Turns off Bypass mode of the LPSR DIG LDO.
555  */
556 void PMU_StaticEnableLpsrDigLdoBypassMode(ANADIG_LDO_SNVS_Type *base, bool enable);
557 
558 /*!
559  * @brief Checks whether the LPSR DIG LDO is in bypass mode.
560  *
561  * @param base PMU peripheral base address.
562  * @return The result used to indicates whether the LPSR DIG LDO is in bypass mode.
563  *              - \b true   The LPSR DIG LDO is in bypass mode.
564  *              - \b false  The LPSR DIG LDO not in bypass mode.
565  */
PMU_StaticCheckLpsrDigLdoBypassMode(ANADIG_LDO_SNVS_Type * base)566 static inline bool PMU_StaticCheckLpsrDigLdoBypassMode(ANADIG_LDO_SNVS_Type *base)
567 {
568     return ((ANADIG_LDO_SNVS->PMU_LDO_LPSR_DIG & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_MASK) != 0UL);
569 }
570 
571 /*!
572  * @brief Gets the default configuration of LPSR DIG LDO.
573  *
574  * The default values are:
575  *  @code
576  *          config->enableStableDetect = false;
577  *          config->voltageStepTime    = kPMU_LpsrDigVoltageStepInc50us;
578  *          config->brownOutConfig     = kPMU_LpsrDigBrownOutDisable;
579  *          config->targetVoltage      = kPMU_LpsrDigTargetStableVoltage1P0V;
580  *          config->mode               = kPMU_HighPowerMode;
581  *  @endcode
582  * @param config Pointer to the structure @ref pmu_static_lpsr_dig_config_t.
583  */
584 void PMU_StaticGetLpsrDigLdoDefaultConfig(pmu_static_lpsr_dig_config_t *config);
585 
586 /*!
587  * @brief Initialize the LPSR DIG LDO in static mode.
588  *
589  * @param base ANADIG_LDO_SNVS peripheral base address.
590  * @param config Pointer to the structure @ref pmu_static_lpsr_dig_config_t.
591  */
592 void PMU_StaticLpsrDigLdoInit(ANADIG_LDO_SNVS_Type *base, const pmu_static_lpsr_dig_config_t *config);
593 
594 /*!
595  * @brief Disable the LPSR DIG LDO.
596  *
597  * @param base ANADIG_LDO_SNVS peripheral base address.
598  */
599 void PMU_StaticLpsrDigLdoDeinit(ANADIG_LDO_SNVS_Type *base);
600 
601 /*!
602  * @brief Sets the voltage step of LPSR DIG LDO in certain setpoint during GPC mode.
603  *
604  * @note The function provides the feature to set the voltage step to different setpoints.
605  *
606  * @param setpointMap The map of setpoints should be the OR'ed Value of @ref _pmu_setpoint_map.
607  * @param voltageValue The voltage step to be set. See enumeration @ref pmu_lpsr_dig_target_output_voltage_t.
608  */
609 void PMU_GPCSetLpsrDigLdoTargetVoltage(uint32_t setpointMap, pmu_lpsr_dig_target_output_voltage_t voltageValue);
610 
611 /*!
612  * @brief Gets the default config of the SNVS DIG LDO.
613  *
614  * The default values are:
615  *  @code
616  *      config->mode                   = kPMU_LowPowerMode;
617  *      config->chargePumpCurrent      = kPMU_SnvsDigChargePump12P5nA;
618  *      config->dischargeResistorValue = kPMU_SnvsDigDischargeResistor15K;
619  *      config->trimValue              = 0U;
620  *      config->enablePullDown         = true;
621  *      config->enableLdoStable        = false;
622  *  @endcode
623  *
624  * @param config Pointer to @ref pmu_snvs_dig_config_t.
625  */
626 void PMU_GetSnvsDigLdoDefaultConfig(pmu_snvs_dig_config_t *config);
627 
628 /*!
629  * @brief Initialize the SNVS DIG LDO.
630  *
631  * @param base LDO SNVS DIG peripheral base address.
632  * @param mode Used to control LDO power mode, please refer to @ref pmu_ldo_operate_mode_t.
633  */
634 void PMU_SnvsDigLdoInit(ANADIG_LDO_SNVS_DIG_Type *base, pmu_ldo_operate_mode_t mode);
635 
636 /*!
637  * @brief Disable SNVS DIG LDO.
638  */
PMU_SnvsDigLdoDeinit(ANADIG_LDO_SNVS_DIG_Type * base)639 static inline void PMU_SnvsDigLdoDeinit(ANADIG_LDO_SNVS_DIG_Type *base)
640 {
641     base->PMU_LDO_SNVS_DIG &= ~ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_EN_MASK;
642 }
643 
644 /*!
645  * @brief  Controls the ON/OFF of the selected LDO in certain setpoints with GPC mode.
646  *
647  * @param name The name of the selected ldo. Please see enumeration @ref pmu_ldo_name_t for details.
648  * @param setpointMap The map of setpoints should be the OR'ed Value of @ref _pmu_setpoint_map, 1b'1
649  * means enable specific ldo in that setpoint.
650  * For example, the code PMU_GPCEnableLdo(kPMU_PllLdo, 0x1U) means to enable PLL LDO in setpoint 0 and disable
651  * PLL LDO in other setpoint.
652  */
653 void PMU_GPCEnableLdo(pmu_ldo_name_t name, uint32_t setpointMap);
654 
655 /*!
656  * @brief Sets the operating mode of the selected LDO in certain setpoints with GPC mode.
657  *
658  * @param name The name of the selected ldo. Please see enumeration @ref pmu_ldo_name_t for details.
659  * @param setpointMap The map of setpoints should be the OR'ed Value of @ref _pmu_setpoint_map.
660  * @param mode The operating mode of the selected ldo. Please refer to enumeration @ref pmu_ldo_operate_mode_t for
661  * details.
662  */
663 void PMU_GPCSetLdoOperateMode(pmu_ldo_name_t name, uint32_t setpointMap, pmu_ldo_operate_mode_t mode);
664 
665 /*!
666  * @brief Controls the ON/OFF of the selected LDOs' Tracking mode in certain setpoints with GPC mode.
667  *
668  * @param name The name of the selected ldo. Please see enumeration @ref pmu_ldo_name_t for details.
669  * @param setpointMap The map of setpoints that the LDO tracking mode will be enabled in those setpoints, this value
670  * should be the OR'ed Value of @ref _pmu_setpoint_map.
671  */
672 void PMU_GPCEnableLdoTrackingMode(pmu_ldo_name_t name, uint32_t setpointMap);
673 
674 /*!
675  * @brief Controls the ON/OFF of the selected LDOs' Bypass mode in certain setpoints with GPC mode.
676  *
677  * @param name The name of the selected ldo. Please see enumeration @ref pmu_ldo_name_t for details.
678  * @param setpointMap The map of setpoints that the LDO bypass mode will be enabled in those setpoints, this value
679  * should be the OR'ed Value of @ref _pmu_setpoint_map.
680  */
681 void PMU_GPCEnableLdoBypassMode(pmu_ldo_name_t name, uint32_t setpointMap);
682 
683 /*!
684  * @brief When STBY assert, enable/disable the selected LDO enter it's Low power mode.
685  *
686  * @param name The name of the selected ldo. Please see enumeration @ref pmu_ldo_name_t for details.
687  * @param setpointMap The map of setpoints that the LDO low power mode will be enabled in those setpoints if STBY
688  * assert, this value should be the OR'ed Value of @ref _pmu_setpoint_map.
689  */
690 void PMU_GPCEnableLdoStandbyMode(pmu_ldo_name_t name, uint32_t setpointMap);
691 
692 /*!
693  * @}
694  */
695 
696 /*!
697  * @name Bandgap Control APIs
698  * @{
699  */
700 
701 /*!
702  * @brief Selects the control mode of the Bandgap Reference.
703  *
704  * @param base PMU peripheral base address.
705  * @param mode The control mode of the Bandgap Reference. Please refer to @ref pmu_control_mode_t.
706  */
707 void PMU_SetBandgapControlMode(ANADIG_PMU_Type *base, pmu_control_mode_t mode);
708 
709 /*!
710  * @brief Switches the Bandgap from Static/Software Mode to GPC/Hardware Mode.
711  *
712  * @param base PMU peripheral base address.
713  */
714 void PMU_SwitchBandgapToGPCMode(ANADIG_PMU_Type *base);
715 
716 /*!
717  * @brief Disables Bandgap self bias for best noise performance.
718  *
719  * This function should be invoked after powering up. This function will wait for the bandgap stable and disable the
720  * bandgap self bias. After powering up, it need to wait for the bandgap to get stable and then disable Bandgap Self
721  * bias for best noise performance.
722  */
723 void PMU_DisableBandgapSelfBiasAfterPowerUp(void);
724 
725 /*!
726  * @brief Enables Bandgap self bias before power down.
727  *
728  * This function will enable Bandgap self bias feature before powering down or there
729  * will be risk of Bandgap not starting properly.
730  */
731 void PMU_EnableBandgapSelfBiasBeforePowerDown(void);
732 
733 /*!
734  * @brief Initialize Bandgap.
735  *
736  * @param config Pointer to the structure @ref pmu_static_bandgap_config_t.
737  */
738 void PMU_StaticBandgapInit(const pmu_static_bandgap_config_t *config);
739 
740 /*!
741  * @brief Controls the ON/OFF of the Bandgap in certain setpoints with GPC mode.
742  *
743  * For example, the code PMU_GPCEnableBandgap(PMU, kPMU_SetPoint0 | kPMU_SetPoint1); means enable bandgap in
744  * setpoint0 and setpoint1 and disable bandgap in other setpoints.
745  *
746  * @param base PMU peripheral base address.
747  * @param setpointMap The map of setpoints that the bandgap will be enabled in those setpoints, this parameter
748  * should be the OR'ed Value of @ref _pmu_setpoint_map.
749  */
PMU_GPCEnableBandgap(ANADIG_PMU_Type * base,uint32_t setpointMap)750 static inline void PMU_GPCEnableBandgap(ANADIG_PMU_Type *base, uint32_t setpointMap)
751 {
752     base->BANDGAP_ENABLE_SP = ~setpointMap;
753 }
754 
755 /*!
756  * @brief Controls the ON/OFF of the Bandgap's Standby mode in certain setpoints with GPC mode.
757  *
758  * @param base PMU peripheral base address.
759  * @param setpointMap The map of setpoints that the bandgap standby mode will be enabled in those setpoints, this value
760  * should be the OR'ed Value of @ref _pmu_setpoint_map.
761  */
PMU_GPCEnableBandgapStandbyMode(ANADIG_PMU_Type * base,uint32_t setpointMap)762 static inline void PMU_GPCEnableBandgapStandbyMode(ANADIG_PMU_Type *base, uint32_t setpointMap)
763 {
764     base->BANDGAP_STBY_EN_SP = setpointMap;
765 }
766 
767 /*!
768  * @}
769  */
770 
771 /*!
772  * @name Body Bias Control APIs
773  * @{
774  */
775 
776 /*!
777  * @brief Configures Well bias, such as power source, clock source and so on.
778  *
779  * @param base PMU peripheral base address.
780  * @param config Pointer to the @ref pmu_well_bias_config_t structure.
781  */
782 void PMU_WellBiasInit(ANADIG_PMU_Type *base, const pmu_well_bias_config_t *config);
783 
784 /*!
785  * @brief Gets the default configuration of well bias.
786  *
787  * @param config The pointer to the @ref pmu_well_bias_config_t structure.
788  */
789 void PMU_GetWellBiasDefaultConfig(pmu_well_bias_config_t *config);
790 
791 /*!
792  * @brief Selects the control mode of the Body Bias.
793  *
794  * @param base PMU peripheral base address.
795  * @param name The name of the body bias. Please refer to @ref pmu_body_bias_name_t.
796  * @param mode The control mode of the Body Bias. Please refer to @ref pmu_control_mode_t.
797  */
798 void PMU_SetBodyBiasControlMode(ANADIG_PMU_Type *base, pmu_body_bias_name_t name, pmu_control_mode_t mode);
799 
800 /*!
801  * @brief Enables/disables the selected body bias.
802  *
803  * @param base PMU peripheral base address.
804  * @param name The name of the body bias to be turned on/off, please refer to @ref pmu_body_bias_name_t.
805  * @param enable Used to turn on/off the specific body bias.
806  *              - \b true Enable the selected body bias.
807  *              - \b false Disable the selected body bias.
808  */
809 void PMU_EnableBodyBias(ANADIG_PMU_Type *base, pmu_body_bias_name_t name, bool enable);
810 
811 /*!
812  * @brief  Controls the ON/OFF of the selected body bias in certain setpoints with GPC mode.
813  *
814  * @param name The name of the selected body bias. Please see enumeration @ref pmu_body_bias_name_t for details.
815  * @param setpointMap The map of setpoints that the specific body bias will be enabled in those setpoints, this value
816  * should be the OR'ed Value of _pmu_setpoint_map.
817  */
818 void PMU_GPCEnableBodyBias(pmu_body_bias_name_t name, uint32_t setpointMap);
819 
820 /*!
821  * @brief Controls the ON/OFF of the selected Body Bias' Wbias power switch in certain setpoints with GPC mode.
822  *
823  * @param name The name of the selected body bias. Please see the enumeration @ref pmu_body_bias_name_t for details.
824  * @param setpointMap The map of setpoints that the specific body bias's wbias power switch will be turn on in those
825  * setpoints, this value should be the OR'ed Value of @ref _pmu_setpoint_map.
826  */
827 void PMU_GPCEnableBodyBiasStandbyMode(pmu_body_bias_name_t name, uint32_t setpointMap);
828 
829 /*!
830  * @brief Gets the default config of body bias in GPC mode.
831  *
832  * @param config Pointer to structure @ref pmu_gpc_body_bias_config_t.
833  */
834 void PMU_GPCGetBodyBiasDefaultConfig(pmu_gpc_body_bias_config_t *config);
835 
836 /*!
837  * @brief Sets the config of the selected Body Bias in GPC mode.
838  *
839  * @param name The name of the selected body bias. Please see enumeration @ref pmu_body_bias_name_t for details.
840  * @param config Pointer to structure @ref pmu_gpc_body_bias_config_t.
841  */
842 void PMU_GPCSetBodyBiasConfig(pmu_body_bias_name_t name, const pmu_gpc_body_bias_config_t *config);
843 
844 /*!
845  * @}
846  */
847 
848 #if defined(__cplusplus)
849 }
850 #endif
851 /*!
852  * @}
853  */
854 
855 #endif /* _FSL_PMU_H_ */
856