1 /*
2  * Copyright 2021-2022 NXP
3  * All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 #ifndef _CLOCK_CONFIG_H_
9 #define _CLOCK_CONFIG_H_
10 
11 #include "fsl_common.h"
12 
13 /*******************************************************************************
14  * Definitions
15  ******************************************************************************/
16 #define BOARD_XTAL0_CLK_HZ                         24000000U  /*!< Board xtal0 frequency in Hz */
17 
18 #define BOARD_XTAL32K_CLK_HZ                          32768U  /*!< Board xtal32k frequency in Hz */
19 /*******************************************************************************
20  ************************ BOARD_InitBootClocks function ************************
21  ******************************************************************************/
22 
23 #if defined(__cplusplus)
24 extern "C" {
25 #endif /* __cplusplus*/
26 
27 /*!
28  * @brief This function executes default configuration of clocks.
29  *
30  */
31 void BOARD_InitBootClocks(void);
32 
33 #if defined(__cplusplus)
34 }
35 #endif /* __cplusplus*/
36 
37 /*******************************************************************************
38  ********************** Configuration BOARD_BootClockRUN ***********************
39  ******************************************************************************/
40 /*******************************************************************************
41  * Definitions for BOARD_BootClockRUN configuration
42  ******************************************************************************/
43 #define BOARD_BOOTCLOCKRUN_CORE_CLOCK              12000000U  /*!< Core clock frequency: 12000000Hz */
44 
45 /* Clock outputs (values are in Hz): */
46 #define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT               12000000UL
47 #define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT               2000000UL
48 #define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT         0UL
49 #define BOARD_BOOTCLOCKRUN_CLKO1_CLK                  0UL
50 #define BOARD_BOOTCLOCKRUN_CLKO2_CLK                  0UL
51 #define BOARD_BOOTCLOCKRUN_CLK_1M                     1000000UL
52 #define BOARD_BOOTCLOCKRUN_CLK_24M                    24000000UL
53 #define BOARD_BOOTCLOCKRUN_ENET_125M_CLK              2400000UL
54 #define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK           1200000UL
55 #define BOARD_BOOTCLOCKRUN_ENET_REF_CLK               0UL
56 #define BOARD_BOOTCLOCKRUN_ENET_TX_CLK                0UL
57 #define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT           1500000UL
58 #define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT           1500000UL
59 #define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT          12000000UL
60 #define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT           2000000UL
61 #define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ      3000000UL
62 #define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ      3000000UL
63 #define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT               3000000UL
64 #define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT             3000000UL
65 #define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT             6000000UL
66 #define BOARD_BOOTCLOCKRUN_LVDS1_CLK                  24000000UL
67 #define BOARD_BOOTCLOCKRUN_MQS_MCLK                   3000000UL
68 #define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT            3000000UL
69 #define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT              3000000UL
70 #define BOARD_BOOTCLOCKRUN_SAI1_MCLK1                 3000000UL
71 #define BOARD_BOOTCLOCKRUN_SAI1_MCLK2                 3000000UL
72 #define BOARD_BOOTCLOCKRUN_SAI1_MCLK3                 1500000UL
73 #define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT              3000000UL
74 #define BOARD_BOOTCLOCKRUN_SAI2_MCLK1                 3000000UL
75 #define BOARD_BOOTCLOCKRUN_SAI2_MCLK2                 0UL
76 #define BOARD_BOOTCLOCKRUN_SAI2_MCLK3                 1500000UL
77 #define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT              3000000UL
78 #define BOARD_BOOTCLOCKRUN_SAI3_MCLK1                 3000000UL
79 #define BOARD_BOOTCLOCKRUN_SAI3_MCLK2                 0UL
80 #define BOARD_BOOTCLOCKRUN_SAI3_MCLK3                 1500000UL
81 #define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT              4000000UL
82 #define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT            1500000UL
83 #define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT          0UL
84 #define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT             6000000UL
85 #define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT              4000000UL
86 #define BOARD_BOOTCLOCKRUN_USBPHY_CLK                 0UL
87 #define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT            12000000UL
88 #define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT            12000000UL
89 
90 /*! @brief Arm PLL set for BOARD_BootClockRUN configuration.
91  */
92 extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN;
93 /*! @brief Sys PLL for BOARD_BootClockRUN configuration.
94  */
95 extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
96 /*! @brief Enet PLL set for BOARD_BootClockRUN configuration.
97  */
98 extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN;
99 
100 /*******************************************************************************
101  * API for BOARD_BootClockRUN configuration
102  ******************************************************************************/
103 #if defined(__cplusplus)
104 extern "C" {
105 #endif /* __cplusplus*/
106 
107 /*!
108  * @brief This function executes configuration of clocks.
109  *
110  */
111 void BOARD_BootClockRUN(void);
112 
113 #if defined(__cplusplus)
114 }
115 #endif /* __cplusplus*/
116 
117 #endif /* _CLOCK_CONFIG_H_ */
118 
119