1 /*
2 * Copyright 2018-2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include "fsl_common.h"
9 #include "fsl_debug_console.h"
10 #include "board.h"
11 #if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
12 #include "fsl_lpi2c.h"
13 #endif /* SDK_I2C_BASED_COMPONENT_USED */
14 #include "fsl_iomuxc.h"
15
16 /*******************************************************************************
17 * Variables
18 ******************************************************************************/
19
20 /*******************************************************************************
21 * Code
22 ******************************************************************************/
23
24 /* Get debug console frequency. */
BOARD_DebugConsoleSrcFreq(void)25 uint32_t BOARD_DebugConsoleSrcFreq(void)
26 {
27 uint32_t freq;
28
29 /* To make it simple, we assume default PLL and divider settings, and the only variable
30 from application is use PLL3 source or OSC source */
31 if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */
32 {
33 freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
34 }
35 else
36 {
37 freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
38 }
39
40 return freq;
41 }
42
43 /* Initialize debug console. */
BOARD_InitDebugConsole(void)44 void BOARD_InitDebugConsole(void)
45 {
46 uint32_t uartClkSrcFreq = BOARD_DebugConsoleSrcFreq();
47
48 DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
49 }
50
51 /* MPU configuration. */
BOARD_ConfigMPU(void)52 void BOARD_ConfigMPU(void)
53 {
54 /* Disable I cache and D cache */
55 if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR))
56 {
57 SCB_DisableICache();
58 }
59 if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR))
60 {
61 SCB_DisableDCache();
62 }
63
64 /* Disable MPU */
65 ARM_MPU_Disable();
66
67 /* MPU configure:
68 * Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable,
69 * SubRegionDisable, Size)
70 * API in mpu_armv7.h.
71 * param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches
72 * disabled.
73 * param AccessPermission Data access permissions, allows you to configure read/write access for User and
74 * Privileged mode.
75 * Use MACROS defined in mpu_armv7.h:
76 * ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
77 * Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes.
78 * TypeExtField IsShareable IsCacheable IsBufferable Memory Attribute Shareability Cache
79 * 0 x 0 0 Strongly Ordered shareable
80 * 0 x 0 1 Device shareable
81 * 0 0 1 0 Normal not shareable Outer and inner write
82 * through no write allocate
83 * 0 0 1 1 Normal not shareable Outer and inner write
84 * back no write allocate
85 * 0 1 1 0 Normal shareable Outer and inner write
86 * through no write allocate
87 * 0 1 1 1 Normal shareable Outer and inner write
88 * back no write allocate
89 * 1 0 0 0 Normal not shareable outer and inner
90 * noncache
91 * 1 1 0 0 Normal shareable outer and inner
92 * noncache
93 * 1 0 1 1 Normal not shareable outer and inner write
94 * back write/read acllocate
95 * 1 1 1 1 Normal shareable outer and inner write
96 * back write/read acllocate
97 * 2 x 0 0 Device not shareable
98 * Above are normal use settings, if your want to see more details or want to config different inner/outter cache
99 * policy.
100 * please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide <dui0646b_cortex_m7_dgug.pdf>
101 * param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled.
102 * param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in
103 * mpu_armv7.h.
104 */
105
106 /*
107 * Add default region to deny access to whole address space to workaround speculative prefetch.
108 * Refer to Arm errata 1013783-B for more details.
109 *
110 */
111 /* Region 0 setting: Instruction access disabled, No data access permission. */
112 MPU->RBAR = ARM_MPU_RBAR(0, 0x00000000U);
113 MPU->RASR = ARM_MPU_RASR(1, ARM_MPU_AP_NONE, 0, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4GB);
114
115 /* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */
116 MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
117 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
118
119 /* Region 2 setting: Memory with Device type, not shareable, non-cacheable. */
120 MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
121 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
122
123 #if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
124 /* Region 3 setting: Memory with Normal type, not shareable, outer/inner write back. */
125 MPU->RBAR = ARM_MPU_RBAR(3, 0x60000000U);
126 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_8MB);
127 #endif
128
129 /* Region 4 setting: Memory with Device type, not shareable, non-cacheable. */
130 MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
131 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
132
133 /* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */
134 MPU->RBAR = ARM_MPU_RBAR(5, 0x00000000U);
135 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64KB);
136
137 /* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */
138 MPU->RBAR = ARM_MPU_RBAR(6, 0x20000000U);
139 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64KB);
140
141 /* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */
142 MPU->RBAR = ARM_MPU_RBAR(7, 0x20200000U);
143 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
144
145 /* Region 8 setting: Memory with Normal type, not shareable, outer/inner write back */
146 MPU->RBAR = ARM_MPU_RBAR(8, 0x80000000U);
147 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
148
149 /* Region 10 setting: Memory with Device type, not shareable, non-cacheable */
150 MPU->RBAR = ARM_MPU_RBAR(10, 0x40000000);
151 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4MB);
152
153 /* Enable MPU */
154 ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
155
156 /* Enable I cache and D cache */
157 SCB_EnableDCache();
158 SCB_EnableICache();
159 }
160
161 #if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
BOARD_LPI2C_Init(LPI2C_Type * base,uint32_t clkSrc_Hz)162 void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz)
163 {
164 lpi2c_master_config_t lpi2cConfig = {0};
165
166 /*
167 * lpi2cConfig.debugEnable = false;
168 * lpi2cConfig.ignoreAck = false;
169 * lpi2cConfig.pinConfig = kLPI2C_2PinOpenDrain;
170 * lpi2cConfig.baudRate_Hz = 100000U;
171 * lpi2cConfig.busIdleTimeout_ns = 0;
172 * lpi2cConfig.pinLowTimeout_ns = 0;
173 * lpi2cConfig.sdaGlitchFilterWidth_ns = 0;
174 * lpi2cConfig.sclGlitchFilterWidth_ns = 0;
175 */
176 LPI2C_MasterGetDefaultConfig(&lpi2cConfig);
177 LPI2C_MasterInit(base, &lpi2cConfig, clkSrc_Hz);
178 }
179
BOARD_LPI2C_Send(LPI2C_Type * base,uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,uint8_t * txBuff,uint8_t txBuffSize)180 status_t BOARD_LPI2C_Send(LPI2C_Type *base,
181 uint8_t deviceAddress,
182 uint32_t subAddress,
183 uint8_t subAddressSize,
184 uint8_t *txBuff,
185 uint8_t txBuffSize)
186 {
187 lpi2c_master_transfer_t xfer;
188
189 xfer.flags = kLPI2C_TransferDefaultFlag;
190 xfer.slaveAddress = deviceAddress;
191 xfer.direction = kLPI2C_Write;
192 xfer.subaddress = subAddress;
193 xfer.subaddressSize = subAddressSize;
194 xfer.data = txBuff;
195 xfer.dataSize = txBuffSize;
196
197 return LPI2C_MasterTransferBlocking(base, &xfer);
198 }
199
BOARD_LPI2C_Receive(LPI2C_Type * base,uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,uint8_t * rxBuff,uint8_t rxBuffSize)200 status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
201 uint8_t deviceAddress,
202 uint32_t subAddress,
203 uint8_t subAddressSize,
204 uint8_t *rxBuff,
205 uint8_t rxBuffSize)
206 {
207 lpi2c_master_transfer_t xfer;
208
209 xfer.flags = kLPI2C_TransferDefaultFlag;
210 xfer.slaveAddress = deviceAddress;
211 xfer.direction = kLPI2C_Read;
212 xfer.subaddress = subAddress;
213 xfer.subaddressSize = subAddressSize;
214 xfer.data = rxBuff;
215 xfer.dataSize = rxBuffSize;
216
217 return LPI2C_MasterTransferBlocking(base, &xfer);
218 }
219
BOARD_Accel_I2C_Init(void)220 void BOARD_Accel_I2C_Init(void)
221 {
222 BOARD_LPI2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
223 }
224
BOARD_Accel_I2C_Send(uint8_t deviceAddress,uint32_t subAddress,uint8_t subaddressSize,uint32_t txBuff)225 status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)
226 {
227 uint8_t data = (uint8_t)txBuff;
228
229 return BOARD_LPI2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);
230 }
231
BOARD_Accel_I2C_Receive(uint8_t deviceAddress,uint32_t subAddress,uint8_t subaddressSize,uint8_t * rxBuff,uint8_t rxBuffSize)232 status_t BOARD_Accel_I2C_Receive(
233 uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
234 {
235 return BOARD_LPI2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);
236 }
237
BOARD_Codec_I2C_Init(void)238 void BOARD_Codec_I2C_Init(void)
239 {
240 BOARD_LPI2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
241 }
242
BOARD_Codec_I2C_Send(uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,const uint8_t * txBuff,uint8_t txBuffSize)243 status_t BOARD_Codec_I2C_Send(
244 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
245 {
246 return BOARD_LPI2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
247 txBuffSize);
248 }
249
BOARD_Codec_I2C_Receive(uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,uint8_t * rxBuff,uint8_t rxBuffSize)250 status_t BOARD_Codec_I2C_Receive(
251 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
252 {
253 return BOARD_LPI2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
254 }
255 #endif /* SDK_I2C_BASED_COMPONENT_USED */
256
