1 /*
2 ** ###################################################################
3 ** Processors: MIMX8UX5AVLFZ
4 ** MIMX8UX5AVOFZ
5 ** MIMX8UX5CVLDZ
6 **
7 ** Compilers: GNU C Compiler
8 ** IAR ANSI C/C++ Compiler for ARM
9 ** Keil ARM C/C++ Compiler
10 **
11 ** Reference manual: IMX8DQXPRM, Rev. E, 6/2019
12 ** Version: rev. 4.0, 2020-06-19
13 ** Build: b200806
14 **
15 ** Abstract:
16 ** Provides a system configuration function and a global variable that
17 ** contains the system frequency. It configures the device and initializes
18 ** the oscillator (PLL) that is part of the microcontroller device.
19 **
20 ** Copyright 2016 Freescale Semiconductor, Inc.
21 ** Copyright 2016-2020 NXP
22 ** All rights reserved.
23 **
24 ** SPDX-License-Identifier: BSD-3-Clause
25 **
26 ** http: www.nxp.com
27 ** mail: support@nxp.com
28 **
29 ** Revisions:
30 ** - rev. 1.0 (2016-06-02)
31 ** Initial version.
32 ** - rev. 2.0 (2017-08-23)
33 ** RevA Header EAR
34 ** - rev. 3.0 (2018-08-22)
35 ** RevB Header EAR
36 ** - rev. 4.0 (2020-06-19)
37 ** RevC Header RFP
38 **
39 ** ###################################################################
40 */
41
42 /*!
43 * @file MIMX8UX5_cm4
44 * @version 1.0
45 * @date 060820
46 * @brief Device specific configuration file for MIMX8UX5_cm4 (implementation file)
47 *
48 * Provides a system configuration function and a global variable that contains
49 * the system frequency. It configures the device and initializes the oscillator
50 * (PLL) that is part of the microcontroller device.
51 */
52
53 #include <stdint.h>
54 #include "fsl_device_registers.h"
55
56 /* ----------------------------------------------------------------------------
57 -- Core clock
58 ---------------------------------------------------------------------------- */
59
60 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
61 static sc_ipc_t ipcHandle;
62
63 /* ----------------------------------------------------------------------------
64 -- SystemInit()
65 ---------------------------------------------------------------------------- */
66
SystemInit(void)67 void SystemInit(void)
68 {
69 #if (ENABLE_ECC_DEBUG)
70 volatile uint32_t *p = (uint32_t *)0xE0080480U;
71
72 /* Configure LMEM Parity/ECC Control Register
73 ;
74 ; Note: ECC Multi-bit IRQ should be disabled
75 ; prior to list/dump of locations that
76 ; have not been written to avoid vectoring
77 ; to the NMI
78 ;
79 ; 31:22 RESERVED
80 ; 21 Enable Cache Parity IRQ
81 ; 20 Enable Cache Parity Report
82 ; 19:17 RESERVED
83 ; 16 Enable RAM Parity Reporting
84 ; 15:10 RESERVED
85 ; 9 Enable RAM ECC 1-bit IRQ
86 ; 8 Enable RAM ECC 1-bit Report
87 ; 7:2 RESERVED
88 ; 1 Enable RAM ECC Multi-bit IRQ
89 ; 0 Enable RAM ECC Multi-bit
90 */
91 *p = 0x00300003;
92 #endif
93
94 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
95 SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access */
96 #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
97
98 #if (DISABLE_WDOG)
99 CM4__WDOG->CNT = WDOG_UPDATE_KEY;
100 CM4__WDOG->TOVAL = 0xFFFF;
101 CM4__WDOG->CS = (uint32_t)((CM4__WDOG->CS) & ~WDOG_CS_EN_MASK) | WDOG_CS_UPDATE_MASK;
102 #endif /* (DISABLE_WDOG) */
103
104 /* Initialize Cache */
105 /* Enable Code Bus Cache */
106 /* set command to invalidate all ways, and write GO bit to initiate command */
107 LMEM->PCCCR |= LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_INVW0_MASK;
108 LMEM->PCCCR |= LMEM_PCCCR_GO_MASK;
109 /* Wait until the command completes */
110 while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0UL)
111 {
112 }
113 /* Enable cache, enable write buffer */
114 LMEM->PCCCR |= (LMEM_PCCCR_ENWRBUF_MASK | LMEM_PCCCR_ENCACHE_MASK);
115
116 /* Enable System Bus Cache */
117 /* set command to invalidate all ways, and write GO bit to initiate command */
118 LMEM->PSCCR |= LMEM_PSCCR_INVW1_MASK | LMEM_PSCCR_INVW0_MASK;
119 LMEM->PSCCR |= LMEM_PSCCR_GO_MASK;
120 /* Wait until the command completes */
121 while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0UL)
122 {
123 }
124 /* Enable cache, enable write buffer */
125 LMEM->PSCCR |= (LMEM_PSCCR_ENWRBUF_MASK | LMEM_PSCCR_ENCACHE_MASK);
126 /* i.MX8QX systemInit */
127 }
128
129 /* ----------------------------------------------------------------------------
130 -- SystemCoreClockUpdate()
131 ---------------------------------------------------------------------------- */
132
SystemCoreClockUpdate(void)133 void SystemCoreClockUpdate(void)
134 {
135 /* i.MX8QX SystemCoreClockUpdate */
136 sc_err_t err;
137 uint32_t freq = SystemCoreClock;
138
139 err = sc_pm_get_clock_rate(ipcHandle, SC_R_M4_0_PID0, SC_PM_CLK_CPU, &freq);
140
141 if (SC_ERR_NONE == err)
142 {
143 SystemCoreClock = freq;
144 }
145 }
146
147 /* ----------------------------------------------------------------------------
148 -- SystemInitScfwIpc()
149 ---------------------------------------------------------------------------- */
150
SystemInitScfwIpc(void)151 void SystemInitScfwIpc(void)
152 {
153 sc_ipc_t ipc;
154 sc_err_t err;
155
156 err = sc_ipc_open(&ipc, (sc_ipc_id_t)CM4__MU1_A);
157
158 if (err == SC_ERR_NONE)
159 {
160 ipcHandle = ipc;
161 }
162 else
163 {
164 ipcHandle = 0;
165 }
166 }
167
168 /* ----------------------------------------------------------------------------
169 -- SystemGetScfwIpcHandle()
170 ---------------------------------------------------------------------------- */
171
SystemGetScfwIpcHandle(void)172 sc_ipc_t SystemGetScfwIpcHandle(void)
173 {
174 return ipcHandle;
175 }
176
