1 /*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2017-2018 NXP
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include "fsl_common.h"
9 #include "fsl_debug_console.h"
10 #include "board.h"
11 #include "fsl_gpio.h"
12
13 /*******************************************************************************
14 * Variables
15 ******************************************************************************/
16 static sc_ipc_t ipcHandle; /* ipc handle */
17
18 /*******************************************************************************
19 * Code
20 ******************************************************************************/
BOARD_InitRpc(void)21 sc_ipc_t BOARD_InitRpc(void)
22 {
23 /* Initialize the IPC channel to communicate with SCFW */
24 SystemInitScfwIpc();
25
26 ipcHandle = SystemGetScfwIpcHandle();
27 if (ipcHandle)
28 {
29 CLOCK_Init(ipcHandle);
30 }
31 return ipcHandle;
32 }
33
BOARD_GetRpcHandle(void)34 sc_ipc_t BOARD_GetRpcHandle(void)
35 {
36 return ipcHandle;
37 }
38
39 /*
40 * Pre Configuration of some pins
41 * - Some physical pins default map to the same functionality and has priority, avoid such conflict
42 * at the beginning.
43 */
BOARD_InitPinsPre(void)44 void BOARD_InitPinsPre(void)
45 {
46 sc_err_t err = SC_ERR_NONE;
47
48 err = sc_pad_set_mux(ipcHandle, SC_P_USB_SS3_TC0, 3U, SC_PAD_CONFIG_NORMAL, SC_PAD_ISO_OFF);
49 if (SC_ERR_NONE != err)
50 {
51 assert(false);
52 }
53
54 err = sc_pad_set_mux(ipcHandle, SC_P_USB_SS3_TC1, 3U, SC_PAD_CONFIG_NORMAL, SC_PAD_ISO_OFF);
55 if (SC_ERR_NONE != err)
56 {
57 assert(false);
58 }
59
60 err = sc_pad_set_mux(ipcHandle, SC_P_USB_SS3_TC2, 3U, SC_PAD_CONFIG_NORMAL, SC_PAD_ISO_OFF);
61 if (SC_ERR_NONE != err)
62 {
63 assert(false);
64 }
65
66 err = sc_pad_set_mux(ipcHandle, SC_P_USB_SS3_TC3, 3U, SC_PAD_CONFIG_NORMAL, SC_PAD_ISO_OFF);
67 if (SC_ERR_NONE != err)
68 {
69 assert(false);
70 }
71 }
72
73 /* Initialize debug console. */
BOARD_InitDebugConsole(void)74 void BOARD_InitDebugConsole(void)
75 {
76 uint32_t freq = SC_133MHZ;
77
78 /* Power on Local LPUART for M4 Core0. */
79 sc_pm_set_resource_power_mode(ipcHandle, SC_R_M4_0_UART, SC_PM_PW_MODE_ON);
80 /* Enable clock of Local LPUART for M4 Core0. */
81 CLOCK_EnableClockExt(kCLOCK_M4_0_Lpuart, 0);
82 /* Set clock Frequncy of Local LPUART for M4 Core0. */
83 freq = CLOCK_SetIpFreq(kCLOCK_M4_0_Lpuart, freq);
84
85 /* Initialize Debug Console using local LPUART for M4 Core0. */
86 DbgConsole_Init(BOARD_DEBUG_UART_BASEADDR, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, freq);
87 }
88
89 /* Power on base board*/
BOARD_PowerOnBaseBoard(void)90 void BOARD_PowerOnBaseBoard(void)
91 {
92 sc_err_t err = SC_ERR_NONE;
93 gpio_pin_config_t pin_config;
94
95 if (sc_pm_set_resource_power_mode(ipcHandle, SC_R_GPIO_5, SC_PM_PW_MODE_ON) != SC_ERR_NONE)
96 {
97 assert(false);
98 }
99
100 if (!CLOCK_EnableClockExt(kCLOCK_LSIO_Gpio5, 0))
101 assert(false);
102
103 /*Configure BB_PWR_EN GPIO pin*/
104 pin_config.direction = kGPIO_DigitalOutput;
105 pin_config.outputLogic = 1U;
106 pin_config.interruptMode = kGPIO_NoIntmode;
107
108 err = sc_pad_set_mux(ipcHandle, SC_P_ENET0_REFCLK_125M_25M, 4U, SC_PAD_CONFIG_NORMAL, SC_PAD_ISO_OFF);
109 if (SC_ERR_NONE != err)
110 {
111 assert(false);
112 }
113
114 GPIO_PinInit(BOARD_BASEBOARD_PWR_GPIO, BOARD_BASEBOARD_PWR_GPIO_PIN, &pin_config);
115 GPIO_PinWrite(BOARD_BASEBOARD_PWR_GPIO, BOARD_BASEBOARD_PWR_GPIO_PIN, 1U);
116 }
117
118 /* Initialize MPU, configure non-cacheable memory */
BOARD_InitMemory(void)119 void BOARD_InitMemory(void)
120 {
121 extern uint32_t __CACHE_REGION_START[];
122 extern uint32_t __CACHE_REGION_SIZE[];
123 uint32_t cacheStart = (uint32_t)__CACHE_REGION_START;
124 uint32_t size = (uint32_t)__CACHE_REGION_SIZE;
125 uint32_t i = 0;
126 /* Make sure outstanding transfers are done. */
127 __DMB();
128 /* Disable the MPU. */
129 MPU->CTRL = 0;
130
131 /*
132 The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but there the address
133 space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need change the default memory attributes.
134 Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set the all 512M of SRAM space
135 with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~ 0x27FFFFFF) to use the background memory attributes。
136 */
137
138 /* Select Region 0 and set its base address to the M4 code bus start address. */
139 MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos);
140
141 /* Region 0 setting:
142 * 1) Enable Instruction Access;
143 * 2) AP = 011b, full access;
144 * 3) Non-shared device;
145 * 4) Region Not Shared;
146 * 5) Sub-Region 0,1 Disabled;
147 * 6) MPU Protection Region size = 512M byte;
148 * 7) Enable Region 0.
149 */
150 MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) |
151 (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
152
153 /*
154 Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4 cores.
155 You can put global or static uninitialized variables in NonCacheable section(initialized variables in NonCacheable.init section)
156 to make them uncacheable. Since the base address of MPU region should be multiples of region size, to make it simple,
157 the MPU region 1 set the address space 0x80000000 ~ 0xFFFFFFFF to be non-cacheable(disable sub-region 6,7 to use the background memory
158 attributes for address space 0xE0000000 ~ 0xFFFFFFFF). Then MPU region 2 set the text and data section to be cacheable if the program running
159 on DDR. The cacheable area base address should be multiples of its size in linker file, they can be modified per your needs.
160 */
161
162 /* Select Region 1 and set its base address to the DDR start address. */
163 MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos);
164
165 /* Region 1 setting:
166 * 1) Enable Instruction Access;
167 * 2) AP = 011b, full access;
168 * 3) Shared Device;
169 * 4) Sub-Region 6,7 Disabled;
170 * 5) MPU Protection Region size = 2048M byte;
171 * 6) Enable Region 1.
172 */
173 MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (0xC0 << MPU_RASR_SRD_Pos) |
174 (30 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
175
176 while ((size >> i) > 0x1U)
177 {
178 i++;
179 }
180
181 /* If run on DDR, configure text and data section to be cacheable */
182 if (i != 0)
183 {
184 /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
185 assert((size & (size - 1)) == 0);
186 assert(!(cacheStart % size));
187 assert(size == (uint32_t)(1 << i));
188 assert(i >= 5);
189
190 /* Select Region 2 and set its base address to the cache able region start address. */
191 MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos);
192
193 /* Region 2 setting:
194 * 1) Enable Instruction Access;
195 * 2) AP = 011b, full access;
196 * 3) Outer and inner Cacheable, write and read allocate;
197 * 4) Region Not Shared;
198 * 5) All Sub-Region Enabled;
199 * 6) MPU Protection Region size get from linker file;
200 * 7) Enable Region 2.
201 */
202 MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) |
203 (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
204 }
205
206 /* Enable Privileged default memory map and the MPU. */
207 MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
208 /* Memory barriers to ensure subsequence data & instruction
209 * transfers using updated MPU settings.
210 */
211 __DSB();
212 __ISB();
213 }
214
