1 /*
2 ** ###################################################################
3 ** Processor: MIMX8QX4AVLFZ
4 ** Compilers: GNU C Compiler
5 ** IAR ANSI C/C++ Compiler for ARM
6 ** Keil ARM C/C++ Compiler
7 **
8 ** Reference manual: IMX8DQXPRM, Rev. E, 6/2019
9 ** Version: rev. 4.0, 2020-06-19
10 ** Build: b200806
11 **
12 ** Abstract:
13 ** Provides a system configuration function and a global variable that
14 ** contains the system frequency. It configures the device and initializes
15 ** the oscillator (PLL) that is part of the microcontroller device.
16 **
17 ** Copyright 2016 Freescale Semiconductor, Inc.
18 ** Copyright 2016-2020 NXP
19 ** All rights reserved.
20 **
21 ** SPDX-License-Identifier: BSD-3-Clause
22 **
23 ** http: www.nxp.com
24 ** mail: support@nxp.com
25 **
26 ** Revisions:
27 ** - rev. 1.0 (2016-06-02)
28 ** Initial version.
29 ** - rev. 2.0 (2017-08-23)
30 ** RevA Header EAR
31 ** - rev. 3.0 (2018-08-22)
32 ** RevB Header EAR
33 ** - rev. 4.0 (2020-06-19)
34 ** RevC Header RFP
35 **
36 ** ###################################################################
37 */
38
39 /*!
40 * @file MIMX8QX4_cm4
41 * @version 1.0
42 * @date 060820
43 * @brief Device specific configuration file for MIMX8QX4_cm4 (implementation file)
44 *
45 * Provides a system configuration function and a global variable that contains
46 * the system frequency. It configures the device and initializes the oscillator
47 * (PLL) that is part of the microcontroller device.
48 */
49
50 #include <stdint.h>
51 #include "fsl_device_registers.h"
52
53 /* ----------------------------------------------------------------------------
54 -- Core clock
55 ---------------------------------------------------------------------------- */
56
57 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
58 static sc_ipc_t ipcHandle;
59
60 /* ----------------------------------------------------------------------------
61 -- SystemInit()
62 ---------------------------------------------------------------------------- */
63
SystemInit(void)64 void SystemInit(void)
65 {
66 #if (ENABLE_ECC_DEBUG)
67 volatile uint32_t *p = (uint32_t *)0xE0080480U;
68
69 /* Configure LMEM Parity/ECC Control Register
70 ;
71 ; Note: ECC Multi-bit IRQ should be disabled
72 ; prior to list/dump of locations that
73 ; have not been written to avoid vectoring
74 ; to the NMI
75 ;
76 ; 31:22 RESERVED
77 ; 21 Enable Cache Parity IRQ
78 ; 20 Enable Cache Parity Report
79 ; 19:17 RESERVED
80 ; 16 Enable RAM Parity Reporting
81 ; 15:10 RESERVED
82 ; 9 Enable RAM ECC 1-bit IRQ
83 ; 8 Enable RAM ECC 1-bit Report
84 ; 7:2 RESERVED
85 ; 1 Enable RAM ECC Multi-bit IRQ
86 ; 0 Enable RAM ECC Multi-bit
87 */
88 *p = 0x00300003;
89 #endif
90
91 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
92 SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access */
93 #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
94
95 #if (DISABLE_WDOG)
96 CM4__WDOG->CNT = WDOG_UPDATE_KEY;
97 CM4__WDOG->TOVAL = 0xFFFF;
98 CM4__WDOG->CS = (uint32_t)((CM4__WDOG->CS) & ~WDOG_CS_EN_MASK) | WDOG_CS_UPDATE_MASK;
99 #endif /* (DISABLE_WDOG) */
100
101 /* Initialize Cache */
102 /* Enable Code Bus Cache */
103 /* set command to invalidate all ways, and write GO bit to initiate command */
104 LMEM->PCCCR |= LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_INVW0_MASK;
105 LMEM->PCCCR |= LMEM_PCCCR_GO_MASK;
106 /* Wait until the command completes */
107 while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0UL)
108 {
109 }
110 /* Enable cache, enable write buffer */
111 LMEM->PCCCR |= (LMEM_PCCCR_ENWRBUF_MASK | LMEM_PCCCR_ENCACHE_MASK);
112
113 /* Enable System Bus Cache */
114 /* set command to invalidate all ways, and write GO bit to initiate command */
115 LMEM->PSCCR |= LMEM_PSCCR_INVW1_MASK | LMEM_PSCCR_INVW0_MASK;
116 LMEM->PSCCR |= LMEM_PSCCR_GO_MASK;
117 /* Wait until the command completes */
118 while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0UL)
119 {
120 }
121 /* Enable cache, enable write buffer */
122 LMEM->PSCCR |= (LMEM_PSCCR_ENWRBUF_MASK | LMEM_PSCCR_ENCACHE_MASK);
123 /* i.MX8QX systemInit */
124 }
125
126 /* ----------------------------------------------------------------------------
127 -- SystemCoreClockUpdate()
128 ---------------------------------------------------------------------------- */
129
SystemCoreClockUpdate(void)130 void SystemCoreClockUpdate(void)
131 {
132 /* i.MX8QX SystemCoreClockUpdate */
133 sc_err_t err;
134 uint32_t freq = SystemCoreClock;
135
136 err = sc_pm_get_clock_rate(ipcHandle, SC_R_M4_0_PID0, SC_PM_CLK_CPU, &freq);
137
138 if (SC_ERR_NONE == err)
139 {
140 SystemCoreClock = freq;
141 }
142 }
143
144 /* ----------------------------------------------------------------------------
145 -- SystemInitScfwIpc()
146 ---------------------------------------------------------------------------- */
147
SystemInitScfwIpc(void)148 void SystemInitScfwIpc(void)
149 {
150 sc_ipc_t ipc;
151 sc_err_t err;
152
153 err = sc_ipc_open(&ipc, (sc_ipc_id_t)CM4__MU1_A);
154
155 if (err == SC_ERR_NONE)
156 {
157 ipcHandle = ipc;
158 }
159 else
160 {
161 ipcHandle = 0;
162 }
163 }
164
165 /* ----------------------------------------------------------------------------
166 -- SystemGetScfwIpcHandle()
167 ---------------------------------------------------------------------------- */
168
SystemGetScfwIpcHandle(void)169 sc_ipc_t SystemGetScfwIpcHandle(void)
170 {
171 return ipcHandle;
172 }
173
