1 /*
2 ** ###################################################################
3 ** Processors: MIMX8QX1AVLFZ
4 ** MIMX8QX1AVOFZ
5 **
6 ** Compilers: GNU C Compiler
7 ** IAR ANSI C/C++ Compiler for ARM
8 ** Keil ARM C/C++ Compiler
9 **
10 ** Reference manual: IMX8DQXPRM, Rev. E, 6/2019
11 ** Version: rev. 4.0, 2020-06-19
12 ** Build: b200806
13 **
14 ** Abstract:
15 ** Provides a system configuration function and a global variable that
16 ** contains the system frequency. It configures the device and initializes
17 ** the oscillator (PLL) that is part of the microcontroller device.
18 **
19 ** Copyright 2016 Freescale Semiconductor, Inc.
20 ** Copyright 2016-2020 NXP
21 ** All rights reserved.
22 **
23 ** SPDX-License-Identifier: BSD-3-Clause
24 **
25 ** http: www.nxp.com
26 ** mail: support@nxp.com
27 **
28 ** Revisions:
29 ** - rev. 1.0 (2016-06-02)
30 ** Initial version.
31 ** - rev. 2.0 (2017-08-23)
32 ** RevA Header EAR
33 ** - rev. 3.0 (2018-08-22)
34 ** RevB Header EAR
35 ** - rev. 4.0 (2020-06-19)
36 ** RevC Header RFP
37 **
38 ** ###################################################################
39 */
40
41 /*!
42 * @file MIMX8QX1_cm4
43 * @version 1.0
44 * @date 060820
45 * @brief Device specific configuration file for MIMX8QX1_cm4 (implementation file)
46 *
47 * Provides a system configuration function and a global variable that contains
48 * the system frequency. It configures the device and initializes the oscillator
49 * (PLL) that is part of the microcontroller device.
50 */
51
52 #include <stdint.h>
53 #include "fsl_device_registers.h"
54
55 /* ----------------------------------------------------------------------------
56 -- Core clock
57 ---------------------------------------------------------------------------- */
58
59 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
60 static sc_ipc_t ipcHandle;
61
62 /* ----------------------------------------------------------------------------
63 -- SystemInit()
64 ---------------------------------------------------------------------------- */
65
SystemInit(void)66 void SystemInit(void)
67 {
68 #if (ENABLE_ECC_DEBUG)
69 volatile uint32_t *p = (uint32_t *)0xE0080480U;
70
71 /* Configure LMEM Parity/ECC Control Register
72 ;
73 ; Note: ECC Multi-bit IRQ should be disabled
74 ; prior to list/dump of locations that
75 ; have not been written to avoid vectoring
76 ; to the NMI
77 ;
78 ; 31:22 RESERVED
79 ; 21 Enable Cache Parity IRQ
80 ; 20 Enable Cache Parity Report
81 ; 19:17 RESERVED
82 ; 16 Enable RAM Parity Reporting
83 ; 15:10 RESERVED
84 ; 9 Enable RAM ECC 1-bit IRQ
85 ; 8 Enable RAM ECC 1-bit Report
86 ; 7:2 RESERVED
87 ; 1 Enable RAM ECC Multi-bit IRQ
88 ; 0 Enable RAM ECC Multi-bit
89 */
90 *p = 0x00300003;
91 #endif
92
93 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
94 SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access */
95 #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
96
97 #if (DISABLE_WDOG)
98 CM4__WDOG->CNT = WDOG_UPDATE_KEY;
99 CM4__WDOG->TOVAL = 0xFFFF;
100 CM4__WDOG->CS = (uint32_t)((CM4__WDOG->CS) & ~WDOG_CS_EN_MASK) | WDOG_CS_UPDATE_MASK;
101 #endif /* (DISABLE_WDOG) */
102
103 /* Initialize Cache */
104 /* Enable Code Bus Cache */
105 /* set command to invalidate all ways, and write GO bit to initiate command */
106 LMEM->PCCCR |= LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_INVW0_MASK;
107 LMEM->PCCCR |= LMEM_PCCCR_GO_MASK;
108 /* Wait until the command completes */
109 while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0UL)
110 {
111 }
112 /* Enable cache, enable write buffer */
113 LMEM->PCCCR |= (LMEM_PCCCR_ENWRBUF_MASK | LMEM_PCCCR_ENCACHE_MASK);
114
115 /* Enable System Bus Cache */
116 /* set command to invalidate all ways, and write GO bit to initiate command */
117 LMEM->PSCCR |= LMEM_PSCCR_INVW1_MASK | LMEM_PSCCR_INVW0_MASK;
118 LMEM->PSCCR |= LMEM_PSCCR_GO_MASK;
119 /* Wait until the command completes */
120 while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0UL)
121 {
122 }
123 /* Enable cache, enable write buffer */
124 LMEM->PSCCR |= (LMEM_PSCCR_ENWRBUF_MASK | LMEM_PSCCR_ENCACHE_MASK);
125 /* i.MX8QX systemInit */
126 }
127
128 /* ----------------------------------------------------------------------------
129 -- SystemCoreClockUpdate()
130 ---------------------------------------------------------------------------- */
131
SystemCoreClockUpdate(void)132 void SystemCoreClockUpdate(void)
133 {
134 /* i.MX8QX SystemCoreClockUpdate */
135 sc_err_t err;
136 uint32_t freq = SystemCoreClock;
137
138 err = sc_pm_get_clock_rate(ipcHandle, SC_R_M4_0_PID0, SC_PM_CLK_CPU, &freq);
139
140 if (SC_ERR_NONE == err)
141 {
142 SystemCoreClock = freq;
143 }
144 }
145
146 /* ----------------------------------------------------------------------------
147 -- SystemInitScfwIpc()
148 ---------------------------------------------------------------------------- */
149
SystemInitScfwIpc(void)150 void SystemInitScfwIpc(void)
151 {
152 sc_ipc_t ipc;
153 sc_err_t err;
154
155 err = sc_ipc_open(&ipc, (sc_ipc_id_t)CM4__MU1_A);
156
157 if (err == SC_ERR_NONE)
158 {
159 ipcHandle = ipc;
160 }
161 else
162 {
163 ipcHandle = 0;
164 }
165 }
166
167 /* ----------------------------------------------------------------------------
168 -- SystemGetScfwIpcHandle()
169 ---------------------------------------------------------------------------- */
170
SystemGetScfwIpcHandle(void)171 sc_ipc_t SystemGetScfwIpcHandle(void)
172 {
173 return ipcHandle;
174 }
175
