1 /* 2 ** ################################################################### 3 ** Version: rev. 2.0, 2019-09-23 4 ** Build: b211028 5 ** 6 ** Abstract: 7 ** Chip specific module features. 8 ** 9 ** Copyright 2016 Freescale Semiconductor, Inc. 10 ** Copyright 2016-2021 NXP 11 ** All rights reserved. 12 ** 13 ** SPDX-License-Identifier: BSD-3-Clause 14 ** 15 ** http: www.nxp.com 16 ** mail: support@nxp.com 17 ** 18 ** Revisions: 19 ** - rev. 1.0 (2019-04-22) 20 ** Initial version. 21 ** - rev. 2.0 (2019-09-23) 22 ** Rev.B Header RFP 23 ** 24 ** ################################################################### 25 */ 26 27 #ifndef _MIMX8MN6_ca53_FEATURES_H_ 28 #define _MIMX8MN6_ca53_FEATURES_H_ 29 30 /* SOC module features */ 31 32 /* @brief AIPSTZ availability on the SoC. */ 33 #define FSL_FEATURE_SOC_AIPSTZ_COUNT (1) 34 /* @brief APBH availability on the SoC. */ 35 #define FSL_FEATURE_SOC_APBH_COUNT (1) 36 /* @brief ASRC availability on the SoC. */ 37 #define FSL_FEATURE_SOC_ASRC_COUNT (1) 38 /* @brief BCH availability on the SoC. */ 39 #define FSL_FEATURE_SOC_BCH_COUNT (1) 40 /* @brief CCM availability on the SoC. */ 41 #define FSL_FEATURE_SOC_CCM_COUNT (1) 42 /* @brief CCM_ANALOG availability on the SoC. */ 43 #define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1) 44 /* @brief ECSPI availability on the SoC. */ 45 #define FSL_FEATURE_SOC_ECSPI_COUNT (3) 46 /* @brief ENET availability on the SoC. */ 47 #define FSL_FEATURE_SOC_ENET_COUNT (1) 48 /* @brief GPC availability on the SoC. */ 49 #define FSL_FEATURE_SOC_GPC_COUNT (1) 50 /* @brief GPC_PGC availability on the SoC. */ 51 #define FSL_FEATURE_SOC_GPC_PGC_COUNT (1) 52 /* @brief GPMI availability on the SoC. */ 53 #define FSL_FEATURE_SOC_GPMI_COUNT (1) 54 /* @brief GPT availability on the SoC. */ 55 #define FSL_FEATURE_SOC_GPT_COUNT (6) 56 /* @brief I2S availability on the SoC. */ 57 #define FSL_FEATURE_SOC_I2S_COUNT (5) 58 /* @brief IGPIO availability on the SoC. */ 59 #define FSL_FEATURE_SOC_IGPIO_COUNT (5) 60 /* @brief II2C availability on the SoC. */ 61 #define FSL_FEATURE_SOC_II2C_COUNT (4) 62 /* @brief IOMUXC availability on the SoC. */ 63 #define FSL_FEATURE_SOC_IOMUXC_COUNT (1) 64 /* @brief IOMUXC_GPR availability on the SoC. */ 65 #define FSL_FEATURE_SOC_IOMUXC_GPR_COUNT (1) 66 /* @brief IPWM availability on the SoC. */ 67 #define FSL_FEATURE_SOC_IPWM_COUNT (4) 68 /* @brief ISI availability on the SoC. */ 69 #define FSL_FEATURE_SOC_ISI_COUNT (1) 70 /* @brief IUART availability on the SoC. */ 71 #define FSL_FEATURE_SOC_IUART_COUNT (4) 72 /* @brief LCDIF availability on the SoC. */ 73 #define FSL_FEATURE_SOC_LCDIF_COUNT (1) 74 /* @brief MU availability on the SoC. */ 75 #define FSL_FEATURE_SOC_MU_COUNT (1) 76 /* @brief OCOTP availability on the SoC. */ 77 #define FSL_FEATURE_SOC_OCOTP_COUNT (1) 78 /* @brief PDM availability on the SoC. */ 79 #define FSL_FEATURE_SOC_PDM_COUNT (1) 80 /* @brief RDC availability on the SoC. */ 81 #define FSL_FEATURE_SOC_RDC_COUNT (1) 82 /* @brief RDC_SEMAPHORE availability on the SoC. */ 83 #define FSL_FEATURE_SOC_RDC_SEMAPHORE_COUNT (2) 84 /* @brief SDMA availability on the SoC. */ 85 #define FSL_FEATURE_SOC_SDMA_COUNT (3) 86 /* @brief SEMA4 availability on the SoC. */ 87 #define FSL_FEATURE_SOC_SEMA4_COUNT (1) 88 /* @brief SNVS availability on the SoC. */ 89 #define FSL_FEATURE_SOC_SNVS_COUNT (1) 90 /* @brief SPBA availability on the SoC. */ 91 #define FSL_FEATURE_SOC_SPBA_COUNT (2) 92 /* @brief SPDIF availability on the SoC. */ 93 #define FSL_FEATURE_SOC_SPDIF_COUNT (2) 94 /* @brief SRC availability on the SoC. */ 95 #define FSL_FEATURE_SOC_SRC_COUNT (1) 96 /* @brief USB availability on the SoC. */ 97 #define FSL_FEATURE_SOC_USB_COUNT (1) 98 /* @brief USBNC availability on the SoC. */ 99 #define FSL_FEATURE_SOC_USBNC_COUNT (1) 100 /* @brief USDHC availability on the SoC. */ 101 #define FSL_FEATURE_SOC_USDHC_COUNT (3) 102 /* @brief WDOG availability on the SoC. */ 103 #define FSL_FEATURE_SOC_WDOG_COUNT (3) 104 /* @brief XTALOSC availability on the SoC. */ 105 #define FSL_FEATURE_SOC_XTALOSC_COUNT (1) 106 107 /* CCM module features */ 108 109 /* @brief Is affected by errata with ID 50235 (Incorrect clock setting for CAN affects by LPUART clock gate). */ 110 #define FSL_FEATURE_CCM_HAS_ERRATA_50235 (0) 111 112 /* ECSPI module features */ 113 114 /* @brief ECSPI Tx FIFO Size. */ 115 #define FSL_FEATURE_ECSPI_TX_FIFO_SIZEn(x) (64) 116 117 /* ENET module features */ 118 119 /* @brief Support Interrupt Coalesce */ 120 #define FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE (1) 121 /* @brief Queue Size. */ 122 #define FSL_FEATURE_ENET_QUEUE (3) 123 /* @brief Has AVB Support. */ 124 #define FSL_FEATURE_ENET_HAS_AVB (1) 125 /* @brief Has Timer Pulse Width control. */ 126 #define FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL (0) 127 /* @brief Has Extend MDIO Support. */ 128 #define FSL_FEATURE_ENET_HAS_EXTEND_MDIO (1) 129 /* @brief Has Additional 1588 Timer Channel Interrupt. */ 130 #define FSL_FEATURE_ENET_HAS_ADD_1588_TIMER_CHN_INT (1) 131 /* @brief Support Interrupt Coalesce for each instance */ 132 #define FSL_FEATURE_ENET_INSTANCE_HAS_INTERRUPT_COALESCEn(x) (1) 133 /* @brief Queue Size for each instance. */ 134 #define FSL_FEATURE_ENET_INSTANCE_QUEUEn(x) (3) 135 /* @brief Has AVB Support for each instance. */ 136 #define FSL_FEATURE_ENET_INSTANCE_HAS_AVBn(x) (1) 137 /* @brief Has Timer Pulse Width control for each instance. */ 138 #define FSL_FEATURE_ENET_INSTANCE_HAS_TIMER_PWCONTROLn(x) (0) 139 /* @brief Has Extend MDIO Support for each instance. */ 140 #define FSL_FEATURE_ENET_INSTANCE_HAS_EXTEND_MDIOn(x) (1) 141 /* @brief Has Additional 1588 Timer Channel Interrupt for each instance. */ 142 #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (1) 143 /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ 144 #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) 145 /* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ 146 #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (0) 147 /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ 148 #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0) 149 /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ 150 #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0) 151 152 /* GPC module features */ 153 154 /* @brief Has PGC MF. */ 155 #define FSL_FEATURE_GPC_HAS_PGC_MF (0) 156 157 /* IGPIO module features */ 158 159 /* @brief Has data register set DR_SET. */ 160 #define FSL_FEATURE_IGPIO_HAS_DR_SET (0) 161 /* @brief Has data register clear DR_CLEAR. */ 162 #define FSL_FEATURE_IGPIO_HAS_DR_CLEAR (0) 163 /* @brief Has data register toggle DR_TOGGLE. */ 164 #define FSL_FEATURE_IGPIO_HAS_DR_TOGGLE (0) 165 166 /* SAI module features */ 167 168 /* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ 169 #define FSL_FEATURE_SAI_HAS_FIFO (1) 170 /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ 171 #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (128) 172 /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ 173 #define FSL_FEATURE_SAI_CHANNEL_COUNTn(x) (4) 174 /* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ 175 #define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32) 176 /* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ 177 #define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (1) 178 /* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ 179 #define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1) 180 /* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ 181 #define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1) 182 /* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ 183 #define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1) 184 /* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ 185 #define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) 186 /* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */ 187 #define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0) 188 /* @brief Interrupt source number */ 189 #define FSL_FEATURE_SAI_INT_SOURCE_NUM (1) 190 /* @brief Has register of MCR. */ 191 #define FSL_FEATURE_SAI_HAS_MCR (1) 192 /* @brief Has bit field MICS of the MCR register. */ 193 #define FSL_FEATURE_SAI_HAS_NO_MCR_MICS (1) 194 /* @brief Has register of MDR */ 195 #define FSL_FEATURE_SAI_HAS_MDR (0) 196 /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ 197 #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) 198 /* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ 199 #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) 200 /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ 201 #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) 202 /* @brief SAI5 AND SAI6 SHARE ONE IRQNUMBER. */ 203 #define FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ (1) 204 205 /* ISI module features */ 206 207 /* No feature definitions */ 208 209 /* CACHE module features */ 210 211 /* @brief L1 ICACHE line size in byte. */ 212 #define FSL_FEATURE_L1ICACHE_LINESIZE_BYTE (64) 213 /* @brief L1 DCACHE line size in byte. */ 214 #define FSL_FEATURE_L1DCACHE_LINESIZE_BYTE (64) 215 /* @brief Has no NONCACHEABLE section. */ 216 #define FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION (0) 217 218 /* MEMORY module features */ 219 220 /* @brief Memory map doesn't have offset between subsystems. */ 221 #define FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET (0) 222 223 /* MU module features */ 224 225 /* @brief MU side for current core */ 226 #define FSL_FEATURE_MU_SIDE_B (1) 227 /* @brief MU Has register CCR */ 228 #define FSL_FEATURE_MU_HAS_CCR (0) 229 /* @brief MU Has register SR[RS], BSR[ARS] */ 230 #define FSL_FEATURE_MU_HAS_SR_RS (1) 231 /* @brief MU Has register CR[RDIE], CR[RAIE], SR[RDIP], SR[RAIP] */ 232 #define FSL_FEATURE_MU_HAS_RESET_INT (0) 233 /* @brief MU Has register SR[MURIP] */ 234 #define FSL_FEATURE_MU_HAS_SR_MURIP (0) 235 /* @brief MU Has register SR[HRIP] */ 236 #define FSL_FEATURE_MU_HAS_SR_HRIP (0) 237 /* @brief MU does not support enable clock of the other core, CR[CLKE] or CCR[CLKE]. */ 238 #define FSL_FEATURE_MU_NO_CLKE (1) 239 /* @brief MU does not support NMI, CR[NMI]. */ 240 #define FSL_FEATURE_MU_NO_NMI (1) 241 /* @brief MU does not support hold the other core reset. CR[RSTH] or CCR[RSTH]. */ 242 #define FSL_FEATURE_MU_NO_RSTH (1) 243 /* @brief MU does not supports MU reset, CR[MUR]. */ 244 #define FSL_FEATURE_MU_NO_MUR (1) 245 /* @brief MU does not supports hardware reset, CR[HR] or CCR[HR]. */ 246 #define FSL_FEATURE_MU_NO_HR (1) 247 /* @brief MU supports mask the hardware reset. CR[HRM] or CCR[HRM]. */ 248 #define FSL_FEATURE_MU_HAS_HRM (1) 249 /* @brief MU does not support check the other core power mode. SR[PM] or BSR[APM]. */ 250 #define FSL_FEATURE_MU_NO_PM (0) 251 /* @brief MU supports reset assert interrupt. CR[RAIE] or BCR[RAIE]. */ 252 #define FSL_FEATURE_MU_HAS_RESET_ASSERT_INT (0) 253 /* @brief MU supports reset de-assert interrupt. CR[RDIE] or BCR[RDIE]. */ 254 #define FSL_FEATURE_MU_HAS_RESET_DEASSERT_INT (0) 255 256 /* PDM module features */ 257 258 /* @brief PDM FIFO offset */ 259 #define FSL_FEATURE_PDM_FIFO_OFFSET (4) 260 /* @brief PDM Channel Number */ 261 #define FSL_FEATURE_PDM_CHANNEL_NUM (8) 262 /* @brief PDM FIFO WIDTH Size */ 263 #define FSL_FEATURE_PDM_FIFO_WIDTH (2) 264 /* @brief PDM FIFO DEPTH Size */ 265 #define FSL_FEATURE_PDM_FIFO_DEPTH (8) 266 /* @brief PDM has RANGE_CTRL register */ 267 #define FSL_FEATURE_PDM_HAS_RANGE_CTRL (0) 268 /* @brief PDM Has Low Frequency */ 269 #define FSL_FEATURE_PDM_HAS_STATUS_LOW_FREQ (1) 270 /* @brief CLKDIV factor in Medium, High and Low Quality modes */ 271 #define FSL_FEATURE_PDM_HIGH_QUALITY_CLKDIV_FACTOR (125) 272 /* @brief CLKDIV factor in Very Low Quality modes */ 273 #define FSL_FEATURE_PDM_VERY_LOW_QUALITY_CLKDIV_FACTOR (19) 274 /* @brief PDM Has No VADEF Bitfield In PDM VAD0_STAT Register */ 275 #define FSL_FEATURE_PDM_HAS_NO_VADEF (0) 276 277 /* SDMA module features */ 278 279 /* @brief SDMA module channel number. */ 280 #define FSL_FEATURE_SDMA_MODULE_CHANNEL (32) 281 /* @brief SDMA module event number. */ 282 #define FSL_FEATURE_SDMA_EVENT_NUM (48) 283 /* @brief SDMA ROM memory to memory script start address. */ 284 #define FSL_FEATURE_SDMA_M2M_ADDR (644) 285 /* @brief SDMA ROM peripheral to memory script start address. */ 286 #define FSL_FEATURE_SDMA_P2M_ADDR (685) 287 /* @brief SDMA ROM memory to peripheral script start address. */ 288 #define FSL_FEATURE_SDMA_M2P_ADDR (749) 289 /* @brief SDMA ROM uart to memory script start address. */ 290 #define FSL_FEATURE_SDMA_UART2M_ADDR (819) 291 /* @brief SDMA ROM peripheral on SPBA to memory script start address. */ 292 #define FSL_FEATURE_SDMA_SHP2M_ADDR (893) 293 /* @brief SDMA ROM memory to peripheral on SPBA script start address. */ 294 #define FSL_FEATURE_SDMA_M2SHP_ADDR (962) 295 /* @brief SDMA ROM UART on SPBA to memory script start address. */ 296 #define FSL_FEATURE_SDMA_UARTSH2M_ADDR (1034) 297 /* @brief SDMA ROM SPDIF to memory script start address. */ 298 #define FSL_FEATURE_SDMA_SPDIF2M_ADDR (1102) 299 /* @brief SDMA ROM memory to SPDIF script start address. */ 300 #define FSL_FEATURE_SDMA_M2SPDIF_ADDR (1136) 301 /* @brief SDMA ROM memory to MULTI_FIFO_SAI_TX script start address. */ 302 #define FSL_FEATURE_SDMA_MULTI_FIFO_SAI_TX_ADDR (6235) 303 /* @brief SDMA ROM memory to MULTI_FIFO_SAI_RX script start address. */ 304 #define FSL_FEATURE_SDMA_MULTI_FIFO_SAI_RX_ADDR (6729) 305 306 /* SEMA4 module features */ 307 308 /* @brief Gate counts */ 309 #define FSL_FEATURE_SEMA4_GATE_COUNT (16) 310 311 /* SPBA module features */ 312 313 /* @brief SPBA module start address. */ 314 #define FSL_FEATURE_SPBA_STARTn(x) \ 315 (((x) == SPBA2) ? (0x30000000) : \ 316 (((x) == SPBA1) ? (0x30800000) : (-1))) 317 /* @brief SPBA module end address. */ 318 #define FSL_FEATURE_SPBA_ENDn(x) \ 319 (((x) == SPBA2) ? (0x300FFFFF) : \ 320 (((x) == SPBA1) ? (0x308FFFFF) : (-1))) 321 322 /* IUART module features */ 323 324 /* @brief UART Transmit/Receive FIFO Size */ 325 #define FSL_FEATURE_IUART_FIFO_SIZEn(x) (32) 326 /* @brief UART RX MUXed input selected option */ 327 #define FSL_FEATURE_IUART_RXDMUXSEL (1) 328 329 /* USDHC module features */ 330 331 /* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */ 332 #define FSL_FEATURE_USDHC_HAS_EXT_DMA (1) 333 /* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */ 334 #define FSL_FEATURE_USDHC_HAS_HS400_MODE (1) 335 /* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */ 336 #define FSL_FEATURE_USDHC_HAS_SDR50_MODE (1) 337 /* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */ 338 #define FSL_FEATURE_USDHC_HAS_SDR104_MODE (1) 339 /* @brief USDHC has reset control */ 340 #define FSL_FEATURE_USDHC_HAS_RESET (0) 341 /* @brief USDHC has no bitfield WTMK_LVL[WR_BRST_LEN] and WTMK_LVL[RD_BRST_LEN] */ 342 #define FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN (0) 343 /* @brief If USDHC instance support 8 bit width */ 344 #define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_8_BIT_WIDTHn(x) (1) 345 /* @brief If USDHC instance support HS400 mode */ 346 #define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn(x) (0) 347 /* @brief If USDHC instance support 1v8 signal */ 348 #define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_1V8_SIGNALn(x) (1) 349 /* @brief Has no retuning time counter (HOST_CTRL_CAP[TIME_COUNT_RETURNING]) */ 350 #define FSL_FEATURE_USDHC_REGISTER_HOST_CTRL_CAP_HAS_NO_RETUNING_TIME_COUNTER (0) 351 352 #endif /* _MIMX8MN6_ca53_FEATURES_H_ */ 353 354
