1 /*
2 * Copyright 2018-2021 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include "fsl_common.h"
9 #include "fsl_debug_console.h"
10 #include "fsl_rdc.h"
11 #include "fsl_iomuxc.h"
12 #include "pin_mux.h"
13 #include "board.h"
14 #include "fsl_clock.h"
15
16 /*******************************************************************************
17 * Variables
18 ******************************************************************************/
19
20 /*******************************************************************************
21 * Code
22 ******************************************************************************/
23 /* Initialize debug console. */
BOARD_InitDebugConsole(void)24 void BOARD_InitDebugConsole(void)
25 {
26 uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
27 CLOCK_EnableClock(kCLOCK_Uart4);
28 DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
29 }
30
31 /* Initialize MPU, configure memory attributes for each region */
BOARD_InitMemory(void)32 void BOARD_InitMemory(void)
33 {
34 /* Disable I cache and D cache */
35 if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR))
36 {
37 SCB_DisableICache();
38 }
39 if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR))
40 {
41 SCB_DisableDCache();
42 }
43
44 /* Disable MPU */
45 ARM_MPU_Disable();
46
47 /* MPU configure:
48 * Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable,
49 * SubRegionDisable, Size)
50 * API in mpu_armv7.h.
51 * param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches
52 * disabled.
53 * param AccessPermission Data access permissions, allows you to configure read/write access for User and
54 * Privileged mode.
55 * Use MACROS defined in mpu_armv7.h:
56 * ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
57 * Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes.
58 * TypeExtField IsShareable IsCacheable IsBufferable Memory Attribute Shareability Cache
59 * 0 x 0 0 Strongly Ordered shareable
60 * 0 x 0 1 Device shareable
61 * 0 0 1 0 Normal not shareable Outer and inner write
62 * through no write allocate
63 * 0 0 1 1 Normal not shareable Outer and inner write
64 * back no write allocate
65 * 0 1 1 0 Normal shareable Outer and inner write
66 * through no write allocate
67 * 0 1 1 1 Normal shareable Outer and inner write
68 * back no write allocate
69 * 1 0 0 0 Normal not shareable outer and inner
70 * noncache
71 * 1 1 0 0 Normal shareable outer and inner
72 * noncache
73 * 1 0 1 1 Normal not shareable outer and inner write
74 * back write/read acllocate
75 * 1 1 1 1 Normal shareable outer and inner write
76 * back write/read acllocate
77 * 2 x 0 0 Device not shareable
78 * Above are normal use settings, if your want to see more details or want to config different inner/outter cache
79 * policy.
80 * please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide <dui0646b_cortex_m7_dgug.pdf>
81 * param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled.
82 * param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in
83 * mpu_armv7.h.
84 */
85
86 /* Region 0 [0x0000_0000 - 0x4000_0000] : Memory with Device type, not executable, not shareable, non-cacheable. */
87 MPU->RBAR = ARM_MPU_RBAR(0, 0x00000000U);
88 MPU->RASR = ARM_MPU_RASR(1, ARM_MPU_AP_FULL, 0, 0, 0, 1, 0, ARM_MPU_REGION_SIZE_1GB);
89
90 /* Region 1 TCML[0x0000_0000 - 0x0001_FFFF]: Memory with Normal type, shareable, non-cacheable */
91 MPU->RBAR = ARM_MPU_RBAR(1, 0x00000000U);
92 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 1, 0, 0, 0, ARM_MPU_REGION_SIZE_128KB);
93
94 /* Region 2 QSPI[0x0800_0000 - 0x0FFF_FFFF]: Memory with Normal type, shareable, non-cacheable */
95 MPU->RBAR = ARM_MPU_RBAR(2, 0x08000000U);
96 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 1, 0, 0, 0, ARM_MPU_REGION_SIZE_128MB);
97
98 /* Region 3 TCMU[0x2000_0000 - 0x2002_0000]: Memory with Normal type, shareable, non-cacheable */
99 MPU->RBAR = ARM_MPU_RBAR(3, 0x20000000U);
100 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 1, 0, 0, 0, ARM_MPU_REGION_SIZE_128KB);
101
102 /* Region 4 DDR[0x4000_0000 - 0x8000_0000]: Memory with Normal type, shareable, non-cacheable */
103 MPU->RBAR = ARM_MPU_RBAR(4, 0x40000000U);
104 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 1, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
105
106 /* Region 5 DDR[0x8000_0000 - 0xF000_0000]: Memory with Normal type, shareable, non-cacheable */
107 MPU->RBAR = ARM_MPU_RBAR(5, 0x80000000U);
108 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 1, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
109
110 /*
111 * Enable MPU and HFNMIENA feature
112 * HFNMIENA ensures that M7 core uses MPU configuration when in hard fault, NMI, and FAULTMASK handlers,
113 * otherwise all memory regions are accessed without MPU protection, which has high risks of cacheable,
114 * especially for AIPS systems.
115 */
116 ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk);
117
118 /* Configure the force_incr programmable bit in GPV_5 of PL301_display, which fixes partial write issue.
119 * The AXI2AHB bridge is used for masters that access the TCM through system bus.
120 * Please refer to errata ERR050362 for more information */
121 /* Only configure the GPV5 if the M core access type is secure. */
122 if ((*(uint32_t *)(CSU_SA_ADDR)&CSU_SA_NSN_M_BIT_MASK) == 0U)
123 {
124 *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) =
125 *(uint32_t *)(GPV5_BASE_ADDR + FORCE_INCR_OFFSET) | FORCE_INCR_BIT_MASK;
126 }
127 }
128
BOARD_RdcInit(void)129 void BOARD_RdcInit(void)
130 {
131 /* Move M7 core to specific RDC domain 1 */
132 rdc_domain_assignment_t assignment = {0};
133 uint8_t domainId = 0U;
134
135 domainId = RDC_GetCurrentMasterDomainId(RDC);
136 /* Only configure the RDC if RDC peripheral write access is allowed. */
137 if ((0x1U & RDC_GetPeriphAccessPolicy(RDC, kRDC_Periph_RDC, domainId)) != 0U)
138 {
139 assignment.domainId = BOARD_DOMAIN_ID;
140 RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M7, &assignment);
141 }
142
143 /*
144 * The M7 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in domain 1 in the CCM.
145 * In this way, to ensure the clock of the peripherals used by M core not be affected by A core which is running at
146 * domain 0.
147 */
148 CLOCK_EnableClock(kCLOCK_Iomux);
149
150 CLOCK_EnableClock(kCLOCK_Ipmux1);
151 CLOCK_EnableClock(kCLOCK_Ipmux2);
152 CLOCK_EnableClock(kCLOCK_Ipmux3);
153 CLOCK_EnableClock(kCLOCK_Ipmux4);
154
155 #if defined(FLASH_TARGET)
156 CLOCK_EnableClock(kCLOCK_Qspi);
157 #endif
158
159 CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL1 in Domain 1 */
160 CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL2 in Domain 1 */
161 CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for SysPLL3 in Domain 1 */
162 CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL1 in Domain 1 */
163 CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for AudioPLL2 in Domain 1 */
164 CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable the CCGR gate for VideoPLL1 in Domain 1 */
165 }
166
