1 /*
2 * Copyright 2018 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include "fsl_common.h"
9 #include "clock_config.h"
10
11 /*******************************************************************************
12 * Definitions
13 ******************************************************************************/
14 /* Fractional PLLs: Fout = ((mainDiv+dsm/65536) * refSel) / (preDiv * 2^ postDiv) */
15 /* AUDIO PLL1 configuration */
16 const ccm_analog_frac_pll_config_t g_audioPll1Config = {
17 .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
18 .mainDiv = 262U,
19 .dsm = 9437U,
20 .preDiv = 2U,
21 .postDiv = 3U, /*!< AUDIO PLL1 frequency = 393215996HZ */
22 };
23
24 /* AUDIO PLL2 configuration */
25 const ccm_analog_frac_pll_config_t g_audioPll2Config = {
26 .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
27 .mainDiv = 361U,
28 .dsm = 17511U,
29 .preDiv = 3U,
30 .postDiv = 3U, /*!< AUDIO PLL2 frequency = 361267197HZ */
31 };
32
33 /* Integer PLLs: Fout = (mainDiv * refSel) / (preDiv * 2^ postDiv) */
34 /* SYSTEM PLL1 configuration */
35 const ccm_analog_integer_pll_config_t g_sysPll1Config = {
36 .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
37 .mainDiv = 400U,
38 .preDiv = 3U,
39 .postDiv = 2U, /*!< SYSTEM PLL1 frequency = 800MHZ */
40 };
41
42 /* SYSTEM PLL2 configuration */
43 const ccm_analog_integer_pll_config_t g_sysPll2Config = {
44 .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
45 .mainDiv = 250U,
46 .preDiv = 3U,
47 .postDiv = 1U, /*!< SYSTEM PLL2 frequency = 1000MHZ */
48 };
49
50 /* SYSTEM PLL3 configuration */
51 const ccm_analog_integer_pll_config_t g_sysPll3Config = {
52 .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
53 .mainDiv = 300,
54 .preDiv = 3U,
55 .postDiv = 2U, /*!< SYSTEM PLL3 frequency = 600MHZ */
56 };
57
58 /*******************************************************************************
59 * Variables
60 ******************************************************************************/
61
62 /*******************************************************************************
63 * Code
64 ******************************************************************************/
BOARD_BootClockRUN(void)65 void BOARD_BootClockRUN(void)
66 {
67 /* * The following steps just show how to configure the PLL clock sources using the clock driver on M7 core side .
68 * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core
69 * would enable the Div output for SYSTEM PLL1 & PLL2 by U-Boot.
70 * Therefore, there is no need to configure the system PLL again on M7 side, otherwise it would have a risk to make
71 * the SOC hang.
72 */
73
74 /* switch AHB NOC root to 24M first in order to configure the SYSTEM PLL1. */
75 CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc24M);
76
77 /* switch AXI M7 root to 24M first in order to configure the SYSTEM PLL2. */
78 CLOCK_SetRootMux(kCLOCK_RootM7, kCLOCK_M7RootmuxOsc24M);
79
80 /* Init Audio PLL1/Audio PLL2 */
81 CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 393215996HZ */
82 CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 361267197HZ */
83
84 CLOCK_SetRootDivider(kCLOCK_RootM7, 1U, 1U); /* Set M7 root clock freq to 600M / 1 = 600M */
85 CLOCK_SetRootMux(kCLOCK_RootM7, kCLOCK_M7RootmuxSysPll3); /* switch cortex-m7 to SYSTEM PLL3 */
86
87 CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U); /* Set root clock freq to 133M / 1= 133MHZ */
88 CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 */
89
90 CLOCK_SetRootDivider(kCLOCK_RootAudioAhb, 1U, 2U); /* Set root clock freq to 800MHZ/ 2= 400MHZ*/
91 CLOCK_SetRootMux(kCLOCK_RootAudioAhb, kCLOCK_AudioAhbRootmuxSysPll1); /* switch AUDIO AHB to SYSTEM PLL1 */
92
93 CLOCK_SetRootDivider(kCLOCK_RootUart4, 1U, 1U); /* Set root clock freq to 80MHZ/ 1= 80MHZ */
94 CLOCK_SetRootMux(kCLOCK_RootUart4, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */
95
96 CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */
97 CLOCK_EnableClock(kCLOCK_Ocram); /* Enable Ocram clock */
98
99 /* The purpose to enable the following modules clock is to make sure the M7 core could work normally when A53 core
100 * enters the low power status.*/
101 CLOCK_EnableClock(kCLOCK_Sim_display);
102 CLOCK_EnableClock(kCLOCK_Sim_m);
103 CLOCK_EnableClock(kCLOCK_Sim_main);
104 CLOCK_EnableClock(kCLOCK_Sim_s);
105 CLOCK_EnableClock(kCLOCK_Sim_wakeup);
106 CLOCK_EnableClock(kCLOCK_Debug);
107 CLOCK_EnableClock(kCLOCK_Dram);
108 CLOCK_EnableClock(kCLOCK_Sec_Debug);
109
110 /* Update core clock */
111 SystemCoreClockUpdate();
112 }
113
