1 /*
2 * Copyright 2018 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include "fsl_common.h"
9 #include "fsl_debug_console.h"
10 #include "fsl_rdc.h"
11 #include "fsl_iomuxc.h"
12 #include "pin_mux.h"
13 #include "board.h"
14 #include "fsl_clock.h"
15 /*******************************************************************************
16 * Variables
17 ******************************************************************************/
18
19 /*******************************************************************************
20 * Code
21 ******************************************************************************/
22 /* Initialize debug console. */
BOARD_InitDebugConsole(void)23 void BOARD_InitDebugConsole(void)
24 {
25 uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
26 CLOCK_EnableClock(kCLOCK_Uart4);
27 DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
28 }
29 /* Initialize MPU, configure non-cacheable memory */
BOARD_InitMemory(void)30 void BOARD_InitMemory(void)
31 {
32 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
33 extern uint32_t Load$$LR$$LR_cache_region$$Base[];
34 extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit[];
35 uint32_t cacheStart = (uint32_t)Load$$LR$$LR_cache_region$$Base;
36 uint32_t size = (cacheStart < 0x20000000U) ? (0) : ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Limit - cacheStart);
37 #else
38 extern uint32_t __CACHE_REGION_START[];
39 extern uint32_t __CACHE_REGION_SIZE[];
40 uint32_t cacheStart = (uint32_t)__CACHE_REGION_START;
41 uint32_t size = (uint32_t)__CACHE_REGION_SIZE;
42 #endif
43 uint32_t i = 0;
44 /* Make sure outstanding transfers are done. */
45 __DMB();
46 /* Disable the MPU. */
47 MPU->CTRL = 0;
48
49 /*
50 * The ARMv7-M default address map define the address space 0x20000000 to 0x3FFFFFFF as SRAM with Normal type, but
51 * there the address space 0x28000000 ~ 0x3FFFFFFF has been physically mapped to smart subsystems, so there need
52 * change the default memory attributes.
53 * Since the base address of MPU region should be multiples of region size, to make it simple, the MPU region 0 set
54 * the all 512M of SRAM space with device attributes, then disable subregion 0 and 1 (address space 0x20000000 ~
55 * 0x27FFFFFF) to use the
56 * background memory attributes.
57 */
58
59 /* Select Region 0 and set its base address to the M4 code bus start address. */
60 MPU->RBAR = (0x20000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (0 << MPU_RBAR_REGION_Pos);
61
62 /* Region 0 setting:
63 * 1) Disable Instruction Access;
64 * 2) AP = 011b, full access;
65 * 3) Non-shared device;
66 * 4) Region Not Shared;
67 * 5) Sub-Region 0,1 Disabled;
68 * 6) MPU Protection Region size = 512M byte;
69 * 7) Enable Region 0.
70 */
71 MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) |
72 (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
73
74 /*
75 * Non-cacheable area is provided in DDR memory, the DDR region 2MB - 128MB totally 126MB is revserved for CM4
76 * cores. You can put global or static uninitialized variables in NonCacheable section(initialized variables in
77 * NonCacheable.init section) to make them uncacheable. Since the base address of MPU region should be multiples of
78 * region size,
79 * to make it simple, the MPU region 1 & 2 set all DDR address space 0x40000000 ~ 0xBFFFFFFF to be non-cacheable).
80 * Then MPU region 3 set the text and data section to be cacheable if the program running on DDR.
81 * The cacheable area base address should be multiples of its size in linker file, they can be modified per your
82 * needs.
83 */
84
85 /* Select Region 1 and set its base address to the DDR start address. */
86 MPU->RBAR = (0x40000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (1 << MPU_RBAR_REGION_Pos);
87
88 /* Region 1 setting:
89 * 1) Enable Instruction Access;
90 * 2) AP = 011b, full access;
91 * 3) Shared Device;
92 * 4) MPU Protection Region size = 1024M byte;
93 * 5) Enable Region 1.
94 */
95 MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
96
97 /* Select Region 2 and set its base address to the DDR start address. */
98 MPU->RBAR = (0x80000000U & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (2 << MPU_RBAR_REGION_Pos);
99
100 /* Region 2 setting:
101 * 1) Enable Instruction Access;
102 * 2) AP = 011b, full access;
103 * 3) Shared Device;
104 * 4) MPU Protection Region size = 1024M byte;
105 * 5) Enable Region 2.
106 */
107 MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
108
109 while ((size >> i) > 0x1U)
110 {
111 i++;
112 }
113
114 /* If run on DDR, configure text and data section to be cacheable */
115 if (i != 0)
116 {
117 /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
118 assert((size & (size - 1)) == 0);
119 assert(!(cacheStart % size));
120 assert(size == (uint32_t)(1 << i));
121 assert(i >= 5);
122
123 /* Select Region 3 and set its base address to the cache able region start address. */
124 MPU->RBAR = (cacheStart & MPU_RBAR_ADDR_Msk) | MPU_RBAR_VALID_Msk | (3 << MPU_RBAR_REGION_Pos);
125
126 /* Region 3 setting:
127 * 1) Enable Instruction Access;
128 * 2) AP = 011b, full access;
129 * 3) Outer and inner Cacheable, write and read allocate;
130 * 4) Region Not Shared;
131 * 5) All Sub-Region Enabled;
132 * 6) MPU Protection Region size get from linker file;
133 * 7) Enable Region 3.
134 */
135 MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) |
136 (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk;
137 }
138
139 /* Enable Privileged default memory map and the MPU. */
140 MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
141 /* Memory barriers to ensure subsequence data & instruction
142 * transfers using updated MPU settings.
143 */
144 __DSB();
145 __ISB();
146 }
147
BOARD_RdcInit(void)148 void BOARD_RdcInit(void)
149 {
150 /* Move M4 core to specific RDC domain 1 */
151 rdc_domain_assignment_t assignment = {0};
152
153 assignment.domainId = BOARD_DOMAIN_ID;
154 RDC_SetMasterDomainAssignment(RDC, kRDC_Master_M4, &assignment);
155
156 /*
157 * The M4 core is running at domain 1, enable clock gate for Iomux to run at domain 1.
158 */
159 CLOCK_EnableClock(kCLOCK_Iomux0);
160 CLOCK_EnableClock(kCLOCK_Iomux1);
161 CLOCK_EnableClock(kCLOCK_Iomux2);
162 CLOCK_EnableClock(kCLOCK_Iomux3);
163 CLOCK_EnableClock(kCLOCK_Iomux4);
164
165 /*
166 * The M4 core is running at domain 1, enable the QSPI clock sources to domain 1 for flash target.
167 */
168 #if defined(FLASH_TARGET)
169 CLOCK_EnableClock(kCLOCK_Qspi);
170 #endif
171 /*
172 * The M4 core is running at domain 1, enable the PLL clock sources to domain 1.
173 */
174 CLOCK_ControlGate(kCLOCK_SysPll1Gate, kCLOCK_ClockNeededAll); /* Enabel SysPLL1 to Domain 1 */
175 CLOCK_ControlGate(kCLOCK_SysPll2Gate, kCLOCK_ClockNeededAll); /* Enable SysPLL2 to Domain 1 */
176 CLOCK_ControlGate(kCLOCK_SysPll3Gate, kCLOCK_ClockNeededAll); /* Enable SysPLL3 to Domain 1 */
177 CLOCK_ControlGate(kCLOCK_AudioPll1Gate, kCLOCK_ClockNeededAll); /* Enable AudioPLL1 to Domain 1 */
178 CLOCK_ControlGate(kCLOCK_AudioPll2Gate, kCLOCK_ClockNeededAll); /* Enable AudioPLL2 to Domain 1 */
179 CLOCK_ControlGate(kCLOCK_VideoPll1Gate, kCLOCK_ClockNeededAll); /* Enable VideoPLL1 to Domain 1 */
180 }
181
