1 /*
2 * Copyright 2019-2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include "fsl_common.h"
9 #include "clock_config.h"
10 #include "fsl_audiomix.h"
11 /*******************************************************************************
12 * Definitions
13 ******************************************************************************/
14 /* Fractional PLLs: Fout = ((mainDiv+dsm/65536) * refSel) / (preDiv * 2^ postDiv) */
15 /* AUDIO PLL1 configuration */
16 const ccm_analog_frac_pll_config_t g_audioPll1Config = {
17 .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
18 .mainDiv = 262U,
19 .dsm = 9437U,
20 .preDiv = 2U,
21 .postDiv = 3U, /*!< AUDIO PLL1 frequency = 393216000HZ */
22 };
23
24 /* AUDIO PLL2 configuration */
25 const ccm_analog_frac_pll_config_t g_audioPll2Config = {
26 .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
27 .mainDiv = 361U,
28 .dsm = 17511U,
29 .preDiv = 3U,
30 .postDiv = 3U, /*!< AUDIO PLL2 frequency = 361267200HZ */
31 };
32
33 /* AUDIOMIX SAI PLL configuration */
34 const ccm_analog_frac_pll_config_t g_saiPLLConfig = {
35 .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
36 .mainDiv = 361U,
37 .dsm = 17511U,
38 .preDiv = 3U,
39 .postDiv = 3U, /*!< SAI PLL frequency = 361267200HZ */
40 };
41 /* Integer PLLs: Fout = (mainDiv * refSel) / (preDiv * 2^ postDiv) */
42 /* SYSTEM PLL1 configuration */
43 const ccm_analog_integer_pll_config_t g_sysPll1Config = {
44 .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
45 .mainDiv = 400U,
46 .preDiv = 3U,
47 .postDiv = 2U, /*!< SYSTEM PLL1 frequency = 800MHZ */
48 };
49
50 /* SYSTEM PLL2 configuration */
51 const ccm_analog_integer_pll_config_t g_sysPll2Config = {
52 .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
53 .mainDiv = 250U,
54 .preDiv = 3U,
55 .postDiv = 1U, /*!< SYSTEM PLL2 frequency = 1000MHZ */
56 };
57
58 /* SYSTEM PLL3 configuration */
59 const ccm_analog_integer_pll_config_t g_sysPll3Config = {
60 .refSel = kANALOG_PllRefOsc24M, /*!< PLL reference OSC24M */
61 .mainDiv = 300,
62 .preDiv = 3U,
63 .postDiv = 2U, /*!< SYSTEM PLL3 frequency = 600MHZ */
64 };
65
66 /*******************************************************************************
67 * Variables
68 ******************************************************************************/
69
70 /*******************************************************************************
71 * Code
72 ******************************************************************************/
BOARD_BootClockRUN(void)73 void BOARD_BootClockRUN(void)
74 {
75 /* * The following steps just show how to configure the PLL clock sources using the clock driver on M7 core side .
76 * Please note that the ROM has already configured the SYSTEM PLL1 to 800Mhz when power up the SOC, meanwhile A core
77 * would enable SYSTEM PLL1, SYSTEM PLL2 and SYSTEM PLL3 by U-Boot.
78 * Therefore, there is no need to configure the system PLL again on M7 side, otherwise it would have a risk to make
79 * the SOC hang.
80 */
81
82 /* switch AHB NOC root to 24M first in order to configure the SYSTEM PLL1. */
83 CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxOsc24M);
84
85 /* switch AXI M7 root to 24M first in order to configure the SYSTEM PLL2. */
86 CLOCK_SetRootMux(kCLOCK_RootM7, kCLOCK_M7RootmuxOsc24M);
87
88 // CLOCK_InitSysPll2(&g_sysPll2Config); /* init SYSTEM PLL2 run at 1000MHZ */
89 // CLOCK_InitSysPll3(&g_sysPll3Config); /* init SYSTEM PLL3 run at 600MHZ */
90
91 CLOCK_InitAudioPll1(&g_audioPll1Config); /* init AUDIO PLL1 run at 393216000HZ */
92 CLOCK_InitAudioPll2(&g_audioPll2Config); /* init AUDIO PLL2 run at 361267200HZ */
93 CLOCK_SetRootDivider(kCLOCK_RootM7, 1U, 1U); /* Set root clock to 800M */
94 CLOCK_SetRootMux(kCLOCK_RootM7, kCLOCK_M7RootmuxSysPll1); /* switch cortex-m7 to SYSTEM PLL1 */
95
96 // CLOCK_SetRootDivider(kCLOCK_RootQspi, 1U, 2U); /* Set root clock to 800M */
97 // CLOCK_SetRootMux(kCLOCK_RootM7, kCLOCK_M7RootmuxSysPll1); /* switch QSPI to SYSTEM PLL1 */
98
99 CLOCK_SetRootDivider(kCLOCK_RootAhb, 1U, 1U); /* Set root clock freq to 133M / 1= 133MHZ */
100 CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6); /* switch AHB to SYSTEM PLL1 DIV6 */
101
102 CLOCK_SetRootDivider(kCLOCK_RootAudioAhb, 1U, 2U); /* Set root clock freq to 800MHZ/ 2= 400MHZ*/
103 CLOCK_SetRootMux(kCLOCK_RootAudioAhb, kCLOCK_AudioAhbRootmuxSysPll1); /* switch AUDIO AHB to SYSTEM PLL1 */
104
105 CLOCK_SetRootMux(kCLOCK_RootUart4, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */
106 CLOCK_SetRootDivider(kCLOCK_RootUart4, 1U, 1U); /* Set root clock to 80MHZ/ 1= 80MHZ */
107
108 CLOCK_EnableClock(kCLOCK_Rdc); /* Enable RDC clock */
109 CLOCK_EnableClock(kCLOCK_Ocram); /* Enable Ocram clock */
110 CLOCK_EnableClock(kCLOCK_Audio); /* Enable Audio clock to power on the audiomix domain*/
111
112 /* The purpose to enable the following modules clock is to make sure the M7 core could work normally when A53 core
113 * enters the low power status.*/
114 CLOCK_EnableClock(kCLOCK_Sim_m);
115 CLOCK_EnableClock(kCLOCK_Sim_main);
116 CLOCK_EnableClock(kCLOCK_Sim_s);
117 CLOCK_EnableClock(kCLOCK_Sim_wakeup);
118 CLOCK_EnableClock(kCLOCK_Debug);
119 CLOCK_EnableClock(kCLOCK_Dram);
120 CLOCK_EnableClock(kCLOCK_Sec_Debug);
121
122 /* Power up the audiomix domain by M7 core.*/
123 GPC->PGC_CPU_M7_MAPPING |= 1U << GPC_PGC_CPU_M7_MAPPING_AUDIOMIX_DOMAIN_SHIFT; /* Map the audiomix domain to M7 */
124 GPC->PU_PGC_SW_PUP_REQ |= 1U << GPC_PU_PGC_SW_PUP_REQ_AUDIOMIX_SW_PUP_REQ_SHIFT; /* Software request to trigger power up the domain */
125
126 while(GPC->PU_PGC_SW_PUP_REQ & (1U << GPC_PU_PGC_SW_PUP_REQ_AUDIOMIX_SW_PUP_REQ_SHIFT)); /* Waiting the GPC_PU_PGC_SW_PUP_REQ_AUDIOMIX_SW_PUP_REQ bit self-cleared after power up */
127 /* Do the handshake to make sure the NOC bus ready after power up the AUDIOMIX domain. */
128 GPC->PU_PWRHSK |= 1U << GPC_PU_PWRHSK_GPC_AUDIOMIX_NOC_PWRDNREQN_SHIFT;
129 while(!(GPC->PU_PWRHSK & (1U << GPC_PU_PWRHSK_GPC_AUDIOMIX_PWRDNACKN_SHIFT))) ;
130
131 AUDIOMIX_InitAudioPll(AUDIOMIX, &g_saiPLLConfig); /* init SAI PLL run at 361267200HZ */
132 /* Update core clock */
133 SystemCoreClockUpdate();
134 }
135
