1 /*
2 * Copyright 2019-2022 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #ifndef _FSL_CLOCK_H_
9 #define _FSL_CLOCK_H_
10
11 #include "fsl_device_registers.h"
12 #include "fsl_common.h"
13 #include <stdint.h>
14 #include <stdbool.h>
15 #include <stddef.h>
16 #include <assert.h>
17
18 /*!
19 * @addtogroup clock
20 * @{
21 */
22
23 /*******************************************************************************
24 * Definitions
25 ******************************************************************************/
26
27 /*! @name Driver version */
28 /*@{*/
29 /*! @brief CLOCK driver version 2.2.0. */
30 #define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 2, 0))
31 /*@}*/
32
33 /* Definition for delay API in clock driver, users can redefine it to the real application. */
34 #ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
35 #define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (800000000UL)
36 #endif
37
38 /*!
39 * @brief XTAL 24M clock frequency.
40 */
41 #define OSC24M_CLK_FREQ 24000000U
42 /*!
43 * @brief pad clock frequency.
44 */
45 #define CLKPAD_FREQ 0U
46
47 /*! @brief Clock ip name array for ECSPI. */
48 #define ECSPI_CLOCKS \
49 { \
50 kCLOCK_IpInvalid, kCLOCK_Ecspi1, kCLOCK_Ecspi2, kCLOCK_Ecspi3, \
51 }
52
53 /*! @brief Clock ip name array for EDMA. */
54 #define EDMA_CLOCKS \
55 { \
56 kCLOCK_Edma, \
57 }
58
59 /*! @brief Clock ip name array for ENET. */
60 #define ENET_CLOCKS \
61 { \
62 kCLOCK_Enet1, \
63 }
64
65 /*! @brief Clock ip name array for ENET_QOS. */
66 #define ENETQOS_CLOCKS \
67 { \
68 kCLOCK_Enet_Qos \
69 }
70
71 /*! @brief Clock ip name array for FLEXCAN. */
72 #define FLEXCAN_CLOCKS \
73 { \
74 kCLOCK_IpInvalid, kCLOCK_Can1, kCLOCK_Can2, \
75 }
76
77 /*! @brief Clock ip name array for GPIO. */
78 #define GPIO_CLOCKS \
79 { \
80 kCLOCK_IpInvalid, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5, \
81 }
82
83 /*! @brief Clock ip name array for GPT. */
84 #define GPT_CLOCKS \
85 { \
86 kCLOCK_IpInvalid, kCLOCK_Gpt1, kCLOCK_Gpt2, kCLOCK_Gpt3, kCLOCK_Gpt4, kCLOCK_Gpt5, kCLOCK_Gpt6, \
87 }
88
89 /*! @brief Clock ip name array for I2C. */
90 #define I2C_CLOCKS \
91 { \
92 kCLOCK_IpInvalid, kCLOCK_I2c1, kCLOCK_I2c2, kCLOCK_I2c3, kCLOCK_I2c4, kCLOCK_I2c5, kCLOCK_I2c6, \
93 }
94
95 /*! @brief Clock ip name array for IOMUX. */
96 #define IOMUX_CLOCKS \
97 { \
98 kCLOCK_Iomux, \
99 }
100
101 /*! @brief Clock ip name array for IPMUX. */
102 #define IPMUX_CLOCKS \
103 { \
104 kCLOCK_Ipmux1, kCLOCK_Ipmux2, kCLOCK_Ipmux3, \
105 }
106
107 /*! @brief Clock ip name array for PWM. */
108 #define PWM_CLOCKS \
109 { \
110 kCLOCK_IpInvalid, kCLOCK_Pwm1, kCLOCK_Pwm2, kCLOCK_Pwm3, kCLOCK_Pwm4, \
111 }
112
113 /*! @brief Clock ip name array for RDC. */
114 #define RDC_CLOCKS \
115 { \
116 kCLOCK_Rdc, \
117 }
118
119 /*! @brief Clock ip name array for SAI. */
120 #define SAI_CLOCKS \
121 { \
122 kCLOCK_IpInvalid, kCLOCK_Sai1, kCLOCK_Sai2, kCLOCK_Sai3, kCLOCK_IpInvalid, kCLOCK_Sai5, kCLOCK_Sai6, \
123 kCLOCK_Sai7 \
124 }
125
126 /*! @brief Clock ip name array for RDC SEMA42. */
127 #define RDC_SEMA42_CLOCKS \
128 { \
129 kCLOCK_IpInvalid, kCLOCK_Sema42_1, kCLOCK_Sema42_2 \
130 }
131
132 /*! @brief Clock ip name array for UART. */
133 #define UART_CLOCKS \
134 { \
135 kCLOCK_IpInvalid, kCLOCK_Uart1, kCLOCK_Uart2, kCLOCK_Uart3, kCLOCK_Uart4, \
136 }
137
138 /*! @brief Clock ip name array for USDHC. */
139 #define USDHC_CLOCKS \
140 { \
141 kCLOCK_IpInvalid, kCLOCK_Usdhc1, kCLOCK_Usdhc2, kCLOCK_Usdhc3 \
142 }
143
144 /*! @brief Clock ip name array for WDOG. */
145 #define WDOG_CLOCKS \
146 { \
147 kCLOCK_IpInvalid, kCLOCK_Wdog1, kCLOCK_Wdog2, kCLOCK_Wdog3 \
148 }
149
150 /*! @brief Clock ip name array for TEMPSENSOR. */
151 #define TMU_CLOCKS \
152 { \
153 kCLOCK_TempSensor, \
154 }
155
156 /*! @brief Clock ip name array for SDMA. */
157 #define SDMA_CLOCKS \
158 { \
159 kCLOCK_Sdma1, kCLOCK_Sdma2, kCLOCK_Sdma3, \
160 }
161
162 /*! @brief Clock ip name array for MU. */
163 #define MU_CLOCKS \
164 { \
165 kCLOCK_Mu \
166 }
167
168 /*! @brief Clock ip name array for QSPI. */
169 #define QSPI_CLOCKS \
170 { \
171 kCLOCK_Qspi \
172 }
173
174 /*! @brief Clock ip name array for PDM. */
175 #define PDM_CLOCKS \
176 { \
177 kCLOCK_Pdm \
178 }
179
180 /*! @brief Clock ip name array for ASRC. */
181 #define ASRC_CLOCKS \
182 { \
183 kCLOCK_Asrc \
184 }
185
186 /*!
187 * @brief CCM reg macros to extract corresponding registers bit field.
188 */
189 #define CCM_BIT_FIELD_EXTRACTION(val, mask, shift) (((val) & (mask)) >> (shift))
190
191 /*!
192 * @brief CCM reg macros to map corresponding registers.
193 */
194 #define CCM_REG_OFF(root, off) (*((volatile uint32_t *)((uintptr_t)(root) + (off))))
195 #define CCM_REG(root) CCM_REG_OFF(root, 0U)
196 #define CCM_REG_SET(root) CCM_REG_OFF(root, 4U)
197 #define CCM_REG_CLR(root) CCM_REG_OFF(root, 8U)
198
199 /*!
200 * @brief CCM Analog registers offset.
201 */
202 #define AUDIO_PLL1_GEN_CTRL_OFFSET 0x00
203 #define AUDIO_PLL2_GEN_CTRL_OFFSET 0x14
204 #define VIDEO_PLL1_GEN_CTRL_OFFSET 0x28
205 #define GPU_PLL_GEN_CTRL_OFFSET 0x64
206 #define VPU_PLL_GEN_CTRL_OFFSET 0x74
207 #define ARM_PLL_GEN_CTRL_OFFSET 0x84
208 #define SYS_PLL1_GEN_CTRL_OFFSET 0x94
209 #define SYS_PLL2_GEN_CTRL_OFFSET 0x104
210 #define SYS_PLL3_GEN_CTRL_OFFSET 0x114
211 #define DRAM_PLL_GEN_CTRL_OFFSET 0x50
212
213 /*!
214 * @brief CCM ANALOG tuple macros to map corresponding registers and bit fields.
215 */
216 #define CCM_ANALOG_TUPLE(reg, shift) ((((reg)&0xFFFFU) << 16U) | ((shift)))
217 #define CCM_ANALOG_TUPLE_SHIFT(tuple) (((uint32_t)(tuple)) & 0x1FU)
218 #define CCM_ANALOG_TUPLE_REG_OFF(base, tuple, off) \
219 (*((volatile uint32_t *)((uintptr_t)(base) + (((uint32_t)(tuple) >> 16U) & 0xFFFFU) + (off))))
220 #define CCM_ANALOG_TUPLE_REG(base, tuple) CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 0U)
221
222 /*!
223 * @brief CCM CCGR and root tuple
224 */
225 #define CLOCK_GATE_IN_AUDIOMIX (1U)
226 #define CLOCK_GATE_IN_CCM (0U)
227 #define CLOCK_GATE_TYPE(tuple) ((uint32_t)(tuple) >> 28U)
228 #define CCM_TUPLE(ccgr, root) ((((ccgr)&0xFFFFU) << 16U) | (root))
229 #define CCM_TUPLE_CCGR(tuple) ((uintptr_t)(&(CCM)->CCGR[(uint32_t)(tuple) >> 16U].CCGR))
230 #define CCM_TUPLE_ROOT(tuple) ((uintptr_t)(&(CCM)->ROOT[(uint32_t)(tuple)&0xFFFFU].TARGET_ROOT))
231 /*!@brief audio mix CCGR */
232 #define AUDIOMIX_TUPLE(offset, gate, root) \
233 (((CLOCK_GATE_IN_AUDIOMIX) << 28U) | (((offset)&0xFU) << 24U) | (((gate)&0xFFU) << 16U) | ((root)&0xFFFFU))
234 #define AUDIOMIX_TUPLE_OFFSET(tuple) (((uint32_t)(tuple) >> 24U) & 0xFU)
235 #define AUDIOMIX_TUPLE_GATE(tuple) (((uint32_t)(tuple) >> 16U) & 0xFFU)
236 #define AUDIOMIX_TUPLE_ROOT(tuple) ((uint32_t)(tuple)&0xFFFFU)
237
238 /*!
239 * @brief clock root source
240 */
241 #define CLOCK_ROOT_SOURCE \
242 { \
243 {kCLOCK_Osc24MClk, kCLOCK_SysPll2Div5Clk, kCLOCK_SysPll2Div4Clk, kCLOCK_VpuPllClk, kCLOCK_SysPll1Clk, \
244 kCLOCK_AudioPll1Clk, kCLOCK_VideoPll1Clk, kCLOCK_SysPll3Clk}, /* Cortex-M7 Clock Root. */ \
245 { \
246 kCLOCK_Osc24MClk, kCLOCK_SysPll2Div2Clk, kCLOCK_SysPll1Clk, \
247 kCLOCK_SysPll2Div10Clk, kCLOCK_SysPll2Div5Clk, kCLOCK_ExtClk2, \
248 kCLOCK_ExtClk4, kCLOCK_AudioPll2Clk}, /* Hsio AXI Clock Root. */ \
249 { \
250 kCLOCK_Osc24MClk, kCLOCK_SysPll2Div3Clk, kCLOCK_SysPll1Clk, \
251 kCLOCK_SysPll2Div4Clk, kCLOCK_SysPll2Clk, kCLOCK_AudioPll1Clk, \
252 kCLOCK_VideoPll1Clk, kCLOCK_SysPll1Div8Clk}, /* Main AXI Clock Root. */ \
253 {kCLOCK_Osc24MClk, kCLOCK_SysPll1Div3Clk, kCLOCK_SysPll1Clk, \
254 kCLOCK_SysPll2Div4Clk, kCLOCK_SysPll2Div5Clk, kCLOCK_AudioPll1Clk, \
255 kCLOCK_VideoPll1Clk, kCLOCK_SysPll3Clk}, /* Enet AXI Clock Root. */ \
256 { \
257 kCLOCK_Osc24MClk, kCLOCK_SysPll1Div3Clk, kCLOCK_SysPll1Clk, \
258 kCLOCK_SysPll2Div5Clk, kCLOCK_SysPll1Div6Clk, kCLOCK_SysPll3Clk, \
259 kCLOCK_SysPll2Div4Clk, kCLOCK_AudioPll1Clk}, /* Nand Usdhc Bus Clock Root. */ \
260 {kCLOCK_Osc24MClk, kCLOCK_SysPll1Clk, kCLOCK_VpuPllClk, kCLOCK_AudioPll2Clk, kCLOCK_SysPll3Clk, \
261 kCLOCK_SysPll2Clk, kCLOCK_SysPll2Div5Clk, kCLOCK_SysPll1Div8Clk}, /* Vpu Bus Clock Root. */ \
262 {kCLOCK_Osc24MClk, kCLOCK_SysPll2Clk, kCLOCK_SysPll1Clk, kCLOCK_SysPll3Clk, kCLOCK_SysPll1Div20Clk, \
263 kCLOCK_AudioPll2Clk, kCLOCK_ExtClk1, kCLOCK_SysPll2Div2Clk}, /* Media AXI Clock Root. */ \
264 {kCLOCK_Osc24MClk, kCLOCK_SysPll2Div8Clk, kCLOCK_SysPll1Clk, \
265 kCLOCK_SysPll3Clk, kCLOCK_SysPll1Div20Clk, kCLOCK_AudioPll2Clk, \
266 kCLOCK_ExtClk1, kCLOCK_SysPll1Div6Clk}, /* Media APB Clock Root. */ \
267 {kCLOCK_Osc24MClk, kCLOCK_SysPll2Div8Clk, kCLOCK_SysPll1Clk, \
268 kCLOCK_SysPll3Clk, kCLOCK_SysPll1Div20Clk, kCLOCK_AudioPll2Clk, \
269 kCLOCK_ExtClk1, kCLOCK_SysPll1Div6Clk}, /* Hdmi APB Clock Root. */ \
270 {kCLOCK_Osc24MClk, kCLOCK_SysPll1Clk, kCLOCK_SysPll3Clk, kCLOCK_SysPll2Clk, kCLOCK_SysPll2Div2Clk, \
271 kCLOCK_AudioPll1Clk, kCLOCK_VideoPll1Clk, kCLOCK_AudioPll2Clk}, /* NOC Clock Root. */ \
272 { \
273 kCLOCK_Osc24MClk, kCLOCK_SysPll1Div6Clk, kCLOCK_SysPll1Clk, \
274 kCLOCK_SysPll1Div2Clk, kCLOCK_SysPll2Div8Clk, kCLOCK_SysPll3Clk, \
275 kCLOCK_AudioPll1Clk, kCLOCK_VideoPll1Clk}, /* AHB Clock Root. */ \
276 { \
277 kCLOCK_Osc24MClk, kCLOCK_SysPll1Div6Clk, kCLOCK_SysPll1Clk, \
278 kCLOCK_SysPll1Div2Clk, kCLOCK_SysPll2Div8Clk, kCLOCK_SysPll3Clk, \
279 kCLOCK_AudioPll1Clk, kCLOCK_VideoPll1Clk}, /* IPG Clock Root. */ \
280 {kCLOCK_Osc24MClk, kCLOCK_SysPll2Div2Clk, kCLOCK_SysPll1Clk, kCLOCK_SysPll2Clk, kCLOCK_SysPll2Div6Clk, \
281 kCLOCK_SysPll3Clk, kCLOCK_AudioPll1Clk, kCLOCK_VideoPll1Clk}, /* Audio AHB Clock Root. */ \
282 {kCLOCK_Osc24MClk, kCLOCK_SysPll2Div2Clk, kCLOCK_SysPll1Clk, kCLOCK_SysPll2Clk, kCLOCK_SysPll2Div6Clk, \
283 kCLOCK_SysPll3Clk, kCLOCK_AudioPll1Clk, kCLOCK_VideoPll1Clk}, /* Audio IPG Clock Root. */ \
284 {kCLOCK_Osc24MClk, kCLOCK_SysPll1Clk, kCLOCK_SysPll1Div8Clk, kCLOCK_SysPll2Div2Clk, kCLOCK_SysPll2Clk, \
285 kCLOCK_SysPll3Clk, kCLOCK_AudioPll1Clk, kCLOCK_SysPll1Div3Clk}, /* DRAM ALT Clock Root */ \
286 { \
287 kCLOCK_Osc24MClk, kCLOCK_SysPll2Div5Clk, kCLOCK_SysPll1Div20Clk, \
288 kCLOCK_SysPll1Div5Clk, kCLOCK_SysPll1Clk, kCLOCK_SysPll3Clk, \
289 kCLOCK_SysPll2Div4Clk, kCLOCK_AudioPll2Clk}, /* FLEXCAN1 Clock Root */ \
290 { \
291 kCLOCK_Osc24MClk, kCLOCK_SysPll2Div5Clk, kCLOCK_SysPll1Div20Clk, \
292 kCLOCK_SysPll1Div5Clk, kCLOCK_SysPll1Clk, kCLOCK_SysPll3Clk, \
293 kCLOCK_SysPll2Div4Clk, kCLOCK_AudioPll2Clk}, /* FLEXCAN2 Clock Root */ \
294 {kCLOCK_Osc24MClk, kCLOCK_AudioPll1Clk, kCLOCK_AudioPll2Clk, kCLOCK_VideoPll1Clk, \
295 kCLOCK_SysPll1Div6Clk, kCLOCK_NoneName, kCLOCK_ExtClk1, kCLOCK_ExtClk2}, /* SAI1 Clock Root */ \
296 {kCLOCK_Osc24MClk, kCLOCK_AudioPll1Clk, kCLOCK_AudioPll2Clk, kCLOCK_VideoPll1Clk, \
297 kCLOCK_SysPll1Div6Clk, kCLOCK_NoneName, kCLOCK_ExtClk2, kCLOCK_ExtClk3}, /* SAI2 Clock Root */ \
298 {kCLOCK_Osc24MClk, kCLOCK_AudioPll1Clk, kCLOCK_AudioPll2Clk, kCLOCK_VideoPll1Clk, \
299 kCLOCK_SysPll1Div6Clk, kCLOCK_NoneName, kCLOCK_ExtClk3, kCLOCK_ExtClk4}, /* SAI3 Clock Root */ \
300 {kCLOCK_Osc24MClk, kCLOCK_AudioPll1Clk, kCLOCK_AudioPll2Clk, kCLOCK_VideoPll1Clk, \
301 kCLOCK_SysPll1Div6Clk, kCLOCK_NoneName, kCLOCK_ExtClk2, kCLOCK_ExtClk3}, /* SAI5 Clock Root */ \
302 {kCLOCK_Osc24MClk, kCLOCK_AudioPll1Clk, kCLOCK_AudioPll2Clk, kCLOCK_VideoPll1Clk, \
303 kCLOCK_SysPll1Div6Clk, kCLOCK_NoneName, kCLOCK_ExtClk3, kCLOCK_ExtClk4}, /* SAI6 Clock Root. */ \
304 {kCLOCK_Osc24MClk, kCLOCK_AudioPll1Clk, kCLOCK_AudioPll2Clk, kCLOCK_VideoPll1Clk, \
305 kCLOCK_SysPll1Div6Clk, kCLOCK_NoneName, kCLOCK_ExtClk3, kCLOCK_ExtClk4}, /* SAI7 Clock Root */ \
306 {kCLOCK_Osc24MClk, kCLOCK_SysPll2Div8Clk, kCLOCK_SysPll2Div20Clk, \
307 kCLOCK_SysPll2Div10Clk, kCLOCK_SysPll1Div5Clk, kCLOCK_AudioPll1Clk, \
308 kCLOCK_VideoPll1Clk, kCLOCK_ExtClk4}, /* Enet Qos Clock Root */ \
309 {kCLOCK_Osc24MClk, kCLOCK_SysPll2Div10Clk, kCLOCK_AudioPll1Clk, kCLOCK_ExtClk1, kCLOCK_ExtClk2, \
310 kCLOCK_ExtClk3, kCLOCK_ExtClk4, kCLOCK_VideoPll1Clk}, /* Enet Qos Timer Clock Root */ \
311 {kCLOCK_Osc24MClk, kCLOCK_SysPll2Div8Clk, kCLOCK_SysPll2Div20Clk, \
312 kCLOCK_SysPll2Div10Clk, kCLOCK_SysPll1Div5Clk, kCLOCK_AudioPll1Clk, \
313 kCLOCK_VideoPll1Clk, kCLOCK_ExtClk4}, /* Enet Ref Clock Root */ \
314 {kCLOCK_Osc24MClk, kCLOCK_SysPll2Div10Clk, kCLOCK_AudioPll1Clk, kCLOCK_ExtClk1, kCLOCK_ExtClk2, \
315 kCLOCK_ExtClk3, kCLOCK_ExtClk4, kCLOCK_VideoPll1Clk}, /* Enet Timer Clock Root */ \
316 {kCLOCK_Osc24MClk, kCLOCK_SysPll2Div20Clk, kCLOCK_SysPll2Div8Clk, \
317 kCLOCK_SysPll2Div5Clk, kCLOCK_SysPll2Div2Clk, kCLOCK_AudioPll1Clk, \
318 kCLOCK_VideoPll1Clk, kCLOCK_AudioPll2Clk}, /* Enet Phy Clock Root */ \
319 { \
320 kCLOCK_Osc24MClk, kCLOCK_SysPll2Div2Clk, kCLOCK_AudioPll1Clk, \
321 kCLOCK_SysPll1Div2Clk, kCLOCK_AudioPll2Clk, kCLOCK_SysPll3Clk, \
322 kCLOCK_SysPll2Div4Clk, kCLOCK_VideoPll1Clk}, /* Nand Clock Root */ \
323 {kCLOCK_Osc24MClk, kCLOCK_SysPll1Div2Clk, kCLOCK_SysPll1Clk, \
324 kCLOCK_SysPll2Div2Clk, kCLOCK_SysPll3Clk, kCLOCK_SysPll1Div3Clk, \
325 kCLOCK_AudioPll2Clk, kCLOCK_SysPll1Div8Clk}, /* QSPI Clock Root */ \
326 {kCLOCK_Osc24MClk, kCLOCK_SysPll1Div2Clk, kCLOCK_SysPll1Clk, \
327 kCLOCK_SysPll2Div2Clk, kCLOCK_SysPll3Clk, kCLOCK_SysPll1Div3Clk, \
328 kCLOCK_AudioPll2Clk, kCLOCK_SysPll1Div8Clk}, /* Usdhc1 Clock Root */ \
329 {kCLOCK_Osc24MClk, kCLOCK_SysPll1Div2Clk, kCLOCK_SysPll1Clk, \
330 kCLOCK_SysPll2Div2Clk, kCLOCK_SysPll3Clk, kCLOCK_SysPll1Div3Clk, \
331 kCLOCK_AudioPll2Clk, kCLOCK_SysPll1Div8Clk}, /* Usdhc2 Clock Root */ \
332 {kCLOCK_Osc24MClk, kCLOCK_SysPll1Div2Clk, kCLOCK_SysPll1Clk, \
333 kCLOCK_SysPll2Div2Clk, kCLOCK_SysPll3Clk, kCLOCK_SysPll1Div3Clk, \
334 kCLOCK_AudioPll2Clk, kCLOCK_SysPll1Div8Clk}, /* Usdhc3 Clock Root */ \
335 { \
336 kCLOCK_Osc24MClk, kCLOCK_SysPll1Div5Clk, kCLOCK_SysPll2Div20Clk, \
337 kCLOCK_SysPll3Clk, kCLOCK_AudioPll1Clk, kCLOCK_VideoPll1Clk, \
338 kCLOCK_AudioPll2Clk, kCLOCK_SysPll1Div6Clk}, /* I2C1 Clock Root */ \
339 { \
340 kCLOCK_Osc24MClk, kCLOCK_SysPll1Div5Clk, kCLOCK_SysPll2Div20Clk, \
341 kCLOCK_SysPll3Clk, kCLOCK_AudioPll1Clk, kCLOCK_VideoPll1Clk, \
342 kCLOCK_AudioPll2Clk, kCLOCK_SysPll1Div6Clk}, /* I2C2 Clock Root */ \
343 { \
344 kCLOCK_Osc24MClk, kCLOCK_SysPll1Div5Clk, kCLOCK_SysPll2Div20Clk, \
345 kCLOCK_SysPll3Clk, kCLOCK_AudioPll1Clk, kCLOCK_VideoPll1Clk, \
346 kCLOCK_AudioPll2Clk, kCLOCK_SysPll1Div6Clk}, /* I2C3 Clock Root */ \
347 { \
348 kCLOCK_Osc24MClk, kCLOCK_SysPll1Div5Clk, kCLOCK_SysPll2Div20Clk, \
349 kCLOCK_SysPll3Clk, kCLOCK_AudioPll1Clk, kCLOCK_VideoPll1Clk, \
350 kCLOCK_AudioPll2Clk, kCLOCK_SysPll1Div6Clk}, /* I2C4 Clock Root */ \
351 { \
352 kCLOCK_Osc24MClk, kCLOCK_SysPll1Div5Clk, kCLOCK_SysPll2Div20Clk, \
353 kCLOCK_SysPll3Clk, kCLOCK_AudioPll1Clk, kCLOCK_VideoPll1Clk, \
354 kCLOCK_AudioPll2Clk, kCLOCK_SysPll1Div6Clk}, /* I2C5 Clock Root */ \
355 { \
356 kCLOCK_Osc24MClk, kCLOCK_SysPll1Div5Clk, kCLOCK_SysPll2Div20Clk, \
357 kCLOCK_SysPll3Clk, kCLOCK_AudioPll1Clk, kCLOCK_VideoPll1Clk, \
358 kCLOCK_AudioPll2Clk, kCLOCK_SysPll1Div6Clk}, /* I2C6 Clock Root */ \
359 { \
360 kCLOCK_Osc24MClk, kCLOCK_SysPll1Div10Clk, kCLOCK_SysPll2Div5Clk, \
361 kCLOCK_SysPll2Div10Clk, kCLOCK_SysPll3Clk, kCLOCK_ExtClk2, \
362 kCLOCK_ExtClk4, kCLOCK_AudioPll2Clk}, /* UART1 Clock Root */ \
363 { \
364 kCLOCK_Osc24MClk, kCLOCK_SysPll1Div10Clk, kCLOCK_SysPll2Div5Clk, \
365 kCLOCK_SysPll2Div10Clk, kCLOCK_SysPll3Clk, kCLOCK_ExtClk2, \
366 kCLOCK_ExtClk3, kCLOCK_AudioPll2Clk}, /* UART2 Clock Root */ \
367 { \
368 kCLOCK_Osc24MClk, kCLOCK_SysPll1Div10Clk, kCLOCK_SysPll2Div5Clk, \
369 kCLOCK_SysPll2Div10Clk, kCLOCK_SysPll3Clk, kCLOCK_ExtClk2, \
370 kCLOCK_ExtClk4, kCLOCK_AudioPll2Clk}, /* UART3 Clock Root */ \
371 { \
372 kCLOCK_Osc24MClk, kCLOCK_SysPll1Div10Clk, kCLOCK_SysPll2Div5Clk, \
373 kCLOCK_SysPll2Div10Clk, kCLOCK_SysPll3Clk, kCLOCK_ExtClk2, \
374 kCLOCK_ExtClk3, kCLOCK_AudioPll2Clk}, /* UART4 Clock Root */ \
375 {kCLOCK_Osc24MClk, kCLOCK_SysPll2Div5Clk, kCLOCK_SysPll1Div20Clk, \
376 kCLOCK_SysPll2Div10Clk, kCLOCK_SysPll1Clk, kCLOCK_SysPll2Div2Clk, \
377 kCLOCK_ExtClk4, kCLOCK_AudioPll2Clk}, /* Gic Clock Root */ \
378 { \
379 kCLOCK_Osc24MClk, kCLOCK_SysPll2Div5Clk, kCLOCK_SysPll1Div20Clk, \
380 kCLOCK_SysPll1Div5Clk, kCLOCK_SysPll1Clk, kCLOCK_SysPll3Clk, \
381 kCLOCK_SysPll2Div4Clk, kCLOCK_AudioPll2Clk}, /* ECSPI1 Clock ROOT */ \
382 { \
383 kCLOCK_Osc24MClk, kCLOCK_SysPll2Div5Clk, kCLOCK_SysPll1Div20Clk, \
384 kCLOCK_SysPll1Div5Clk, kCLOCK_SysPll1Clk, kCLOCK_SysPll3Clk, \
385 kCLOCK_SysPll2Div4Clk, kCLOCK_AudioPll2Clk}, /* ECSPI2 Clock ROOT */ \
386 { \
387 kCLOCK_Osc24MClk, kCLOCK_SysPll2Div5Clk, kCLOCK_SysPll1Div20Clk, \
388 kCLOCK_SysPll1Div5Clk, kCLOCK_SysPll1Clk, kCLOCK_SysPll3Clk, \
389 kCLOCK_SysPll2Div4Clk, kCLOCK_AudioPll2Clk}, /* ECSPI3 Clock ROOT */ \
390 { \
391 kCLOCK_Osc24MClk, kCLOCK_SysPll2Div10Clk, kCLOCK_SysPll1Div5Clk, \
392 kCLOCK_SysPll1Div20Clk, kCLOCK_SysPll3Clk, kCLOCK_ExtClk1, \
393 kCLOCK_SysPll1Div10Clk, kCLOCK_VideoPll1Clk}, /* PWM1 Clock ROOT */ \
394 { \
395 kCLOCK_Osc24MClk, kCLOCK_SysPll2Div10Clk, kCLOCK_SysPll1Div5Clk, \
396 kCLOCK_SysPll1Div20Clk, kCLOCK_SysPll3Clk, kCLOCK_ExtClk1, \
397 kCLOCK_SysPll1Div10Clk, kCLOCK_VideoPll1Clk}, /* PWM2 Clock ROOT */ \
398 { \
399 kCLOCK_Osc24MClk, kCLOCK_SysPll2Div10Clk, kCLOCK_SysPll1Div5Clk, \
400 kCLOCK_SysPll1Div20Clk, kCLOCK_SysPll3Clk, kCLOCK_ExtClk2, \
401 kCLOCK_SysPll1Div10Clk, kCLOCK_VideoPll1Clk}, /* PWM3 Clock ROOT */ \
402 { \
403 kCLOCK_Osc24MClk, kCLOCK_SysPll2Div10Clk, kCLOCK_SysPll1Div5Clk, \
404 kCLOCK_SysPll1Div20Clk, kCLOCK_SysPll3Clk, kCLOCK_ExtClk2, \
405 kCLOCK_SysPll1Div10Clk, kCLOCK_VideoPll1Clk}, /* PWM4 Clock ROOT */ \
406 { \
407 kCLOCK_Osc24MClk, kCLOCK_SysPll2Div10Clk, kCLOCK_SysPll1Div2Clk, \
408 kCLOCK_SysPll1Div20Clk, kCLOCK_VideoPll1Clk, kCLOCK_SysPll1Div10Clk, \
409 kCLOCK_AudioPll1Clk, kCLOCK_ExtClk1}, /* GPT1 Clock ROOT */ \
410 { \
411 kCLOCK_Osc24MClk, kCLOCK_SysPll2Div10Clk, kCLOCK_SysPll1Div2Clk, \
412 kCLOCK_SysPll1Div20Clk, kCLOCK_VideoPll1Clk, kCLOCK_SysPll1Div10Clk, \
413 kCLOCK_AudioPll1Clk, kCLOCK_ExtClk2}, /* GPT2 Clock ROOT */ \
414 { \
415 kCLOCK_Osc24MClk, kCLOCK_SysPll2Div10Clk, kCLOCK_SysPll1Div2Clk, \
416 kCLOCK_SysPll1Div20Clk, kCLOCK_VideoPll1Clk, kCLOCK_SysPll1Div10Clk, \
417 kCLOCK_AudioPll1Clk, kCLOCK_ExtClk3}, /* GPT3 Clock ROOT */ \
418 { \
419 kCLOCK_Osc24MClk, kCLOCK_SysPll2Div10Clk, kCLOCK_SysPll1Div2Clk, \
420 kCLOCK_SysPll1Div20Clk, kCLOCK_VideoPll1Clk, kCLOCK_SysPll1Div10Clk, \
421 kCLOCK_AudioPll1Clk, kCLOCK_ExtClk1}, /* GPT4 Clock ROOT */ \
422 { \
423 kCLOCK_Osc24MClk, kCLOCK_SysPll2Div10Clk, kCLOCK_SysPll1Div2Clk, \
424 kCLOCK_SysPll1Div20Clk, kCLOCK_VideoPll1Clk, kCLOCK_SysPll1Div10Clk, \
425 kCLOCK_AudioPll1Clk, kCLOCK_ExtClk2}, /* GPT5 Clock ROOT */ \
426 { \
427 kCLOCK_Osc24MClk, kCLOCK_SysPll2Div10Clk, kCLOCK_SysPll1Div2Clk, \
428 kCLOCK_SysPll1Div20Clk, kCLOCK_VideoPll1Clk, kCLOCK_SysPll1Div10Clk, \
429 kCLOCK_AudioPll1Clk, kCLOCK_ExtClk3}, /* GPT6 Clock ROOT */ \
430 { \
431 kCLOCK_Osc24MClk, kCLOCK_SysPll1Div6Clk, kCLOCK_SysPll1Div5Clk, \
432 kCLOCK_VpuPllClk, kCLOCK_SysPll2Div8Clk, kCLOCK_SysPll3Clk, \
433 kCLOCK_SysPll1Div10Clk, kCLOCK_SysPll2Div6Clk}, /* WDOG Clock ROOT */ \
434 { \
435 kCLOCK_Osc24MClk, kCLOCK_SysPll2Div10Clk, kCLOCK_AudioPll1Clk, kCLOCK_SysPll1Clk, kCLOCK_SysPll2Clk, \
436 kCLOCK_SysPll3Clk, kCLOCK_ExtClk3, kCLOCK_AudioPll2Clk}, /* PDM Clock ROOT */ \
437 }
438
439 #define CLOCK_ROOT_CONTROL_TUPLE \
440 { \
441 kCLOCK_RootM7, kCLOCK_RootHsioAxi, kCLOCK_RootMainAxi, kCLOCK_RootEnetAxi, kCLOCK_RootNandUsdhcBus, \
442 kCLOCK_RootVpuBus, kCLOCK_RootMediaAxi, kCLOCK_RootMediaApb, kCLOCK_RootHdmiApb, kCLOCK_RootNoc, \
443 kCLOCK_RootAhb, kCLOCK_RootAhb, kCLOCK_RootAudioAhb, kCLOCK_RootAudioAhb, kCLOCK_RootDramAlt, \
444 kCLOCK_RootFlexCan1, kCLOCK_RootFlexCan2, kCLOCK_RootSai1, kCLOCK_RootSai2, kCLOCK_RootSai3, \
445 kCLOCK_RootSai5, kCLOCK_RootSai6, kCLOCK_RootSai7, kCLOCK_RootEnetQos, kCLOCK_RootEnetQosTimer, \
446 kCLOCK_RootEnetRef, kCLOCK_RootEnetTimer, kCLOCK_RootEnetPhy, kCLOCK_RootNand, kCLOCK_RootQspi, \
447 kCLOCK_RootUsdhc1, kCLOCK_RootUsdhc2, kCLOCK_RootUsdhc3, kCLOCK_RootI2c1, kCLOCK_RootI2c2, \
448 kCLOCK_RootI2c3, kCLOCK_RootI2c4, kCLOCK_RootI2c5, kCLOCK_RootI2c6, kCLOCK_RootUart1, kCLOCK_RootUart2, \
449 kCLOCK_RootUart3, kCLOCK_RootUart4, kCLOCK_RootGic, kCLOCK_RootEcspi1, kCLOCK_RootEcspi2, \
450 kCLOCK_RootEcspi3, kCLOCK_RootPwm1, kCLOCK_RootPwm2, kCLOCK_RootPwm3, kCLOCK_RootPwm4, kCLOCK_RootGpt1, \
451 kCLOCK_RootGpt2, kCLOCK_RootGpt3, kCLOCK_RootGpt4, kCLOCK_RootGpt5, kCLOCK_RootGpt6, kCLOCK_RootWdog, \
452 kCLOCK_RootPdm, \
453 }
454
455 /*! @brief Clock name used to get clock frequency. */
456 typedef enum _clock_name
457 {
458 kCLOCK_CoreM7Clk, /*!< ARM M7 Core clock */
459
460 kCLOCK_AxiClk, /*!< Main AXI bus clock. */
461 kCLOCK_AhbClk, /*!< AHB bus clock. */
462 kCLOCK_IpgClk, /*!< IPG bus clock. */
463 kCLOCK_PerClk, /*!< Peripheral Clock. */
464 kCLOCK_EnetIpgClk, /*!< ENET IPG Clock. */
465 kCLOCK_Osc24MClk, /*!< OSC 24M clock. */
466 kCLOCK_ArmPllClk, /*!< Arm PLL clock. */
467 kCLOCK_DramPllClk, /*!< Dram PLL clock. */
468 kCLOCK_VpuPllClk, /*!< Vpu PLL clock. */
469 kCLOCK_SysPll1Clk, /*!< Sys PLL1 clock. */
470 kCLOCK_SysPll1Div2Clk, /*!< Sys PLL1 clock divided by 2. */
471 kCLOCK_SysPll1Div3Clk, /*!< Sys PLL1 clock divided by 3. */
472 kCLOCK_SysPll1Div4Clk, /*!< Sys PLL1 clock divided by 4. */
473 kCLOCK_SysPll1Div5Clk, /*!< Sys PLL1 clock divided by 5. */
474 kCLOCK_SysPll1Div6Clk, /*!< Sys PLL1 clock divided by 6. */
475 kCLOCK_SysPll1Div8Clk, /*!< Sys PLL1 clock divided by 8. */
476 kCLOCK_SysPll1Div10Clk, /*!< Sys PLL1 clock divided by 10. */
477 kCLOCK_SysPll1Div20Clk, /*!< Sys PLL1 clock divided by 20. */
478 kCLOCK_SysPll2Clk, /*!< Sys PLL2 clock. */
479 kCLOCK_SysPll2Div2Clk, /*!< Sys PLL2 clock divided by 2. */
480 kCLOCK_SysPll2Div3Clk, /*!< Sys PLL2 clock divided by 3. */
481 kCLOCK_SysPll2Div4Clk, /*!< Sys PLL2 clock divided by 4. */
482 kCLOCK_SysPll2Div5Clk, /*!< Sys PLL2 clock divided by 5. */
483 kCLOCK_SysPll2Div6Clk, /*!< Sys PLL2 clock divided by 6. */
484 kCLOCK_SysPll2Div8Clk, /*!< Sys PLL2 clock divided by 8. */
485 kCLOCK_SysPll2Div10Clk, /*!< Sys PLL2 clock divided by 10. */
486 kCLOCK_SysPll2Div20Clk, /*!< Sys PLL2 clock divided by 20. */
487 kCLOCK_SysPll3Clk, /*!< Sys PLL3 clock. */
488 kCLOCK_AudioPll1Clk, /*!< Audio PLL1 clock. */
489 kCLOCK_AudioPll2Clk, /*!< Audio PLL2 clock. */
490 kCLOCK_VideoPll1Clk, /*!< Video PLL1 clock. */
491 kCLOCK_ExtClk1, /*!< External clock1. */
492 kCLOCK_ExtClk2, /*!< External clock2. */
493 kCLOCK_ExtClk3, /*!< External clock3. */
494 kCLOCK_ExtClk4, /*!< External clock4. */
495 kCLOCK_NoneName, /*!< None Clock Name. */
496 /* -------------------------------- Other clock --------------------------*/
497 } clock_name_t;
498
499 #define kCLOCK_CoreSysClk kCLOCK_CoreM7Clk /*!< For compatible with other platforms without CCM. */
500 #define CLOCK_GetCoreSysClkFreq CLOCK_GetCoreM7Freq /*!< For compatible with other platforms without CCM. */
501
502 /*! @brief CCM CCGR gate control. */
503 typedef enum _clock_ip_name
504 {
505 kCLOCK_IpInvalid = -1,
506
507 kCLOCK_Debug = CCM_TUPLE(4U, 32U), /*!< DEBUG Clock Gate.*/
508
509 kCLOCK_Dram = CCM_TUPLE(5U, 64U), /*!< DRAM Clock Gate.*/
510
511 kCLOCK_Ecspi1 = CCM_TUPLE(7U, 101U), /*!< ECSPI1 Clock Gate.*/
512 kCLOCK_Ecspi2 = CCM_TUPLE(8U, 102U), /*!< ECSPI2 Clock Gate.*/
513 kCLOCK_Ecspi3 = CCM_TUPLE(9U, 131U), /*!< ECSPI3 Clock Gate.*/
514
515 kCLOCK_Enet1 = CCM_TUPLE(10U, 17U), /*!< ENET1 Clock Gate.*/
516
517 kCLOCK_Gpio1 = CCM_TUPLE(11U, 33U), /*!< GPIO1 Clock Gate.*/
518 kCLOCK_Gpio2 = CCM_TUPLE(12U, 33U), /*!< GPIO2 Clock Gate.*/
519 kCLOCK_Gpio3 = CCM_TUPLE(13U, 33U), /*!< GPIO3 Clock Gate.*/
520 kCLOCK_Gpio4 = CCM_TUPLE(14U, 33U), /*!< GPIO4 Clock Gate.*/
521 kCLOCK_Gpio5 = CCM_TUPLE(15U, 33U), /*!< GPIO5 Clock Gate.*/
522
523 kCLOCK_Gpt1 = CCM_TUPLE(16U, 107U), /*!< GPT1 Clock Gate.*/
524 kCLOCK_Gpt2 = CCM_TUPLE(17U, 108U), /*!< GPT2 Clock Gate.*/
525 kCLOCK_Gpt3 = CCM_TUPLE(18U, 109U), /*!< GPT3 Clock Gate.*/
526 kCLOCK_Gpt4 = CCM_TUPLE(19U, 110U), /*!< GPT4 Clock Gate.*/
527 kCLOCK_Gpt5 = CCM_TUPLE(20U, 111U), /*!< GPT5 Clock Gate.*/
528 kCLOCK_Gpt6 = CCM_TUPLE(21U, 112U), /*!< GPT6 Clock Gate.*/
529
530 kCLOCK_I2c1 = CCM_TUPLE(23U, 90U), /*!< I2C1 Clock Gate.*/
531 kCLOCK_I2c2 = CCM_TUPLE(24U, 91U), /*!< I2C2 Clock Gate.*/
532 kCLOCK_I2c3 = CCM_TUPLE(25U, 92U), /*!< I2C3 Clock Gate.*/
533 kCLOCK_I2c4 = CCM_TUPLE(26U, 93U), /*!< I2C4 Clock Gate.*/
534 kCLOCK_I2c5 = CCM_TUPLE(51U, 73U), /*!< I2C5 Clock Gate.*/
535 kCLOCK_I2c6 = CCM_TUPLE(52U, 74U), /*!< I2C6 Clock Gate.*/
536
537 kCLOCK_Can1 = CCM_TUPLE(53U, 68U), /*!< FlexCAN1 Clock Gate.*/
538 kCLOCK_Can2 = CCM_TUPLE(54U, 69U), /*!< FlexCAN2 Clock Gate.*/
539
540 kCLOCK_Enet_Qos = CCM_TUPLE(59U, 81U), /*!< ENET QOS Clock Gate.*/
541
542 kCLOCK_Iomux = CCM_TUPLE(27U, 33U), /*!< IOMUX Clock Gate.*/
543 kCLOCK_Ipmux1 = CCM_TUPLE(28U, 33U), /*!< IPMUX1 Clock Gate.*/
544 kCLOCK_Ipmux2 = CCM_TUPLE(29U, 33U), /*!< IPMUX2 Clock Gate.*/
545 kCLOCK_Ipmux3 = CCM_TUPLE(30U, 33U), /*!< IPMUX3 Clock Gate.*/
546
547 kCLOCK_Mu = CCM_TUPLE(33U, 33U), /*!< MU Clock Gate.*/
548
549 kCLOCK_Ocram = CCM_TUPLE(35U, 33U), /*!< OCRAM Clock Gate.*/
550 kCLOCK_OcramS = CCM_TUPLE(36U, 32U), /*!< OCRAM S Clock Gate.*/
551
552 kCLOCK_Pwm1 = CCM_TUPLE(40U, 103U), /*!< PWM1 Clock Gate.*/
553 kCLOCK_Pwm2 = CCM_TUPLE(41U, 104U), /*!< PWM2 Clock Gate.*/
554 kCLOCK_Pwm3 = CCM_TUPLE(42U, 105U), /*!< PWM3 Clock Gate.*/
555 kCLOCK_Pwm4 = CCM_TUPLE(43U, 106U), /*!< PWM4 Clock Gate.*/
556
557 kCLOCK_Qspi = CCM_TUPLE(47U, 87U), /*!< QSPI Clock Gate.*/
558 kCLOCK_Nand = CCM_TUPLE(48U, 86U), /*!< NAND Clock Gate.*/
559
560 kCLOCK_Rdc = CCM_TUPLE(49U, 33U), /*!< RDC Clock Gate.*/
561
562 kCLOCK_Sdma1 = CCM_TUPLE(58U, 33U), /*!< SDMA1 Clock Gate.*/
563
564 kCLOCK_Sec_Debug = CCM_TUPLE(60U, 33U), /*!< SEC_DEBUG Clock Gate.*/
565
566 kCLOCK_Sema42_1 = CCM_TUPLE(61U, 33U), /*!< RDC SEMA42 Clock Gate.*/
567 kCLOCK_Sema42_2 = CCM_TUPLE(62U, 33U), /*!< RDC SEMA42 Clock Gate.*/
568
569 kCLOCK_Sim_enet = CCM_TUPLE(64U, 17U), /*!< SIM_ENET Clock Gate.*/
570 kCLOCK_Sim_m = CCM_TUPLE(65U, 32U), /*!< SIM_M Clock Gate.*/
571 kCLOCK_Sim_main = CCM_TUPLE(66U, 16U), /*!< SIM_MAIN Clock Gate.*/
572 kCLOCK_Sim_s = CCM_TUPLE(67U, 32U), /*!< SIM_S Clock Gate.*/
573 kCLOCK_Sim_wakeup = CCM_TUPLE(68U, 32U), /*!< SIM_WAKEUP Clock Gate.*/
574
575 kCLOCK_Gpu2D = CCM_TUPLE(69U, 5U), /*!< GPU2D Clock Gate.*/
576 kCLOCK_Gpu3D = CCM_TUPLE(70U, 3U), /*!< GPU3D Clock Gate.*/
577
578 kCLOCK_Uart1 = CCM_TUPLE(73U, 94U), /*!< UART1 Clock Gate.*/
579 kCLOCK_Uart2 = CCM_TUPLE(74U, 95U), /*!< UART2 Clock Gate.*/
580 kCLOCK_Uart3 = CCM_TUPLE(75U, 96U), /*!< UART3 Clock Gate.*/
581 kCLOCK_Uart4 = CCM_TUPLE(76U, 97U), /*!< UART4 Clock Gate.*/
582
583 kCLOCK_Usdhc1 = CCM_TUPLE(81U, 88U), /*!< USDHC1 Clock Gate.*/
584 kCLOCK_Usdhc2 = CCM_TUPLE(82U, 89U), /*!< USDHC2 Clock Gate.*/
585 kCLOCK_Wdog1 = CCM_TUPLE(83U, 114U), /*!< WDOG1 Clock Gate.*/
586 kCLOCK_Wdog2 = CCM_TUPLE(84U, 114U), /*!< WDOG2 Clock Gate.*/
587 kCLOCK_Wdog3 = CCM_TUPLE(85U, 114U), /*!< WDOG3 Clock Gate.*/
588
589 kCLOCK_Vpu_G1 = CCM_TUPLE(86U, 66U), /*!< VPU_G1 Clock Gate.*/
590 kCLOCK_Gpu = CCM_TUPLE(87U, 25U), /*!< GPU Clock Gate.*/
591 kCLOCK_Vpu_Vc8ke = CCM_TUPLE(89U, 133U), /*!< VPU_VC8KE Clock Gate.*/
592 kCLOCK_Vpu_G2 = CCM_TUPLE(90U, 67U), /*!< VPU_G2 Clock Gate.*/
593
594 kCLOCK_Npu = CCM_TUPLE(91U, 2U), /*!< NPU Clock Gate.*/
595 kCLOCK_Hsio = CCM_TUPLE(92U, 7U), /*!< HSIO Clock Gate.*/
596 kCLOCK_Media = CCM_TUPLE(93U, 20U), /*!< MEDIA Clock Gate.*/
597 kCLOCK_Usdhc3 = CCM_TUPLE(94U, 121U), /*!< USDHC3 Clock Gate.*/
598 kCLOCK_Hdmi = CCM_TUPLE(95U, 120U), /*!< HDMI Clock Gate.*/
599
600 kCLOCK_TempSensor = CCM_TUPLE(98U, 0xFFFF), /*!< TempSensor Clock Gate.*/
601
602 kCLOCK_Audio = CCM_TUPLE(101U, 6U), /*!< AUDIO Clock Gate.*/
603
604 kCLOCK_Earc = AUDIOMIX_TUPLE(0U, 31U, 0xFFFF), /*!< EARC clock gate */
605 kCLOCK_AudioDspDebug = AUDIOMIX_TUPLE(0U, 30U, 0xFFFF), /*!< AUDIO DSP DEBUG clock gate*/
606 kCLOCK_AudioDsp = AUDIOMIX_TUPLE(0U, 29U, 0xFFFF), /*!< audio dsp clock gate */
607 kCLOCK_Spba2 = AUDIOMIX_TUPLE(0U, 28U, 0xFFFF), /*!< SPBA2 clock gate */
608 kCLOCK_Sdma3 = AUDIOMIX_TUPLE(0U, 27U, 0xFFFF), /*!< SDMA3 clock gate */
609 kCLOCK_Sdma2 = AUDIOMIX_TUPLE(0U, 26U, 0xFFFF), /*!< SDMA2 clock gate */
610 kCLOCK_Pdm = AUDIOMIX_TUPLE(0U, 25U, 132), /*!< PDM clock gate */
611 kCLOCK_Asrc = AUDIOMIX_TUPLE(0U, 24U, 0xFFFF), /*!< ASRC clock gate */
612 kCLOCK_Sai7_Mclk3 = AUDIOMIX_TUPLE(0U, 23U, 0xFFFF), /*!< SAI7 MCLK3 clock gate */
613 kCLOCK_Sai7_Mclk2 = AUDIOMIX_TUPLE(0U, 22U, 0xFFFF), /*!< SAI7 MCLK2 clock gate */
614 kCLOCK_Sai7_Mclk1 = AUDIOMIX_TUPLE(0U, 21U, 0xFFFF), /*!< SAI7 MCLK1 clock gate */
615 kCLOCK_Sai7 = AUDIOMIX_TUPLE(0U, 20U, 134U), /*!< SAI7 clock gate */
616
617 kCLOCK_Sai6_Mclk3 = AUDIOMIX_TUPLE(0U, 19U, 0xFFFF), /*!< SAI6 MCLK3 clock gate */
618 kCLOCK_Sai6_Mclk2 = AUDIOMIX_TUPLE(0U, 18U, 0xFFFF), /*!< SAI6 MCLK2 clock gate */
619 kCLOCK_Sai6_Mclk1 = AUDIOMIX_TUPLE(0U, 17U, 0xFFFF), /*!< SAI6 MCLK1 clock gate */
620 kCLOCK_Sai6 = AUDIOMIX_TUPLE(0U, 16U, 80U), /*!< SAI6 clock gate */
621
622 kCLOCK_Sai5_Mclk3 = AUDIOMIX_TUPLE(0U, 15U, 0xFFFF), /*!< SAI5 MCLK3 clock gate */
623 kCLOCK_Sai5_Mclk2 = AUDIOMIX_TUPLE(0U, 14U, 0xFFFF), /*!< sai5 MCLK2 clock gate */
624 kCLOCK_Sai5_Mclk1 = AUDIOMIX_TUPLE(0U, 13U, 0xFFFF), /*!< SAI5 MCLK1 clock gate */
625 kCLOCK_Sai5 = AUDIOMIX_TUPLE(0U, 12U, 79U), /*!< SAI5 clock gate */
626
627 kCLOCK_Sai3_Mclk3 = AUDIOMIX_TUPLE(0U, 11U, 0xFFFF), /*!< SAI3 MCLK3 clock gate */
628 kCLOCK_Sai3_Mclk2 = AUDIOMIX_TUPLE(0U, 10U, 0xFFFF), /*!< SAI3 MCLK2 clock gate */
629 kCLOCK_Sai3_Mclk1 = AUDIOMIX_TUPLE(0U, 9U, 0xFFFF), /*!< SAI3 MCLK1 clock gate */
630 kCLOCK_Sai3 = AUDIOMIX_TUPLE(0U, 8U, 77U), /*!< SAI3 clock gate */
631
632 kCLOCK_Sai2_Mclk3 = AUDIOMIX_TUPLE(0U, 7U, 0xFFFF), /*!< SAI2 MCLK3 clock gate */
633 kCLOCK_Sai2_Mclk2 = AUDIOMIX_TUPLE(0U, 6U, 0xFFFF), /*!< SAI2 MCLK2 clock gate */
634 kCLOCK_Sai2_Mclk1 = AUDIOMIX_TUPLE(0U, 5U, 0xFFFF), /*!< SAI2 MCLK1 clock gate */
635 kCLOCK_Sai2 = AUDIOMIX_TUPLE(0U, 4U, 76U), /*!< SAI2 clock gate */
636
637 kCLOCK_Sai1_Mclk3 = AUDIOMIX_TUPLE(0U, 3U, 0xFFFF), /*!< SAI1 MCLK3 clock gate */
638 kCLOCK_Sai1_Mclk2 = AUDIOMIX_TUPLE(0U, 2U, 0xFFFF), /*!< SAI1 MCLK2 clock gate */
639 kCLOCK_Sai1_Mclk1 = AUDIOMIX_TUPLE(0U, 1U, 0xFFFF), /*!< SAI1 MCLK1 clock gate */
640 kCLOCK_Sai1 = AUDIOMIX_TUPLE(0U, 0U, 75U), /*!< SAI1 clock gate */
641
642 kCLOCK_EarcPhy = AUDIOMIX_TUPLE(4U, 6U, 0xFFFF), /*!< EARC PHY clock gate */
643 kCLOCK_Mu3 = AUDIOMIX_TUPLE(4U, 5U, 0xFFFF), /*!< MU3 clock gate */
644 kCLOCK_Mu2 = AUDIOMIX_TUPLE(4U, 4U, 0xFFFF), /*!< MU2 clock gate */
645 kCLOCK_Pll = AUDIOMIX_TUPLE(4U, 3U, 0xFFFF), /*!< PLL clock gate */
646 kCLOCK_Edma = AUDIOMIX_TUPLE(4U, 2U, 0xFFFF), /*!< EDMA clock gate */
647 kCLOCK_Aud2htx = AUDIOMIX_TUPLE(4U, 1U, 0xFFFF), /*!< AUD2HTX clock gate */
648 kCLOCK_Ocram_A = AUDIOMIX_TUPLE(4U, 0U, 0xFFFF), /*!< OCRAM A clock gate */
649 } clock_ip_name_t;
650
651 /*! @brief ccm root name used to get clock frequency. */
652 typedef enum _clock_root_control
653 {
654 kCLOCK_RootM7 =
655 (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[1].TARGET_ROOT), /*!< ARM Cortex-M7 Clock control name.*/
656 kCLOCK_RootHsioAxi =
657 (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[7].TARGET_ROOT), /*!< HSIO AXI Clock control name.*/
658 kCLOCK_RootMainAxi =
659 (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[16].TARGET_ROOT), /*!< MAIN AXI Clock control name.*/
660 kCLOCK_RootEnetAxi =
661 (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[17].TARGET_ROOT), /*!< ENET AXI Clock control name.*/
662 kCLOCK_RootNandUsdhcBus =
663 (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[18].TARGET_ROOT), /*!< NAND USDHC BUS Clock control name.*/
664 kCLOCK_RootVpuBus =
665 (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[19].TARGET_ROOT), /*!< VPU BUS Clock control name.*/
666 kCLOCK_RootMediaAxi =
667 (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[20].TARGET_ROOT), /*!< MEDIA AXI Clock control name.*/
668 kCLOCK_RootMediaApb =
669 (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[21].TARGET_ROOT), /*!< MEDIA APB Clock control name.*/
670 kCLOCK_RootHdmiApb =
671 (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[22].TARGET_ROOT), /*!< HDMI APB Clock control name.*/
672 kCLOCK_RootNoc = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[26].TARGET_ROOT), /*!< NOC Clock control name.*/
673 kCLOCK_RootAhb = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[32].TARGET_ROOT), /*!< AHB Clock control name.*/
674 kCLOCK_RootIpg = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[33].TARGET_ROOT), /*!< IPG Clock control name.*/
675 kCLOCK_RootAudioAhb =
676 (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[34].TARGET_ROOT), /*!< Audio AHB Clock control name.*/
677 kCLOCK_RootAudioIpg =
678 (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[35].TARGET_ROOT), /*!< Audio IPG Clock control name.*/
679 kCLOCK_RootDramAlt =
680 (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[64].TARGET_ROOT), /*!< DRAM ALT Clock control name.*/
681 kCLOCK_RootFlexCan1 =
682 (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[68].TARGET_ROOT), /*!< FLEXCAN1 Clock control name.*/
683 kCLOCK_RootFlexCan2 =
684 (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[69].TARGET_ROOT), /*!< FLEXCAN2 Clock control name.*/
685
686 kCLOCK_RootSai1 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[75].TARGET_ROOT), /*!< SAI1 Clock control name.*/
687 kCLOCK_RootSai2 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[76].TARGET_ROOT), /*!< SAI2 Clock control name.*/
688 kCLOCK_RootSai3 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[77].TARGET_ROOT), /*!< SAI3 Clock control name.*/
689 kCLOCK_RootSai5 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[79].TARGET_ROOT), /*!< SAI5 Clock control name.*/
690 kCLOCK_RootSai6 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[80].TARGET_ROOT), /*!< SAI6 Clock control name.*/
691 kCLOCK_RootSai7 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[134].TARGET_ROOT), /*!< SAI7 Clock control name.*/
692
693 kCLOCK_RootEnetQos =
694 (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[81].TARGET_ROOT), /*!< ENET QOS Clock control name.*/
695 kCLOCK_RootEnetQosTimer =
696 (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[82].TARGET_ROOT), /*!< ENET QOS TIMER Clock control name.*/
697 kCLOCK_RootEnetRef = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[83].TARGET_ROOT), /*!< ENET Clock control name.*/
698 kCLOCK_RootEnetTimer =
699 (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[84].TARGET_ROOT), /*!< ENET TIMER Clock control name.*/
700 kCLOCK_RootEnetPhy =
701 (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[85].TARGET_ROOT), /*!< ENET PHY Clock control name.*/
702
703 kCLOCK_RootNand = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[86].TARGET_ROOT), /*!< NAND Clock control name.*/
704 kCLOCK_RootQspi = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[87].TARGET_ROOT), /*!< QSPI Clock control name.*/
705 kCLOCK_RootUsdhc1 =
706 (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[88].TARGET_ROOT), /*!< USDHC1 Clock control name.*/
707 kCLOCK_RootUsdhc2 =
708 (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[89].TARGET_ROOT), /*!< USDHC2 Clock control name.*/
709 kCLOCK_RootUsdhc3 =
710 (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[121].TARGET_ROOT), /*!< USDHC3 Clock control name.*/
711
712 kCLOCK_RootI2c1 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[90].TARGET_ROOT), /*!< I2C1 Clock control name.*/
713 kCLOCK_RootI2c2 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[91].TARGET_ROOT), /*!< I2C2 Clock control name.*/
714 kCLOCK_RootI2c3 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[92].TARGET_ROOT), /*!< I2C3 Clock control name.*/
715 kCLOCK_RootI2c4 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[93].TARGET_ROOT), /*!< I2C4 Clock control name.*/
716 kCLOCK_RootI2c5 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[73].TARGET_ROOT), /*!< I2C5 Clock control name.*/
717 kCLOCK_RootI2c6 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[74].TARGET_ROOT), /*!< I2C6 Clock control name.*/
718
719 kCLOCK_RootUart1 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[94].TARGET_ROOT), /*!< UART1 Clock control name.*/
720 kCLOCK_RootUart2 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[95].TARGET_ROOT), /*!< UART2 Clock control name.*/
721 kCLOCK_RootUart3 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[96].TARGET_ROOT), /*!< UART3 Clock control name.*/
722 kCLOCK_RootUart4 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[97].TARGET_ROOT), /*!< UART4 Clock control name.*/
723
724 kCLOCK_RootGic = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[100].TARGET_ROOT), /*!< GIC Clock control name.*/
725 kCLOCK_RootEcspi1 =
726 (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[101].TARGET_ROOT), /*!< ECSPI1 Clock control name.*/
727 kCLOCK_RootEcspi2 =
728 (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[102].TARGET_ROOT), /*!< ECSPI2 Clock control name.*/
729 kCLOCK_RootEcspi3 =
730 (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[131].TARGET_ROOT), /*!< ECSPI3 Clock control name.*/
731
732 kCLOCK_RootPwm1 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[103].TARGET_ROOT), /*!< PWM1 Clock control name.*/
733 kCLOCK_RootPwm2 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[104].TARGET_ROOT), /*!< PWM2 Clock control name.*/
734 kCLOCK_RootPwm3 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[105].TARGET_ROOT), /*!< PWM3 Clock control name.*/
735 kCLOCK_RootPwm4 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[106].TARGET_ROOT), /*!< PWM4 Clock control name.*/
736
737 kCLOCK_RootGpt1 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[107].TARGET_ROOT), /*!< GPT1 Clock control name.*/
738 kCLOCK_RootGpt2 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[108].TARGET_ROOT), /*!< GPT2 Clock control name.*/
739 kCLOCK_RootGpt3 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[109].TARGET_ROOT), /*!< GPT3 Clock control name.*/
740 kCLOCK_RootGpt4 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[110].TARGET_ROOT), /*!< GPT4 Clock control name.*/
741 kCLOCK_RootGpt5 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[111].TARGET_ROOT), /*!< GPT5 Clock control name.*/
742 kCLOCK_RootGpt6 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[112].TARGET_ROOT), /*!< GPT6 Clock control name.*/
743
744 kCLOCK_RootWdog = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[114].TARGET_ROOT), /*!< WDOG Clock control name.*/
745
746 kCLOCK_RootPdm = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[132].TARGET_ROOT), /*!< PDM Clock control name.*/
747
748 } clock_root_control_t;
749
750 /*! @brief ccm clock root used to get clock frequency. */
751 typedef enum _clock_root
752 {
753 kCLOCK_M7ClkRoot = 0, /*!< ARM Cortex-M7 Clock control name.*/
754 kCLOCK_HsioAxiClkRoot, /*!< HSIO AXI Clock control name.*/
755 kCLOCK_MainAxiClkRoot, /*!< MAIN AXI Clock control name.*/
756 kCLOCK_EnetAxiClkRoot, /*!< ENET AXI Clock control name.*/
757 kCLOCK_NandUsdhcBusClkRoot, /*!< NAND USDHC BUS Clock control name.*/
758 kCLOCK_VpuBusClkRoot, /*!< VPU BUS Clock control name.*/
759 kCLOCK_MediaAxiClkRoot, /*!< MEDIA AXI Clock control name.*/
760 kCLOCK_MediaApbClkRoot, /*!< MEDIA APB Clock control name.*/
761 kCLOCK_HdmiApbClkRoot, /*!< HDMI APB Clock control name.*/
762 kCLOCK_NocClkRoot, /*!< NOC Clock control name.*/
763 kCLOCK_AhbClkRoot, /*!< AHB Clock control name.*/
764 kCLOCK_IpgClkRoot, /*!< IPG Clock control name.*/
765 kCLOCK_AudioAhbClkRoot, /*!< Audio AHB Clock control name.*/
766 kCLOCK_AudioIpgClkRoot, /*!< Audio IPG Clock control name.*/
767 kCLOCK_DramAltClkRoot, /*!< DRAM ALT Clock control name.*/
768 kCLOCK_FlexCan1ClkRoot, /*!< FLEXCAN1 Clock control name.*/
769 kCLOCK_FlexCan2ClkRoot, /*!< FLEXCAN2 Clock control name.*/
770
771 kCLOCK_Sai1ClkRoot, /*!< SAI1 Clock control name.*/
772 kCLOCK_Sai2ClkRoot, /*!< SAI2 Clock control name.*/
773 kCLOCK_Sai3ClkRoot, /*!< SAI3 Clock control name.*/
774 kCLOCK_Sai5ClkRoot, /*!< SAI5 Clock control name.*/
775 kCLOCK_Sai6ClkRoot, /*!< SAI6 Clock control name.*/
776 kCLOCK_Sai7ClkRoot, /*!< SAI7 Clock control name.*/
777
778 kCLOCK_EnetQosClkRoot, /*!< ENET QOS Clock control name.*/
779 kCLOCK_EnetQosTimerClkRoot, /*!< ENET QOS TIMER Clock control name.*/
780 kCLOCK_EnetRefClkRoot, /*!< ENET Clock control name.*/
781 kCLOCK_EnetTimerClkRoot, /*!< ENET TIMER Clock control name.*/
782 kCLOCK_EnetPhyClkRoot, /*!< ENET PHY Clock control name.*/
783
784 kCLOCK_NandClkRoot, /*!< NAND Clock control name.*/
785 kCLOCK_QspiClkRoot, /*!< QSPI Clock control name.*/
786 kCLOCK_Usdhc1ClkRoot, /*!< USDHC1 Clock control name.*/
787 kCLOCK_Usdhc2ClkRoot, /*!< USDHC2 Clock control name.*/
788 kCLOCK_Usdhc3ClkRoot, /*!< USDHC3 Clock control name.*/
789
790 kCLOCK_I2c1ClkRoot, /*!< I2C1 Clock control name.*/
791 kCLOCK_I2c2ClkRoot, /*!< I2C2 Clock control name.*/
792 kCLOCK_I2c3ClkRoot, /*!< I2C3 Clock control name.*/
793 kCLOCK_I2c4ClkRoot, /*!< I2C4 Clock control name.*/
794 kCLOCK_I2c5ClkRoot, /*!< I2C5 Clock control name.*/
795 kCLOCK_I2c6ClkRoot, /*!< I2C6 Clock control name.*/
796
797 kCLOCK_Uart1ClkRoot, /*!< UART1 Clock control name.*/
798 kCLOCK_Uart2ClkRoot, /*!< UART2 Clock control name.*/
799 kCLOCK_Uart3ClkRoot, /*!< UART3 Clock control name.*/
800 kCLOCK_Uart4ClkRoot, /*!< UART4 Clock control name.*/
801
802 kCLOCK_GicClkRoot, /*!< GIC Clock control name.*/
803 kCLOCK_Ecspi1ClkRoot, /*!< ECSPI1 Clock control name.*/
804 kCLOCK_Ecspi2ClkRoot, /*!< ECSPI2 Clock control name.*/
805 kCLOCK_Ecspi3ClkRoot, /*!< ECSPI3 Clock control name.*/
806
807 kCLOCK_Pwm1ClkRoot, /*!< PWM1 Clock control name.*/
808 kCLOCK_Pwm2ClkRoot, /*!< PWM2 Clock control name.*/
809 kCLOCK_Pwm3ClkRoot, /*!< PWM3 Clock control name.*/
810 kCLOCK_Pwm4ClkRoot, /*!< PWM4 Clock control name.*/
811
812 kCLOCK_Gpt1ClkRoot, /*!< GPT1 Clock control name.*/
813 kCLOCK_Gpt2ClkRoot, /*!< GPT2 Clock control name.*/
814 kCLOCK_Gpt3ClkRoot, /*!< GPT3 Clock control name.*/
815 kCLOCK_Gpt4ClkRoot, /*!< GPT4 Clock control name.*/
816 kCLOCK_Gpt5ClkRoot, /*!< GPT5 Clock control name.*/
817 kCLOCK_Gpt6ClkRoot, /*!< GPT6 Clock control name.*/
818
819 kCLOCK_WdogClkRoot, /*!< WDOG Clock control name.*/
820
821 kCLOCK_PdmClkRoot, /*!< PDM Clock control name.*/
822
823 } clock_root_t;
824
825 /*! @brief Root clock select enumeration for ARM Cortex-M7 core. */
826 typedef enum _clock_rootmux_m7_clk_sel
827 {
828 kCLOCK_M7RootmuxOsc24M = 0U, /*!< ARM Cortex-M7 Clock from OSC 24M.*/
829 kCLOCK_M7RootmuxSysPll2Div5 = 1U, /*!< ARM Cortex-M7 Clock from SYSTEM PLL2 divided by 5.*/
830 kCLOCK_M7RootmuxSysPll2Div4 = 2U, /*!< ARM Cortex-M7 Clock from SYSTEM PLL2 divided by 4.*/
831 kCLOCK_M7RootmuxSysVpuPll = 3U, /*!< ARM Cortex-M7 Clock from VPU PLL.*/
832 kCLOCK_M7RootmuxSysPll1 = 4U, /*!< ARM Cortex-M7 Clock from SYSTEM PLL1.*/
833 kCLOCK_M7RootmuxAudioPll1 = 5U, /*!< ARM Cortex-M7 Clock from AUDIO PLL1.*/
834 kCLOCK_M7RootmuxVideoPll1 = 6U, /*!< ARM Cortex-M7 Clock from VIDEO PLL1.*/
835 kCLOCK_M7RootmuxSysPll3 = 7U, /*!< ARM Cortex-M7 Clock from SYSTEM PLL3.*/
836 } clock_rootmux_m7_clk_sel_t;
837
838 /*! @brief Root clock select enumeration for MAIN AXI bus. */
839 typedef enum _clock_rootmux_axi_clk_sel
840 {
841 kCLOCK_AxiRootmuxOsc24M = 0U, /*!< ARM MAIN AXI Clock from OSC 24M.*/
842 kCLOCK_AxiRootmuxSysPll2Div3 = 1U, /*!< ARM MAIN AXI Clock from SYSTEM PLL2 divided by 3.*/
843 kCLOCK_AxiRootmuxSysPll1 = 2U, /*!< ARM MAIN AXI Clock from SYSTEM PLL1.*/
844 kCLOCK_AxiRootmuxSysPll2Div4 = 3U, /*!< ARM MAIN AXI Clock from SYSTEM PLL2 divided by 4.*/
845 kCLOCK_AxiRootmuxSysPll2 = 4U, /*!< ARM MAIN AXI Clock from SYSTEM PLL2.*/
846 kCLOCK_AxiRootmuxAudioPll1 = 5U, /*!< ARM MAIN AXI Clock from AUDIO PLL1.*/
847 kCLOCK_AxiRootmuxVideoPll1 = 6U, /*!< ARM MAIN AXI Clock from VIDEO PLL1.*/
848 kCLOCK_AxiRootmuxSysPll1Div8 = 7U, /*!< ARM MAIN AXI Clock from SYSTEM PLL1 divided by 8.*/
849 } clock_rootmux_axi_clk_sel_t;
850
851 /*! @brief Root clock select enumeration for AHB bus. */
852 typedef enum _clock_rootmux_ahb_clk_sel
853 {
854 kCLOCK_AhbRootmuxOsc24M = 0U, /*!< ARM AHB Clock from OSC 24M.*/
855 kCLOCK_AhbRootmuxSysPll1Div6 = 1U, /*!< ARM AHB Clock from SYSTEM PLL1 divided by 6.*/
856 kCLOCK_AhbRootmuxSysPll1 = 2U, /*!< ARM AHB Clock from SYSTEM PLL1.*/
857 kCLOCK_AhbRootmuxSysPll1Div2 = 3U, /*!< ARM AHB Clock from SYSTEM PLL1 divided by 2.*/
858 kCLOCK_AhbRootmuxSysPll2Div8 = 4U, /*!< ARM AHB Clock from SYSTEM PLL2 divided by 8.*/
859 kCLOCK_AhbRootmuxSysPll3 = 5U, /*!< ARM AHB Clock from SYSTEM PLL3.*/
860 kCLOCK_AhbRootmuxAudioPll1 = 6U, /*!< ARM AHB Clock from AUDIO PLL1.*/
861 kCLOCK_AhbRootmuxVideoPll1 = 7U, /*!< ARM AHB Clock from VIDEO PLL1.*/
862 } clock_rootmux_ahb_clk_sel_t;
863
864 /*! @brief Root clock select enumeration for Audio AHB bus. */
865 typedef enum _clock_rootmux_audio_ahb_clk_sel
866 {
867 kCLOCK_AudioAhbRootmuxOsc24M = 0U, /*!< ARM Audio AHB Clock from OSC 24M.*/
868 kCLOCK_AudioAhbRootmuxSysPll2Div2 = 1U, /*!< ARM Audio AHB Clock from SYSTEM PLL2 divided by 2.*/
869 kCLOCK_AudioAhbRootmuxSysPll1 = 2U, /*!< ARM Audio AHB Clock from SYSTEM PLL1.*/
870 kCLOCK_AudioAhbRootmuxSysPll2 = 3U, /*!< ARM Audio AHB Clock from SYSTEM PLL2.*/
871 kCLOCK_AudioAhbRootmuxSysPll2Div6 = 4U, /*!< ARM Audio AHB Clock from SYSTEM PLL2 divided by 6.*/
872 kCLOCK_AudioAhbRootmuxSysPll3 = 5U, /*!< ARM Audio AHB Clock from SYSTEM PLL3.*/
873 kCLOCK_AudioAhbRootmuxAudioPll1 = 6U, /*!< ARM Audio AHB Clock from AUDIO PLL1.*/
874 kCLOCK_AudioAhbRootmuxVideoPll1 = 7U, /*!< ARM Audio AHB Clock from VIDEO PLL1.*/
875 } clock_rootmux_audio_ahb_clk_sel_t;
876 /*! @brief Root clock select enumeration for QSPI peripheral. */
877 typedef enum _clock_rootmux_qspi_clk_sel
878 {
879 kCLOCK_QspiRootmuxOsc24M = 0U, /*!< ARM QSPI Clock from OSC 24M.*/
880 kCLOCK_QspiRootmuxSysPll1Div2 = 1U, /*!< ARM QSPI Clock from SYSTEM PLL1 divided by 2.*/
881 kCLOCK_QspiRootmuxSysPll2Div3 = 2U, /*!< ARM QSPI Clock from SYSTEM PLL2 divided by 3.*/
882 kCLOCK_QspiRootmuxSysPll2Div2 = 3U, /*!< ARM QSPI Clock from SYSTEM PLL2 divided by 2.*/
883 kCLOCK_QspiRootmuxAudioPll2 = 4U, /*!< ARM QSPI Clock from AUDIO PLL2.*/
884 kCLOCK_QspiRootmuxSysPll1Div3 = 5U, /*!< ARM QSPI Clock from SYSTEM PLL1 divided by 3 */
885 kCLOCK_QspiRootmuxSysPll3 = 6, /*!< ARM QSPI Clock from SYSTEM PLL3.*/
886 kCLOCK_QspiRootmuxSysPll1Div8 = 7U, /*!< ARM QSPI Clock from SYSTEM PLL1 divided by 8.*/
887 } clock_rootmux_qspi_clk_sel_t;
888
889 /*! @brief Root clock select enumeration for ECSPI peripheral. */
890 typedef enum _clock_rootmux_ecspi_clk_sel
891 {
892 kCLOCK_EcspiRootmuxOsc24M = 0U, /*!< ECSPI Clock from OSC 24M.*/
893 kCLOCK_EcspiRootmuxSysPll2Div5 = 1U, /*!< ECSPI Clock from SYSTEM PLL2 divided by 5.*/
894 kCLOCK_EcspiRootmuxSysPll1Div20 = 2U, /*!< ECSPI Clock from SYSTEM PLL1 divided by 20.*/
895 kCLOCK_EcspiRootmuxSysPll1Div5 = 3U, /*!< ECSPI Clock from SYSTEM PLL1 divided by 5.*/
896 kCLOCK_EcspiRootmuxSysPll1 = 4U, /*!< ECSPI Clock from SYSTEM PLL1.*/
897 kCLOCK_EcspiRootmuxSysPll3 = 5U, /*!< ECSPI Clock from SYSTEM PLL3.*/
898 kCLOCK_EcspiRootmuxSysPll2Div4 = 6U, /*!< ECSPI Clock from SYSTEM PLL2 divided by 4.*/
899 kCLOCK_EcspiRootmuxAudioPll2 = 7U, /*!< ECSPI Clock from AUDIO PLL2.*/
900 } clock_rootmux_ecspi_clk_sel_t;
901
902 /*! @brief Root clock select enumeration for ENET AXI bus. */
903 typedef enum _clock_rootmux_enet_axi_clk_sel
904 {
905 kCLOCK_EnetAxiRootmuxOsc24M = 0U, /*!< ENET AXI Clock from OSC 24M.*/
906 kCLOCK_EnetAxiRootmuxSysPll1Div3 = 1U, /*!< ENET AXI Clock from SYSTEM PLL1 divided by 3.*/
907 kCLOCK_EnetAxiRootmuxSysPll1 = 2U, /*!< ENET AXI Clock from SYSTEM PLL1.*/
908 kCLOCK_EnetAxiRootmuxSysPll2Div4 = 3U, /*!< ENET AXI Clock from SYSTEM PLL2 divided by 4.*/
909 kCLOCK_EnetAxiRootmuxSysPll2Div5 = 4U, /*!< ENET AXI Clock from SYSTEM PLL2 divided by 5.*/
910 kCLOCK_EnetAxiRootmuxAudioPll1 = 5U, /*!< ENET AXI Clock from AUDIO PLL1.*/
911 kCLOCK_EnetAxiRootmuxVideoPll1 = 6U, /*!< ENET AXI Clock from VIDEO PLL1.*/
912 kCLOCK_EnetAxiRootmuxSysPll3 = 7U, /*!< ENET AXI Clock from SYSTEM PLL3.*/
913 } clock_rootmux_enet_axi_clk_sel_t;
914
915 /*! @brief Root clock select enumeration for ENET QOS Clcok. */
916 typedef enum _clock_rootmux_enet_qos_clk_sel
917 {
918 kCLOCK_EnetQosRootmuxOsc24M = 0U, /*!< ENET QOS Clock from OSC 24M.*/
919 kCLOCK_EnetQosRootmuxSysPll2Div8 = 1U, /*!< ENET QOS Clock from SYSTEM PLL2 divided by 8.*/
920 kCLOCK_EnetQosRootmuxSysPll2Div20 = 2U, /*!< ENET QOS Clock from SYSTEM PLL2 divided by 20.*/
921 kCLOCK_EnetQosRootmuxSysPll2Div10 = 3U, /*!< ENET QOS Clock from SYSTEM PLL2 divided by 10.*/
922 kCLOCK_EnetQosRootmuxSysPll1Div5 = 4U, /*!< ENET QOS Clock from SYSTEM PLL1 divided by 5.*/
923 kCLOCK_EnetQosRootmuxAudioPll1 = 5U, /*!< ENET QOS Clock from AUDIO PLL1.*/
924 kCLOCK_EnetQosRootmuxVideoPll1 = 6U, /*!< ENET QOS Clock from VIDEO PLL1.*/
925 kCLOCK_EnetQosRootmuxExtClk4 = 7U, /*!< ENET QOS Clock from External Clock 4.*/
926 } clock_rootmux_enet_qos_clk_sel_t;
927
928 /*! @brief Root clock select enumeration for ENET REF Clcok. */
929 typedef enum _clock_rootmux_enet_ref_clk_sel
930 {
931 kCLOCK_EnetRefRootmuxOsc24M = 0U, /*!< ENET REF Clock from OSC 24M.*/
932 kCLOCK_EnetRefRootmuxSysPll2Div8 = 1U, /*!< ENET REF Clock from SYSTEM PLL2 divided by 8.*/
933 kCLOCK_EnetRefRootmuxSysPll2Div20 = 2U, /*!< ENET REF Clock from SYSTEM PLL2 divided by 20.*/
934 kCLOCK_EnetRefRootmuxSysPll2Div10 = 3U, /*!< ENET REF Clock from SYSTEM PLL2 divided by 10.*/
935 kCLOCK_EnetRefRootmuxSysPll1Div5 = 4U, /*!< ENET REF Clock from SYSTEM PLL1 divided by 5.*/
936 kCLOCK_EnetRefRootmuxAudioPll1 = 5U, /*!< ENET REF Clock from AUDIO PLL1.*/
937 kCLOCK_EnetRefRootmuxVideoPll1 = 6U, /*!< ENET REF Clock from VIDEO PLL1.*/
938 kCLOCK_EnetRefRootmuxExtClk4 = 7U, /*!< ENET REF Clock from External Clock 4.*/
939 } clock_rootmux_enet_ref_clk_sel_t;
940
941 /*! @brief Root clock select enumeration for ENET QOS TIMER Clcok. */
942 typedef enum _clock_rootmux_enet_qos_timer_clk_sel
943 {
944 kCLOCK_EnetQosTimerRootmuxOsc24M = 0U, /*!< ENET QOS TIMER Clock from OSC 24M.*/
945 kCLOCK_EnetQosTimerRootmuxSysPll2Div10 = 1U, /*!< ENET QOS TIMER Clock from SYSTEM PLL2 divided by 10.*/
946 kCLOCK_EnetQosTimerRootmuxAudioPll1 = 2U, /*!< ENET QOS TIMER Clock from AUDIO PLL1.*/
947 kCLOCK_EnetQosTimerRootmuxExtClk1 = 3U, /*!< ENET QOS TIMER Clock from External Clock 1.*/
948 kCLOCK_EnetQosTimerRootmuxExtClk2 = 4U, /*!< ENET QOS TIMER Clock External Clock 2.*/
949 kCLOCK_EnetQosTimerRootmuxExtClk3 = 5U, /*!< ENET QOS TIMER Clock from External Clock 3.*/
950 kCLOCK_EnetQosTimerRootmuxExtClk4 = 6U, /*!< ENET QOS TIMER Clock from External Clock 4.*/
951 kCLOCK_EnetQosTimerRootmuxVideoPll1 = 7U, /*!< ENET QOS TIMER Clock from VIDEO PLL1.*/
952 } clock_rootmux_enet_qos_timer_clk_sel_t;
953
954 /*! @brief Root clock select enumeration for ENET TIMER Clcok. */
955 typedef enum _clock_rootmux_enet_timer_clk_sel
956 {
957 kCLOCK_EnetTimerRootmuxOsc24M = 0U, /*!< ENET TIMER Clock from OSC 24M.*/
958 kCLOCK_EnetTimerRootmuxSysPll2Div10 = 1U, /*!< ENET TIMER Clock from SYSTEM PLL2 divided by 10.*/
959 kCLOCK_EnetTimerRootmuxAudioPll1 = 2U, /*!< ENET TIMER Clock from AUDIO PLL1.*/
960 kCLOCK_EnetTimerRootmuxExtClk1 = 3U, /*!< ENET TIMER Clock from External Clock 1.*/
961 kCLOCK_EnetTimerRootmuxExtClk2 = 4U, /*!< ENET TIMER Clock External Clock 2.*/
962 kCLOCK_EnetTimerRootmuxExtClk3 = 5U, /*!< ENET TIMER Clock from External Clock 3.*/
963 kCLOCK_EnetTimerRootmuxExtClk4 = 6U, /*!< ENET TIMER Clock from External Clock 4.*/
964 kCLOCK_EnetTimerRootmuxVideoPll1 = 7U, /*!< ENET TIMER Clock from VIDEO PLL1.*/
965 } clock_rootmux_enet_timer_clk_sel_t;
966
967 /*! @brief Root clock select enumeration for ENET PHY Clcok. */
968 typedef enum _clock_rootmux_enet_phy_clk_sel
969 {
970 kCLOCK_EnetPhyRootmuxOsc24M = 0U, /*!< ENET PHY Clock from OSC 24M.*/
971 kCLOCK_EnetPhyRootmuxSysPll2Div20 = 1U, /*!< ENET PHY Clock from SYSTEM PLL2 divided by 20.*/
972 kCLOCK_EnetPhyRootmuxSysPll2Div8 = 2U, /*!< ENET PHY Clock from SYSTEM PLL2 divided by 8.*/
973 kCLOCK_EnetPhyRootmuxSysPll2Div5 = 3U, /*!< ENET PHY Clock from SYSTEM PLL2 divided by 5.*/
974 kCLOCK_EnetPhyRootmuxSysPll2Div2 = 4U, /*!< ENET PHY Clock from SYSTEM PLL2 divided by 2.*/
975 kCLOCK_EnetPhyRootmuxAudioPll1 = 5U, /*!< ENET PHY Clock from AUDIO PLL1.*/
976 kCLOCK_EnetPhyRootmuxVideoPll1 = 6U, /*!< ENET PHY Clock from VIDEO PLL1.*/
977 kCLOCK_EnetPhyRootmuxAudioPll2 = 7U, /*!< ENET PHY Clock from AUDIO PLL2.*/
978 } clock_rootmux_enet_phy_clk_sel_t;
979
980 /*! @brief Root clock select enumeration for FLEXCAN peripheral. */
981 typedef enum _clock_rootmux_flexcan_clk_sel
982 {
983 kCLOCK_FlexCanRootmuxOsc24M = 0U, /*!< FLEXCAN Clock from OSC 24M.*/
984 kCLOCK_FlexCanRootmuxSysPll2Div5 = 1U, /*!< FLEXCAN Clock from SYSTEM PLL2 divided by 5.*/
985 kCLOCK_FlexCanRootmuxSysPll1Div20 = 2U, /*!< FLEXCAN Clock from SYSTEM PLL1 divided by 20.*/
986 kCLOCK_FlexCanRootmuxSysPll1Div5 = 3U, /*!< FLEXCAN Clock from SYSTEM PLL1 divided by 5.*/
987 kCLOCK_FlexCanRootmuxSysPll1 = 4U, /*!< FLEXCAN Clock from SYSTEM PLL1.*/
988 kCLOCK_FlexCanRootmuxSysPll3 = 5U, /*!< FLEXCAN Clock from SYSTEM PLL3.*/
989 kCLOCK_FlexCanRootmuxSysPll2Div4 = 6U, /*!< FLEXCAN Clock from SYSTEM PLL2 divided by 4.*/
990 kCLOCK_FlexCanRootmuxAudioPll2 = 7U, /*!< FLEXCAN Clock from AUDIO PLL2.*/
991 } clock_rootmux_flexcan_clk_sel_t;
992
993 /*! @brief Root clock select enumeration for I2C peripheral. */
994 typedef enum _clock_rootmux_i2c_clk_sel
995 {
996 kCLOCK_I2cRootmuxOsc24M = 0U, /*!< I2C Clock from OSC 24M.*/
997 kCLOCK_I2cRootmuxSysPll1Div5 = 1U, /*!< I2C Clock from SYSTEM PLL1 divided by 5.*/
998 kCLOCK_I2cRootmuxSysPll2Div20 = 2U, /*!< I2C Clock from SYSTEM PLL2 divided by 20.*/
999 kCLOCK_I2cRootmuxSysPll3 = 3U, /*!< I2C Clock from SYSTEM PLL3 .*/
1000 kCLOCK_I2cRootmuxAudioPll1 = 4U, /*!< I2C Clock from AUDIO PLL1.*/
1001 kCLOCK_I2cRootmuxVideoPll1 = 5U, /*!< I2C Clock from VIDEO PLL1.*/
1002 kCLOCK_I2cRootmuxAudioPll2 = 6U, /*!< I2C Clock from AUDIO PLL2.*/
1003 kCLOCK_I2cRootmuxSysPll1Div6 = 7U, /*!< I2C Clock from SYSTEM PLL1 divided by 6.*/
1004 } clock_rootmux_i2c_clk_sel_t;
1005
1006 /*! @brief Root clock select enumeration for UART peripheral. */
1007 typedef enum _clock_rootmux_uart_clk_sel
1008 {
1009 kCLOCK_UartRootmuxOsc24M = 0U, /*!< UART Clock from OSC 24M.*/
1010 kCLOCK_UartRootmuxSysPll1Div10 = 1U, /*!< UART Clock from SYSTEM PLL1 divided by 10.*/
1011 kCLOCK_UartRootmuxSysPll2Div5 = 2U, /*!< UART Clock from SYSTEM PLL2 divided by 5.*/
1012 kCLOCK_UartRootmuxSysPll2Div10 = 3U, /*!< UART Clock from SYSTEM PLL2 divided by 10.*/
1013 kCLOCK_UartRootmuxSysPll3 = 4U, /*!< UART Clock from SYSTEM PLL3.*/
1014 kCLOCK_UartRootmuxExtClk2 = 5U, /*!< UART Clock from External Clock 2.*/
1015 kCLOCK_UartRootmuxExtClk34 = 6U, /*!< UART Clock from External Clock 3, External Clock 4.*/
1016 kCLOCK_UartRootmuxAudioPll2 = 7U, /*!< UART Clock from Audio PLL2.*/
1017 } clock_rootmux_uart_clk_sel_t;
1018
1019 /*! @brief Root clock select enumeration for GPT peripheral. */
1020 typedef enum _clock_rootmux_gpt
1021 {
1022 kCLOCK_GptRootmuxOsc24M = 0U, /*!< GPT Clock from OSC 24M.*/
1023 kCLOCK_GptRootmuxSystemPll2Div10 = 1U, /*!< GPT Clock from SYSTEM PLL2 divided by 10.*/
1024 kCLOCK_GptRootmuxSysPll1Div2 = 2U, /*!< GPT Clock from SYSTEM PLL1 divided by 2.*/
1025 kCLOCK_GptRootmuxSysPll1Div20 = 3U, /*!< GPT Clock from SYSTEM PLL1 divided by 20.*/
1026 kCLOCK_GptRootmuxVideoPll1 = 4U, /*!< GPT Clock from VIDEO PLL1.*/
1027 kCLOCK_GptRootmuxSystemPll1Div10 = 5U, /*!< GPT Clock from SYSTEM PLL1 divided by 10.*/
1028 kCLOCK_GptRootmuxAudioPll1 = 6U, /*!< GPT Clock from AUDIO PLL1.*/
1029 kCLOCK_GptRootmuxExtClk123 = 7U, /*!< GPT Clock from External Clock1, External Clock2, External Clock3.*/
1030 } clock_rootmux_gpt_t;
1031
1032 /*! @brief Root clock select enumeration for WDOG peripheral. */
1033 typedef enum _clock_rootmux_wdog_clk_sel
1034 {
1035 kCLOCK_WdogRootmuxOsc24M = 0U, /*!< WDOG Clock from OSC 24M.*/
1036 kCLOCK_WdogRootmuxSysPll1Div6 = 1U, /*!< WDOG Clock from SYSTEM PLL1 divided by 6.*/
1037 kCLOCK_WdogRootmuxSysPll1Div5 = 2U, /*!< WDOG Clock from SYSTEM PLL1 divided by 5.*/
1038 kCLOCK_WdogRootmuxVpuPll = 3U, /*!< WDOG Clock from VPU DLL.*/
1039 kCLOCK_WdogRootmuxSystemPll2Div8 = 4U, /*!< WDOG Clock from SYSTEM PLL2 divided by 8.*/
1040 kCLOCK_WdogRootmuxSystemPll3 = 5U, /*!< WDOG Clock from SYSTEM PLL3.*/
1041 kCLOCK_WdogRootmuxSystemPll1Div10 = 6U, /*!< WDOG Clock from SYSTEM PLL1 divided by 10.*/
1042 kCLOCK_WdogRootmuxSystemPll2Div6 = 7U, /*!< WDOG Clock from SYSTEM PLL2 divided by 6.*/
1043 } clock_rootmux_wdog_clk_sel_t;
1044
1045 /*! @brief Root clock select enumeration for PWM peripheral. */
1046 typedef enum _clock_rootmux_pwm_clk_sel
1047 {
1048 kCLOCK_PwmRootmuxOsc24M = 0U, /*!< PWM Clock from OSC 24M.*/
1049 kCLOCK_PwmRootmuxSysPll2Div10 = 1U, /*!< PWM Clock from SYSTEM PLL2 divided by 10.*/
1050 kCLOCK_PwmRootmuxSysPll1Div5 = 2U, /*!< PWM Clock from SYSTEM PLL1 divided by 5.*/
1051 kCLOCK_PwmRootmuxSysPll1Div20 = 3U, /*!< PWM Clock from SYSTEM PLL1 divided by 20.*/
1052 kCLOCK_PwmRootmuxSystemPll3 = 4U, /*!< PWM Clock from SYSTEM PLL3.*/
1053 kCLOCK_PwmRootmuxExtClk12 = 5U, /*!< PWM Clock from External Clock1, External Clock2.*/
1054 kCLOCK_PwmRootmuxSystemPll1Div10 = 6U, /*!< PWM Clock from SYSTEM PLL1 divided by 10.*/
1055 kCLOCK_PwmRootmuxVideoPll1 = 7U, /*!< PWM Clock from VIDEO PLL1.*/
1056 } clock_rootmux_Pwm_clk_sel_t;
1057
1058 /*! @brief Root clock select enumeration for SAI peripheral. */
1059 typedef enum _clock_rootmux_sai_clk_sel
1060 {
1061 kCLOCK_SaiRootmuxOsc24M = 0U, /*!< SAI Clock from OSC 24M.*/
1062 kCLOCK_SaiRootmuxAudioPll1 = 1U, /*!< SAI Clock from AUDIO PLL1.*/
1063 kCLOCK_SaiRootmuxAudioPll2 = 2U, /*!< SAI Clock from AUDIO PLL2.*/
1064 kCLOCK_SaiRootmuxVideoPll1 = 3U, /*!< SAI Clock from VIDEO PLL1.*/
1065 kCLOCK_SaiRootmuxSysPll1Div6 = 4U, /*!< SAI Clock from SYSTEM PLL1 divided by 6.*/
1066 kCLOCK_SaiRootmuxOsc26m = 5U, /*!< SAI Clock from OSC HDMI 26M.*/
1067 kCLOCK_SaiRootmuxExtClk1 = 6U, /*!< SAI Clock from External Clock1, External Clock2, External Clock3.*/
1068 kCLOCK_SaiRootmuxExtClk2 = 7U, /*!< SAI Clock from External Clock2, External Clock3, External Clock4.*/
1069 } clock_rootmux_sai_clk_sel_t;
1070
1071 /*! @brief Root clock select enumeration for PDM peripheral. */
1072 typedef enum _clock_rootmux_pdm_clk_sel
1073 {
1074 kCLOCK_PdmRootmuxOsc24M = 0U, /*!< PDM Clock from OSC 24M.*/
1075 kCLOCK_PdmRootmuxSysPll2Div10 = 1U, /*!< PDM Clock from SYSTEM PLL2 divided by 10.*/
1076 kCLOCK_PdmRootmuxAudioPll1 = 2U, /*!< PDM Clock from AUDIO PLL1.*/
1077 kCLOCK_PdmRootmuxSysPll1 = 3U, /*!< PDM Clock from SYSTEM PLL1.*/
1078 kCLOCK_PdmRootmuxSysPll2 = 4U, /*!< PDM Clock from SYSTEM PLL2.*/
1079 kCLOCK_PdmRootmuxSysPll3 = 5U, /*!< PDM Clock from SYSTEM PLL3.*/
1080 kCLOCK_PdmRootmuxExtClk3 = 6U, /*!< PDM Clock from External Clock3.*/
1081 kCLOCK_PdmRootmuxAudioPll2 = 7U, /*!< PDM Clock from AUDIO PLL2.*/
1082 } clock_rootmux_pdm_clk_sel_t;
1083
1084 /*! @brief Root clock select enumeration for NOC CLK. */
1085 typedef enum _clock_rootmux_noc_clk_sel
1086 {
1087 kCLOCK_NocRootmuxOsc24M = 0U, /*!< NOC Clock from OSC 24M.*/
1088 kCLOCK_NocRootmuxSysPll1 = 1U, /*!< NOC Clock from SYSTEM PLL1.*/
1089 kCLOCK_NocRootmuxSysPll3 = 2U, /*!< NOC Clock from SYSTEM PLL3.*/
1090 kCLOCK_NocRootmuxSysPll2 = 3U, /*!< NOC Clock from SYSTEM PLL2.*/
1091 kCLOCK_NocRootmuxSysPll2Div2 = 4U, /*!< NOC Clock from SYSTEM PLL2 divided by 2.*/
1092 kCLOCK_NocRootmuxAudioPll1 = 5U, /*!< NOC Clock from AUDIO PLL1.*/
1093 kCLOCK_NocRootmuxVideoPll1 = 6U, /*!< NOC Clock from VIDEO PLL1.*/
1094 kCLOCK_NocRootmuxAudioPll2 = 7U, /*!< NOC Clock from AUDIO PLL2.*/
1095
1096 } clock_rootmux_noc_clk_sel_t;
1097
1098 /*! @brief CCM PLL gate control. */
1099 typedef enum _clock_pll_gate
1100 {
1101 kCLOCK_ArmPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[12].PLL_CTRL), /*!< ARM PLL Gate.*/
1102
1103 kCLOCK_GpuPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[13].PLL_CTRL), /*!< GPU PLL Gate.*/
1104 kCLOCK_VpuPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[14].PLL_CTRL), /*!< VPU PLL Gate.*/
1105 kCLOCK_DramPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[15].PLL_CTRL), /*!< DRAM PLL1 Gate.*/
1106
1107 kCLOCK_SysPll1Gate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[16].PLL_CTRL), /*!< SYSTEM PLL1 Gate.*/
1108 kCLOCK_SysPll1Div2Gate =
1109 (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[17].PLL_CTRL), /*!< SYSTEM PLL1 Div2 Gate.*/
1110 kCLOCK_SysPll1Div3Gate =
1111 (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[18].PLL_CTRL), /*!< SYSTEM PLL1 Div3 Gate.*/
1112 kCLOCK_SysPll1Div4Gate =
1113 (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[19].PLL_CTRL), /*!< SYSTEM PLL1 Div4 Gate.*/
1114 kCLOCK_SysPll1Div5Gate =
1115 (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[20].PLL_CTRL), /*!< SYSTEM PLL1 Div5 Gate.*/
1116 kCLOCK_SysPll1Div6Gate =
1117 (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[21].PLL_CTRL), /*!< SYSTEM PLL1 Div6 Gate.*/
1118 kCLOCK_SysPll1Div8Gate =
1119 (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[22].PLL_CTRL), /*!< SYSTEM PLL1 Div8 Gate.*/
1120 kCLOCK_SysPll1Div10Gate =
1121 (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[23].PLL_CTRL), /*!< SYSTEM PLL1 Div10 Gate.*/
1122 kCLOCK_SysPll1Div20Gate =
1123 (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[24].PLL_CTRL), /*!< SYSTEM PLL1 Div20 Gate.*/
1124
1125 kCLOCK_SysPll2Gate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[25].PLL_CTRL), /*!< SYSTEM PLL2 Gate.*/
1126 kCLOCK_SysPll2Div2Gate =
1127 (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[26].PLL_CTRL), /*!< SYSTEM PLL2 Div2 Gate.*/
1128 kCLOCK_SysPll2Div3Gate =
1129 (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[27].PLL_CTRL), /*!< SYSTEM PLL2 Div3 Gate.*/
1130 kCLOCK_SysPll2Div4Gate =
1131 (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[28].PLL_CTRL), /*!< SYSTEM PLL2 Div4 Gate.*/
1132 kCLOCK_SysPll2Div5Gate =
1133 (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[29].PLL_CTRL), /*!< SYSTEM PLL2 Div5 Gate.*/
1134 kCLOCK_SysPll2Div6Gate =
1135 (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[30].PLL_CTRL), /*!< SYSTEM PLL2 Div6 Gate.*/
1136 kCLOCK_SysPll2Div8Gate =
1137 (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[31].PLL_CTRL), /*!< SYSTEM PLL2 Div8 Gate.*/
1138 kCLOCK_SysPll2Div10Gate =
1139 (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[32].PLL_CTRL), /*!< SYSTEM PLL2 Div10 Gate.*/
1140 kCLOCK_SysPll2Div20Gate =
1141 (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[33].PLL_CTRL), /*!< SYSTEM PLL2 Div20 Gate.*/
1142
1143 kCLOCK_SysPll3Gate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[34].PLL_CTRL), /*!< SYSTEM PLL3 Gate.*/
1144
1145 kCLOCK_AudioPll1Gate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[35].PLL_CTRL), /*!< AUDIO PLL1 Gate.*/
1146 kCLOCK_AudioPll2Gate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[36].PLL_CTRL), /*!< AUDIO PLL2 Gate.*/
1147 kCLOCK_VideoPll1Gate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[37].PLL_CTRL), /*!< VIDEO PLL1 Gate.*/
1148 kCLOCK_VideoPll2Gate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[38].PLL_CTRL), /*!< VIDEO PLL2 Gate.*/
1149 } clock_pll_gate_t;
1150
1151 /*! @brief CCM gate control value. */
1152 typedef enum _clock_gate_value
1153 {
1154 kCLOCK_ClockNotNeeded = 0x0U, /*!< Clock always disabled.*/
1155 kCLOCK_ClockNeededRun = 0x1111U, /*!< Clock enabled when CPU is running.*/
1156 kCLOCK_ClockNeededRunWait = 0x2222U, /*!< Clock enabled when CPU is running or in WAIT mode.*/
1157 kCLOCK_ClockNeededAll = 0x3333U, /*!< Clock always enabled.*/
1158 } clock_gate_value_t;
1159
1160 /*!
1161 * @brief PLL control names for PLL bypass.
1162 *
1163 * These constants define the PLL control names for PLL bypass.\n
1164 * - 0:15: REG offset to CCM_ANALOG_BASE in bytes.
1165 * - 16:20: bypass bit shift.
1166 */
1167 typedef enum _clock_pll_bypass_ctrl
1168 {
1169 kCLOCK_AudioPll1BypassCtrl =
1170 CCM_ANALOG_TUPLE(AUDIO_PLL1_GEN_CTRL_OFFSET,
1171 CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_BYPASS_SHIFT), /*!< CCM Audio PLL1 bypass Control.*/
1172
1173 kCLOCK_AudioPll2BypassCtrl =
1174 CCM_ANALOG_TUPLE(AUDIO_PLL2_GEN_CTRL_OFFSET,
1175 CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_BYPASS_SHIFT), /*!< CCM Audio PLL2 bypass Control.*/
1176
1177 kCLOCK_VideoPll1BypassCtrl =
1178 CCM_ANALOG_TUPLE(VIDEO_PLL1_GEN_CTRL_OFFSET,
1179 CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_BYPASS_SHIFT), /*!< CCM Video Pll1 bypass Control.*/
1180
1181 kCLOCK_DramPllInternalPll1BypassCtrl = CCM_ANALOG_TUPLE(
1182 DRAM_PLL_GEN_CTRL_OFFSET, CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_BYPASS_SHIFT), /*!< CCM DRAM PLL bypass Control.*/
1183
1184 kCLOCK_ArmPllPwrBypassCtrl = CCM_ANALOG_TUPLE(
1185 ARM_PLL_GEN_CTRL_OFFSET, CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_BYPASS_SHIFT), /*!< CCM Arm PLL bypass Control.*/
1186
1187 kCLOCK_SysPll1InternalPll1BypassCtrl = CCM_ANALOG_TUPLE(
1188 SYS_PLL1_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_BYPASS_SHIFT), /*!< CCM System PLL1 bypass Control.*/
1189
1190 kCLOCK_SysPll2InternalPll1BypassCtrl = CCM_ANALOG_TUPLE(
1191 SYS_PLL2_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_BYPASS_SHIFT), /*!< CCM System PLL2 bypass Control.*/
1192
1193 kCLOCK_SysPll3InternalPll1BypassCtrl = CCM_ANALOG_TUPLE(
1194 SYS_PLL3_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_BYPASS_SHIFT), /*!< CCM System PLL3 bypass Control.*/
1195 } clock_pll_bypass_ctrl_t;
1196
1197 /*!
1198 * @brief PLL clock names for clock enable/disable settings.
1199 *
1200 * These constants define the PLL clock names for PLL clock enable/disable operations.\n
1201 * - 0:15: REG offset to CCM_ANALOG_BASE in bytes.
1202 * - 16:20: Clock enable bit shift.
1203 */
1204 typedef enum _ccm_analog_pll_clke
1205 {
1206 kCLOCK_AudioPll1Clke = CCM_ANALOG_TUPLE(AUDIO_PLL1_GEN_CTRL_OFFSET,
1207 CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_SHIFT), /*!< Audio pll1 clke */
1208 kCLOCK_AudioPll2Clke = CCM_ANALOG_TUPLE(AUDIO_PLL2_GEN_CTRL_OFFSET,
1209 CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_SHIFT), /*!< Audio pll2 clke */
1210 kCLOCK_VideoPll1Clke = CCM_ANALOG_TUPLE(VIDEO_PLL1_GEN_CTRL_OFFSET,
1211 CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_SHIFT), /*!< Video pll1 clke */
1212 kCLOCK_DramPllClke =
1213 CCM_ANALOG_TUPLE(DRAM_PLL_GEN_CTRL_OFFSET, CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_SHIFT), /*!< Dram pll clke */
1214
1215 kCLOCK_ArmPllClke =
1216 CCM_ANALOG_TUPLE(ARM_PLL_GEN_CTRL_OFFSET, CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_SHIFT), /*!< Arm pll clke */
1217
1218 kCLOCK_SystemPll1Clke = CCM_ANALOG_TUPLE(SYS_PLL1_GEN_CTRL_OFFSET,
1219 CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_SHIFT), /*!< System pll1 clke */
1220 kCLOCK_SystemPll1Div2Clke = CCM_ANALOG_TUPLE(
1221 SYS_PLL1_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_SHIFT), /*!< System pll1 Div2 clke */
1222 kCLOCK_SystemPll1Div3Clke = CCM_ANALOG_TUPLE(
1223 SYS_PLL1_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_SHIFT), /*!< System pll1 Div3 clke */
1224 kCLOCK_SystemPll1Div4Clke = CCM_ANALOG_TUPLE(
1225 SYS_PLL1_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_SHIFT), /*!< System pll1 Div4 clke */
1226 kCLOCK_SystemPll1Div5Clke = CCM_ANALOG_TUPLE(
1227 SYS_PLL1_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_SHIFT), /*!< System pll1 Div5 clke */
1228 kCLOCK_SystemPll1Div6Clke = CCM_ANALOG_TUPLE(
1229 SYS_PLL1_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_SHIFT), /*!< System pll1 Div6 clke */
1230 kCLOCK_SystemPll1Div8Clke = CCM_ANALOG_TUPLE(
1231 SYS_PLL1_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_SHIFT), /*!< System pll1 Div8 clke */
1232 kCLOCK_SystemPll1Div10Clke = CCM_ANALOG_TUPLE(
1233 SYS_PLL1_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_SHIFT), /*!< System pll1 Div10 clke */
1234 kCLOCK_SystemPll1Div20Clke = CCM_ANALOG_TUPLE(
1235 SYS_PLL1_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_SHIFT), /*!< System pll1 Div20 clke */
1236
1237 kCLOCK_SystemPll2Clke = CCM_ANALOG_TUPLE(SYS_PLL2_GEN_CTRL_OFFSET,
1238 CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_SHIFT), /*!< System pll2 clke */
1239 kCLOCK_SystemPll2Div2Clke = CCM_ANALOG_TUPLE(
1240 SYS_PLL2_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_SHIFT), /*!< System pll2 Div2 clke */
1241 kCLOCK_SystemPll2Div3Clke = CCM_ANALOG_TUPLE(
1242 SYS_PLL2_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_SHIFT), /*!< System pll2 Div3 clke */
1243 kCLOCK_SystemPll2Div4Clke = CCM_ANALOG_TUPLE(
1244 SYS_PLL2_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_SHIFT), /*!< System pll2 Div4 clke */
1245 kCLOCK_SystemPll2Div5Clke = CCM_ANALOG_TUPLE(
1246 SYS_PLL2_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_SHIFT), /*!< System pll2 Div5 clke */
1247 kCLOCK_SystemPll2Div6Clke = CCM_ANALOG_TUPLE(
1248 SYS_PLL2_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_SHIFT), /*!< System pll2 Div6 clke */
1249 kCLOCK_SystemPll2Div8Clke = CCM_ANALOG_TUPLE(
1250 SYS_PLL2_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_SHIFT), /*!< System pll2 Div8 clke */
1251 kCLOCK_SystemPll2Div10Clke = CCM_ANALOG_TUPLE(
1252 SYS_PLL2_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_SHIFT), /*!< System pll2 Div10 clke */
1253 kCLOCK_SystemPll2Div20Clke = CCM_ANALOG_TUPLE(
1254 SYS_PLL2_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_SHIFT), /*!< System pll2 Div20 clke */
1255
1256 kCLOCK_SystemPll3Clke = CCM_ANALOG_TUPLE(SYS_PLL3_GEN_CTRL_OFFSET,
1257 CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_SHIFT), /*!< System pll3 clke */
1258 } clock_pll_clke_t;
1259
1260 /*!
1261 * @brief ANALOG Power down override control.
1262 */
1263 typedef enum _clock_pll_ctrl
1264 {
1265 /* Fractional PLL frequency */
1266 kCLOCK_AudioPll1Ctrl = CCM_ANALOG_TUPLE(AUDIO_PLL1_GEN_CTRL_OFFSET, CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_SHIFT),
1267 kCLOCK_AudioPll2Ctrl = CCM_ANALOG_TUPLE(AUDIO_PLL2_GEN_CTRL_OFFSET, CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_SHIFT),
1268 kCLOCK_VideoPll1Ctrl = CCM_ANALOG_TUPLE(VIDEO_PLL1_GEN_CTRL_OFFSET, CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_SHIFT),
1269 kCLOCK_DramPllCtrl = CCM_ANALOG_TUPLE(DRAM_PLL_GEN_CTRL_OFFSET, CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_SHIFT),
1270 /* Integer PLL frequency */
1271 kCLOCK_VpuPllCtrl = CCM_ANALOG_TUPLE(VPU_PLL_GEN_CTRL_OFFSET, CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_RST_SHIFT),
1272 kCLOCK_ArmPllCtrl = CCM_ANALOG_TUPLE(ARM_PLL_GEN_CTRL_OFFSET, CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_SHIFT),
1273 kCLOCK_SystemPll1Ctrl = CCM_ANALOG_TUPLE(SYS_PLL1_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_SHIFT),
1274 kCLOCK_SystemPll2Ctrl = CCM_ANALOG_TUPLE(SYS_PLL2_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_SHIFT),
1275 kCLOCK_SystemPll3Ctrl = CCM_ANALOG_TUPLE(SYS_PLL3_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_SHIFT),
1276 } clock_pll_ctrl_t;
1277
1278 /*! @brief PLL reference clock select. */
1279 enum
1280 {
1281 kANALOG_PllRefOsc24M = 0U, /*!< reference OSC 24M */
1282 kANALOG_PllPadClk = 1U, /*!< reference PAD CLK */
1283 };
1284
1285 /*!
1286 * @brief Fractional-N PLL configuration.
1287 * Note: all the dividers in this configuration structure are the actually divider, software will map it to register
1288 * value
1289 */
1290 typedef struct _ccm_analog_frac_pll_config
1291 {
1292 uint8_t refSel; /*!< pll reference clock sel */
1293
1294 uint32_t mainDiv; /*!< Value of the 10-bit programmable main-divider, range must be 64~1023 */
1295
1296 uint32_t dsm; /*!< Value of 16-bit DSM */
1297
1298 uint8_t preDiv; /*!< Value of the 6-bit programmable pre-divider, range must be 1~63 */
1299
1300 uint8_t postDiv; /*!< Value of the 3-bit programmable Scaler, range must be 0~6 */
1301 } ccm_analog_frac_pll_config_t;
1302
1303 /*!
1304 * @brief Integer PLL configuration.
1305 * Note: all the dividers in this configuration structure are the actually divider, software will map it to register
1306 * value
1307 */
1308 typedef struct _ccm_analog_integer_pll_config
1309 {
1310 uint8_t refSel; /*!< pll reference clock sel */
1311
1312 uint32_t mainDiv; /*!< Value of the 10-bit programmable main-divider, range must be 64~1023 */
1313
1314 uint8_t preDiv; /*!< Value of the 6-bit programmable pre-divider, range must be 1~63 */
1315
1316 uint8_t postDiv; /*!< Value of the 3-bit programmable Scaler, range must be 0~6 */
1317
1318 } ccm_analog_integer_pll_config_t;
1319
1320 /*******************************************************************************
1321 * API
1322 ******************************************************************************/
1323
1324 #if defined(__cplusplus)
1325 extern "C" {
1326 #endif
1327
1328 /*!
1329 * @name CCM Root Clock Setting
1330 * @{
1331 */
1332
1333 /*!
1334 * @brief Set clock root mux.
1335 * User maybe need to set more than one mux ROOT according to the clock tree
1336 * description in the reference manual.
1337 *
1338 * @param rootClk Root clock control (see @ref clock_root_control_t enumeration).
1339 * @param mux Root mux value (see _ccm_rootmux_xxx enumeration).
1340 */
CLOCK_SetRootMux(clock_root_control_t rootClk,uint32_t mux)1341 static inline void CLOCK_SetRootMux(clock_root_control_t rootClk, uint32_t mux)
1342 {
1343 CCM_REG(rootClk) = (CCM_REG(rootClk) & (~CCM_TARGET_ROOT_MUX_MASK)) | CCM_TARGET_ROOT_MUX(mux);
1344 }
1345
1346 /*!
1347 * @brief Get clock root mux.
1348 * In order to get the clock source of root, user maybe need to get more than one
1349 * ROOT's mux value to obtain the final clock source of root.
1350 *
1351 * @param rootClk Root clock control (see @ref clock_root_control_t enumeration).
1352 * @return Root mux value (see _ccm_rootmux_xxx enumeration).
1353 */
CLOCK_GetRootMux(clock_root_control_t rootClk)1354 static inline uint32_t CLOCK_GetRootMux(clock_root_control_t rootClk)
1355 {
1356 return (CCM_REG(rootClk) & CCM_TARGET_ROOT_MUX_MASK) >> CCM_TARGET_ROOT_MUX_SHIFT;
1357 }
1358
1359 /*!
1360 * @brief Enable clock root
1361 *
1362 * @param rootClk Root clock control (see @ref clock_root_control_t enumeration)
1363 */
CLOCK_EnableRoot(clock_root_control_t rootClk)1364 static inline void CLOCK_EnableRoot(clock_root_control_t rootClk)
1365 {
1366 CCM_REG_SET(rootClk) = CCM_TARGET_ROOT_SET_ENABLE_MASK;
1367 }
1368
1369 /*!
1370 * @brief Disable clock root
1371 *
1372 * @param rootClk Root control (see @ref clock_root_control_t enumeration)
1373 */
CLOCK_DisableRoot(clock_root_control_t rootClk)1374 static inline void CLOCK_DisableRoot(clock_root_control_t rootClk)
1375 {
1376 CCM_REG_CLR(rootClk) = CCM_TARGET_ROOT_CLR_ENABLE_MASK;
1377 }
1378
1379 /*!
1380 * @brief Check whether clock root is enabled
1381 *
1382 * @param rootClk Root control (see @ref clock_root_control_t enumeration)
1383 * @return CCM root enabled or not.
1384 * - true: Clock root is enabled.
1385 * - false: Clock root is disabled.
1386 */
CLOCK_IsRootEnabled(clock_root_control_t rootClk)1387 static inline bool CLOCK_IsRootEnabled(clock_root_control_t rootClk)
1388 {
1389 return (bool)(CCM_REG(rootClk) & CCM_TARGET_ROOT_ENABLE_MASK);
1390 }
1391
1392 /*!
1393 * @brief Update clock root in one step, for dynamical clock switching
1394 * Note: The PRE and POST dividers in this function are the actually divider, software will map it to register value
1395 *
1396 * @param ccmRootClk Root control (see @ref clock_root_control_t enumeration)
1397 * @param mux mux value (see _ccm_rootmux_xxx enumeration)
1398 * @param pre Pre divider value (0-7, divider=n+1)
1399 * @param post Post divider value (0-63, divider=n+1)
1400 */
1401 void CLOCK_UpdateRoot(clock_root_control_t ccmRootClk, uint32_t mux, uint32_t pre, uint32_t post);
1402
1403 /*!
1404 * @brief Set root clock divider
1405 * Note: The PRE and POST dividers in this function are the actually divider, software will map it to register value
1406 *
1407 * @param ccmRootClk Root control (see @ref clock_root_control_t enumeration)
1408 * @param pre Pre divider value (1-8)
1409 * @param post Post divider value (1-64)
1410 */
1411 void CLOCK_SetRootDivider(clock_root_control_t ccmRootClk, uint32_t pre, uint32_t post);
1412
1413 /*!
1414 * @brief Get clock root PRE_PODF.
1415 * In order to get the clock source of root, user maybe need to get more than one
1416 * ROOT's mux value to obtain the final clock source of root.
1417 *
1418 * @param rootClk Root clock name (see @ref clock_root_control_t enumeration).
1419 * @return Root Pre divider value.
1420 */
CLOCK_GetRootPreDivider(clock_root_control_t rootClk)1421 static inline uint32_t CLOCK_GetRootPreDivider(clock_root_control_t rootClk)
1422 {
1423 return ((CCM_REG(rootClk) & CCM_TARGET_ROOT_PRE_PODF_MASK) >> CCM_TARGET_ROOT_PRE_PODF_SHIFT) + 1U;
1424 }
1425
1426 /*!
1427 * @brief Get clock root POST_PODF.
1428 * In order to get the clock source of root, user maybe need to get more than one
1429 * ROOT's mux value to obtain the final clock source of root.
1430 *
1431 * @param rootClk Root clock name (see @ref clock_root_control_t enumeration).
1432 * @return Root Post divider value.
1433 */
CLOCK_GetRootPostDivider(clock_root_control_t rootClk)1434 static inline uint32_t CLOCK_GetRootPostDivider(clock_root_control_t rootClk)
1435 {
1436 return ((CCM_REG(rootClk) & CCM_TARGET_ROOT_POST_PODF_MASK) >> CCM_TARGET_ROOT_POST_PODF_SHIFT) + 1U;
1437 }
1438
1439 /*!
1440 * @name CCM Gate Control
1441 * @{
1442 */
1443
1444 /*!
1445 * @brief Set PLL or CCGR gate control
1446 *
1447 * @param ccmGate Gate control (see @ref clock_pll_gate_t and @ref clock_ip_name_t enumeration)
1448 * @param control Gate control value (see @ref clock_gate_value_t)
1449 */
CLOCK_ControlGate(uintptr_t ccmGate,clock_gate_value_t control)1450 static inline void CLOCK_ControlGate(uintptr_t ccmGate, clock_gate_value_t control)
1451 {
1452 CCM_REG(ccmGate) = (uint32_t)control;
1453 }
1454
1455 /*!
1456 * @brief Enable CCGR clock gate and root clock gate for each module
1457 * User should set specific gate for each module according to the description
1458 * of the table of system clocks, gating and override in CCM chapter of
1459 * reference manual. Take care of that one module may need to set more than
1460 * one clock gate.
1461 *
1462 * @param ccmGate Gate control for each module (see @ref clock_ip_name_t enumeration).
1463 */
1464 void CLOCK_EnableClock(clock_ip_name_t ccmGate);
1465
1466 /*!
1467 * @brief Disable CCGR clock gate for the each module
1468 * User should set specific gate for each module according to the description
1469 * of the table of system clocks, gating and override in CCM chapter of
1470 * reference manual. Take care of that one module may need to set more than
1471 * one clock gate.
1472 *
1473 * @param ccmGate Gate control for each module (see @ref clock_ip_name_t enumeration).
1474 */
1475 void CLOCK_DisableClock(clock_ip_name_t ccmGate);
1476
1477 /*!
1478 * @name CCM Analog PLL Operatoin Functions
1479 * @{
1480 */
1481
1482 /*!
1483 * @brief Power up PLL
1484 *
1485 * @param base CCM_ANALOG base pointer.
1486 * @param pllControl PLL control name (see @ref clock_pll_ctrl_t enumeration)
1487 */
CLOCK_PowerUpPll(CCM_ANALOG_Type * base,clock_pll_ctrl_t pllControl)1488 static inline void CLOCK_PowerUpPll(CCM_ANALOG_Type *base, clock_pll_ctrl_t pllControl)
1489 {
1490 CCM_ANALOG_TUPLE_REG(base, pllControl) |= (1UL << CCM_ANALOG_TUPLE_SHIFT(pllControl));
1491 }
1492
1493 /*!
1494 * @brief Power down PLL
1495 *
1496 * @param base CCM_ANALOG base pointer.
1497 * @param pllControl PLL control name (see @ref clock_pll_ctrl_t enumeration)
1498 */
CLOCK_PowerDownPll(CCM_ANALOG_Type * base,clock_pll_ctrl_t pllControl)1499 static inline void CLOCK_PowerDownPll(CCM_ANALOG_Type *base, clock_pll_ctrl_t pllControl)
1500 {
1501 CCM_ANALOG_TUPLE_REG(base, pllControl) &= ~(1UL << CCM_ANALOG_TUPLE_SHIFT(pllControl));
1502 }
1503
1504 /*!
1505 * @brief PLL bypass setting
1506 *
1507 * @param base CCM_ANALOG base pointer.
1508 * @param pllControl PLL control name (see @ref clock_pll_bypass_ctrl_t enumeration)
1509 * @param bypass Bypass the PLL.
1510 * - true: Bypass the PLL.
1511 * - false: Do not bypass the PLL.
1512 */
CLOCK_SetPllBypass(CCM_ANALOG_Type * base,clock_pll_bypass_ctrl_t pllControl,bool bypass)1513 static inline void CLOCK_SetPllBypass(CCM_ANALOG_Type *base, clock_pll_bypass_ctrl_t pllControl, bool bypass)
1514 {
1515 if (bypass)
1516 {
1517 CCM_ANALOG_TUPLE_REG(base, pllControl) |= 1UL << CCM_ANALOG_TUPLE_SHIFT(pllControl);
1518 }
1519 else
1520 {
1521 CCM_ANALOG_TUPLE_REG(base, pllControl) &= ~(1UL << CCM_ANALOG_TUPLE_SHIFT(pllControl));
1522 }
1523 }
1524
1525 /*!
1526 * @brief Check if PLL is bypassed
1527 *
1528 * @param base CCM_ANALOG base pointer.
1529 * @param pllControl PLL control name (see @ref clock_pll_bypass_ctrl_t enumeration)
1530 * @return PLL bypass status.
1531 * - true: The PLL is bypassed.
1532 * - false: The PLL is not bypassed.
1533 */
CLOCK_IsPllBypassed(CCM_ANALOG_Type * base,clock_pll_bypass_ctrl_t pllControl)1534 static inline bool CLOCK_IsPllBypassed(CCM_ANALOG_Type *base, clock_pll_bypass_ctrl_t pllControl)
1535 {
1536 return (bool)(CCM_ANALOG_TUPLE_REG(base, pllControl) & (1UL << CCM_ANALOG_TUPLE_SHIFT(pllControl)));
1537 }
1538
1539 /*!
1540 * @brief Check if PLL clock is locked
1541 *
1542 * @param base CCM_ANALOG base pointer.
1543 * @param pllControl PLL control name (see @ref clock_pll_ctrl_t enumeration)
1544 * @return PLL lock status.
1545 * - true: The PLL clock is locked.
1546 * - false: The PLL clock is not locked.
1547 */
CLOCK_IsPllLocked(CCM_ANALOG_Type * base,clock_pll_ctrl_t pllControl)1548 static inline bool CLOCK_IsPllLocked(CCM_ANALOG_Type *base, clock_pll_ctrl_t pllControl)
1549 {
1550 return (bool)(CCM_ANALOG_TUPLE_REG(base, pllControl) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_MASK);
1551 }
1552
1553 /*!
1554 * @brief Enable PLL clock
1555 *
1556 * @param base CCM_ANALOG base pointer.
1557 * @param pllClock PLL clock name (see @ref clock_pll_clke_t enumeration)
1558 */
CLOCK_EnableAnalogClock(CCM_ANALOG_Type * base,clock_pll_clke_t pllClock)1559 static inline void CLOCK_EnableAnalogClock(CCM_ANALOG_Type *base, clock_pll_clke_t pllClock)
1560 {
1561 CCM_ANALOG_TUPLE_REG(base, pllClock) |= 1UL << CCM_ANALOG_TUPLE_SHIFT(pllClock);
1562 }
1563
1564 /*!
1565 * @brief Disable PLL clock
1566 *
1567 * @param base CCM_ANALOG base pointer.
1568 * @param pllClock PLL clock name (see @ref clock_pll_clke_t enumeration)
1569 */
CLOCK_DisableAnalogClock(CCM_ANALOG_Type * base,clock_pll_clke_t pllClock)1570 static inline void CLOCK_DisableAnalogClock(CCM_ANALOG_Type *base, clock_pll_clke_t pllClock)
1571 {
1572 CCM_ANALOG_TUPLE_REG(base, pllClock) &= ~(1UL << CCM_ANALOG_TUPLE_SHIFT(pllClock));
1573 }
1574
1575 /*!
1576 * @brief Override PLL clock output enable
1577 *
1578 * @param base CCM_ANALOG base pointer.
1579 * @param ovClock PLL clock name (see @ref clock_pll_clke_t enumeration)
1580 * @param override Override the PLL.
1581 * - true: Override the PLL clke, CCM will handle it.
1582 * - false: Do not override the PLL clke.
1583 */
CLOCK_OverridePllClke(CCM_ANALOG_Type * base,clock_pll_clke_t ovClock,bool override)1584 static inline void CLOCK_OverridePllClke(CCM_ANALOG_Type *base, clock_pll_clke_t ovClock, bool override)
1585 {
1586 if (override)
1587 {
1588 CCM_ANALOG_TUPLE_REG(base, ovClock) |= 1UL << (CCM_ANALOG_TUPLE_SHIFT(ovClock) - 1UL);
1589 }
1590 else
1591 {
1592 CCM_ANALOG_TUPLE_REG(base, ovClock) &= ~(1UL << (CCM_ANALOG_TUPLE_SHIFT(ovClock) - 1UL));
1593 }
1594 }
1595
1596 /*!
1597 * @brief Override PLL power down
1598 *
1599 * @param base CCM_ANALOG base pointer.
1600 * @param pdClock PLL clock name (see @ref clock_pll_ctrl_t enumeration)
1601 * @param override Override the PLL.
1602 * - true: Override the PLL clke, CCM will handle it.
1603 * - false: Do not override the PLL clke.
1604 */
CLOCK_OverridePllPd(CCM_ANALOG_Type * base,clock_pll_ctrl_t pdClock,bool override)1605 static inline void CLOCK_OverridePllPd(CCM_ANALOG_Type *base, clock_pll_ctrl_t pdClock, bool override)
1606 {
1607 if (override)
1608 {
1609 CCM_ANALOG_TUPLE_REG(base, pdClock) |= 1UL << (CCM_ANALOG_TUPLE_SHIFT(pdClock) - 1UL);
1610 }
1611 else
1612 {
1613 CCM_ANALOG_TUPLE_REG(base, pdClock) &= ~(1UL << (CCM_ANALOG_TUPLE_SHIFT(pdClock) - 1UL));
1614 }
1615 }
1616
1617 /*!
1618 * @brief Initializes the ANALOG ARM PLL.
1619 *
1620 * @param config Pointer to the configuration structure(see @ref ccm_analog_integer_pll_config_t enumeration).
1621 *
1622 * @note This function can't detect whether the Arm PLL has been enabled and
1623 * used by some IPs.
1624 */
1625 void CLOCK_InitArmPll(const ccm_analog_integer_pll_config_t *config);
1626
1627 /*!
1628 * @brief De-initialize the ARM PLL.
1629 */
1630 void CLOCK_DeinitArmPll(void);
1631
1632 /*!
1633 * @brief Initializes the ANALOG SYS PLL1.
1634 *
1635 * @param config Pointer to the configuration structure(see @ref ccm_analog_integer_pll_config_t enumeration).
1636 *
1637 * @note This function can't detect whether the SYS PLL has been enabled and
1638 * used by some IPs.
1639 */
1640 void CLOCK_InitSysPll1(const ccm_analog_integer_pll_config_t *config);
1641
1642 /*!
1643 * @brief De-initialize the System PLL1.
1644 */
1645 void CLOCK_DeinitSysPll1(void);
1646
1647 /*!
1648 * @brief Initializes the ANALOG SYS PLL2.
1649 *
1650 * @param config Pointer to the configuration structure(see @ref ccm_analog_integer_pll_config_t enumeration).
1651 *
1652 * @note This function can't detect whether the SYS PLL has been enabled and
1653 * used by some IPs.
1654 */
1655 void CLOCK_InitSysPll2(const ccm_analog_integer_pll_config_t *config);
1656
1657 /*!
1658 * @brief De-initialize the System PLL2.
1659 */
1660 void CLOCK_DeinitSysPll2(void);
1661
1662 /*!
1663 * @brief Initializes the ANALOG SYS PLL3.
1664 *
1665 * @param config Pointer to the configuration structure(see @ref ccm_analog_integer_pll_config_t enumeration).
1666 *
1667 * @note This function can't detect whether the SYS PLL has been enabled and
1668 * used by some IPs.
1669 */
1670 void CLOCK_InitSysPll3(const ccm_analog_integer_pll_config_t *config);
1671
1672 /*!
1673 * @brief De-initialize the System PLL3.
1674 */
1675 void CLOCK_DeinitSysPll3(void);
1676
1677 /*!
1678 * @brief Initializes the ANALOG AUDIO PLL1.
1679 *
1680 * @param config Pointer to the configuration structure(see @ref ccm_analog_frac_pll_config_t enumeration).
1681 *
1682 * @note This function can't detect whether the AUDIO PLL has been enabled and
1683 * used by some IPs.
1684 */
1685 void CLOCK_InitAudioPll1(const ccm_analog_frac_pll_config_t *config);
1686
1687 /*!
1688 * @brief De-initialize the Audio PLL1.
1689 */
1690 void CLOCK_DeinitAudioPll1(void);
1691
1692 /*!
1693 * @brief Initializes the ANALOG AUDIO PLL2.
1694 *
1695 * @param config Pointer to the configuration structure(see @ref ccm_analog_frac_pll_config_t enumeration).
1696 *
1697 * @note This function can't detect whether the AUDIO PLL has been enabled and
1698 * used by some IPs.
1699 */
1700 void CLOCK_InitAudioPll2(const ccm_analog_frac_pll_config_t *config);
1701
1702 /*!
1703 * @brief De-initialize the Audio PLL2.
1704 */
1705 void CLOCK_DeinitAudioPll2(void);
1706
1707 /*!
1708 * @brief Initializes the ANALOG VIDEO PLL1.
1709 *
1710 * @param config Pointer to the configuration structure(see @ref ccm_analog_frac_pll_config_t enumeration).
1711 *
1712 */
1713 void CLOCK_InitVideoPll1(const ccm_analog_frac_pll_config_t *config);
1714
1715 /*!
1716 * @brief De-initialize the Video PLL1.
1717 */
1718 void CLOCK_DeinitVideoPll1(void);
1719
1720 /*!
1721 * @brief Initializes the ANALOG Integer PLL.
1722 *
1723 * @param base CCM ANALOG base address
1724 * @param config Pointer to the configuration structure(see @ref ccm_analog_integer_pll_config_t enumeration).
1725 * @param type integer pll type
1726 *
1727 */
1728 void CLOCK_InitIntegerPll(CCM_ANALOG_Type *base, const ccm_analog_integer_pll_config_t *config, clock_pll_ctrl_t type);
1729
1730 /*!
1731 * @brief Get the ANALOG Integer PLL clock frequency.
1732 *
1733 * @param base CCM ANALOG base address.
1734 * @param type integer pll type
1735 * @param refClkFreq Reference clock frequency.
1736 * @param pll1Bypass pll1 bypass flag
1737 *
1738 * @return Clock frequency
1739 */
1740 uint32_t CLOCK_GetIntegerPllFreq(CCM_ANALOG_Type *base, clock_pll_ctrl_t type, uint32_t refClkFreq, bool pll1Bypass);
1741
1742 /*!
1743 * @brief Initializes the ANALOG Fractional PLL.
1744 *
1745 * @param base CCM ANALOG base address.
1746 * @param config Pointer to the configuration structure(see @ref ccm_analog_frac_pll_config_t enumeration).
1747 * @param type fractional pll type.
1748 *
1749 */
1750 void CLOCK_InitFracPll(CCM_ANALOG_Type *base, const ccm_analog_frac_pll_config_t *config, clock_pll_ctrl_t type);
1751
1752 /*!
1753 * @brief Gets the ANALOG Fractional PLL clock frequency.
1754 *
1755 * @param base CCM_ANALOG base pointer.
1756 * @param type fractional pll type.
1757 * @param refClkFreq Reference clock frequency.
1758 *
1759 * @return Clock frequency
1760 */
1761 uint32_t CLOCK_GetFracPllFreq(CCM_ANALOG_Type *base, clock_pll_ctrl_t type, uint32_t refClkFreq);
1762
1763 /*!
1764 * @brief Gets PLL clock frequency.
1765 *
1766 * @param pll fractional pll type.
1767
1768 * @return Clock frequency
1769 */
1770 uint32_t CLOCK_GetPllFreq(clock_pll_ctrl_t pll);
1771
1772 /*!
1773 * @brief Gets PLL reference clock frequency.
1774 *
1775 * @param ctrl fractional pll type.
1776
1777 * @return Clock frequency
1778 */
1779 uint32_t CLOCK_GetPllRefClkFreq(clock_pll_ctrl_t ctrl);
1780
1781 /*!
1782 * @name CCM Get frequency
1783 * @{
1784 */
1785
1786 /*!
1787 * @brief Gets the clock frequency for a specific clock name.
1788 *
1789 * This function checks the current clock configurations and then calculates
1790 * the clock frequency for a specific clock name defined in clock_name_t.
1791 *
1792 * @param clockName Clock names defined in clock_name_t
1793 * @return Clock frequency value in hertz
1794 */
1795 uint32_t CLOCK_GetFreq(clock_name_t clockName);
1796
1797 /*!
1798 * @brief Gets the frequency of selected clock root.
1799 *
1800 * @param clockRoot The clock root used to get the frequency, please refer to @ref clock_root_t.
1801 * @return The frequency of selected clock root.
1802 */
1803 uint32_t CLOCK_GetClockRootFreq(clock_root_t clockRoot);
1804
1805 /*!
1806 * @brief Get the CCM Cortex M7 core frequency.
1807 *
1808 * @return Clock frequency; If the clock is invalid, returns 0.
1809 */
1810 uint32_t CLOCK_GetCoreM7Freq(void);
1811
1812 /*!
1813 * @brief Get the CCM Axi bus frequency.
1814 *
1815 * @return Clock frequency; If the clock is invalid, returns 0.
1816 */
1817 uint32_t CLOCK_GetAxiFreq(void);
1818
1819 /*!
1820 * @brief Get the CCM Ahb bus frequency.
1821 *
1822 * @return Clock frequency; If the clock is invalid, returns 0.
1823 */
1824 uint32_t CLOCK_GetAhbFreq(void);
1825
1826 /*!
1827 * brief Get the CCM Enet AXI bus frequency.
1828 *
1829 * return Clock frequency; If the clock is invalid, returns 0.
1830 */
1831 uint32_t CLOCK_GetEnetAxiFreq(void);
1832
1833 /* @} */
1834
1835 #if defined(__cplusplus)
1836 }
1837 #endif
1838 /* @} */
1839 #endif
1840
