1/* ------------------------------------------------------------------------- */ 2/* @file: startup_MIMX8MD7_cm4.s */ 3/* @purpose: CMSIS Cortex-M4 Core Device Startup File */ 4/* MIMX8MD7_cm4 */ 5/* @version: 4.0 */ 6/* @date: 2018-1-26 */ 7/* @build: b220621 */ 8/* ------------------------------------------------------------------------- */ 9/* */ 10/* Copyright 1997-2016 Freescale Semiconductor, Inc. */ 11/* Copyright 2016-2022 NXP */ 12/* All rights reserved. */ 13/* */ 14/* SPDX-License-Identifier: BSD-3-Clause */ 15/*****************************************************************************/ 16/* Version: GCC for ARM Embedded Processors */ 17/*****************************************************************************/ 18 .syntax unified 19 .arch armv7-m 20 21 .section .isr_vector, "a" 22 .align 2 23 .globl __isr_vector 24__isr_vector: 25 .long __StackTop /* Top of Stack */ 26 .long Reset_Handler /* Reset Handler */ 27 .long NMI_Handler /* NMI Handler*/ 28 .long HardFault_Handler /* Hard Fault Handler*/ 29 .long MemManage_Handler /* MPU Fault Handler*/ 30 .long BusFault_Handler /* Bus Fault Handler*/ 31 .long UsageFault_Handler /* Usage Fault Handler*/ 32 .long 0 /* Reserved*/ 33 .long 0 /* Reserved*/ 34 .long 0 /* Reserved*/ 35 .long 0 /* Reserved*/ 36 .long SVC_Handler /* SVCall Handler*/ 37 .long DebugMon_Handler /* Debug Monitor Handler*/ 38 .long 0 /* Reserved*/ 39 .long PendSV_Handler /* PendSV Handler*/ 40 .long SysTick_Handler /* SysTick Handler*/ 41 42 /* External Interrupts*/ 43 .long GPR_IRQ_IRQHandler /* GPR Interrupt. Used to notify cores on exception condition while boot.*/ 44 .long DAP_IRQHandler /* DAP Interrupt*/ 45 .long SDMA1_IRQHandler /* AND of all 48 SDMA interrupts (events) from all the channels*/ 46 .long GPU_IRQHandler /* GPU Interrupt*/ 47 .long SNVS_IRQHandler /* ON-OFF button press shorter than 5 seconds (pulse event)*/ 48 .long LCDIF_IRQHandler /* LCDIF Sync Interrupt*/ 49 .long SPDIF1_IRQHandler /* SPDIF1 Interrupt*/ 50 .long H264_IRQHandler /* h264 Decoder Interrupt*/ 51 .long VPUDMA_IRQHandler /* VPU DMA Interrupt*/ 52 .long QOS_IRQHandler /* QOS interrupt*/ 53 .long WDOG3_IRQHandler /* Watchdog Timer reset*/ 54 .long HS_CP1_IRQHandler /* HS Interrupt Request*/ 55 .long APBHDMA_IRQHandler /* GPMI operation channel 0-3 description complete interrupt*/ 56 .long SPDIF2_IRQHandler /* SPDIF2 Interrupt*/ 57 .long BCH_IRQHandler /* BCH operation complete interrupt*/ 58 .long GPMI_IRQHandler /* GPMI operation TIMEOUT ERROR interrupt*/ 59 .long HDMI_IRQ0_IRQHandler /* HDMI Interrupt 0*/ 60 .long HDMI_IRQ1_IRQHandler /* HDMI Interrupt 1*/ 61 .long HDMI_IRQ2_IRQHandler /* HDMI Interrupt 2*/ 62 .long SNVS_Consolidated_IRQHandler /* SRTC Consolidated Interrupt. Non TZ.*/ 63 .long SNVS_Security_IRQHandler /* SRTC Security Interrupt. TZ.*/ 64 .long CSU_IRQHandler /* CSU Interrupt Request. Indicates to the processor that one or more alarm inputs were asserted.*/ 65 .long USDHC1_IRQHandler /* uSDHC1 Enhanced SDHC Interrupt Request*/ 66 .long USDHC2_IRQHandler /* uSDHC2 Enhanced SDHC Interrupt Request*/ 67 .long DDC_IRQHandler /* DC8000 Display Controller IRQ*/ 68 .long DTRC_IRQHandler /* DTRC interrupt*/ 69 .long UART1_IRQHandler /* UART-1 ORed interrupt*/ 70 .long UART2_IRQHandler /* UART-2 ORed interrupt*/ 71 .long UART3_IRQHandler /* UART-3 ORed interrupt*/ 72 .long UART4_IRQHandler /* UART-4 ORed interrupt*/ 73 .long VP9_IRQHandler /* VP9 Decoder interrupt*/ 74 .long ECSPI1_IRQHandler /* ECSPI1 interrupt request line to the core.*/ 75 .long ECSPI2_IRQHandler /* ECSPI2 interrupt request line to the core.*/ 76 .long ECSPI3_IRQHandler /* ECSPI3 interrupt request line to the core.*/ 77 .long MIPI_DSI_IRQHandler /* DSI Interrupt*/ 78 .long I2C1_IRQHandler /* I2C-1 Interrupt*/ 79 .long I2C2_IRQHandler /* I2C-2 Interrupt*/ 80 .long I2C3_IRQHandler /* I2C-3 Interrupt*/ 81 .long I2C4_IRQHandler /* I2C-4 Interrupt*/ 82 .long RDC_IRQHandler /* RDC interrupt*/ 83 .long USB1_IRQHandler /* USB1 Interrupt*/ 84 .long USB2_IRQHandler /* USB1 Interrupt*/ 85 .long CSI1_IRQHandler /* CSI1 interrupt*/ 86 .long CSI2_IRQHandler /* CSI2 interrupt*/ 87 .long MIPI_CSI1_IRQHandler /* MIPI-CSI-1 Interrupt*/ 88 .long MIPI_CSI2_IRQHandler /* MIPI-CSI-2 Interrupt*/ 89 .long GPT6_IRQHandler /* OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines*/ 90 .long SCTR_IRQ0_IRQHandler /* ISO7816IP Interrupt 0*/ 91 .long SCTR_IRQ1_IRQHandler /* ISO7816IP Interrupt 1*/ 92 .long TEMPMON_IRQHandler /* TempSensor (Temperature alarm).*/ 93 .long I2S3_IRQHandler /* SAI3 Receive / Transmit Interrupt*/ 94 .long GPT5_IRQHandler /* OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines*/ 95 .long GPT4_IRQHandler /* OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines*/ 96 .long GPT3_IRQHandler /* OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines*/ 97 .long GPT2_IRQHandler /* OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines*/ 98 .long GPT1_IRQHandler /* OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines*/ 99 .long GPIO1_INT7_IRQHandler /* Active HIGH Interrupt from INT7 from GPIO*/ 100 .long GPIO1_INT6_IRQHandler /* Active HIGH Interrupt from INT6 from GPIO*/ 101 .long GPIO1_INT5_IRQHandler /* Active HIGH Interrupt from INT5 from GPIO*/ 102 .long GPIO1_INT4_IRQHandler /* Active HIGH Interrupt from INT4 from GPIO*/ 103 .long GPIO1_INT3_IRQHandler /* Active HIGH Interrupt from INT3 from GPIO*/ 104 .long GPIO1_INT2_IRQHandler /* Active HIGH Interrupt from INT2 from GPIO*/ 105 .long GPIO1_INT1_IRQHandler /* Active HIGH Interrupt from INT1 from GPIO*/ 106 .long GPIO1_INT0_IRQHandler /* Active HIGH Interrupt from INT0 from GPIO*/ 107 .long GPIO1_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO1 signal 0 throughout 15*/ 108 .long GPIO1_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO1 signal 16 throughout 31*/ 109 .long GPIO2_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO2 signal 0 throughout 15*/ 110 .long GPIO2_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO2 signal 16 throughout 31*/ 111 .long GPIO3_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO3 signal 0 throughout 15*/ 112 .long GPIO3_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO3 signal 16 throughout 31*/ 113 .long GPIO4_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO4 signal 0 throughout 15*/ 114 .long GPIO4_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO4 signal 16 throughout 31*/ 115 .long GPIO5_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO5 signal 0 throughout 15*/ 116 .long GPIO5_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO5 signal 16 throughout 31*/ 117 .long PCIE_CTRL2_IRQ0_IRQHandler /* Coming from GLUE logic, of set / reset FF, driven by PCIE signals.*/ 118 .long PCIE_CTRL2_IRQ1_IRQHandler /* Coming from GLUE logic, of set / reset FF, driven by PCIE signals.*/ 119 .long PCIE_CTRL2_IRQ2_IRQHandler /* Coming from GLUE logic, of set / reset FF, driven by PCIE signals.*/ 120 .long PCIE_CTRL2_IRQ3_IRQHandler /* Coming from GLUE logic, of set / reset FF, driven by PCIE signals.*/ 121 .long WDOG1_IRQHandler /* Watchdog Timer reset*/ 122 .long WDOG2_IRQHandler /* Watchdog Timer reset*/ 123 .long PCIE_CTRL2_IRQHandler /* Channels [63:32] interrupts requests*/ 124 .long PWM1_IRQHandler /* Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line.*/ 125 .long PWM2_IRQHandler /* Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line.*/ 126 .long PWM3_IRQHandler /* Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line.*/ 127 .long PWM4_IRQHandler /* Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line.*/ 128 .long CCM_IRQ1_IRQHandler /* CCM, Interrupt Request 1*/ 129 .long CCM_IRQ2_IRQHandler /* CCM, Interrupt Request 2*/ 130 .long GPC_IRQHandler /* GPC Interrupt Request 1*/ 131 .long MU_A53_IRQHandler /* Interrupt to A53*/ 132 .long SRC_IRQHandler /* SRC interrupt request*/ 133 .long I2S56_IRQHandler /* SAI5/6 Receive / Transmit Interrupt*/ 134 .long RTIC_IRQHandler /* RTIC Interrupt*/ 135 .long CPU_PerformanceUnit_IRQHandler /* Performance Unit Interrupts from Cheetah (interrnally: PMUIRQ[n]*/ 136 .long CPU_CTI_Trigger_IRQHandler /* CTI trigger outputs (internal: nCTIIRQ[n]*/ 137 .long SRC_Combined_IRQHandler /* Combined CPU wdog interrupts (4x) out of SRC.*/ 138 .long I2S1_IRQHandler /* SAI1 Receive / Transmit Interrupt*/ 139 .long I2S2_IRQHandler /* SAI2 Receive / Transmit Interrupt*/ 140 .long MU_M4_IRQHandler /* Interrupt to M4*/ 141 .long DDR_PerformanceMonitor_IRQHandler /* ddr Interrupt for performance monitor*/ 142 .long DDR_IRQHandler /* ddr Interrupt*/ 143 .long I2S4_IRQHandler /* SAI4 Receive / Transmit Interrupt*/ 144 .long CPU_Error_AXI_IRQHandler /* CPU Error indicator for AXI transaction with a write response error condition*/ 145 .long CPU_Error_L2RAM_IRQHandler /* CPU Error indicator for L2 RAM double-bit ECC error*/ 146 .long SDMA2_IRQHandler /* AND of all 48 SDMA interrupts (events) from all the channels*/ 147 .long Reserved120_IRQHandler /* Reserved*/ 148 .long CAAM_IRQ0_IRQHandler /* CAAM interrupt queue for JQ*/ 149 .long CAAM_IRQ1_IRQHandler /* CAAM interrupt queue for JQ*/ 150 .long QSPI_IRQHandler /* QSPI Interrupt*/ 151 .long TZASC_IRQHandler /* TZASC (PL380) interrupt*/ 152 .long Reserved125_IRQHandler /* Reserved*/ 153 .long Reserved126_IRQHandler /* Reserved*/ 154 .long Reserved127_IRQHandler /* Reserved*/ 155 .long PERFMON1_IRQHandler /* General Interrupt*/ 156 .long PERFMON2_IRQHandler /* General Interrupt*/ 157 .long CAAM_IRQ2_IRQHandler /* CAAM interrupt queue for JQ*/ 158 .long CAAM_ERROR_IRQHandler /* Recoverable error interrupt*/ 159 .long HS_CP0_IRQHandler /* HS Interrupt Request*/ 160 .long HEVC_IRQHandler /* HEVC interrupt*/ 161 .long ENET1_MAC0_Rx_Tx_Done1_IRQHandler /* MAC 0 Receive / Trasmit Frame / Buffer Done*/ 162 .long ENET1_MAC0_Rx_Tx_Done2_IRQHandler /* MAC 0 Receive / Trasmit Frame / Buffer Done*/ 163 .long ENET1_IRQHandler /* MAC 0 IRQ*/ 164 .long ENET1_1588_Timer_IRQHandler /* MAC 0 1588 Timer Interrupt - synchronous*/ 165 .long PCIE_CTRL1_IRQ0_IRQHandler /* Coming from GLUE logic, of set / reset FF, driven by PCIE signals.*/ 166 .long PCIE_CTRL1_IRQ1_IRQHandler /* Coming from GLUE logic, of set / reset FF, driven by PCIE signals.*/ 167 .long PCIE_CTRL1_IRQ2_IRQHandler /* Coming from GLUE logic, of set / reset FF, driven by PCIE signals.*/ 168 .long PCIE_CTRL1_IRQ3_IRQHandler /* Coming from GLUE logic, of set / reset FF, driven by PCIE signals.*/ 169 .long Reserved142_IRQHandler /* Reserved*/ 170 .long PCIE_CTRL1_IRQHandler /* Channels [63:32] interrupts requests*/ 171 172 .size __isr_vector, . - __isr_vector 173 174 .text 175 .thumb 176 177/* Reset Handler */ 178 179 .thumb_func 180 .align 2 181 .globl Reset_Handler 182 .weak Reset_Handler 183 .type Reset_Handler, %function 184Reset_Handler: 185 cpsid i /* Mask interrupts */ 186 .equ VTOR, 0xE000ED08 187 ldr r0, =VTOR 188 ldr r1, =__isr_vector 189 str r1, [r0] 190 ldr r2, [r1] 191 msr msp, r2 192#ifndef __NO_SYSTEM_INIT 193 ldr r0,=SystemInit 194 blx r0 195#endif 196/* Loop to copy data from read only memory to RAM. The ranges 197 * of copy from/to are specified by following symbols evaluated in 198 * linker script. 199 * __etext: End of code section, i.e., begin of data sections to copy from. 200 * __data_start__/__data_end__: RAM address range that data should be 201 * __noncachedata_start__/__noncachedata_end__ : none cachable region 202 * copied to. Both must be aligned to 4 bytes boundary. */ 203 204 ldr r1, =__etext 205 ldr r2, =__data_start__ 206 ldr r3, =__data_end__ 207 208#ifdef __PERFORMANCE_IMPLEMENTATION 209/* Here are two copies of loop implementations. First one favors performance 210 * and the second one favors code size. Default uses the second one. 211 * Define macro "__PERFORMANCE_IMPLEMENTATION" in project to use the first one */ 212 subs r3, r2 213 ble .LC1 214.LC0: 215 subs r3, #4 216 ldr r0, [r1, r3] 217 str r0, [r2, r3] 218 bgt .LC0 219.LC1: 220#else /* code size implemenation */ 221.LC0: 222 cmp r2, r3 223 ittt lt 224 ldrlt r0, [r1], #4 225 strlt r0, [r2], #4 226 blt .LC0 227#endif 228#ifdef __STARTUP_INITIALIZE_NONCACHEDATA 229 ldr r2, =__noncachedata_start__ 230 ldr r3, =__noncachedata_init_end__ 231#ifdef __PERFORMANCE_IMPLEMENTATION 232/* Here are two copies of loop implementations. First one favors performance 233 * and the second one favors code size. Default uses the second one. 234 * Define macro "__PERFORMANCE_IMPLEMENTATION" in project to use the first one */ 235 subs r3, r2 236 ble .LC3 237.LC2: 238 subs r3, #4 239 ldr r0, [r1, r3] 240 str r0, [r2, r3] 241 bgt .LC2 242.LC3: 243#else /* code size implemenation */ 244.LC2: 245 cmp r2, r3 246 ittt lt 247 ldrlt r0, [r1], #4 248 strlt r0, [r2], #4 249 blt .LC2 250#endif 251/* zero inited ncache section initialization */ 252 ldr r3, =__noncachedata_end__ 253 movs r0,0 254.LC4: 255 cmp r2,r3 256 itt lt 257 strlt r0,[r2],#4 258 blt .LC4 259#endif /* __STARTUP_INITIALIZE_NONCACHEDATA */ 260 261#ifdef __STARTUP_CLEAR_BSS 262/* This part of work usually is done in C library startup code. Otherwise, 263 * define this macro to enable it in this startup. 264 * 265 * Loop to zero out BSS section, which uses following symbols 266 * in linker script: 267 * __bss_start__: start of BSS section. Must align to 4 268 * __bss_end__: end of BSS section. Must align to 4 269 */ 270 ldr r1, =__bss_start__ 271 ldr r2, =__bss_end__ 272 273 movs r0, 0 274.LC5: 275 cmp r1, r2 276 itt lt 277 strlt r0, [r1], #4 278 blt .LC5 279#endif /* __STARTUP_CLEAR_BSS */ 280 281 cpsie i /* Unmask interrupts */ 282#ifndef __START 283#define __START _start 284#endif 285#ifndef __ATOLLIC__ 286 ldr r0,=__START 287 blx r0 288#else 289 ldr r0,=__libc_init_array 290 blx r0 291 ldr r0,=main 292 bx r0 293#endif 294 .pool 295 .size Reset_Handler, . - Reset_Handler 296 297 .align 1 298 .thumb_func 299 .weak DefaultISR 300 .type DefaultISR, %function 301DefaultISR: 302 b DefaultISR 303 .size DefaultISR, . - DefaultISR 304 305 .align 1 306 .thumb_func 307 .weak NMI_Handler 308 .type NMI_Handler, %function 309NMI_Handler: 310 ldr r0,=NMI_Handler 311 bx r0 312 .size NMI_Handler, . - NMI_Handler 313 314 .align 1 315 .thumb_func 316 .weak HardFault_Handler 317 .type HardFault_Handler, %function 318HardFault_Handler: 319 ldr r0,=HardFault_Handler 320 bx r0 321 .size HardFault_Handler, . - HardFault_Handler 322 323 .align 1 324 .thumb_func 325 .weak SVC_Handler 326 .type SVC_Handler, %function 327SVC_Handler: 328 ldr r0,=SVC_Handler 329 bx r0 330 .size SVC_Handler, . - SVC_Handler 331 332 .align 1 333 .thumb_func 334 .weak PendSV_Handler 335 .type PendSV_Handler, %function 336PendSV_Handler: 337 ldr r0,=PendSV_Handler 338 bx r0 339 .size PendSV_Handler, . - PendSV_Handler 340 341 .align 1 342 .thumb_func 343 .weak SysTick_Handler 344 .type SysTick_Handler, %function 345SysTick_Handler: 346 ldr r0,=SysTick_Handler 347 bx r0 348 .size SysTick_Handler, . - SysTick_Handler 349 350 .align 1 351 .thumb_func 352 .weak SDMA1_IRQHandler 353 .type SDMA1_IRQHandler, %function 354SDMA1_IRQHandler: 355 ldr r0,=SDMA1_DriverIRQHandler 356 bx r0 357 .size SDMA1_IRQHandler, . - SDMA1_IRQHandler 358 359 .align 1 360 .thumb_func 361 .weak SPDIF1_IRQHandler 362 .type SPDIF1_IRQHandler, %function 363SPDIF1_IRQHandler: 364 ldr r0,=SPDIF1_DriverIRQHandler 365 bx r0 366 .size SPDIF1_IRQHandler, . - SPDIF1_IRQHandler 367 368 .align 1 369 .thumb_func 370 .weak VPUDMA_IRQHandler 371 .type VPUDMA_IRQHandler, %function 372VPUDMA_IRQHandler: 373 ldr r0,=VPUDMA_DriverIRQHandler 374 bx r0 375 .size VPUDMA_IRQHandler, . - VPUDMA_IRQHandler 376 377 .align 1 378 .thumb_func 379 .weak APBHDMA_IRQHandler 380 .type APBHDMA_IRQHandler, %function 381APBHDMA_IRQHandler: 382 ldr r0,=APBHDMA_DriverIRQHandler 383 bx r0 384 .size APBHDMA_IRQHandler, . - APBHDMA_IRQHandler 385 386 .align 1 387 .thumb_func 388 .weak SPDIF2_IRQHandler 389 .type SPDIF2_IRQHandler, %function 390SPDIF2_IRQHandler: 391 ldr r0,=SPDIF2_DriverIRQHandler 392 bx r0 393 .size SPDIF2_IRQHandler, . - SPDIF2_IRQHandler 394 395 .align 1 396 .thumb_func 397 .weak USDHC1_IRQHandler 398 .type USDHC1_IRQHandler, %function 399USDHC1_IRQHandler: 400 ldr r0,=USDHC1_DriverIRQHandler 401 bx r0 402 .size USDHC1_IRQHandler, . - USDHC1_IRQHandler 403 404 .align 1 405 .thumb_func 406 .weak USDHC2_IRQHandler 407 .type USDHC2_IRQHandler, %function 408USDHC2_IRQHandler: 409 ldr r0,=USDHC2_DriverIRQHandler 410 bx r0 411 .size USDHC2_IRQHandler, . - USDHC2_IRQHandler 412 413 .align 1 414 .thumb_func 415 .weak UART1_IRQHandler 416 .type UART1_IRQHandler, %function 417UART1_IRQHandler: 418 ldr r0,=UART1_DriverIRQHandler 419 bx r0 420 .size UART1_IRQHandler, . - UART1_IRQHandler 421 422 .align 1 423 .thumb_func 424 .weak UART2_IRQHandler 425 .type UART2_IRQHandler, %function 426UART2_IRQHandler: 427 ldr r0,=UART2_DriverIRQHandler 428 bx r0 429 .size UART2_IRQHandler, . - UART2_IRQHandler 430 431 .align 1 432 .thumb_func 433 .weak UART3_IRQHandler 434 .type UART3_IRQHandler, %function 435UART3_IRQHandler: 436 ldr r0,=UART3_DriverIRQHandler 437 bx r0 438 .size UART3_IRQHandler, . - UART3_IRQHandler 439 440 .align 1 441 .thumb_func 442 .weak UART4_IRQHandler 443 .type UART4_IRQHandler, %function 444UART4_IRQHandler: 445 ldr r0,=UART4_DriverIRQHandler 446 bx r0 447 .size UART4_IRQHandler, . - UART4_IRQHandler 448 449 .align 1 450 .thumb_func 451 .weak ECSPI1_IRQHandler 452 .type ECSPI1_IRQHandler, %function 453ECSPI1_IRQHandler: 454 ldr r0,=ECSPI1_DriverIRQHandler 455 bx r0 456 .size ECSPI1_IRQHandler, . - ECSPI1_IRQHandler 457 458 .align 1 459 .thumb_func 460 .weak ECSPI2_IRQHandler 461 .type ECSPI2_IRQHandler, %function 462ECSPI2_IRQHandler: 463 ldr r0,=ECSPI2_DriverIRQHandler 464 bx r0 465 .size ECSPI2_IRQHandler, . - ECSPI2_IRQHandler 466 467 .align 1 468 .thumb_func 469 .weak ECSPI3_IRQHandler 470 .type ECSPI3_IRQHandler, %function 471ECSPI3_IRQHandler: 472 ldr r0,=ECSPI3_DriverIRQHandler 473 bx r0 474 .size ECSPI3_IRQHandler, . - ECSPI3_IRQHandler 475 476 .align 1 477 .thumb_func 478 .weak I2C1_IRQHandler 479 .type I2C1_IRQHandler, %function 480I2C1_IRQHandler: 481 ldr r0,=I2C1_DriverIRQHandler 482 bx r0 483 .size I2C1_IRQHandler, . - I2C1_IRQHandler 484 485 .align 1 486 .thumb_func 487 .weak I2C2_IRQHandler 488 .type I2C2_IRQHandler, %function 489I2C2_IRQHandler: 490 ldr r0,=I2C2_DriverIRQHandler 491 bx r0 492 .size I2C2_IRQHandler, . - I2C2_IRQHandler 493 494 .align 1 495 .thumb_func 496 .weak I2C3_IRQHandler 497 .type I2C3_IRQHandler, %function 498I2C3_IRQHandler: 499 ldr r0,=I2C3_DriverIRQHandler 500 bx r0 501 .size I2C3_IRQHandler, . - I2C3_IRQHandler 502 503 .align 1 504 .thumb_func 505 .weak I2C4_IRQHandler 506 .type I2C4_IRQHandler, %function 507I2C4_IRQHandler: 508 ldr r0,=I2C4_DriverIRQHandler 509 bx r0 510 .size I2C4_IRQHandler, . - I2C4_IRQHandler 511 512 .align 1 513 .thumb_func 514 .weak I2S3_IRQHandler 515 .type I2S3_IRQHandler, %function 516I2S3_IRQHandler: 517 ldr r0,=I2S3_DriverIRQHandler 518 bx r0 519 .size I2S3_IRQHandler, . - I2S3_IRQHandler 520 521 .align 1 522 .thumb_func 523 .weak I2S56_IRQHandler 524 .type I2S56_IRQHandler, %function 525I2S56_IRQHandler: 526 ldr r0,=I2S56_DriverIRQHandler 527 bx r0 528 .size I2S56_IRQHandler, . - I2S56_IRQHandler 529 530 .align 1 531 .thumb_func 532 .weak I2S1_IRQHandler 533 .type I2S1_IRQHandler, %function 534I2S1_IRQHandler: 535 ldr r0,=I2S1_DriverIRQHandler 536 bx r0 537 .size I2S1_IRQHandler, . - I2S1_IRQHandler 538 539 .align 1 540 .thumb_func 541 .weak I2S2_IRQHandler 542 .type I2S2_IRQHandler, %function 543I2S2_IRQHandler: 544 ldr r0,=I2S2_DriverIRQHandler 545 bx r0 546 .size I2S2_IRQHandler, . - I2S2_IRQHandler 547 548 .align 1 549 .thumb_func 550 .weak I2S4_IRQHandler 551 .type I2S4_IRQHandler, %function 552I2S4_IRQHandler: 553 ldr r0,=I2S4_DriverIRQHandler 554 bx r0 555 .size I2S4_IRQHandler, . - I2S4_IRQHandler 556 557 .align 1 558 .thumb_func 559 .weak SDMA2_IRQHandler 560 .type SDMA2_IRQHandler, %function 561SDMA2_IRQHandler: 562 ldr r0,=SDMA2_DriverIRQHandler 563 bx r0 564 .size SDMA2_IRQHandler, . - SDMA2_IRQHandler 565 566 .align 1 567 .thumb_func 568 .weak QSPI_IRQHandler 569 .type QSPI_IRQHandler, %function 570QSPI_IRQHandler: 571 ldr r0,=QSPI_DriverIRQHandler 572 bx r0 573 .size QSPI_IRQHandler, . - QSPI_IRQHandler 574 575 .align 1 576 .thumb_func 577 .weak ENET1_MAC0_Rx_Tx_Done1_IRQHandler 578 .type ENET1_MAC0_Rx_Tx_Done1_IRQHandler, %function 579ENET1_MAC0_Rx_Tx_Done1_IRQHandler: 580 ldr r0,=ENET1_MAC0_Rx_Tx_Done1_DriverIRQHandler 581 bx r0 582 .size ENET1_MAC0_Rx_Tx_Done1_IRQHandler, . - ENET1_MAC0_Rx_Tx_Done1_IRQHandler 583 584 .align 1 585 .thumb_func 586 .weak ENET1_MAC0_Rx_Tx_Done2_IRQHandler 587 .type ENET1_MAC0_Rx_Tx_Done2_IRQHandler, %function 588ENET1_MAC0_Rx_Tx_Done2_IRQHandler: 589 ldr r0,=ENET1_MAC0_Rx_Tx_Done2_DriverIRQHandler 590 bx r0 591 .size ENET1_MAC0_Rx_Tx_Done2_IRQHandler, . - ENET1_MAC0_Rx_Tx_Done2_IRQHandler 592 593 .align 1 594 .thumb_func 595 .weak ENET1_IRQHandler 596 .type ENET1_IRQHandler, %function 597ENET1_IRQHandler: 598 ldr r0,=ENET1_DriverIRQHandler 599 bx r0 600 .size ENET1_IRQHandler, . - ENET1_IRQHandler 601 602 .align 1 603 .thumb_func 604 .weak ENET1_1588_Timer_IRQHandler 605 .type ENET1_1588_Timer_IRQHandler, %function 606ENET1_1588_Timer_IRQHandler: 607 ldr r0,=ENET1_1588_Timer_DriverIRQHandler 608 bx r0 609 .size ENET1_1588_Timer_IRQHandler, . - ENET1_1588_Timer_IRQHandler 610 611 612/* Macro to define default handlers. Default handler 613 * will be weak symbol and just dead loops. They can be 614 * overwritten by other handlers */ 615 .macro def_irq_handler handler_name 616 .weak \handler_name 617 .set \handler_name, DefaultISR 618 .endm 619/* Exception Handlers */ 620 def_irq_handler MemManage_Handler 621 def_irq_handler BusFault_Handler 622 def_irq_handler UsageFault_Handler 623 def_irq_handler DebugMon_Handler 624 def_irq_handler GPR_IRQ_IRQHandler 625 def_irq_handler DAP_IRQHandler 626 def_irq_handler SDMA1_DriverIRQHandler 627 def_irq_handler GPU_IRQHandler 628 def_irq_handler SNVS_IRQHandler 629 def_irq_handler LCDIF_IRQHandler 630 def_irq_handler SPDIF1_DriverIRQHandler 631 def_irq_handler H264_IRQHandler 632 def_irq_handler VPUDMA_DriverIRQHandler 633 def_irq_handler QOS_IRQHandler 634 def_irq_handler WDOG3_IRQHandler 635 def_irq_handler HS_CP1_IRQHandler 636 def_irq_handler APBHDMA_DriverIRQHandler 637 def_irq_handler SPDIF2_DriverIRQHandler 638 def_irq_handler BCH_IRQHandler 639 def_irq_handler GPMI_IRQHandler 640 def_irq_handler HDMI_IRQ0_IRQHandler 641 def_irq_handler HDMI_IRQ1_IRQHandler 642 def_irq_handler HDMI_IRQ2_IRQHandler 643 def_irq_handler SNVS_Consolidated_IRQHandler 644 def_irq_handler SNVS_Security_IRQHandler 645 def_irq_handler CSU_IRQHandler 646 def_irq_handler USDHC1_DriverIRQHandler 647 def_irq_handler USDHC2_DriverIRQHandler 648 def_irq_handler DDC_IRQHandler 649 def_irq_handler DTRC_IRQHandler 650 def_irq_handler UART1_DriverIRQHandler 651 def_irq_handler UART2_DriverIRQHandler 652 def_irq_handler UART3_DriverIRQHandler 653 def_irq_handler UART4_DriverIRQHandler 654 def_irq_handler VP9_IRQHandler 655 def_irq_handler ECSPI1_DriverIRQHandler 656 def_irq_handler ECSPI2_DriverIRQHandler 657 def_irq_handler ECSPI3_DriverIRQHandler 658 def_irq_handler MIPI_DSI_IRQHandler 659 def_irq_handler I2C1_DriverIRQHandler 660 def_irq_handler I2C2_DriverIRQHandler 661 def_irq_handler I2C3_DriverIRQHandler 662 def_irq_handler I2C4_DriverIRQHandler 663 def_irq_handler RDC_IRQHandler 664 def_irq_handler USB1_IRQHandler 665 def_irq_handler USB2_IRQHandler 666 def_irq_handler CSI1_IRQHandler 667 def_irq_handler CSI2_IRQHandler 668 def_irq_handler MIPI_CSI1_IRQHandler 669 def_irq_handler MIPI_CSI2_IRQHandler 670 def_irq_handler GPT6_IRQHandler 671 def_irq_handler SCTR_IRQ0_IRQHandler 672 def_irq_handler SCTR_IRQ1_IRQHandler 673 def_irq_handler TEMPMON_IRQHandler 674 def_irq_handler I2S3_DriverIRQHandler 675 def_irq_handler GPT5_IRQHandler 676 def_irq_handler GPT4_IRQHandler 677 def_irq_handler GPT3_IRQHandler 678 def_irq_handler GPT2_IRQHandler 679 def_irq_handler GPT1_IRQHandler 680 def_irq_handler GPIO1_INT7_IRQHandler 681 def_irq_handler GPIO1_INT6_IRQHandler 682 def_irq_handler GPIO1_INT5_IRQHandler 683 def_irq_handler GPIO1_INT4_IRQHandler 684 def_irq_handler GPIO1_INT3_IRQHandler 685 def_irq_handler GPIO1_INT2_IRQHandler 686 def_irq_handler GPIO1_INT1_IRQHandler 687 def_irq_handler GPIO1_INT0_IRQHandler 688 def_irq_handler GPIO1_Combined_0_15_IRQHandler 689 def_irq_handler GPIO1_Combined_16_31_IRQHandler 690 def_irq_handler GPIO2_Combined_0_15_IRQHandler 691 def_irq_handler GPIO2_Combined_16_31_IRQHandler 692 def_irq_handler GPIO3_Combined_0_15_IRQHandler 693 def_irq_handler GPIO3_Combined_16_31_IRQHandler 694 def_irq_handler GPIO4_Combined_0_15_IRQHandler 695 def_irq_handler GPIO4_Combined_16_31_IRQHandler 696 def_irq_handler GPIO5_Combined_0_15_IRQHandler 697 def_irq_handler GPIO5_Combined_16_31_IRQHandler 698 def_irq_handler PCIE_CTRL2_IRQ0_IRQHandler 699 def_irq_handler PCIE_CTRL2_IRQ1_IRQHandler 700 def_irq_handler PCIE_CTRL2_IRQ2_IRQHandler 701 def_irq_handler PCIE_CTRL2_IRQ3_IRQHandler 702 def_irq_handler WDOG1_IRQHandler 703 def_irq_handler WDOG2_IRQHandler 704 def_irq_handler PCIE_CTRL2_IRQHandler 705 def_irq_handler PWM1_IRQHandler 706 def_irq_handler PWM2_IRQHandler 707 def_irq_handler PWM3_IRQHandler 708 def_irq_handler PWM4_IRQHandler 709 def_irq_handler CCM_IRQ1_IRQHandler 710 def_irq_handler CCM_IRQ2_IRQHandler 711 def_irq_handler GPC_IRQHandler 712 def_irq_handler MU_A53_IRQHandler 713 def_irq_handler SRC_IRQHandler 714 def_irq_handler I2S56_DriverIRQHandler 715 def_irq_handler RTIC_IRQHandler 716 def_irq_handler CPU_PerformanceUnit_IRQHandler 717 def_irq_handler CPU_CTI_Trigger_IRQHandler 718 def_irq_handler SRC_Combined_IRQHandler 719 def_irq_handler I2S1_DriverIRQHandler 720 def_irq_handler I2S2_DriverIRQHandler 721 def_irq_handler MU_M4_IRQHandler 722 def_irq_handler DDR_PerformanceMonitor_IRQHandler 723 def_irq_handler DDR_IRQHandler 724 def_irq_handler I2S4_DriverIRQHandler 725 def_irq_handler CPU_Error_AXI_IRQHandler 726 def_irq_handler CPU_Error_L2RAM_IRQHandler 727 def_irq_handler SDMA2_DriverIRQHandler 728 def_irq_handler Reserved120_IRQHandler 729 def_irq_handler CAAM_IRQ0_IRQHandler 730 def_irq_handler CAAM_IRQ1_IRQHandler 731 def_irq_handler QSPI_DriverIRQHandler 732 def_irq_handler TZASC_IRQHandler 733 def_irq_handler Reserved125_IRQHandler 734 def_irq_handler Reserved126_IRQHandler 735 def_irq_handler Reserved127_IRQHandler 736 def_irq_handler PERFMON1_IRQHandler 737 def_irq_handler PERFMON2_IRQHandler 738 def_irq_handler CAAM_IRQ2_IRQHandler 739 def_irq_handler CAAM_ERROR_IRQHandler 740 def_irq_handler HS_CP0_IRQHandler 741 def_irq_handler HEVC_IRQHandler 742 def_irq_handler ENET1_MAC0_Rx_Tx_Done1_DriverIRQHandler 743 def_irq_handler ENET1_MAC0_Rx_Tx_Done2_DriverIRQHandler 744 def_irq_handler ENET1_DriverIRQHandler 745 def_irq_handler ENET1_1588_Timer_DriverIRQHandler 746 def_irq_handler PCIE_CTRL1_IRQ0_IRQHandler 747 def_irq_handler PCIE_CTRL1_IRQ1_IRQHandler 748 def_irq_handler PCIE_CTRL1_IRQ2_IRQHandler 749 def_irq_handler PCIE_CTRL1_IRQ3_IRQHandler 750 def_irq_handler Reserved142_IRQHandler 751 def_irq_handler PCIE_CTRL1_IRQHandler 752 753 .end 754
