1 /*
2 * Copyright 2017-2018 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 /***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12 /*
13 * How to set up clock using clock driver functions:
14 *
15 * 1. Setup clock sources.
16 *
17 * 2. Set up wait states of the flash.
18 *
19 * 3. Set up all dividers.
20 *
21 * 4. Set up all selectors to provide selected clocks.
22 */
23
24 /* clang-format off */
25 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
26 !!GlobalInfo
27 product: Clocks v7.0
28 processor: LPC55S06
29 mcu_data: ksdk2_0
30 processor_version: 0.0.0
31 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
32 /* clang-format on */
33
34 #include "fsl_power.h"
35 #include "fsl_clock.h"
36 #include "clock_config.h"
37
38 /*******************************************************************************
39 * Definitions
40 ******************************************************************************/
41
42 /*******************************************************************************
43 * Variables
44 ******************************************************************************/
45 /* System clock frequency. */
46 extern uint32_t SystemCoreClock;
47
48 /*******************************************************************************
49 ************************ BOARD_InitBootClocks function ************************
50 ******************************************************************************/
BOARD_InitBootClocks(void)51 void BOARD_InitBootClocks(void)
52 {
53 BOARD_BootClockFROHF96M();
54 }
55 /*******************************************************************************
56 ******************** Configuration BOARD_BootClockFRO12M **********************
57 ******************************************************************************/
58 /* clang-format off */
59 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
60 !!Configuration
61 name: BOARD_BootClockFRO12M
62 outputs:
63 - {id: FRO_12MHz_clock.outFreq, value: 12 MHz}
64 - {id: System_clock.outFreq, value: 12 MHz}
65 settings:
66 - {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
67 sources:
68 - {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
69 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
70 /* clang-format on */
71
72 /*******************************************************************************
73 * Variables for BOARD_BootClockFRO12M configuration
74 ******************************************************************************/
75 /*******************************************************************************
76 * Code for BOARD_BootClockFRO12M configuration
77 ******************************************************************************/
BOARD_BootClockFRO12M(void)78 void BOARD_BootClockFRO12M(void)
79 {
80 #ifndef SDK_SECONDARY_CORE
81 /*!< Set up the clock sources */
82 /*!< Configure FRO192M */
83 POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
84 CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
85 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
86
87 CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */
88
89 POWER_SetVoltageForFreq(12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
90 CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */
91
92 /*!< Set up dividers */
93 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
94
95 /*!< Set up clock selectors - Attach clocks to the peripheries */
96 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */
97
98 /*< Set SystemCoreClock variable. */
99 SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
100 #endif
101 }
102
103 /*******************************************************************************
104 ******************* Configuration BOARD_BootClockFROHF96M *********************
105 ******************************************************************************/
106 /* clang-format off */
107 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
108 !!Configuration
109 name: BOARD_BootClockFROHF96M
110 outputs:
111 - {id: FRO_12MHz_clock.outFreq, value: 12 MHz}
112 - {id: System_clock.outFreq, value: 96 MHz}
113 settings:
114 - {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
115 - {id: SYSCON.MAINCLKSELA.sel, value: ANACTRL.fro_hf_clk}
116 sources:
117 - {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
118 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
119 /* clang-format on */
120
121 /*******************************************************************************
122 * Variables for BOARD_BootClockFROHF96M configuration
123 ******************************************************************************/
124 /*******************************************************************************
125 * Code for BOARD_BootClockFROHF96M configuration
126 ******************************************************************************/
BOARD_BootClockFROHF96M(void)127 void BOARD_BootClockFROHF96M(void)
128 {
129 #ifndef SDK_SECONDARY_CORE
130 /*!< Set up the clock sources */
131 /*!< Configure FRO192M */
132 POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
133 CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
134 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
135
136 CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */
137
138 POWER_SetVoltageForFreq(96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
139 CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */
140
141 /*!< Set up dividers */
142 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
143
144 /*!< Set up clock selectors - Attach clocks to the peripheries */
145 CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
146
147 /*< Set SystemCoreClock variable. */
148 SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK;
149 #endif
150 }
151
152 /*******************************************************************************
153 ******************** Configuration BOARD_BootClockPLL96M **********************
154 ******************************************************************************/
155 /* clang-format off */
156 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
157 !!Configuration
158 name: BOARD_BootClockPLL96M
159 outputs:
160 - {id: CLKOUT_clock.outFreq, value: 16 MHz}
161 - {id: FRO_12MHz_clock.outFreq, value: 12 MHz}
162 - {id: System_clock.outFreq, value: 96 MHz}
163 settings:
164 - {id: PLL0_Mode, value: Normal}
165 - {id: ENABLE_CLKIN_ENA, value: Enabled}
166 - {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
167 - {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS}
168 - {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN}
169 - {id: SYSCON.PLL0M_MULT.scale, value: '96', locked: true}
170 - {id: SYSCON.PLL0N_DIV.scale, value: '4', locked: true}
171 - {id: SYSCON.PLL0_PDEC.scale, value: '4', locked: true}
172 sources:
173 - {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
174 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
175 /* clang-format on */
176
177 /*******************************************************************************
178 * Variables for BOARD_BootClockPLL96M configuration
179 ******************************************************************************/
180 /*******************************************************************************
181 * Code for BOARD_BootClockPLL96M configuration
182 ******************************************************************************/
BOARD_BootClockPLL96M(void)183 void BOARD_BootClockPLL96M(void)
184 {
185 #ifndef SDK_SECONDARY_CORE
186 /*!< Set up the clock sources */
187 /*!< Configure FRO192M */
188 POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
189 CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
190 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
191
192 /*!< Configure XTAL32M */
193 POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */
194 POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */
195 CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */
196 SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */
197 ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */
198
199 POWER_SetVoltageForFreq(96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
200 CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */
201
202 /*!< Set up PLL */
203 CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */
204 POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */
205 POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
206 const pll_setup_t pll0Setup = {
207 .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(51U) | SYSCON_PLL0CTRL_SELP(25U),
208 .pllndec = SYSCON_PLL0NDEC_NDIV(4U),
209 .pllpdec = SYSCON_PLL0PDEC_PDIV(2U),
210 .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(96U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
211 .pllRate = 96000000U,
212 .flags = PLL_SETUPFLAG_WAITLOCK
213 };
214 CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */
215
216 /*!< Set up dividers */
217 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
218
219 /*!< Set up clock selectors - Attach clocks to the peripheries */
220 CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */
221
222 /*< Set SystemCoreClock variable. */
223 SystemCoreClock = BOARD_BOOTCLOCKPLL96M_CORE_CLOCK;
224 #endif
225 }
226
227
