1 /*
2 * Copyright 2021 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 /***********************************************************************************************************************
8 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
9 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
10 **********************************************************************************************************************/
11 /*
12 * How to set up clock using clock driver functions:
13 *
14 * 1. Setup clock sources.
15 *
16 * 2. Set up all selectors to provide selected clocks.
17 *
18 * 3. Set up all dividers.
19 */
20
21 /* clang-format off */
22 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
23 !!GlobalInfo
24 product: Clocks v7.0
25 processor: MIMXRT685S
26 package_id: MIMXRT685SFVKB
27 mcu_data: ksdk2_0
28 processor_version: 0.9.6
29 board: MIMXRT685-AUD-EVK
30 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
31 /* clang-format on */
32
33 #include "fsl_power.h"
34 #include "fsl_clock.h"
35 #include "clock_config.h"
36
37 /*******************************************************************************
38 * Definitions
39 ******************************************************************************/
40
41 /*******************************************************************************
42 * Variables
43 ******************************************************************************/
44 /* System clock frequency. */
45 extern uint32_t SystemCoreClock;
46
47 /*FUNCTION**********************************************************************
48 *
49 * Function Name : BOARD_FlexspiClockSafeConfig
50 * Description : FLEXSPI clock source safe configuration weak function.
51 * Called before clock source(Such as PLL, Main clock) configuration.
52 * Note : Users need override this function to change FLEXSPI clock source to stable source when executing
53 * code on FLEXSPI memory(XIP). If XIP, the function should runs in RAM and move the FLEXSPI clock
54 *source to an stable clock to avoid instruction/data fetch issue during clock updating.
55 *END**************************************************************************/
BOARD_FlexspiClockSafeConfig(void)56 __attribute__((weak)) void BOARD_FlexspiClockSafeConfig(void)
57 {
58 }
59
60 /*FUNCTION**********************************************************************
61 *
62 * Function Name : BOARD_SetFlexspiClock
63 * Description : This function should be overridden if executing code on FLEXSPI memory(XIP).
64 * To Change FLEXSPI clock, should move to run from RAM and then configure FLEXSPI clock source.
65 * After the clock is changed and stable, move back to run on FLEXSPI.
66 * Param src : FLEXSPI clock source.
67 * Param divider : FLEXSPI clock divider.
68 *END**************************************************************************/
BOARD_SetFlexspiClock(uint32_t src,uint32_t divider)69 __attribute__((weak)) void BOARD_SetFlexspiClock(uint32_t src, uint32_t divider)
70 {
71 CLKCTL0->FLEXSPIFCLKSEL = CLKCTL0_FLEXSPIFCLKSEL_SEL(src);
72 CLKCTL0->FLEXSPIFCLKDIV |= CLKCTL0_FLEXSPIFCLKDIV_RESET_MASK; /* Reset the divider counter */
73 CLKCTL0->FLEXSPIFCLKDIV = CLKCTL0_FLEXSPIFCLKDIV_DIV(divider - 1);
74 while ((CLKCTL0->FLEXSPIFCLKDIV) & CLKCTL0_FLEXSPIFCLKDIV_REQFLAG_MASK)
75 {
76 }
77 }
78
79 /*******************************************************************************
80 ************************ BOARD_InitBootClocks function ************************
81 ******************************************************************************/
BOARD_InitBootClocks(void)82 void BOARD_InitBootClocks(void)
83 {
84 BOARD_BootClockRUN();
85 }
86
87 /*******************************************************************************
88 ********************** Configuration BOARD_BootClockRUN ***********************
89 ******************************************************************************/
90 /* clang-format off */
91 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
92 !!Configuration
93 name: BOARD_BootClockRUN
94 called_from_default_init: true
95 outputs:
96 - {id: FLEXSPI_clock.outFreq, value: 1056/19 MHz}
97 - {id: LPOSC1M_clock.outFreq, value: 1 MHz}
98 - {id: OSTIMER_clock.outFreq, value: 1 MHz}
99 - {id: System_clock.outFreq, value: 4752/19 MHz}
100 - {id: TRACE_clock.outFreq, value: 4752/19 MHz}
101 - {id: WAKE_32K_clock.outFreq, value: 31.25 kHz}
102 settings:
103 - {id: AUDIOPLL0_PFD0_CLK_GATE, value: Enabled}
104 - {id: PFC0DIV_HALT, value: Enable}
105 - {id: PLL0_PFD0_CLK_GATE, value: Enabled}
106 - {id: PLL0_PFD2_CLK_GATE, value: Enabled}
107 - {id: SYSCON.AUDIOPLL0CLKSEL.sel, value: SYSCON.SYSOSCBYPASS}
108 - {id: SYSCON.AUDIOPLL0_PFD0_DIV.scale, value: '26', locked: true}
109 - {id: SYSCON.AUDIOPLLCLKDIV.scale, value: '15', locked: true}
110 - {id: SYSCON.AUDIO_PLL0_PFD0_MUL.scale, value: '18', locked: true}
111 - {id: SYSCON.FLEXSPIFCLKDIV.scale, value: '9', locked: true}
112 - {id: SYSCON.FLEXSPIFCLKSEL.sel, value: SYSCON.MAINPLLCLKDIV}
113 - {id: SYSCON.FRGPLLCLKDIV.scale, value: '12', locked: true}
114 - {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.MAINPLLCLKDIV}
115 - {id: SYSCON.PFC0DIV.scale, value: '2', locked: true}
116 - {id: SYSCON.PFC1DIV.scale, value: '1', locked: true}
117 - {id: SYSCON.PLL0.denom, value: '1'}
118 - {id: SYSCON.PLL0.div, value: '22', locked: true}
119 - {id: SYSCON.PLL0.num, value: '0'}
120 - {id: SYSCON.PLL0_PFD0_DIV.scale, value: '19', locked: true}
121 - {id: SYSCON.PLL0_PFD0_MUL.scale, value: '18', locked: true}
122 - {id: SYSCON.PLL0_PFD2_DIV.scale, value: '24', locked: true}
123 - {id: SYSCON.PLL0_PFD2_MUL.scale, value: '18', locked: true}
124 - {id: SYSCON.PLL1.denom, value: '27000', locked: true}
125 - {id: SYSCON.PLL1.div, value: '22'}
126 - {id: SYSCON.PLL1.num, value: '5040', locked: true}
127 - {id: SYSCON.SYSCPUAHBCLKDIV.scale, value: '2'}
128 - {id: SYSCON.SYSPLL0CLKSEL.sel, value: SYSCON.SYSOSCBYPASS}
129 - {id: SYSCTL_PDRUNCFG_AUDIOPLL_CFG, value: 'No'}
130 - {id: SYSCTL_PDRUNCFG_SYSPLL_CFG, value: 'No'}
131 - {id: SYSCTL_PDRUNCFG_SYSXTAL_CFG, value: Power_up}
132 - {id: XTAL_LP_Enable, value: LowPowerMode}
133 sources:
134 - {id: SYSCON.XTAL.outFreq, value: 24 MHz, enabled: true}
135 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
136 /* clang-format on */
137
138 /*******************************************************************************
139 * Variables for BOARD_BootClockRUN configuration
140 ******************************************************************************/
141 const clock_sys_pll_config_t g_sysPllConfig_BOARD_BootClockRUN = {
142 .sys_pll_src = kCLOCK_SysPllXtalIn, /* OSC clock */
143 .numerator = 0, /* Numerator of the SYSPLL0 fractional loop divider isnull */
144 .denominator = 1, /* Denominator of the SYSPLL0 fractional loop divider isnull */
145 .sys_pll_mult = kCLOCK_SysPllMult22 /* Divide by 22 */
146 };
147 const clock_audio_pll_config_t g_audioPllConfig_BOARD_BootClockRUN = {
148 .audio_pll_src = kCLOCK_AudioPllXtalIn, /* OSC clock */
149 .numerator = 5040, /* Numerator of the Audio PLL fractional loop divider is null */
150 .denominator = 27000, /* Denominator of the Audio PLL fractional loop divider is null */
151 .audio_pll_mult = kCLOCK_AudioPllMult22 /* Divide by 22 */
152 };
153 /*******************************************************************************
154 * Code for BOARD_BootClockRUN configuration
155 ******************************************************************************/
BOARD_BootClockRUN(void)156 void BOARD_BootClockRUN(void)
157 {
158 /* Configure LPOSC clock*/
159 POWER_DisablePD(kPDRUNCFG_PD_LPOSC); /* Power on LPOSC (1MHz) */
160 /* Configure FFRO clock */
161 POWER_DisablePD(kPDRUNCFG_PD_FFRO); /* Power on FFRO (48/60MHz) */
162 CLOCK_EnableFfroClk(kCLOCK_Ffro48M); /* Enable FFRO clock*/
163 /* Configure SFRO clock */
164 POWER_DisablePD(kPDRUNCFG_PD_SFRO); /* Power on SFRO (16MHz) */
165 CLOCK_EnableSfroClk(); /* Wait until SFRO stable */
166
167 /* Call function BOARD_FlexspiClockSafeConfig() to move FLEXSPI clock to a stable clock source to avoid
168 instruction/data fetch issue when updating PLL and Main clock if XIP(execute code on FLEXSPI memory). */
169 BOARD_FlexspiClockSafeConfig();
170
171 /* Let CPU run on ffro for safe switching */
172 CLOCK_AttachClk(kFFRO_to_MAIN_CLK);
173
174 /* Configure SYSOSC clock source */
175 POWER_DisablePD(kPDRUNCFG_PD_SYSXTAL); /* Power on SYSXTAL */
176 POWER_UpdateOscSettlingTime(BOARD_SYSOSC_SETTLING_US); /* Updated XTAL oscillator settling time */
177 CLOCK_EnableSysOscClk(true, true, BOARD_SYSOSC_SETTLING_US); /* Enable system OSC */
178 CLOCK_SetXtalFreq(BOARD_XTAL_SYS_CLK_HZ); /* Sets external XTAL OSC freq */
179
180 /* Configure SysPLL0 clock source */
181 CLOCK_InitSysPll(&g_sysPllConfig_BOARD_BootClockRUN);
182 CLOCK_InitSysPfd(kCLOCK_Pfd0, 19); /* Enable MAIN PLL clock */
183 CLOCK_InitSysPfd(kCLOCK_Pfd2, 24); /* Enable AUX0 PLL clock */
184
185 /* Configure Audio PLL clock source */
186 CLOCK_InitAudioPll(&g_audioPllConfig_BOARD_BootClockRUN);
187 CLOCK_InitAudioPfd(kCLOCK_Pfd0, 26); /* Enable Audio PLL clock */
188
189 CLOCK_SetClkDiv(kCLOCK_DivSysCpuAhbClk, 2U); /* Set SYSCPUAHBCLKDIV divider to value 2 */
190
191 /* Set up clock selectors - Attach clocks to the peripheries */
192 CLOCK_AttachClk(kMAIN_PLL_to_MAIN_CLK); /* Switch MAIN_CLK to MAIN_PLL */
193
194 /* Set up dividers */
195 CLOCK_SetClkDiv(kCLOCK_DivAudioPllClk, 15U); /* Set AUDIOPLLCLKDIV divider to value 15 */
196 CLOCK_SetClkDiv(kCLOCK_DivPfc0Clk, 2U); /* Set PFC0DIV divider to value 2 */
197 CLOCK_SetClkDiv(kCLOCK_DivPllFrgClk, 12U); /* Set FRGPLLCLKDIV divider to value 12 */
198
199 /* Call weak function BOARD_SetFlexspiClock() to set user configured clock source/divider for FLEXSPI. */
200 BOARD_SetFlexspiClock(1U, 9U);
201
202 /*!< Set SystemCoreClock variable. */
203 SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
204 }
205
