1 /*
2 * Copyright 2017-2018 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 /***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12 /*
13 * How to set up clock using clock driver functions:
14 *
15 * 1. Setup clock sources.
16 *
17 * 2. Set up wait states of the flash.
18 *
19 * 3. Set up all dividers.
20 *
21 * 4. Set up all selectors to provide selected clocks.
22 */
23
24 /* clang-format off */
25 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
26 !!GlobalInfo
27 product: Clocks v7.0
28 processor: LPC55S06
29 package_id: LPC55S06JBD64
30 mcu_data: ksdk2_0
31 processor_version: 0.0.0
32 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
33 /* clang-format on */
34
35 #include "fsl_power.h"
36 #include "fsl_clock.h"
37 #include "clock_config.h"
38
39 /*******************************************************************************
40 * Definitions
41 ******************************************************************************/
42
43 /*******************************************************************************
44 * Variables
45 ******************************************************************************/
46 /* System clock frequency. */
47 extern uint32_t SystemCoreClock;
48
49 /*******************************************************************************
50 ************************ BOARD_InitBootClocks function ************************
51 ******************************************************************************/
BOARD_InitBootClocks(void)52 void BOARD_InitBootClocks(void)
53 {
54 BOARD_BootClockFROHF96M();
55 }
56 /*******************************************************************************
57 ******************** Configuration BOARD_BootClockFRO12M **********************
58 ******************************************************************************/
59 /* clang-format off */
60 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
61 !!Configuration
62 name: BOARD_BootClockFRO12M
63 outputs:
64 - {id: FRO_12MHz_clock.outFreq, value: 12 MHz}
65 - {id: System_clock.outFreq, value: 12 MHz}
66 settings:
67 - {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
68 sources:
69 - {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
70 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
71 /* clang-format on */
72
73 /*******************************************************************************
74 * Variables for BOARD_BootClockFRO12M configuration
75 ******************************************************************************/
76 /*******************************************************************************
77 * Code for BOARD_BootClockFRO12M configuration
78 ******************************************************************************/
BOARD_BootClockFRO12M(void)79 void BOARD_BootClockFRO12M(void)
80 {
81 #ifndef SDK_SECONDARY_CORE
82 /*!< Set up the clock sources */
83 /*!< Configure FRO192M */
84 POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
85 CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
86 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
87
88 CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */
89
90 POWER_SetVoltageForFreq(12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
91 CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */
92
93 /*!< Set up dividers */
94 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
95
96 /*!< Set up clock selectors - Attach clocks to the peripheries */
97 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */
98
99 /*< Set SystemCoreClock variable. */
100 SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
101 #endif
102 }
103
104 /*******************************************************************************
105 ******************* Configuration BOARD_BootClockFROHF96M *********************
106 ******************************************************************************/
107 /* clang-format off */
108 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
109 !!Configuration
110 name: BOARD_BootClockFROHF96M
111 outputs:
112 - {id: FRO_12MHz_clock.outFreq, value: 12 MHz}
113 - {id: System_clock.outFreq, value: 96 MHz}
114 settings:
115 - {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
116 - {id: SYSCON.MAINCLKSELA.sel, value: ANACTRL.fro_hf_clk}
117 sources:
118 - {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
119 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
120 /* clang-format on */
121
122 /*******************************************************************************
123 * Variables for BOARD_BootClockFROHF96M configuration
124 ******************************************************************************/
125 /*******************************************************************************
126 * Code for BOARD_BootClockFROHF96M configuration
127 ******************************************************************************/
BOARD_BootClockFROHF96M(void)128 void BOARD_BootClockFROHF96M(void)
129 {
130 #ifndef SDK_SECONDARY_CORE
131 /*!< Set up the clock sources */
132 /*!< Configure FRO192M */
133 POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
134 CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
135 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
136
137 CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */
138
139 POWER_SetVoltageForFreq(96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
140 CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */
141
142 /*!< Set up dividers */
143 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
144
145 /*!< Set up clock selectors - Attach clocks to the peripheries */
146 CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
147
148 /*< Set SystemCoreClock variable. */
149 SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK;
150 #endif
151 }
152
153 /*******************************************************************************
154 ******************** Configuration BOARD_BootClockPLL96M **********************
155 ******************************************************************************/
156 /* clang-format off */
157 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
158 !!Configuration
159 name: BOARD_BootClockPLL96M
160 outputs:
161 - {id: CLKOUT_clock.outFreq, value: 16 MHz}
162 - {id: FRO_12MHz_clock.outFreq, value: 12 MHz}
163 - {id: System_clock.outFreq, value: 96 MHz}
164 settings:
165 - {id: PLL0_Mode, value: Normal}
166 - {id: ENABLE_CLKIN_ENA, value: Enabled}
167 - {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
168 - {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS}
169 - {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN}
170 - {id: SYSCON.PLL0M_MULT.scale, value: '96', locked: true}
171 - {id: SYSCON.PLL0N_DIV.scale, value: '4', locked: true}
172 - {id: SYSCON.PLL0_PDEC.scale, value: '4', locked: true}
173 sources:
174 - {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
175 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
176 /* clang-format on */
177
178 /*******************************************************************************
179 * Variables for BOARD_BootClockPLL96M configuration
180 ******************************************************************************/
181 /*******************************************************************************
182 * Code for BOARD_BootClockPLL96M configuration
183 ******************************************************************************/
BOARD_BootClockPLL96M(void)184 void BOARD_BootClockPLL96M(void)
185 {
186 #ifndef SDK_SECONDARY_CORE
187 /*!< Set up the clock sources */
188 /*!< Configure FRO192M */
189 POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
190 CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
191 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
192
193 /*!< Configure XTAL32M */
194 POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */
195 POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */
196 CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */
197 SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */
198 ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */
199
200 POWER_SetVoltageForFreq(96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
201 CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */
202
203 /*!< Set up PLL */
204 CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */
205 POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */
206 POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
207 const pll_setup_t pll0Setup = {
208 .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(51U) | SYSCON_PLL0CTRL_SELP(25U),
209 .pllndec = SYSCON_PLL0NDEC_NDIV(4U),
210 .pllpdec = SYSCON_PLL0PDEC_PDIV(2U),
211 .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(96U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
212 .pllRate = 96000000U,
213 .flags = PLL_SETUPFLAG_WAITLOCK
214 };
215 CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */
216
217 /*!< Set up dividers */
218 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
219
220 /*!< Set up clock selectors - Attach clocks to the peripheries */
221 CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */
222
223 /*< Set SystemCoreClock variable. */
224 SystemCoreClock = BOARD_BOOTCLOCKPLL96M_CORE_CLOCK;
225 #endif
226 }
227
228
