1 /*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016-2018 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #include <stdint.h>
10 #include "clock_config.h"
11 #include "board.h"
12 #include "fsl_common.h"
13 #include "fsl_debug_console.h"
14 #include "fsl_emc.h"
15 #if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
16 #include "fsl_i2c.h"
17 #endif /* SDK_I2C_BASED_COMPONENT_USED */
18 #if defined BOARD_USE_CODEC
19 #include "fsl_wm8904.h"
20 #endif
21 /*******************************************************************************
22 * Definitions
23 ******************************************************************************/
24 /* The SDRAM timing. */
25
26 #define W9812G6JB6I
27
28 #ifdef MTL48LC8M16A2B
29 #define SDRAM_REFRESHPERIOD_NS (64 * 1000000 / 4096) /* 4096 rows/ 64ms */
30 #define SDRAM_TRP_NS (18u)
31 #define SDRAM_TRAS_NS (42u)
32 #define SDRAM_TSREX_NS (67u)
33 #define SDRAM_TAPR_NS (18u)
34 #define SDRAM_TWRDELT_NS (6u)
35 #define SDRAM_TRC_NS (60u)
36 #define SDRAM_RFC_NS (60u)
37 #define SDRAM_XSR_NS (67u)
38 #define SDRAM_RRD_NS (12u)
39 #define SDRAM_MRD_NCLK (2u)
40 #define SDRAM_RAS_NCLK (2u)
41 #define SDRAM_MODEREG_VALUE (0x33u)
42 #define SDRAM_DEV_MEMORYMAP (0x09u) /* 128Mbits (8M*16, 4banks, 12 rows, 9 columns)*/
43 #endif
44
45 #ifdef W9812G6JB6I
46 #define SDRAM_REFRESHPERIOD_NS (64 * 1000000 / 4096) /* 4096 rows/ 64ms */
47 #define SDRAM_TRP_NS (20u)
48 #define SDRAM_TRAS_NS (42u)
49 #define SDRAM_TSREX_NS (72u)
50 #define SDRAM_TAPR_NS (18u)
51 #define SDRAM_TWRDELT_NS (12u)
52 #define SDRAM_TRC_NS (60u)
53 #define SDRAM_RFC_NS (60u)
54 #define SDRAM_XSR_NS (67u)
55 #define SDRAM_RRD_NS (12u)
56 #define SDRAM_MRD_NCLK (2u)
57 #define SDRAM_RAS_NCLK (2u)
58 #define SDRAM_MODEREG_VALUE (0x33u)
59 #define SDRAM_DEV_MEMORYMAP (0x09u) /* 128Mbits (8M*16, 4banks, 12 rows, 9 columns)*/
60 #endif
61
62 /*******************************************************************************
63 * Variables
64 ******************************************************************************/
65
66 /* Clock rate on the CLKIN pin */
67 const uint32_t ExtClockIn = BOARD_EXTCLKINRATE;
68
69 /*******************************************************************************
70 * Code
71 ******************************************************************************/
72 /* Initialize debug console. */
BOARD_InitDebugConsole(void)73 status_t BOARD_InitDebugConsole(void)
74 {
75 #if ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART))
76 status_t result;
77 /* attach 12 MHz clock to FLEXCOMM0 (debug console) */
78 CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH);
79 RESET_PeripheralReset(BOARD_DEBUG_UART_RST);
80 result = DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE,
81 BOARD_DEBUG_UART_CLK_FREQ);
82 assert(kStatus_Success == result);
83 return result;
84 #else
85 return kStatus_Success;
86 #endif
87 }
88
89 /* Initialize the external memory. */
BOARD_InitSDRAM(void)90 void BOARD_InitSDRAM(void)
91 {
92 uint32_t emcFreq;
93 emc_basic_config_t basicConfig;
94 emc_dynamic_timing_config_t dynTiming;
95 emc_dynamic_chip_config_t dynChipConfig;
96
97 emcFreq = CLOCK_GetEmcClkFreq();
98 assert(emcFreq != 0); /* Check the clock of emc */
99 /* Basic configuration. */
100 basicConfig.endian = kEMC_LittleEndian;
101 basicConfig.fbClkSrc = kEMC_IntloopbackEmcclk;
102 /* EMC Clock = CPU FREQ/2 here can fit CPU freq from 12M ~ 180M.
103 * If you change the divide to 0 and EMC clock is larger than 100M
104 * please take refer to emc.dox to adjust EMC clock delay.
105 */
106 basicConfig.emcClkDiv = 1;
107 /* Dynamic memory timing configuration. */
108 dynTiming.readConfig = kEMC_Cmddelay;
109 dynTiming.refreshPeriod_Nanosec = SDRAM_REFRESHPERIOD_NS;
110 dynTiming.tRp_Ns = SDRAM_TRP_NS;
111 dynTiming.tRas_Ns = SDRAM_TRAS_NS;
112 dynTiming.tSrex_Ns = SDRAM_TSREX_NS;
113 dynTiming.tApr_Ns = SDRAM_TAPR_NS;
114 dynTiming.tWr_Ns = (1000000000 / emcFreq + SDRAM_TWRDELT_NS); /* one clk + 6ns */
115 dynTiming.tDal_Ns = dynTiming.tWr_Ns + dynTiming.tRp_Ns;
116 dynTiming.tRc_Ns = SDRAM_TRC_NS;
117 dynTiming.tRfc_Ns = SDRAM_RFC_NS;
118 dynTiming.tXsr_Ns = SDRAM_XSR_NS;
119 dynTiming.tRrd_Ns = SDRAM_RRD_NS;
120 dynTiming.tMrd_Nclk = SDRAM_MRD_NCLK;
121 /* Dynamic memory chip specific configuration: Chip 0 - W9812G6JB-6I */
122 dynChipConfig.chipIndex = 0;
123 dynChipConfig.dynamicDevice = kEMC_Sdram;
124 dynChipConfig.rAS_Nclk = SDRAM_RAS_NCLK;
125 dynChipConfig.sdramModeReg = SDRAM_MODEREG_VALUE;
126 dynChipConfig.sdramExtModeReg = 0; /* it has no use for normal sdram */
127 dynChipConfig.devAddrMap = SDRAM_DEV_MEMORYMAP;
128 /* EMC Basic configuration. */
129 EMC_Init(EMC, &basicConfig);
130 /* EMC Dynamc memory configuration. */
131 EMC_DynamicMemInit(EMC, &dynTiming, &dynChipConfig, 1);
132 }
133 #if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
BOARD_I2C_Init(I2C_Type * base,uint32_t clkSrc_Hz)134 void BOARD_I2C_Init(I2C_Type *base, uint32_t clkSrc_Hz)
135 {
136 i2c_master_config_t i2cConfig = {0};
137
138 I2C_MasterGetDefaultConfig(&i2cConfig);
139 I2C_MasterInit(base, &i2cConfig, clkSrc_Hz);
140 }
141
BOARD_I2C_Send(I2C_Type * base,uint8_t deviceAddress,uint32_t subAddress,uint8_t subaddressSize,uint8_t * txBuff,uint8_t txBuffSize)142 status_t BOARD_I2C_Send(I2C_Type *base,
143 uint8_t deviceAddress,
144 uint32_t subAddress,
145 uint8_t subaddressSize,
146 uint8_t *txBuff,
147 uint8_t txBuffSize)
148 {
149 i2c_master_transfer_t masterXfer;
150
151 /* Prepare transfer structure. */
152 masterXfer.slaveAddress = deviceAddress;
153 masterXfer.direction = kI2C_Write;
154 masterXfer.subaddress = subAddress;
155 masterXfer.subaddressSize = subaddressSize;
156 masterXfer.data = txBuff;
157 masterXfer.dataSize = txBuffSize;
158 masterXfer.flags = kI2C_TransferDefaultFlag;
159
160 return I2C_MasterTransferBlocking(base, &masterXfer);
161 }
162
BOARD_I2C_Receive(I2C_Type * base,uint8_t deviceAddress,uint32_t subAddress,uint8_t subaddressSize,uint8_t * rxBuff,uint8_t rxBuffSize)163 status_t BOARD_I2C_Receive(I2C_Type *base,
164 uint8_t deviceAddress,
165 uint32_t subAddress,
166 uint8_t subaddressSize,
167 uint8_t *rxBuff,
168 uint8_t rxBuffSize)
169 {
170 i2c_master_transfer_t masterXfer;
171
172 /* Prepare transfer structure. */
173 masterXfer.slaveAddress = deviceAddress;
174 masterXfer.subaddress = subAddress;
175 masterXfer.subaddressSize = subaddressSize;
176 masterXfer.data = rxBuff;
177 masterXfer.dataSize = rxBuffSize;
178 masterXfer.direction = kI2C_Read;
179 masterXfer.flags = kI2C_TransferDefaultFlag;
180
181 return I2C_MasterTransferBlocking(base, &masterXfer);
182 }
183
BOARD_Accel_I2C_Init(void)184 void BOARD_Accel_I2C_Init(void)
185 {
186 BOARD_I2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
187 }
188
BOARD_Accel_I2C_Send(uint8_t deviceAddress,uint32_t subAddress,uint8_t subaddressSize,uint32_t txBuff)189 status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)
190 {
191 uint8_t data = (uint8_t)txBuff;
192
193 return BOARD_I2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);
194 }
195
BOARD_Accel_I2C_Receive(uint8_t deviceAddress,uint32_t subAddress,uint8_t subaddressSize,uint8_t * rxBuff,uint8_t rxBuffSize)196 status_t BOARD_Accel_I2C_Receive(
197 uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
198 {
199 return BOARD_I2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);
200 }
201
BOARD_Codec_I2C_Init(void)202 void BOARD_Codec_I2C_Init(void)
203 {
204 BOARD_I2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
205 }
206
BOARD_Codec_I2C_Send(uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,const uint8_t * txBuff,uint8_t txBuffSize)207 status_t BOARD_Codec_I2C_Send(
208 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
209 {
210 return BOARD_I2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
211 txBuffSize);
212 }
213
BOARD_Codec_I2C_Receive(uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,uint8_t * rxBuff,uint8_t rxBuffSize)214 status_t BOARD_Codec_I2C_Receive(
215 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
216 {
217 return BOARD_I2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
218 }
219
BOARD_Touch_I2C_Send(uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,const uint8_t * txBuff,uint8_t txBuffSize)220 status_t BOARD_Touch_I2C_Send(
221 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
222 {
223 return BOARD_I2C_Send(BOARD_TOUCH_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
224 txBuffSize);
225 }
226
BOARD_Touch_I2C_Receive(uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,uint8_t * rxBuff,uint8_t rxBuffSize)227 status_t BOARD_Touch_I2C_Receive(
228 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
229 {
230 return BOARD_I2C_Receive(BOARD_TOUCH_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
231 }
232 #endif /* SDK_I2C_BASED_COMPONENT_USED */
233
