1 /*
2 * Copyright 2022 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 /*
9 * How to setup clock using clock driver functions:
10 *
11 * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
12 *
13 * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
14 *
15 * 3. Call CLOCK_SetRootClock() to configure corresponding module clock source and divider.
16 *
17 */
18
19 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
20 !!GlobalInfo
21 product: Clocks v10.0
22 processor: MIMXRT1176xxxxx
23 package_id: MIMXRT1176DVMAA
24 mcu_data: ksdk2_0
25 processor_version: 0.12.10
26 board: MIMXRT1170-EVK
27 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
28
29 #include "clock_config.h"
30 #include "fsl_iomuxc.h"
31 #include "fsl_dcdc.h"
32 #include "fsl_pmu.h"
33 #include "fsl_clock.h"
34
35 /*******************************************************************************
36 * Definitions
37 ******************************************************************************/
38
39 /*******************************************************************************
40 * Variables
41 ******************************************************************************/
42
43 /*******************************************************************************
44 ************************ BOARD_InitBootClocks function ************************
45 ******************************************************************************/
BOARD_InitBootClocks(void)46 void BOARD_InitBootClocks(void)
47 {
48 BOARD_BootClockRUN();
49 }
50
51 #if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
52 #if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
53 /* This function should not run from SDRAM since it will change SEMC configuration. */
54 AT_QUICKACCESS_SECTION_CODE(void UpdateSemcClock(void));
UpdateSemcClock(void)55 void UpdateSemcClock(void)
56 {
57 /* Enable self-refresh mode and update semc clock root to 200MHz. */
58 SEMC->IPCMD = 0xA55A000D;
59 while ((SEMC->INTR & 0x3) == 0)
60 ;
61 SEMC->INTR = 0x3;
62 SEMC->DCCR = 0x0B;
63 /*
64 * Currently we are using SEMC parameter which fit both 166MHz and 200MHz, only
65 * need to change the SEMC clock root here. If customer is using their own DCD and
66 * want to switch from 166MHz to 200MHz, extra SEMC configuration might need to be
67 * adjusted here to fine tune the SDRAM performance
68 */
69 CCM->CLOCK_ROOT[kCLOCK_Root_Semc].CONTROL = 0x602;
70 }
71 #endif
72 #endif
73
74 /*******************************************************************************
75 ********************** Configuration BOARD_BootClockRUN ***********************
76 ******************************************************************************/
77 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
78 !!Configuration
79 name: BOARD_BootClockRUN
80 called_from_default_init: true
81 outputs:
82 - {id: ACMP_CLK_ROOT.outFreq, value: 24 MHz}
83 - {id: ADC1_CLK_ROOT.outFreq, value: 24 MHz}
84 - {id: ADC2_CLK_ROOT.outFreq, value: 24 MHz}
85 - {id: ARM_PLL_CLK.outFreq, value: 996 MHz}
86 - {id: ASRC_CLK_ROOT.outFreq, value: 24 MHz}
87 - {id: AXI_CLK_ROOT.outFreq, value: 996 MHz}
88 - {id: BUS_CLK_ROOT.outFreq, value: 240 MHz}
89 - {id: BUS_LPSR_CLK_ROOT.outFreq, value: 160 MHz}
90 - {id: CAN1_CLK_ROOT.outFreq, value: 24 MHz}
91 - {id: CAN2_CLK_ROOT.outFreq, value: 24 MHz}
92 - {id: CAN3_CLK_ROOT.outFreq, value: 24 MHz}
93 - {id: CCM_CLKO1_CLK_ROOT.outFreq, value: 24 MHz}
94 - {id: CCM_CLKO2_CLK_ROOT.outFreq, value: 24 MHz}
95 - {id: CLK_1M.outFreq, value: 1 MHz}
96 - {id: CSI2_CLK_ROOT.outFreq, value: 24 MHz}
97 - {id: CSI2_ESC_CLK_ROOT.outFreq, value: 24 MHz}
98 - {id: CSI2_UI_CLK_ROOT.outFreq, value: 24 MHz}
99 - {id: CSI_CLK_ROOT.outFreq, value: 24 MHz}
100 - {id: CSSYS_CLK_ROOT.outFreq, value: 24 MHz}
101 - {id: CSTRACE_CLK_ROOT.outFreq, value: 132 MHz}
102 - {id: ELCDIF_CLK_ROOT.outFreq, value: 24 MHz}
103 - {id: EMV1_CLK_ROOT.outFreq, value: 24 MHz}
104 - {id: EMV2_CLK_ROOT.outFreq, value: 24 MHz}
105 - {id: ENET1_CLK_ROOT.outFreq, value: 24 MHz}
106 - {id: ENET2_CLK_ROOT.outFreq, value: 24 MHz}
107 - {id: ENET_1G_TX_CLK.outFreq, value: 24 MHz}
108 - {id: ENET_25M_CLK_ROOT.outFreq, value: 24 MHz}
109 - {id: ENET_QOS_CLK_ROOT.outFreq, value: 24 MHz}
110 - {id: ENET_TIMER1_CLK_ROOT.outFreq, value: 24 MHz}
111 - {id: ENET_TIMER2_CLK_ROOT.outFreq, value: 24 MHz}
112 - {id: ENET_TIMER3_CLK_ROOT.outFreq, value: 24 MHz}
113 - {id: FLEXIO1_CLK_ROOT.outFreq, value: 24 MHz}
114 - {id: FLEXIO2_CLK_ROOT.outFreq, value: 24 MHz}
115 - {id: FLEXSPI1_CLK_ROOT.outFreq, value: 24 MHz}
116 - {id: FLEXSPI2_CLK_ROOT.outFreq, value: 24 MHz}
117 - {id: GC355_CLK_ROOT.outFreq, value: 492.0000125 MHz}
118 - {id: GPT1_CLK_ROOT.outFreq, value: 24 MHz}
119 - {id: GPT1_ipg_clk_highfreq.outFreq, value: 24 MHz}
120 - {id: GPT2_CLK_ROOT.outFreq, value: 24 MHz}
121 - {id: GPT2_ipg_clk_highfreq.outFreq, value: 24 MHz}
122 - {id: GPT3_CLK_ROOT.outFreq, value: 24 MHz}
123 - {id: GPT3_ipg_clk_highfreq.outFreq, value: 24 MHz}
124 - {id: GPT4_CLK_ROOT.outFreq, value: 24 MHz}
125 - {id: GPT4_ipg_clk_highfreq.outFreq, value: 24 MHz}
126 - {id: GPT5_CLK_ROOT.outFreq, value: 24 MHz}
127 - {id: GPT5_ipg_clk_highfreq.outFreq, value: 24 MHz}
128 - {id: GPT6_CLK_ROOT.outFreq, value: 24 MHz}
129 - {id: GPT6_ipg_clk_highfreq.outFreq, value: 24 MHz}
130 - {id: LCDIFV2_CLK_ROOT.outFreq, value: 24 MHz}
131 - {id: LPI2C1_CLK_ROOT.outFreq, value: 24 MHz}
132 - {id: LPI2C2_CLK_ROOT.outFreq, value: 24 MHz}
133 - {id: LPI2C3_CLK_ROOT.outFreq, value: 24 MHz}
134 - {id: LPI2C4_CLK_ROOT.outFreq, value: 24 MHz}
135 - {id: LPI2C5_CLK_ROOT.outFreq, value: 24 MHz}
136 - {id: LPI2C6_CLK_ROOT.outFreq, value: 24 MHz}
137 - {id: LPSPI1_CLK_ROOT.outFreq, value: 24 MHz}
138 - {id: LPSPI2_CLK_ROOT.outFreq, value: 24 MHz}
139 - {id: LPSPI3_CLK_ROOT.outFreq, value: 24 MHz}
140 - {id: LPSPI4_CLK_ROOT.outFreq, value: 24 MHz}
141 - {id: LPSPI5_CLK_ROOT.outFreq, value: 24 MHz}
142 - {id: LPSPI6_CLK_ROOT.outFreq, value: 24 MHz}
143 - {id: LPUART10_CLK_ROOT.outFreq, value: 24 MHz}
144 - {id: LPUART11_CLK_ROOT.outFreq, value: 24 MHz}
145 - {id: LPUART12_CLK_ROOT.outFreq, value: 24 MHz}
146 - {id: LPUART1_CLK_ROOT.outFreq, value: 24 MHz}
147 - {id: LPUART2_CLK_ROOT.outFreq, value: 24 MHz}
148 - {id: LPUART3_CLK_ROOT.outFreq, value: 24 MHz}
149 - {id: LPUART4_CLK_ROOT.outFreq, value: 24 MHz}
150 - {id: LPUART5_CLK_ROOT.outFreq, value: 24 MHz}
151 - {id: LPUART6_CLK_ROOT.outFreq, value: 24 MHz}
152 - {id: LPUART7_CLK_ROOT.outFreq, value: 24 MHz}
153 - {id: LPUART8_CLK_ROOT.outFreq, value: 24 MHz}
154 - {id: LPUART9_CLK_ROOT.outFreq, value: 24 MHz}
155 - {id: M4_CLK_ROOT.outFreq, value: 4320/11 MHz}
156 - {id: M4_SYSTICK_CLK_ROOT.outFreq, value: 24 MHz}
157 - {id: M7_CLK_ROOT.outFreq, value: 996 MHz}
158 - {id: M7_SYSTICK_CLK_ROOT.outFreq, value: 100 kHz}
159 - {id: MIC_CLK_ROOT.outFreq, value: 24 MHz}
160 - {id: MIPI_DSI_TX_CLK_ESC_ROOT.outFreq, value: 24 MHz}
161 - {id: MIPI_ESC_CLK_ROOT.outFreq, value: 24 MHz}
162 - {id: MIPI_REF_CLK_ROOT.outFreq, value: 24 MHz}
163 - {id: MQS_CLK_ROOT.outFreq, value: 24 MHz}
164 - {id: MQS_MCLK.outFreq, value: 24 MHz}
165 - {id: OSC_24M.outFreq, value: 24 MHz}
166 - {id: OSC_32K.outFreq, value: 32.768 kHz}
167 - {id: OSC_RC_16M.outFreq, value: 16 MHz}
168 - {id: OSC_RC_400M.outFreq, value: 400 MHz}
169 - {id: OSC_RC_48M.outFreq, value: 48 MHz}
170 - {id: OSC_RC_48M_DIV2.outFreq, value: 24 MHz}
171 - {id: PLL_VIDEO_CLK.outFreq, value: 984.000025 MHz}
172 - {id: SAI1_CLK_ROOT.outFreq, value: 24 MHz}
173 - {id: SAI1_MCLK1.outFreq, value: 24 MHz}
174 - {id: SAI1_MCLK3.outFreq, value: 24 MHz}
175 - {id: SAI2_CLK_ROOT.outFreq, value: 24 MHz}
176 - {id: SAI2_MCLK1.outFreq, value: 24 MHz}
177 - {id: SAI2_MCLK3.outFreq, value: 24 MHz}
178 - {id: SAI3_CLK_ROOT.outFreq, value: 24 MHz}
179 - {id: SAI3_MCLK1.outFreq, value: 24 MHz}
180 - {id: SAI3_MCLK3.outFreq, value: 24 MHz}
181 - {id: SAI4_CLK_ROOT.outFreq, value: 24 MHz}
182 - {id: SAI4_MCLK1.outFreq, value: 24 MHz}
183 - {id: SEMC_CLK_ROOT.outFreq, value: 198 MHz}
184 - {id: SPDIF_CLK_ROOT.outFreq, value: 24 MHz}
185 - {id: SYS_PLL2_CLK.outFreq, value: 528 MHz}
186 - {id: SYS_PLL2_PFD0_CLK.outFreq, value: 352 MHz}
187 - {id: SYS_PLL2_PFD1_CLK.outFreq, value: 594 MHz}
188 - {id: SYS_PLL2_PFD2_CLK.outFreq, value: 396 MHz}
189 - {id: SYS_PLL2_PFD3_CLK.outFreq, value: 297 MHz}
190 - {id: SYS_PLL3_CLK.outFreq, value: 480 MHz}
191 - {id: SYS_PLL3_DIV2_CLK.outFreq, value: 240 MHz}
192 - {id: SYS_PLL3_PFD0_CLK.outFreq, value: 8640/13 MHz}
193 - {id: SYS_PLL3_PFD1_CLK.outFreq, value: 8640/17 MHz}
194 - {id: SYS_PLL3_PFD2_CLK.outFreq, value: 270 MHz}
195 - {id: SYS_PLL3_PFD3_CLK.outFreq, value: 4320/11 MHz}
196 - {id: USDHC1_CLK_ROOT.outFreq, value: 24 MHz}
197 - {id: USDHC2_CLK_ROOT.outFreq, value: 24 MHz}
198 settings:
199 - {id: CoreBusClockRootsInitializationConfig, value: selectedCore}
200 - {id: SOCDomainVoltage, value: OD}
201 - {id: ANADIG_OSC_OSC_24M_CTRL_LP_EN_CFG, value: Low}
202 - {id: ANADIG_OSC_OSC_24M_CTRL_OSC_EN_CFG, value: Enabled}
203 - {id: ANADIG_PLL.PLL_AUDIO_BYPASS.sel, value: ANADIG_OSC.OSC_24M}
204 - {id: ANADIG_PLL.PLL_VIDEO.denom, value: '960000'}
205 - {id: ANADIG_PLL.PLL_VIDEO.div, value: '41'}
206 - {id: ANADIG_PLL.PLL_VIDEO.num, value: '1'}
207 - {id: ANADIG_PLL.SYS_PLL1_BYPASS.sel, value: ANADIG_OSC.OSC_24M}
208 - {id: ANADIG_PLL.SYS_PLL2.denom, value: '268435455'}
209 - {id: ANADIG_PLL.SYS_PLL2.div, value: '22'}
210 - {id: ANADIG_PLL.SYS_PLL2.num, value: '0'}
211 - {id: ANADIG_PLL.SYS_PLL2_SS_DIV.scale, value: '268435455'}
212 - {id: ANADIG_PLL.SYS_PLL3_PFD3_DIV.scale, value: '22', locked: true}
213 - {id: ANADIG_PLL.SYS_PLL3_PFD3_MUL.scale, value: '18', locked: true}
214 - {id: ANADIG_PLL_ARM_PLL_CTRL_POWERUP_CFG, value: Enabled}
215 - {id: ANADIG_PLL_PLL_AUDIO_CTRL_GATE_CFG, value: Disabled}
216 - {id: ANADIG_PLL_PLL_VIDEO_CTRL0_POWERUP_CFG, value: Enabled}
217 - {id: ANADIG_PLL_SYS_PLL1_CTRL0_POWERUP_CFG, value: Disabled}
218 - {id: ANADIG_PLL_SYS_PLL1_CTRL_GATE_CFG, value: Disabled}
219 - {id: ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_CFG, value: Enabled}
220 - {id: ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_CFG, value: Enabled}
221 - {id: ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CFG, value: Enabled}
222 - {id: CCM.CLOCK_ROOT0.MUX.sel, value: ANADIG_PLL.ARM_PLL_CLK}
223 - {id: CCM.CLOCK_ROOT1.MUX.sel, value: ANADIG_PLL.SYS_PLL3_PFD3_CLK}
224 - {id: CCM.CLOCK_ROOT2.DIV.scale, value: '2'}
225 - {id: CCM.CLOCK_ROOT2.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK}
226 - {id: CCM.CLOCK_ROOT25.DIV.scale, value: '22'}
227 - {id: CCM.CLOCK_ROOT25.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK}
228 - {id: CCM.CLOCK_ROOT26.DIV.scale, value: '22'}
229 - {id: CCM.CLOCK_ROOT26.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK}
230 - {id: CCM.CLOCK_ROOT3.DIV.scale, value: '3'}
231 - {id: CCM.CLOCK_ROOT3.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK}
232 - {id: CCM.CLOCK_ROOT4.DIV.scale, value: '3'}
233 - {id: CCM.CLOCK_ROOT4.MUX.sel, value: ANADIG_PLL.SYS_PLL2_PFD1_CLK}
234 - {id: CCM.CLOCK_ROOT6.DIV.scale, value: '4'}
235 - {id: CCM.CLOCK_ROOT6.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK}
236 - {id: CCM.CLOCK_ROOT68.DIV.scale, value: '2'}
237 - {id: CCM.CLOCK_ROOT68.MUX.sel, value: ANADIG_PLL.PLL_VIDEO_CLK}
238 - {id: CCM.CLOCK_ROOT8.DIV.scale, value: '240'}
239 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
240
241 /*******************************************************************************
242 * Variables for BOARD_BootClockRUN configuration
243 ******************************************************************************/
244
245 #ifndef SKIP_POWER_ADJUSTMENT
246 #if __CORTEX_M == 7
247 #define BYPASS_LDO_LPSR 1
248 #define SKIP_LDO_ADJUSTMENT 1
249 #elif __CORTEX_M == 4
250 #define SKIP_DCDC_ADJUSTMENT 1
251 #define SKIP_FBB_ENABLE 1
252 #endif
253 #endif
254
255 const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN =
256 {
257 .postDivider = kCLOCK_PllPostDiv2, /* Post divider, 0 - DIV by 2, 1 - DIV by 4, 2 - DIV by 8, 3 - DIV by 1 */
258 .loopDivider = 166, /* PLL Loop divider, Fout = Fin * ( loopDivider / ( 2 * postDivider ) ) */
259 };
260
261 const clock_sys_pll2_config_t sysPll2Config_BOARD_BootClockRUN =
262 {
263 .mfd = 268435455, /* Denominator of spread spectrum */
264 .ss = NULL, /* Spread spectrum parameter */
265 .ssEnable = false, /* Enable spread spectrum or not */
266 };
267
268 const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN =
269 {
270 .loopDivider = 41, /* PLL Loop divider, valid range for DIV_SELECT divider value: 27 ~ 54. */
271 .postDivider = 0, /* Divider after PLL, should only be 1, 2, 4, 8, 16, 32 */
272 .numerator = 1, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
273 .denominator = 960000, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
274 .ss = NULL, /* Spread spectrum parameter */
275 .ssEnable = false, /* Enable spread spectrum or not */
276 };
277
278 /*******************************************************************************
279 * Code for BOARD_BootClockRUN configuration
280 ******************************************************************************/
BOARD_BootClockRUN(void)281 void BOARD_BootClockRUN(void)
282 {
283 clock_root_config_t rootCfg = {0};
284
285 /* Set DCDC to DCM mode to improve the efficiency for light loading in run mode and transient performance with a big loading step. */
286 DCDC_BootIntoDCM(DCDC);
287
288 #if !defined(SKIP_DCDC_ADJUSTMENT) || (!SKIP_DCDC_ADJUSTMENT)
289 if((OCOTP->FUSEN[16].FUSE == 0x57AC5969U) && ((OCOTP->FUSEN[17].FUSE & 0xFFU) == 0x0BU))
290 {
291 DCDC_SetVDD1P0BuckModeTargetVoltage(DCDC, kDCDC_1P0BuckTarget1P15V);
292 }
293 else
294 {
295 /* Set 1.125V for production samples to align with data sheet requirement */
296 DCDC_SetVDD1P0BuckModeTargetVoltage(DCDC, kDCDC_1P0BuckTarget1P125V);
297 }
298 #endif
299
300 #if !defined(SKIP_FBB_ENABLE) || (!SKIP_FBB_ENABLE)
301 /* Check if FBB need to be enabled in OverDrive(OD) mode */
302 if(((OCOTP->FUSEN[7].FUSE & 0x10U) >> 4U) != 1)
303 {
304 PMU_EnableBodyBias(ANADIG_PMU, kPMU_FBB_CM7, true);
305 }
306 else
307 {
308 PMU_EnableBodyBias(ANADIG_PMU, kPMU_FBB_CM7, false);
309 }
310 #endif
311
312 #if defined(BYPASS_LDO_LPSR) && BYPASS_LDO_LPSR
313 PMU_StaticEnableLpsrAnaLdoBypassMode(ANADIG_LDO_SNVS, true);
314 PMU_StaticEnableLpsrDigLdoBypassMode(ANADIG_LDO_SNVS, true);
315 #endif
316
317 #if !defined(SKIP_LDO_ADJUSTMENT) || (!SKIP_LDO_ADJUSTMENT)
318 pmu_static_lpsr_ana_ldo_config_t lpsrAnaConfig;
319 pmu_static_lpsr_dig_config_t lpsrDigConfig;
320
321 if((ANADIG_LDO_SNVS->PMU_LDO_LPSR_ANA & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_MASK) == 0UL)
322 {
323 PMU_StaticGetLpsrAnaLdoDefaultConfig(&lpsrAnaConfig);
324 PMU_StaticLpsrAnaLdoInit(ANADIG_LDO_SNVS, &lpsrAnaConfig);
325 }
326
327 if((ANADIG_LDO_SNVS->PMU_LDO_LPSR_DIG & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_MASK) == 0UL)
328 {
329 PMU_StaticGetLpsrDigLdoDefaultConfig(&lpsrDigConfig);
330 lpsrDigConfig.targetVoltage = kPMU_LpsrDigTargetStableVoltage1P117V;
331 PMU_StaticLpsrDigLdoInit(ANADIG_LDO_SNVS, &lpsrDigConfig);
332 }
333 #endif
334
335 /* Config CLK_1M */
336 CLOCK_OSC_Set1MHzOutputBehavior(kCLOCK_1MHzOutEnableFreeRunning1Mhz);
337
338 /* Init OSC RC 16M */
339 ANADIG_OSC->OSC_16M_CTRL |= ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_MASK;
340
341 /* Init OSC RC 400M */
342 CLOCK_OSC_EnableOscRc400M();
343 CLOCK_OSC_GateOscRc400M(true);
344
345 /* Init OSC RC 48M */
346 CLOCK_OSC_EnableOsc48M(true);
347 CLOCK_OSC_EnableOsc48MDiv2(true);
348
349 /* Config OSC 24M */
350 ANADIG_OSC->OSC_24M_CTRL |= ANADIG_OSC_OSC_24M_CTRL_OSC_EN(1) | ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN(0) | ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK(0) | ANADIG_OSC_OSC_24M_CTRL_LP_EN(1) | ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE(0);
351 /* Wait for 24M OSC to be stable. */
352 while (ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK !=
353 (ANADIG_OSC->OSC_24M_CTRL & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK))
354 {
355 }
356
357 /* Swicth both core, M7 Systick and Bus_Lpsr to OscRC48MDiv2 first */
358 #if __CORTEX_M == 7
359 rootCfg.mux = kCLOCK_M7_ClockRoot_MuxOscRc48MDiv2;
360 rootCfg.div = 1;
361 CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg);
362
363 rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc48MDiv2;
364 rootCfg.div = 1;
365 CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg);
366 #endif
367
368 #if __CORTEX_M == 4
369 rootCfg.mux = kCLOCK_M4_ClockRoot_MuxOscRc48MDiv2;
370 rootCfg.div = 1;
371 CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg);
372
373 rootCfg.mux = kCLOCK_BUS_LPSR_ClockRoot_MuxOscRc48MDiv2;
374 rootCfg.div = 1;
375 CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg);
376 #endif
377
378 /*
379 * if DCD is used, please make sure the clock source of SEMC is not changed in the following PLL/PFD configuration code.
380 */
381 /* Init Arm Pll. */
382 CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
383
384 /* Bypass Sys Pll1. */
385 CLOCK_SetPllBypass(kCLOCK_PllSys1, true);
386
387 /* DeInit Sys Pll1. */
388 CLOCK_DeinitSysPll1();
389
390 /* Init Sys Pll2. */
391 CLOCK_InitSysPll2(&sysPll2Config_BOARD_BootClockRUN);
392
393 /* Init System Pll2 pfd0. */
394 CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd0, 27);
395
396 /* Init System Pll2 pfd1. */
397 CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd1, 16);
398
399 /* Init System Pll2 pfd2. */
400 CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd2, 24);
401
402 /* Init System Pll2 pfd3. */
403 CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd3, 32);
404
405 /* Init Sys Pll3. */
406 CLOCK_InitSysPll3();
407
408 /* Init System Pll3 pfd0. */
409 CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd0, 13);
410
411 /* Init System Pll3 pfd1. */
412 CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd1, 17);
413
414 /* Init System Pll3 pfd2. */
415 CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd2, 32);
416
417 /* Init System Pll3 pfd3. */
418 CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd3, 22);
419
420 /* Bypass Audio Pll. */
421 CLOCK_SetPllBypass(kCLOCK_PllAudio, true);
422
423 /* DeInit Audio Pll. */
424 CLOCK_DeinitAudioPll();
425
426 /* Init Video Pll. */
427 CLOCK_InitVideoPll(&videoPllConfig_BOARD_BootClockRUN);
428
429 /* Module clock root configurations. */
430 /* Configure M7 using ARM_PLL_CLK */
431 #if __CORTEX_M == 7
432 rootCfg.mux = kCLOCK_M7_ClockRoot_MuxArmPllOut;
433 rootCfg.div = 1;
434 CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg);
435 #endif
436
437 /* Configure M4 using SYS_PLL3_PFD3_CLK */
438 #if __CORTEX_M == 4
439 rootCfg.mux = kCLOCK_M4_ClockRoot_MuxSysPll3Pfd3;
440 rootCfg.div = 1;
441 CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg);
442 #endif
443
444 /* Configure BUS using SYS_PLL3_CLK */
445 rootCfg.mux = kCLOCK_BUS_ClockRoot_MuxSysPll3Out;
446 rootCfg.div = 2;
447 CLOCK_SetRootClock(kCLOCK_Root_Bus, &rootCfg);
448
449 /* Configure BUS_LPSR using SYS_PLL3_CLK */
450 rootCfg.mux = kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll3Out;
451 rootCfg.div = 3;
452 CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg);
453
454 /* Configure SEMC using SYS_PLL2_PFD1_CLK */
455 #ifndef SKIP_SEMC_INIT
456 rootCfg.mux = kCLOCK_SEMC_ClockRoot_MuxSysPll2Pfd1;
457 rootCfg.div = 3;
458 CLOCK_SetRootClock(kCLOCK_Root_Semc, &rootCfg);
459 #endif
460
461 #if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
462 #if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
463 UpdateSemcClock();
464 #endif
465 #endif
466
467 /* Configure CSSYS using OSC_RC_48M_DIV2 */
468 rootCfg.mux = kCLOCK_CSSYS_ClockRoot_MuxOscRc48MDiv2;
469 rootCfg.div = 1;
470 CLOCK_SetRootClock(kCLOCK_Root_Cssys, &rootCfg);
471
472 /* Configure CSTRACE using SYS_PLL2_CLK */
473 rootCfg.mux = kCLOCK_CSTRACE_ClockRoot_MuxSysPll2Out;
474 rootCfg.div = 4;
475 CLOCK_SetRootClock(kCLOCK_Root_Cstrace, &rootCfg);
476
477 /* Configure M4_SYSTICK using OSC_RC_48M_DIV2 */
478 #if __CORTEX_M == 4
479 rootCfg.mux = kCLOCK_M4_SYSTICK_ClockRoot_MuxOscRc48MDiv2;
480 rootCfg.div = 1;
481 CLOCK_SetRootClock(kCLOCK_Root_M4_Systick, &rootCfg);
482 #endif
483
484 /* Configure M7_SYSTICK using OSC_RC_48M_DIV2 */
485 #if __CORTEX_M == 7
486 rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc48MDiv2;
487 rootCfg.div = 240;
488 CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg);
489 #endif
490
491 /* Configure ADC1 using OSC_RC_48M_DIV2 */
492 rootCfg.mux = kCLOCK_ADC1_ClockRoot_MuxOscRc48MDiv2;
493 rootCfg.div = 1;
494 CLOCK_SetRootClock(kCLOCK_Root_Adc1, &rootCfg);
495
496 /* Configure ADC2 using OSC_RC_48M_DIV2 */
497 rootCfg.mux = kCLOCK_ADC2_ClockRoot_MuxOscRc48MDiv2;
498 rootCfg.div = 1;
499 CLOCK_SetRootClock(kCLOCK_Root_Adc2, &rootCfg);
500
501 /* Configure ACMP using OSC_RC_48M_DIV2 */
502 rootCfg.mux = kCLOCK_ACMP_ClockRoot_MuxOscRc48MDiv2;
503 rootCfg.div = 1;
504 CLOCK_SetRootClock(kCLOCK_Root_Acmp, &rootCfg);
505
506 /* Configure FLEXIO1 using OSC_RC_48M_DIV2 */
507 rootCfg.mux = kCLOCK_FLEXIO1_ClockRoot_MuxOscRc48MDiv2;
508 rootCfg.div = 1;
509 CLOCK_SetRootClock(kCLOCK_Root_Flexio1, &rootCfg);
510
511 /* Configure FLEXIO2 using OSC_RC_48M_DIV2 */
512 rootCfg.mux = kCLOCK_FLEXIO2_ClockRoot_MuxOscRc48MDiv2;
513 rootCfg.div = 1;
514 CLOCK_SetRootClock(kCLOCK_Root_Flexio2, &rootCfg);
515
516 /* Configure GPT1 using OSC_RC_48M_DIV2 */
517 rootCfg.mux = kCLOCK_GPT1_ClockRoot_MuxOscRc48MDiv2;
518 rootCfg.div = 1;
519 CLOCK_SetRootClock(kCLOCK_Root_Gpt1, &rootCfg);
520
521 /* Configure GPT2 using OSC_RC_48M_DIV2 */
522 rootCfg.mux = kCLOCK_GPT2_ClockRoot_MuxOscRc48MDiv2;
523 rootCfg.div = 1;
524 CLOCK_SetRootClock(kCLOCK_Root_Gpt2, &rootCfg);
525
526 /* Configure GPT3 using OSC_RC_48M_DIV2 */
527 rootCfg.mux = kCLOCK_GPT3_ClockRoot_MuxOscRc48MDiv2;
528 rootCfg.div = 1;
529 CLOCK_SetRootClock(kCLOCK_Root_Gpt3, &rootCfg);
530
531 /* Configure GPT4 using OSC_RC_48M_DIV2 */
532 rootCfg.mux = kCLOCK_GPT4_ClockRoot_MuxOscRc48MDiv2;
533 rootCfg.div = 1;
534 CLOCK_SetRootClock(kCLOCK_Root_Gpt4, &rootCfg);
535
536 /* Configure GPT5 using OSC_RC_48M_DIV2 */
537 rootCfg.mux = kCLOCK_GPT5_ClockRoot_MuxOscRc48MDiv2;
538 rootCfg.div = 1;
539 CLOCK_SetRootClock(kCLOCK_Root_Gpt5, &rootCfg);
540
541 /* Configure GPT6 using OSC_RC_48M_DIV2 */
542 rootCfg.mux = kCLOCK_GPT6_ClockRoot_MuxOscRc48MDiv2;
543 rootCfg.div = 1;
544 CLOCK_SetRootClock(kCLOCK_Root_Gpt6, &rootCfg);
545
546 /* Configure FLEXSPI1 using OSC_RC_48M_DIV2 */
547 #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1) || defined(FLEXSPI_IN_USE))
548 rootCfg.mux = kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc48MDiv2;
549 rootCfg.div = 1;
550 CLOCK_SetRootClock(kCLOCK_Root_Flexspi1, &rootCfg);
551 #endif
552
553 /* Configure FLEXSPI2 using OSC_RC_48M_DIV2 */
554 rootCfg.mux = kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc48MDiv2;
555 rootCfg.div = 1;
556 CLOCK_SetRootClock(kCLOCK_Root_Flexspi2, &rootCfg);
557
558 /* Configure CAN1 using OSC_RC_48M_DIV2 */
559 rootCfg.mux = kCLOCK_CAN1_ClockRoot_MuxOscRc48MDiv2;
560 rootCfg.div = 1;
561 CLOCK_SetRootClock(kCLOCK_Root_Can1, &rootCfg);
562
563 /* Configure CAN2 using OSC_RC_48M_DIV2 */
564 rootCfg.mux = kCLOCK_CAN2_ClockRoot_MuxOscRc48MDiv2;
565 rootCfg.div = 1;
566 CLOCK_SetRootClock(kCLOCK_Root_Can2, &rootCfg);
567
568 /* Configure CAN3 using OSC_RC_48M_DIV2 */
569 rootCfg.mux = kCLOCK_CAN3_ClockRoot_MuxOscRc48MDiv2;
570 rootCfg.div = 1;
571 CLOCK_SetRootClock(kCLOCK_Root_Can3, &rootCfg);
572
573 /* Configure LPUART1 using SYS_PLL2_CLK */
574 rootCfg.mux = kCLOCK_LPUART1_ClockRoot_MuxSysPll2Out;
575 rootCfg.div = 22;
576 CLOCK_SetRootClock(kCLOCK_Root_Lpuart1, &rootCfg);
577
578 /* Configure LPUART2 using SYS_PLL2_CLK */
579 rootCfg.mux = kCLOCK_LPUART2_ClockRoot_MuxSysPll2Out;
580 rootCfg.div = 22;
581 CLOCK_SetRootClock(kCLOCK_Root_Lpuart2, &rootCfg);
582
583 /* Configure LPUART3 using OSC_RC_48M_DIV2 */
584 rootCfg.mux = kCLOCK_LPUART3_ClockRoot_MuxOscRc48MDiv2;
585 rootCfg.div = 1;
586 CLOCK_SetRootClock(kCLOCK_Root_Lpuart3, &rootCfg);
587
588 /* Configure LPUART4 using OSC_RC_48M_DIV2 */
589 rootCfg.mux = kCLOCK_LPUART4_ClockRoot_MuxOscRc48MDiv2;
590 rootCfg.div = 1;
591 CLOCK_SetRootClock(kCLOCK_Root_Lpuart4, &rootCfg);
592
593 /* Configure LPUART5 using OSC_RC_48M_DIV2 */
594 rootCfg.mux = kCLOCK_LPUART5_ClockRoot_MuxOscRc48MDiv2;
595 rootCfg.div = 1;
596 CLOCK_SetRootClock(kCLOCK_Root_Lpuart5, &rootCfg);
597
598 /* Configure LPUART6 using OSC_RC_48M_DIV2 */
599 rootCfg.mux = kCLOCK_LPUART6_ClockRoot_MuxOscRc48MDiv2;
600 rootCfg.div = 1;
601 CLOCK_SetRootClock(kCLOCK_Root_Lpuart6, &rootCfg);
602
603 /* Configure LPUART7 using OSC_RC_48M_DIV2 */
604 rootCfg.mux = kCLOCK_LPUART7_ClockRoot_MuxOscRc48MDiv2;
605 rootCfg.div = 1;
606 CLOCK_SetRootClock(kCLOCK_Root_Lpuart7, &rootCfg);
607
608 /* Configure LPUART8 using OSC_RC_48M_DIV2 */
609 rootCfg.mux = kCLOCK_LPUART8_ClockRoot_MuxOscRc48MDiv2;
610 rootCfg.div = 1;
611 CLOCK_SetRootClock(kCLOCK_Root_Lpuart8, &rootCfg);
612
613 /* Configure LPUART9 using OSC_RC_48M_DIV2 */
614 rootCfg.mux = kCLOCK_LPUART9_ClockRoot_MuxOscRc48MDiv2;
615 rootCfg.div = 1;
616 CLOCK_SetRootClock(kCLOCK_Root_Lpuart9, &rootCfg);
617
618 /* Configure LPUART10 using OSC_RC_48M_DIV2 */
619 rootCfg.mux = kCLOCK_LPUART10_ClockRoot_MuxOscRc48MDiv2;
620 rootCfg.div = 1;
621 CLOCK_SetRootClock(kCLOCK_Root_Lpuart10, &rootCfg);
622
623 /* Configure LPUART11 using OSC_RC_48M_DIV2 */
624 rootCfg.mux = kCLOCK_LPUART11_ClockRoot_MuxOscRc48MDiv2;
625 rootCfg.div = 1;
626 CLOCK_SetRootClock(kCLOCK_Root_Lpuart11, &rootCfg);
627
628 /* Configure LPUART12 using OSC_RC_48M_DIV2 */
629 rootCfg.mux = kCLOCK_LPUART12_ClockRoot_MuxOscRc48MDiv2;
630 rootCfg.div = 1;
631 CLOCK_SetRootClock(kCLOCK_Root_Lpuart12, &rootCfg);
632
633 /* Configure LPI2C1 using OSC_RC_48M_DIV2 */
634 rootCfg.mux = kCLOCK_LPI2C1_ClockRoot_MuxOscRc48MDiv2;
635 rootCfg.div = 1;
636 CLOCK_SetRootClock(kCLOCK_Root_Lpi2c1, &rootCfg);
637
638 /* Configure LPI2C2 using OSC_RC_48M_DIV2 */
639 rootCfg.mux = kCLOCK_LPI2C2_ClockRoot_MuxOscRc48MDiv2;
640 rootCfg.div = 1;
641 CLOCK_SetRootClock(kCLOCK_Root_Lpi2c2, &rootCfg);
642
643 /* Configure LPI2C3 using OSC_RC_48M_DIV2 */
644 rootCfg.mux = kCLOCK_LPI2C3_ClockRoot_MuxOscRc48MDiv2;
645 rootCfg.div = 1;
646 CLOCK_SetRootClock(kCLOCK_Root_Lpi2c3, &rootCfg);
647
648 /* Configure LPI2C4 using OSC_RC_48M_DIV2 */
649 rootCfg.mux = kCLOCK_LPI2C4_ClockRoot_MuxOscRc48MDiv2;
650 rootCfg.div = 1;
651 CLOCK_SetRootClock(kCLOCK_Root_Lpi2c4, &rootCfg);
652
653 /* Configure LPI2C5 using OSC_RC_48M_DIV2 */
654 rootCfg.mux = kCLOCK_LPI2C5_ClockRoot_MuxOscRc48MDiv2;
655 rootCfg.div = 1;
656 CLOCK_SetRootClock(kCLOCK_Root_Lpi2c5, &rootCfg);
657
658 /* Configure LPI2C6 using OSC_RC_48M_DIV2 */
659 rootCfg.mux = kCLOCK_LPI2C6_ClockRoot_MuxOscRc48MDiv2;
660 rootCfg.div = 1;
661 CLOCK_SetRootClock(kCLOCK_Root_Lpi2c6, &rootCfg);
662
663 /* Configure LPSPI1 using OSC_RC_48M_DIV2 */
664 rootCfg.mux = kCLOCK_LPSPI1_ClockRoot_MuxOscRc48MDiv2;
665 rootCfg.div = 1;
666 CLOCK_SetRootClock(kCLOCK_Root_Lpspi1, &rootCfg);
667
668 /* Configure LPSPI2 using OSC_RC_48M_DIV2 */
669 rootCfg.mux = kCLOCK_LPSPI2_ClockRoot_MuxOscRc48MDiv2;
670 rootCfg.div = 1;
671 CLOCK_SetRootClock(kCLOCK_Root_Lpspi2, &rootCfg);
672
673 /* Configure LPSPI3 using OSC_RC_48M_DIV2 */
674 rootCfg.mux = kCLOCK_LPSPI3_ClockRoot_MuxOscRc48MDiv2;
675 rootCfg.div = 1;
676 CLOCK_SetRootClock(kCLOCK_Root_Lpspi3, &rootCfg);
677
678 /* Configure LPSPI4 using OSC_RC_48M_DIV2 */
679 rootCfg.mux = kCLOCK_LPSPI4_ClockRoot_MuxOscRc48MDiv2;
680 rootCfg.div = 1;
681 CLOCK_SetRootClock(kCLOCK_Root_Lpspi4, &rootCfg);
682
683 /* Configure LPSPI5 using OSC_RC_48M_DIV2 */
684 rootCfg.mux = kCLOCK_LPSPI5_ClockRoot_MuxOscRc48MDiv2;
685 rootCfg.div = 1;
686 CLOCK_SetRootClock(kCLOCK_Root_Lpspi5, &rootCfg);
687
688 /* Configure LPSPI6 using OSC_RC_48M_DIV2 */
689 rootCfg.mux = kCLOCK_LPSPI6_ClockRoot_MuxOscRc48MDiv2;
690 rootCfg.div = 1;
691 CLOCK_SetRootClock(kCLOCK_Root_Lpspi6, &rootCfg);
692
693 /* Configure EMV1 using OSC_RC_48M_DIV2 */
694 rootCfg.mux = kCLOCK_EMV1_ClockRoot_MuxOscRc48MDiv2;
695 rootCfg.div = 1;
696 CLOCK_SetRootClock(kCLOCK_Root_Emv1, &rootCfg);
697
698 /* Configure EMV2 using OSC_RC_48M_DIV2 */
699 rootCfg.mux = kCLOCK_EMV2_ClockRoot_MuxOscRc48MDiv2;
700 rootCfg.div = 1;
701 CLOCK_SetRootClock(kCLOCK_Root_Emv2, &rootCfg);
702
703 /* Configure ENET1 using OSC_RC_48M_DIV2 */
704 rootCfg.mux = kCLOCK_ENET1_ClockRoot_MuxOscRc48MDiv2;
705 rootCfg.div = 1;
706 CLOCK_SetRootClock(kCLOCK_Root_Enet1, &rootCfg);
707
708 /* Configure ENET2 using OSC_RC_48M_DIV2 */
709 rootCfg.mux = kCLOCK_ENET2_ClockRoot_MuxOscRc48MDiv2;
710 rootCfg.div = 1;
711 CLOCK_SetRootClock(kCLOCK_Root_Enet2, &rootCfg);
712
713 /* Configure ENET_QOS using OSC_RC_48M_DIV2 */
714 rootCfg.mux = kCLOCK_ENET_QOS_ClockRoot_MuxOscRc48MDiv2;
715 rootCfg.div = 1;
716 CLOCK_SetRootClock(kCLOCK_Root_Enet_Qos, &rootCfg);
717
718 /* Configure ENET_25M using OSC_RC_48M_DIV2 */
719 rootCfg.mux = kCLOCK_ENET_25M_ClockRoot_MuxOscRc48MDiv2;
720 rootCfg.div = 1;
721 CLOCK_SetRootClock(kCLOCK_Root_Enet_25m, &rootCfg);
722
723 /* Configure ENET_TIMER1 using OSC_RC_48M_DIV2 */
724 rootCfg.mux = kCLOCK_ENET_TIMER1_ClockRoot_MuxOscRc48MDiv2;
725 rootCfg.div = 1;
726 CLOCK_SetRootClock(kCLOCK_Root_Enet_Timer1, &rootCfg);
727
728 /* Configure ENET_TIMER2 using OSC_RC_48M_DIV2 */
729 rootCfg.mux = kCLOCK_ENET_TIMER2_ClockRoot_MuxOscRc48MDiv2;
730 rootCfg.div = 1;
731 CLOCK_SetRootClock(kCLOCK_Root_Enet_Timer2, &rootCfg);
732
733 /* Configure ENET_TIMER3 using OSC_RC_48M_DIV2 */
734 rootCfg.mux = kCLOCK_ENET_TIMER3_ClockRoot_MuxOscRc48MDiv2;
735 rootCfg.div = 1;
736 CLOCK_SetRootClock(kCLOCK_Root_Enet_Timer3, &rootCfg);
737
738 /* Configure USDHC1 using OSC_RC_48M_DIV2 */
739 rootCfg.mux = kCLOCK_USDHC1_ClockRoot_MuxOscRc48MDiv2;
740 rootCfg.div = 1;
741 CLOCK_SetRootClock(kCLOCK_Root_Usdhc1, &rootCfg);
742
743 /* Configure USDHC2 using OSC_RC_48M_DIV2 */
744 rootCfg.mux = kCLOCK_USDHC2_ClockRoot_MuxOscRc48MDiv2;
745 rootCfg.div = 1;
746 CLOCK_SetRootClock(kCLOCK_Root_Usdhc2, &rootCfg);
747
748 /* Configure ASRC using OSC_RC_48M_DIV2 */
749 rootCfg.mux = kCLOCK_ASRC_ClockRoot_MuxOscRc48MDiv2;
750 rootCfg.div = 1;
751 CLOCK_SetRootClock(kCLOCK_Root_Asrc, &rootCfg);
752
753 /* Configure MQS using OSC_RC_48M_DIV2 */
754 rootCfg.mux = kCLOCK_MQS_ClockRoot_MuxOscRc48MDiv2;
755 rootCfg.div = 1;
756 CLOCK_SetRootClock(kCLOCK_Root_Mqs, &rootCfg);
757
758 /* Configure MIC using OSC_RC_48M_DIV2 */
759 rootCfg.mux = kCLOCK_MIC_ClockRoot_MuxOscRc48MDiv2;
760 rootCfg.div = 1;
761 CLOCK_SetRootClock(kCLOCK_Root_Mic, &rootCfg);
762
763 /* Configure SPDIF using OSC_RC_48M_DIV2 */
764 rootCfg.mux = kCLOCK_SPDIF_ClockRoot_MuxOscRc48MDiv2;
765 rootCfg.div = 1;
766 CLOCK_SetRootClock(kCLOCK_Root_Spdif, &rootCfg);
767
768 /* Configure SAI1 using OSC_RC_48M_DIV2 */
769 rootCfg.mux = kCLOCK_SAI1_ClockRoot_MuxOscRc48MDiv2;
770 rootCfg.div = 1;
771 CLOCK_SetRootClock(kCLOCK_Root_Sai1, &rootCfg);
772
773 /* Configure SAI2 using OSC_RC_48M_DIV2 */
774 rootCfg.mux = kCLOCK_SAI2_ClockRoot_MuxOscRc48MDiv2;
775 rootCfg.div = 1;
776 CLOCK_SetRootClock(kCLOCK_Root_Sai2, &rootCfg);
777
778 /* Configure SAI3 using OSC_RC_48M_DIV2 */
779 rootCfg.mux = kCLOCK_SAI3_ClockRoot_MuxOscRc48MDiv2;
780 rootCfg.div = 1;
781 CLOCK_SetRootClock(kCLOCK_Root_Sai3, &rootCfg);
782
783 /* Configure SAI4 using OSC_RC_48M_DIV2 */
784 rootCfg.mux = kCLOCK_SAI4_ClockRoot_MuxOscRc48MDiv2;
785 rootCfg.div = 1;
786 CLOCK_SetRootClock(kCLOCK_Root_Sai4, &rootCfg);
787
788 /* Configure GC355 using PLL_VIDEO_CLK */
789 rootCfg.mux = kCLOCK_GC355_ClockRoot_MuxVideoPllOut;
790 rootCfg.div = 2;
791 CLOCK_SetRootClock(kCLOCK_Root_Gc355, &rootCfg);
792
793 /* Configure LCDIF using OSC_RC_48M_DIV2 */
794 rootCfg.mux = kCLOCK_LCDIF_ClockRoot_MuxOscRc48MDiv2;
795 rootCfg.div = 1;
796 CLOCK_SetRootClock(kCLOCK_Root_Lcdif, &rootCfg);
797
798 /* Configure LCDIFV2 using OSC_RC_48M_DIV2 */
799 rootCfg.mux = kCLOCK_LCDIFV2_ClockRoot_MuxOscRc48MDiv2;
800 rootCfg.div = 1;
801 CLOCK_SetRootClock(kCLOCK_Root_Lcdifv2, &rootCfg);
802
803 /* Configure MIPI_REF using OSC_RC_48M_DIV2 */
804 rootCfg.mux = kCLOCK_MIPI_REF_ClockRoot_MuxOscRc48MDiv2;
805 rootCfg.div = 1;
806 CLOCK_SetRootClock(kCLOCK_Root_Mipi_Ref, &rootCfg);
807
808 /* Configure MIPI_ESC using OSC_RC_48M_DIV2 */
809 rootCfg.mux = kCLOCK_MIPI_ESC_ClockRoot_MuxOscRc48MDiv2;
810 rootCfg.div = 1;
811 CLOCK_SetRootClock(kCLOCK_Root_Mipi_Esc, &rootCfg);
812
813 /* Configure CSI2 using OSC_RC_48M_DIV2 */
814 rootCfg.mux = kCLOCK_CSI2_ClockRoot_MuxOscRc48MDiv2;
815 rootCfg.div = 1;
816 CLOCK_SetRootClock(kCLOCK_Root_Csi2, &rootCfg);
817
818 /* Configure CSI2_ESC using OSC_RC_48M_DIV2 */
819 rootCfg.mux = kCLOCK_CSI2_ESC_ClockRoot_MuxOscRc48MDiv2;
820 rootCfg.div = 1;
821 CLOCK_SetRootClock(kCLOCK_Root_Csi2_Esc, &rootCfg);
822
823 /* Configure CSI2_UI using OSC_RC_48M_DIV2 */
824 rootCfg.mux = kCLOCK_CSI2_UI_ClockRoot_MuxOscRc48MDiv2;
825 rootCfg.div = 1;
826 CLOCK_SetRootClock(kCLOCK_Root_Csi2_Ui, &rootCfg);
827
828 /* Configure CSI using OSC_RC_48M_DIV2 */
829 rootCfg.mux = kCLOCK_CSI_ClockRoot_MuxOscRc48MDiv2;
830 rootCfg.div = 1;
831 CLOCK_SetRootClock(kCLOCK_Root_Csi, &rootCfg);
832
833 /* Configure CKO1 using OSC_RC_48M_DIV2 */
834 rootCfg.mux = kCLOCK_CKO1_ClockRoot_MuxOscRc48MDiv2;
835 rootCfg.div = 1;
836 CLOCK_SetRootClock(kCLOCK_Root_Cko1, &rootCfg);
837
838 /* Configure CKO2 using OSC_RC_48M_DIV2 */
839 rootCfg.mux = kCLOCK_CKO2_ClockRoot_MuxOscRc48MDiv2;
840 rootCfg.div = 1;
841 CLOCK_SetRootClock(kCLOCK_Root_Cko2, &rootCfg);
842
843 /* Set SAI1 MCLK1 clock source. */
844 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
845 /* Set SAI1 MCLK2 clock source. */
846 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 3);
847 /* Set SAI1 MCLK3 clock source. */
848 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
849 /* Set SAI2 MCLK3 clock source. */
850 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
851 /* Set SAI3 MCLK3 clock source. */
852 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
853
854 /* Set MQS configuration. */
855 IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
856 /* Set ENET Ref clock source. */
857 IOMUXC_GPR->GPR4 &= ~IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_MASK;
858 /* Set ENET_1G Tx clock source. */
859 IOMUXC_GPR->GPR5 = ((IOMUXC_GPR->GPR5 & ~IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_MASK) | IOMUXC_GPR_GPR5_ENET1G_RGMII_EN_MASK);
860 /* Set ENET_1G Ref clock source. */
861 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_MASK;
862 /* Set ENET_QOS Tx clock source. */
863 IOMUXC_GPR->GPR6 &= ~IOMUXC_GPR_GPR6_ENET_QOS_RGMII_EN_MASK;
864 /* Set ENET_QOS Ref clock source. */
865 IOMUXC_GPR->GPR6 &= ~IOMUXC_GPR_GPR6_ENET_QOS_REF_CLK_DIR_MASK;
866 /* Set GPT1 High frequency reference clock source. */
867 IOMUXC_GPR->GPR22 &= ~IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1_MASK;
868 /* Set GPT2 High frequency reference clock source. */
869 IOMUXC_GPR->GPR23 &= ~IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2_MASK;
870 /* Set GPT3 High frequency reference clock source. */
871 IOMUXC_GPR->GPR24 &= ~IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3_MASK;
872 /* Set GPT4 High frequency reference clock source. */
873 IOMUXC_GPR->GPR25 &= ~IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4_MASK;
874 /* Set GPT5 High frequency reference clock source. */
875 IOMUXC_GPR->GPR26 &= ~IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5_MASK;
876 /* Set GPT6 High frequency reference clock source. */
877 IOMUXC_GPR->GPR27 &= ~IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6_MASK;
878
879 #if __CORTEX_M == 7
880 SystemCoreClock = CLOCK_GetRootClockFreq(kCLOCK_Root_M7);
881 #else
882 SystemCoreClock = CLOCK_GetRootClockFreq(kCLOCK_Root_M4);
883 #endif
884 }
885 /*******************************************************************************
886 ******************* Configuration BOARD_BootClockRUN_800M *********************
887 ******************************************************************************/
888 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
889 !!Configuration
890 name: BOARD_BootClockRUN_800M
891 outputs:
892 - {id: ACMP_CLK_ROOT.outFreq, value: 24 MHz}
893 - {id: ADC1_CLK_ROOT.outFreq, value: 24 MHz}
894 - {id: ADC2_CLK_ROOT.outFreq, value: 24 MHz}
895 - {id: ARM_PLL_CLK.outFreq, value: 2.4 GHz}
896 - {id: ASRC_CLK_ROOT.outFreq, value: 24 MHz}
897 - {id: AXI_CLK_ROOT.outFreq, value: 800 MHz}
898 - {id: BUS_CLK_ROOT.outFreq, value: 240 MHz}
899 - {id: BUS_LPSR_CLK_ROOT.outFreq, value: 160 MHz}
900 - {id: CAN1_CLK_ROOT.outFreq, value: 24 MHz}
901 - {id: CAN2_CLK_ROOT.outFreq, value: 24 MHz}
902 - {id: CAN3_CLK_ROOT.outFreq, value: 24 MHz}
903 - {id: CCM_CLKO1_CLK_ROOT.outFreq, value: 24 MHz}
904 - {id: CCM_CLKO2_CLK_ROOT.outFreq, value: 24 MHz}
905 - {id: CLK_1M.outFreq, value: 1 MHz}
906 - {id: CSI2_CLK_ROOT.outFreq, value: 24 MHz}
907 - {id: CSI2_ESC_CLK_ROOT.outFreq, value: 24 MHz}
908 - {id: CSI2_UI_CLK_ROOT.outFreq, value: 24 MHz}
909 - {id: CSI_CLK_ROOT.outFreq, value: 24 MHz}
910 - {id: CSSYS_CLK_ROOT.outFreq, value: 24 MHz}
911 - {id: CSTRACE_CLK_ROOT.outFreq, value: 132 MHz}
912 - {id: ELCDIF_CLK_ROOT.outFreq, value: 24 MHz}
913 - {id: EMV1_CLK_ROOT.outFreq, value: 24 MHz}
914 - {id: EMV2_CLK_ROOT.outFreq, value: 24 MHz}
915 - {id: ENET1_CLK_ROOT.outFreq, value: 24 MHz}
916 - {id: ENET2_CLK_ROOT.outFreq, value: 24 MHz}
917 - {id: ENET_1G_TX_CLK.outFreq, value: 24 MHz}
918 - {id: ENET_25M_CLK_ROOT.outFreq, value: 24 MHz}
919 - {id: ENET_QOS_CLK_ROOT.outFreq, value: 24 MHz}
920 - {id: ENET_TIMER1_CLK_ROOT.outFreq, value: 24 MHz}
921 - {id: ENET_TIMER2_CLK_ROOT.outFreq, value: 24 MHz}
922 - {id: ENET_TIMER3_CLK_ROOT.outFreq, value: 24 MHz}
923 - {id: FLEXIO1_CLK_ROOT.outFreq, value: 24 MHz}
924 - {id: FLEXIO2_CLK_ROOT.outFreq, value: 24 MHz}
925 - {id: FLEXSPI1_CLK_ROOT.outFreq, value: 24 MHz}
926 - {id: FLEXSPI2_CLK_ROOT.outFreq, value: 24 MHz}
927 - {id: GC355_CLK_ROOT.outFreq, value: 492.0000125 MHz}
928 - {id: GPT1_CLK_ROOT.outFreq, value: 24 MHz}
929 - {id: GPT1_ipg_clk_highfreq.outFreq, value: 24 MHz}
930 - {id: GPT2_CLK_ROOT.outFreq, value: 24 MHz}
931 - {id: GPT2_ipg_clk_highfreq.outFreq, value: 24 MHz}
932 - {id: GPT3_CLK_ROOT.outFreq, value: 24 MHz}
933 - {id: GPT3_ipg_clk_highfreq.outFreq, value: 24 MHz}
934 - {id: GPT4_CLK_ROOT.outFreq, value: 24 MHz}
935 - {id: GPT4_ipg_clk_highfreq.outFreq, value: 24 MHz}
936 - {id: GPT5_CLK_ROOT.outFreq, value: 24 MHz}
937 - {id: GPT5_ipg_clk_highfreq.outFreq, value: 24 MHz}
938 - {id: GPT6_CLK_ROOT.outFreq, value: 24 MHz}
939 - {id: GPT6_ipg_clk_highfreq.outFreq, value: 24 MHz}
940 - {id: LCDIFV2_CLK_ROOT.outFreq, value: 24 MHz}
941 - {id: LPI2C1_CLK_ROOT.outFreq, value: 24 MHz}
942 - {id: LPI2C2_CLK_ROOT.outFreq, value: 24 MHz}
943 - {id: LPI2C3_CLK_ROOT.outFreq, value: 24 MHz}
944 - {id: LPI2C4_CLK_ROOT.outFreq, value: 24 MHz}
945 - {id: LPI2C5_CLK_ROOT.outFreq, value: 24 MHz}
946 - {id: LPI2C6_CLK_ROOT.outFreq, value: 24 MHz}
947 - {id: LPSPI1_CLK_ROOT.outFreq, value: 24 MHz}
948 - {id: LPSPI2_CLK_ROOT.outFreq, value: 24 MHz}
949 - {id: LPSPI3_CLK_ROOT.outFreq, value: 24 MHz}
950 - {id: LPSPI4_CLK_ROOT.outFreq, value: 24 MHz}
951 - {id: LPSPI5_CLK_ROOT.outFreq, value: 24 MHz}
952 - {id: LPSPI6_CLK_ROOT.outFreq, value: 24 MHz}
953 - {id: LPUART10_CLK_ROOT.outFreq, value: 24 MHz}
954 - {id: LPUART11_CLK_ROOT.outFreq, value: 24 MHz}
955 - {id: LPUART12_CLK_ROOT.outFreq, value: 24 MHz}
956 - {id: LPUART1_CLK_ROOT.outFreq, value: 24 MHz}
957 - {id: LPUART2_CLK_ROOT.outFreq, value: 24 MHz}
958 - {id: LPUART3_CLK_ROOT.outFreq, value: 24 MHz}
959 - {id: LPUART4_CLK_ROOT.outFreq, value: 24 MHz}
960 - {id: LPUART5_CLK_ROOT.outFreq, value: 24 MHz}
961 - {id: LPUART6_CLK_ROOT.outFreq, value: 24 MHz}
962 - {id: LPUART7_CLK_ROOT.outFreq, value: 24 MHz}
963 - {id: LPUART8_CLK_ROOT.outFreq, value: 24 MHz}
964 - {id: LPUART9_CLK_ROOT.outFreq, value: 24 MHz}
965 - {id: M4_CLK_ROOT.outFreq, value: 4320/11 MHz}
966 - {id: M4_SYSTICK_CLK_ROOT.outFreq, value: 24 MHz}
967 - {id: M7_CLK_ROOT.outFreq, value: 800 MHz, locked: true, accuracy: '0.001'}
968 - {id: M7_SYSTICK_CLK_ROOT.outFreq, value: 100 kHz}
969 - {id: MIC_CLK_ROOT.outFreq, value: 24 MHz}
970 - {id: MIPI_DSI_TX_CLK_ESC_ROOT.outFreq, value: 24 MHz}
971 - {id: MIPI_ESC_CLK_ROOT.outFreq, value: 24 MHz}
972 - {id: MIPI_REF_CLK_ROOT.outFreq, value: 24 MHz}
973 - {id: MQS_CLK_ROOT.outFreq, value: 24 MHz}
974 - {id: MQS_MCLK.outFreq, value: 24 MHz}
975 - {id: OSC_24M.outFreq, value: 24 MHz}
976 - {id: OSC_32K.outFreq, value: 32.768 kHz}
977 - {id: OSC_RC_16M.outFreq, value: 16 MHz}
978 - {id: OSC_RC_400M.outFreq, value: 400 MHz}
979 - {id: OSC_RC_48M.outFreq, value: 48 MHz}
980 - {id: OSC_RC_48M_DIV2.outFreq, value: 24 MHz}
981 - {id: PLL_VIDEO_CLK.outFreq, value: 984.000025 MHz}
982 - {id: SAI1_CLK_ROOT.outFreq, value: 24 MHz}
983 - {id: SAI1_MCLK1.outFreq, value: 24 MHz}
984 - {id: SAI1_MCLK3.outFreq, value: 24 MHz}
985 - {id: SAI2_CLK_ROOT.outFreq, value: 24 MHz}
986 - {id: SAI2_MCLK1.outFreq, value: 24 MHz}
987 - {id: SAI2_MCLK3.outFreq, value: 24 MHz}
988 - {id: SAI3_CLK_ROOT.outFreq, value: 24 MHz}
989 - {id: SAI3_MCLK1.outFreq, value: 24 MHz}
990 - {id: SAI3_MCLK3.outFreq, value: 24 MHz}
991 - {id: SAI4_CLK_ROOT.outFreq, value: 24 MHz}
992 - {id: SAI4_MCLK1.outFreq, value: 24 MHz}
993 - {id: SEMC_CLK_ROOT.outFreq, value: 198 MHz}
994 - {id: SPDIF_CLK_ROOT.outFreq, value: 24 MHz}
995 - {id: SYS_PLL2_CLK.outFreq, value: 528 MHz}
996 - {id: SYS_PLL2_PFD0_CLK.outFreq, value: 352 MHz}
997 - {id: SYS_PLL2_PFD1_CLK.outFreq, value: 594 MHz}
998 - {id: SYS_PLL2_PFD2_CLK.outFreq, value: 396 MHz}
999 - {id: SYS_PLL2_PFD3_CLK.outFreq, value: 297 MHz}
1000 - {id: SYS_PLL3_CLK.outFreq, value: 480 MHz}
1001 - {id: SYS_PLL3_DIV2_CLK.outFreq, value: 240 MHz}
1002 - {id: SYS_PLL3_PFD0_CLK.outFreq, value: 8640/13 MHz}
1003 - {id: SYS_PLL3_PFD1_CLK.outFreq, value: 8640/17 MHz}
1004 - {id: SYS_PLL3_PFD2_CLK.outFreq, value: 270 MHz}
1005 - {id: SYS_PLL3_PFD3_CLK.outFreq, value: 4320/11 MHz}
1006 - {id: USDHC1_CLK_ROOT.outFreq, value: 24 MHz}
1007 - {id: USDHC2_CLK_ROOT.outFreq, value: 24 MHz}
1008 settings:
1009 - {id: CoreBusClockRootsInitializationConfig, value: selectedCore}
1010 - {id: SOCDomainVoltage, value: OD}
1011 - {id: ANADIG_OSC_OSC_24M_CTRL_LP_EN_CFG, value: Low}
1012 - {id: ANADIG_OSC_OSC_24M_CTRL_OSC_EN_CFG, value: Enabled}
1013 - {id: ANADIG_PLL.ARM_PLL_POST_DIV.scale, value: '1'}
1014 - {id: ANADIG_PLL.ARM_PLL_VDIV.scale, value: '100'}
1015 - {id: ANADIG_PLL.PLL_AUDIO_BYPASS.sel, value: ANADIG_OSC.OSC_24M}
1016 - {id: ANADIG_PLL.PLL_VIDEO.denom, value: '960000'}
1017 - {id: ANADIG_PLL.PLL_VIDEO.div, value: '41'}
1018 - {id: ANADIG_PLL.PLL_VIDEO.num, value: '1'}
1019 - {id: ANADIG_PLL.SYS_PLL1_BYPASS.sel, value: ANADIG_OSC.OSC_24M}
1020 - {id: ANADIG_PLL.SYS_PLL2.denom, value: '268435455'}
1021 - {id: ANADIG_PLL.SYS_PLL2.div, value: '22'}
1022 - {id: ANADIG_PLL.SYS_PLL2.num, value: '0'}
1023 - {id: ANADIG_PLL.SYS_PLL2_SS_DIV.scale, value: '268435455'}
1024 - {id: ANADIG_PLL.SYS_PLL3_PFD3_DIV.scale, value: '22', locked: true}
1025 - {id: ANADIG_PLL.SYS_PLL3_PFD3_MUL.scale, value: '18', locked: true}
1026 - {id: ANADIG_PLL_ARM_PLL_CTRL_POWERUP_CFG, value: Enabled}
1027 - {id: ANADIG_PLL_PLL_AUDIO_CTRL_GATE_CFG, value: Disabled}
1028 - {id: ANADIG_PLL_PLL_VIDEO_CTRL0_POWERUP_CFG, value: Enabled}
1029 - {id: ANADIG_PLL_SYS_PLL1_CTRL0_POWERUP_CFG, value: Disabled}
1030 - {id: ANADIG_PLL_SYS_PLL1_CTRL_GATE_CFG, value: Disabled}
1031 - {id: ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_CFG, value: Enabled}
1032 - {id: ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_CFG, value: Enabled}
1033 - {id: ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CFG, value: Enabled}
1034 - {id: CCM.CLOCK_ROOT0.DIV.scale, value: '3'}
1035 - {id: CCM.CLOCK_ROOT0.MUX.sel, value: ANADIG_PLL.ARM_PLL_CLK}
1036 - {id: CCM.CLOCK_ROOT1.MUX.sel, value: ANADIG_PLL.SYS_PLL3_PFD3_CLK}
1037 - {id: CCM.CLOCK_ROOT2.DIV.scale, value: '2'}
1038 - {id: CCM.CLOCK_ROOT2.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK}
1039 - {id: CCM.CLOCK_ROOT25.DIV.scale, value: '22'}
1040 - {id: CCM.CLOCK_ROOT25.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK}
1041 - {id: CCM.CLOCK_ROOT26.DIV.scale, value: '22'}
1042 - {id: CCM.CLOCK_ROOT26.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK}
1043 - {id: CCM.CLOCK_ROOT3.DIV.scale, value: '3'}
1044 - {id: CCM.CLOCK_ROOT3.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK}
1045 - {id: CCM.CLOCK_ROOT4.DIV.scale, value: '3'}
1046 - {id: CCM.CLOCK_ROOT4.MUX.sel, value: ANADIG_PLL.SYS_PLL2_PFD1_CLK}
1047 - {id: CCM.CLOCK_ROOT6.DIV.scale, value: '4'}
1048 - {id: CCM.CLOCK_ROOT6.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK}
1049 - {id: CCM.CLOCK_ROOT68.DIV.scale, value: '2'}
1050 - {id: CCM.CLOCK_ROOT68.MUX.sel, value: ANADIG_PLL.PLL_VIDEO_CLK}
1051 - {id: CCM.CLOCK_ROOT8.DIV.scale, value: '240'}
1052 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
1053
1054 /*******************************************************************************
1055 * Variables for BOARD_BootClockRUN_800M configuration
1056 ******************************************************************************/
1057
1058 #ifndef SKIP_POWER_ADJUSTMENT
1059 #if __CORTEX_M == 7
1060 #define BYPASS_LDO_LPSR 1
1061 #define SKIP_LDO_ADJUSTMENT 1
1062 #elif __CORTEX_M == 4
1063 #define SKIP_DCDC_ADJUSTMENT 1
1064 #define SKIP_FBB_ENABLE 1
1065 #endif
1066 #endif
1067
1068 const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN_800M =
1069 {
1070 .postDivider = kCLOCK_PllPostDiv1, /* Post divider, 0 - DIV by 2, 1 - DIV by 4, 2 - DIV by 8, 3 - DIV by 1 */
1071 .loopDivider = 200, /* PLL Loop divider, Fout = Fin * ( loopDivider / ( 2 * postDivider ) ) */
1072 };
1073
1074 const clock_sys_pll2_config_t sysPll2Config_BOARD_BootClockRUN_800M =
1075 {
1076 .mfd = 268435455, /* Denominator of spread spectrum */
1077 .ss = NULL, /* Spread spectrum parameter */
1078 .ssEnable = false, /* Enable spread spectrum or not */
1079 };
1080
1081 const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN_800M =
1082 {
1083 .loopDivider = 41, /* PLL Loop divider, valid range for DIV_SELECT divider value: 27 ~ 54. */
1084 .postDivider = 0, /* Divider after PLL, should only be 1, 2, 4, 8, 16, 32 */
1085 .numerator = 1, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
1086 .denominator = 960000, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
1087 .ss = NULL, /* Spread spectrum parameter */
1088 .ssEnable = false, /* Enable spread spectrum or not */
1089 };
1090
1091 /*******************************************************************************
1092 * Code for BOARD_BootClockRUN_800M configuration
1093 ******************************************************************************/
BOARD_BootClockRUN_800M(void)1094 void BOARD_BootClockRUN_800M(void)
1095 {
1096 clock_root_config_t rootCfg = {0};
1097
1098 /* Set DCDC to DCM mode to improve the efficiency for light loading in run mode and transient performance with a big loading step. */
1099 DCDC_BootIntoDCM(DCDC);
1100
1101 #if !defined(SKIP_DCDC_ADJUSTMENT) || (!SKIP_DCDC_ADJUSTMENT)
1102 if((OCOTP->FUSEN[16].FUSE == 0x57AC5969U) && ((OCOTP->FUSEN[17].FUSE & 0xFFU) == 0x0BU))
1103 {
1104 DCDC_SetVDD1P0BuckModeTargetVoltage(DCDC, kDCDC_1P0BuckTarget1P15V);
1105 }
1106 else
1107 {
1108 /* Set 1.125V for production samples to align with data sheet requirement */
1109 DCDC_SetVDD1P0BuckModeTargetVoltage(DCDC, kDCDC_1P0BuckTarget1P125V);
1110 }
1111 #endif
1112
1113 #if !defined(SKIP_FBB_ENABLE) || (!SKIP_FBB_ENABLE)
1114 /* Check if FBB need to be enabled in OverDrive(OD) mode */
1115 if(((OCOTP->FUSEN[7].FUSE & 0x10U) >> 4U) != 1)
1116 {
1117 PMU_EnableBodyBias(ANADIG_PMU, kPMU_FBB_CM7, true);
1118 }
1119 else
1120 {
1121 PMU_EnableBodyBias(ANADIG_PMU, kPMU_FBB_CM7, false);
1122 }
1123 #endif
1124
1125 #if defined(BYPASS_LDO_LPSR) && BYPASS_LDO_LPSR
1126 PMU_StaticEnableLpsrAnaLdoBypassMode(ANADIG_LDO_SNVS, true);
1127 PMU_StaticEnableLpsrDigLdoBypassMode(ANADIG_LDO_SNVS, true);
1128 #endif
1129
1130 #if !defined(SKIP_LDO_ADJUSTMENT) || (!SKIP_LDO_ADJUSTMENT)
1131 pmu_static_lpsr_ana_ldo_config_t lpsrAnaConfig;
1132 pmu_static_lpsr_dig_config_t lpsrDigConfig;
1133
1134 if((ANADIG_LDO_SNVS->PMU_LDO_LPSR_ANA & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_MASK) == 0UL)
1135 {
1136 PMU_StaticGetLpsrAnaLdoDefaultConfig(&lpsrAnaConfig);
1137 PMU_StaticLpsrAnaLdoInit(ANADIG_LDO_SNVS, &lpsrAnaConfig);
1138 }
1139
1140 if((ANADIG_LDO_SNVS->PMU_LDO_LPSR_DIG & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_MASK) == 0UL)
1141 {
1142 PMU_StaticGetLpsrDigLdoDefaultConfig(&lpsrDigConfig);
1143 lpsrDigConfig.targetVoltage = kPMU_LpsrDigTargetStableVoltage1P117V;
1144 PMU_StaticLpsrDigLdoInit(ANADIG_LDO_SNVS, &lpsrDigConfig);
1145 }
1146 #endif
1147
1148 /* Config CLK_1M */
1149 CLOCK_OSC_Set1MHzOutputBehavior(kCLOCK_1MHzOutEnableFreeRunning1Mhz);
1150
1151 /* Init OSC RC 16M */
1152 ANADIG_OSC->OSC_16M_CTRL |= ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_MASK;
1153
1154 /* Init OSC RC 400M */
1155 CLOCK_OSC_EnableOscRc400M();
1156 CLOCK_OSC_GateOscRc400M(true);
1157
1158 /* Init OSC RC 48M */
1159 CLOCK_OSC_EnableOsc48M(true);
1160 CLOCK_OSC_EnableOsc48MDiv2(true);
1161
1162 /* Config OSC 24M */
1163 ANADIG_OSC->OSC_24M_CTRL |= ANADIG_OSC_OSC_24M_CTRL_OSC_EN(1) | ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN(0) | ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK(0) | ANADIG_OSC_OSC_24M_CTRL_LP_EN(1) | ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE(0);
1164 /* Wait for 24M OSC to be stable. */
1165 while (ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK !=
1166 (ANADIG_OSC->OSC_24M_CTRL & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK))
1167 {
1168 }
1169
1170 /* Swicth both core, M7 Systick and Bus_Lpsr to OscRC48MDiv2 first */
1171 #if __CORTEX_M == 7
1172 rootCfg.mux = kCLOCK_M7_ClockRoot_MuxOscRc48MDiv2;
1173 rootCfg.div = 1;
1174 CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg);
1175
1176 rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc48MDiv2;
1177 rootCfg.div = 1;
1178 CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg);
1179 #endif
1180
1181 #if __CORTEX_M == 4
1182 rootCfg.mux = kCLOCK_M4_ClockRoot_MuxOscRc48MDiv2;
1183 rootCfg.div = 1;
1184 CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg);
1185
1186 rootCfg.mux = kCLOCK_BUS_LPSR_ClockRoot_MuxOscRc48MDiv2;
1187 rootCfg.div = 1;
1188 CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg);
1189 #endif
1190
1191 /*
1192 * if DCD is used, please make sure the clock source of SEMC is not changed in the following PLL/PFD configuration code.
1193 */
1194 /* Init Arm Pll. */
1195 CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN_800M);
1196
1197 /* Bypass Sys Pll1. */
1198 CLOCK_SetPllBypass(kCLOCK_PllSys1, true);
1199
1200 /* DeInit Sys Pll1. */
1201 CLOCK_DeinitSysPll1();
1202
1203 /* Init Sys Pll2. */
1204 CLOCK_InitSysPll2(&sysPll2Config_BOARD_BootClockRUN_800M);
1205
1206 /* Init System Pll2 pfd0. */
1207 CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd0, 27);
1208
1209 /* Init System Pll2 pfd1. */
1210 CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd1, 16);
1211
1212 /* Init System Pll2 pfd2. */
1213 CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd2, 24);
1214
1215 /* Init System Pll2 pfd3. */
1216 CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd3, 32);
1217
1218 /* Init Sys Pll3. */
1219 CLOCK_InitSysPll3();
1220
1221 /* Init System Pll3 pfd0. */
1222 CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd0, 13);
1223
1224 /* Init System Pll3 pfd1. */
1225 CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd1, 17);
1226
1227 /* Init System Pll3 pfd2. */
1228 CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd2, 32);
1229
1230 /* Init System Pll3 pfd3. */
1231 CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd3, 22);
1232
1233 /* Bypass Audio Pll. */
1234 CLOCK_SetPllBypass(kCLOCK_PllAudio, true);
1235
1236 /* DeInit Audio Pll. */
1237 CLOCK_DeinitAudioPll();
1238
1239 /* Init Video Pll. */
1240 CLOCK_InitVideoPll(&videoPllConfig_BOARD_BootClockRUN_800M);
1241
1242 /* Module clock root configurations. */
1243 /* Configure M7 using ARM_PLL_CLK */
1244 #if __CORTEX_M == 7
1245 rootCfg.mux = kCLOCK_M7_ClockRoot_MuxArmPllOut;
1246 rootCfg.div = 3;
1247 CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg);
1248 #endif
1249
1250 /* Configure M4 using SYS_PLL3_PFD3_CLK */
1251 #if __CORTEX_M == 4
1252 rootCfg.mux = kCLOCK_M4_ClockRoot_MuxSysPll3Pfd3;
1253 rootCfg.div = 1;
1254 CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg);
1255 #endif
1256
1257 /* Configure BUS using SYS_PLL3_CLK */
1258 rootCfg.mux = kCLOCK_BUS_ClockRoot_MuxSysPll3Out;
1259 rootCfg.div = 2;
1260 CLOCK_SetRootClock(kCLOCK_Root_Bus, &rootCfg);
1261
1262 /* Configure BUS_LPSR using SYS_PLL3_CLK */
1263 rootCfg.mux = kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll3Out;
1264 rootCfg.div = 3;
1265 CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg);
1266
1267 /* Configure SEMC using SYS_PLL2_PFD1_CLK */
1268 #ifndef SKIP_SEMC_INIT
1269 rootCfg.mux = kCLOCK_SEMC_ClockRoot_MuxSysPll2Pfd1;
1270 rootCfg.div = 3;
1271 CLOCK_SetRootClock(kCLOCK_Root_Semc, &rootCfg);
1272 #endif
1273
1274 #if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
1275 #if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
1276 UpdateSemcClock();
1277 #endif
1278 #endif
1279
1280 /* Configure CSSYS using OSC_RC_48M_DIV2 */
1281 rootCfg.mux = kCLOCK_CSSYS_ClockRoot_MuxOscRc48MDiv2;
1282 rootCfg.div = 1;
1283 CLOCK_SetRootClock(kCLOCK_Root_Cssys, &rootCfg);
1284
1285 /* Configure CSTRACE using SYS_PLL2_CLK */
1286 rootCfg.mux = kCLOCK_CSTRACE_ClockRoot_MuxSysPll2Out;
1287 rootCfg.div = 4;
1288 CLOCK_SetRootClock(kCLOCK_Root_Cstrace, &rootCfg);
1289
1290 /* Configure M4_SYSTICK using OSC_RC_48M_DIV2 */
1291 #if __CORTEX_M == 4
1292 rootCfg.mux = kCLOCK_M4_SYSTICK_ClockRoot_MuxOscRc48MDiv2;
1293 rootCfg.div = 1;
1294 CLOCK_SetRootClock(kCLOCK_Root_M4_Systick, &rootCfg);
1295 #endif
1296
1297 /* Configure M7_SYSTICK using OSC_RC_48M_DIV2 */
1298 #if __CORTEX_M == 7
1299 rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc48MDiv2;
1300 rootCfg.div = 240;
1301 CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg);
1302 #endif
1303
1304 /* Configure ADC1 using OSC_RC_48M_DIV2 */
1305 rootCfg.mux = kCLOCK_ADC1_ClockRoot_MuxOscRc48MDiv2;
1306 rootCfg.div = 1;
1307 CLOCK_SetRootClock(kCLOCK_Root_Adc1, &rootCfg);
1308
1309 /* Configure ADC2 using OSC_RC_48M_DIV2 */
1310 rootCfg.mux = kCLOCK_ADC2_ClockRoot_MuxOscRc48MDiv2;
1311 rootCfg.div = 1;
1312 CLOCK_SetRootClock(kCLOCK_Root_Adc2, &rootCfg);
1313
1314 /* Configure ACMP using OSC_RC_48M_DIV2 */
1315 rootCfg.mux = kCLOCK_ACMP_ClockRoot_MuxOscRc48MDiv2;
1316 rootCfg.div = 1;
1317 CLOCK_SetRootClock(kCLOCK_Root_Acmp, &rootCfg);
1318
1319 /* Configure FLEXIO1 using OSC_RC_48M_DIV2 */
1320 rootCfg.mux = kCLOCK_FLEXIO1_ClockRoot_MuxOscRc48MDiv2;
1321 rootCfg.div = 1;
1322 CLOCK_SetRootClock(kCLOCK_Root_Flexio1, &rootCfg);
1323
1324 /* Configure FLEXIO2 using OSC_RC_48M_DIV2 */
1325 rootCfg.mux = kCLOCK_FLEXIO2_ClockRoot_MuxOscRc48MDiv2;
1326 rootCfg.div = 1;
1327 CLOCK_SetRootClock(kCLOCK_Root_Flexio2, &rootCfg);
1328
1329 /* Configure GPT1 using OSC_RC_48M_DIV2 */
1330 rootCfg.mux = kCLOCK_GPT1_ClockRoot_MuxOscRc48MDiv2;
1331 rootCfg.div = 1;
1332 CLOCK_SetRootClock(kCLOCK_Root_Gpt1, &rootCfg);
1333
1334 /* Configure GPT2 using OSC_RC_48M_DIV2 */
1335 rootCfg.mux = kCLOCK_GPT2_ClockRoot_MuxOscRc48MDiv2;
1336 rootCfg.div = 1;
1337 CLOCK_SetRootClock(kCLOCK_Root_Gpt2, &rootCfg);
1338
1339 /* Configure GPT3 using OSC_RC_48M_DIV2 */
1340 rootCfg.mux = kCLOCK_GPT3_ClockRoot_MuxOscRc48MDiv2;
1341 rootCfg.div = 1;
1342 CLOCK_SetRootClock(kCLOCK_Root_Gpt3, &rootCfg);
1343
1344 /* Configure GPT4 using OSC_RC_48M_DIV2 */
1345 rootCfg.mux = kCLOCK_GPT4_ClockRoot_MuxOscRc48MDiv2;
1346 rootCfg.div = 1;
1347 CLOCK_SetRootClock(kCLOCK_Root_Gpt4, &rootCfg);
1348
1349 /* Configure GPT5 using OSC_RC_48M_DIV2 */
1350 rootCfg.mux = kCLOCK_GPT5_ClockRoot_MuxOscRc48MDiv2;
1351 rootCfg.div = 1;
1352 CLOCK_SetRootClock(kCLOCK_Root_Gpt5, &rootCfg);
1353
1354 /* Configure GPT6 using OSC_RC_48M_DIV2 */
1355 rootCfg.mux = kCLOCK_GPT6_ClockRoot_MuxOscRc48MDiv2;
1356 rootCfg.div = 1;
1357 CLOCK_SetRootClock(kCLOCK_Root_Gpt6, &rootCfg);
1358
1359 /* Configure FLEXSPI1 using OSC_RC_48M_DIV2 */
1360 #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1) || defined(FLEXSPI_IN_USE))
1361 rootCfg.mux = kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc48MDiv2;
1362 rootCfg.div = 1;
1363 CLOCK_SetRootClock(kCLOCK_Root_Flexspi1, &rootCfg);
1364 #endif
1365
1366 /* Configure FLEXSPI2 using OSC_RC_48M_DIV2 */
1367 rootCfg.mux = kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc48MDiv2;
1368 rootCfg.div = 1;
1369 CLOCK_SetRootClock(kCLOCK_Root_Flexspi2, &rootCfg);
1370
1371 /* Configure CAN1 using OSC_RC_48M_DIV2 */
1372 rootCfg.mux = kCLOCK_CAN1_ClockRoot_MuxOscRc48MDiv2;
1373 rootCfg.div = 1;
1374 CLOCK_SetRootClock(kCLOCK_Root_Can1, &rootCfg);
1375
1376 /* Configure CAN2 using OSC_RC_48M_DIV2 */
1377 rootCfg.mux = kCLOCK_CAN2_ClockRoot_MuxOscRc48MDiv2;
1378 rootCfg.div = 1;
1379 CLOCK_SetRootClock(kCLOCK_Root_Can2, &rootCfg);
1380
1381 /* Configure CAN3 using OSC_RC_48M_DIV2 */
1382 rootCfg.mux = kCLOCK_CAN3_ClockRoot_MuxOscRc48MDiv2;
1383 rootCfg.div = 1;
1384 CLOCK_SetRootClock(kCLOCK_Root_Can3, &rootCfg);
1385
1386 /* Configure LPUART1 using SYS_PLL2_CLK */
1387 rootCfg.mux = kCLOCK_LPUART1_ClockRoot_MuxSysPll2Out;
1388 rootCfg.div = 22;
1389 CLOCK_SetRootClock(kCLOCK_Root_Lpuart1, &rootCfg);
1390
1391 /* Configure LPUART2 using SYS_PLL2_CLK */
1392 rootCfg.mux = kCLOCK_LPUART2_ClockRoot_MuxSysPll2Out;
1393 rootCfg.div = 22;
1394 CLOCK_SetRootClock(kCLOCK_Root_Lpuart2, &rootCfg);
1395
1396 /* Configure LPUART3 using OSC_RC_48M_DIV2 */
1397 rootCfg.mux = kCLOCK_LPUART3_ClockRoot_MuxOscRc48MDiv2;
1398 rootCfg.div = 1;
1399 CLOCK_SetRootClock(kCLOCK_Root_Lpuart3, &rootCfg);
1400
1401 /* Configure LPUART4 using OSC_RC_48M_DIV2 */
1402 rootCfg.mux = kCLOCK_LPUART4_ClockRoot_MuxOscRc48MDiv2;
1403 rootCfg.div = 1;
1404 CLOCK_SetRootClock(kCLOCK_Root_Lpuart4, &rootCfg);
1405
1406 /* Configure LPUART5 using OSC_RC_48M_DIV2 */
1407 rootCfg.mux = kCLOCK_LPUART5_ClockRoot_MuxOscRc48MDiv2;
1408 rootCfg.div = 1;
1409 CLOCK_SetRootClock(kCLOCK_Root_Lpuart5, &rootCfg);
1410
1411 /* Configure LPUART6 using OSC_RC_48M_DIV2 */
1412 rootCfg.mux = kCLOCK_LPUART6_ClockRoot_MuxOscRc48MDiv2;
1413 rootCfg.div = 1;
1414 CLOCK_SetRootClock(kCLOCK_Root_Lpuart6, &rootCfg);
1415
1416 /* Configure LPUART7 using OSC_RC_48M_DIV2 */
1417 rootCfg.mux = kCLOCK_LPUART7_ClockRoot_MuxOscRc48MDiv2;
1418 rootCfg.div = 1;
1419 CLOCK_SetRootClock(kCLOCK_Root_Lpuart7, &rootCfg);
1420
1421 /* Configure LPUART8 using OSC_RC_48M_DIV2 */
1422 rootCfg.mux = kCLOCK_LPUART8_ClockRoot_MuxOscRc48MDiv2;
1423 rootCfg.div = 1;
1424 CLOCK_SetRootClock(kCLOCK_Root_Lpuart8, &rootCfg);
1425
1426 /* Configure LPUART9 using OSC_RC_48M_DIV2 */
1427 rootCfg.mux = kCLOCK_LPUART9_ClockRoot_MuxOscRc48MDiv2;
1428 rootCfg.div = 1;
1429 CLOCK_SetRootClock(kCLOCK_Root_Lpuart9, &rootCfg);
1430
1431 /* Configure LPUART10 using OSC_RC_48M_DIV2 */
1432 rootCfg.mux = kCLOCK_LPUART10_ClockRoot_MuxOscRc48MDiv2;
1433 rootCfg.div = 1;
1434 CLOCK_SetRootClock(kCLOCK_Root_Lpuart10, &rootCfg);
1435
1436 /* Configure LPUART11 using OSC_RC_48M_DIV2 */
1437 rootCfg.mux = kCLOCK_LPUART11_ClockRoot_MuxOscRc48MDiv2;
1438 rootCfg.div = 1;
1439 CLOCK_SetRootClock(kCLOCK_Root_Lpuart11, &rootCfg);
1440
1441 /* Configure LPUART12 using OSC_RC_48M_DIV2 */
1442 rootCfg.mux = kCLOCK_LPUART12_ClockRoot_MuxOscRc48MDiv2;
1443 rootCfg.div = 1;
1444 CLOCK_SetRootClock(kCLOCK_Root_Lpuart12, &rootCfg);
1445
1446 /* Configure LPI2C1 using OSC_RC_48M_DIV2 */
1447 rootCfg.mux = kCLOCK_LPI2C1_ClockRoot_MuxOscRc48MDiv2;
1448 rootCfg.div = 1;
1449 CLOCK_SetRootClock(kCLOCK_Root_Lpi2c1, &rootCfg);
1450
1451 /* Configure LPI2C2 using OSC_RC_48M_DIV2 */
1452 rootCfg.mux = kCLOCK_LPI2C2_ClockRoot_MuxOscRc48MDiv2;
1453 rootCfg.div = 1;
1454 CLOCK_SetRootClock(kCLOCK_Root_Lpi2c2, &rootCfg);
1455
1456 /* Configure LPI2C3 using OSC_RC_48M_DIV2 */
1457 rootCfg.mux = kCLOCK_LPI2C3_ClockRoot_MuxOscRc48MDiv2;
1458 rootCfg.div = 1;
1459 CLOCK_SetRootClock(kCLOCK_Root_Lpi2c3, &rootCfg);
1460
1461 /* Configure LPI2C4 using OSC_RC_48M_DIV2 */
1462 rootCfg.mux = kCLOCK_LPI2C4_ClockRoot_MuxOscRc48MDiv2;
1463 rootCfg.div = 1;
1464 CLOCK_SetRootClock(kCLOCK_Root_Lpi2c4, &rootCfg);
1465
1466 /* Configure LPI2C5 using OSC_RC_48M_DIV2 */
1467 rootCfg.mux = kCLOCK_LPI2C5_ClockRoot_MuxOscRc48MDiv2;
1468 rootCfg.div = 1;
1469 CLOCK_SetRootClock(kCLOCK_Root_Lpi2c5, &rootCfg);
1470
1471 /* Configure LPI2C6 using OSC_RC_48M_DIV2 */
1472 rootCfg.mux = kCLOCK_LPI2C6_ClockRoot_MuxOscRc48MDiv2;
1473 rootCfg.div = 1;
1474 CLOCK_SetRootClock(kCLOCK_Root_Lpi2c6, &rootCfg);
1475
1476 /* Configure LPSPI1 using OSC_RC_48M_DIV2 */
1477 rootCfg.mux = kCLOCK_LPSPI1_ClockRoot_MuxOscRc48MDiv2;
1478 rootCfg.div = 1;
1479 CLOCK_SetRootClock(kCLOCK_Root_Lpspi1, &rootCfg);
1480
1481 /* Configure LPSPI2 using OSC_RC_48M_DIV2 */
1482 rootCfg.mux = kCLOCK_LPSPI2_ClockRoot_MuxOscRc48MDiv2;
1483 rootCfg.div = 1;
1484 CLOCK_SetRootClock(kCLOCK_Root_Lpspi2, &rootCfg);
1485
1486 /* Configure LPSPI3 using OSC_RC_48M_DIV2 */
1487 rootCfg.mux = kCLOCK_LPSPI3_ClockRoot_MuxOscRc48MDiv2;
1488 rootCfg.div = 1;
1489 CLOCK_SetRootClock(kCLOCK_Root_Lpspi3, &rootCfg);
1490
1491 /* Configure LPSPI4 using OSC_RC_48M_DIV2 */
1492 rootCfg.mux = kCLOCK_LPSPI4_ClockRoot_MuxOscRc48MDiv2;
1493 rootCfg.div = 1;
1494 CLOCK_SetRootClock(kCLOCK_Root_Lpspi4, &rootCfg);
1495
1496 /* Configure LPSPI5 using OSC_RC_48M_DIV2 */
1497 rootCfg.mux = kCLOCK_LPSPI5_ClockRoot_MuxOscRc48MDiv2;
1498 rootCfg.div = 1;
1499 CLOCK_SetRootClock(kCLOCK_Root_Lpspi5, &rootCfg);
1500
1501 /* Configure LPSPI6 using OSC_RC_48M_DIV2 */
1502 rootCfg.mux = kCLOCK_LPSPI6_ClockRoot_MuxOscRc48MDiv2;
1503 rootCfg.div = 1;
1504 CLOCK_SetRootClock(kCLOCK_Root_Lpspi6, &rootCfg);
1505
1506 /* Configure EMV1 using OSC_RC_48M_DIV2 */
1507 rootCfg.mux = kCLOCK_EMV1_ClockRoot_MuxOscRc48MDiv2;
1508 rootCfg.div = 1;
1509 CLOCK_SetRootClock(kCLOCK_Root_Emv1, &rootCfg);
1510
1511 /* Configure EMV2 using OSC_RC_48M_DIV2 */
1512 rootCfg.mux = kCLOCK_EMV2_ClockRoot_MuxOscRc48MDiv2;
1513 rootCfg.div = 1;
1514 CLOCK_SetRootClock(kCLOCK_Root_Emv2, &rootCfg);
1515
1516 /* Configure ENET1 using OSC_RC_48M_DIV2 */
1517 rootCfg.mux = kCLOCK_ENET1_ClockRoot_MuxOscRc48MDiv2;
1518 rootCfg.div = 1;
1519 CLOCK_SetRootClock(kCLOCK_Root_Enet1, &rootCfg);
1520
1521 /* Configure ENET2 using OSC_RC_48M_DIV2 */
1522 rootCfg.mux = kCLOCK_ENET2_ClockRoot_MuxOscRc48MDiv2;
1523 rootCfg.div = 1;
1524 CLOCK_SetRootClock(kCLOCK_Root_Enet2, &rootCfg);
1525
1526 /* Configure ENET_QOS using OSC_RC_48M_DIV2 */
1527 rootCfg.mux = kCLOCK_ENET_QOS_ClockRoot_MuxOscRc48MDiv2;
1528 rootCfg.div = 1;
1529 CLOCK_SetRootClock(kCLOCK_Root_Enet_Qos, &rootCfg);
1530
1531 /* Configure ENET_25M using OSC_RC_48M_DIV2 */
1532 rootCfg.mux = kCLOCK_ENET_25M_ClockRoot_MuxOscRc48MDiv2;
1533 rootCfg.div = 1;
1534 CLOCK_SetRootClock(kCLOCK_Root_Enet_25m, &rootCfg);
1535
1536 /* Configure ENET_TIMER1 using OSC_RC_48M_DIV2 */
1537 rootCfg.mux = kCLOCK_ENET_TIMER1_ClockRoot_MuxOscRc48MDiv2;
1538 rootCfg.div = 1;
1539 CLOCK_SetRootClock(kCLOCK_Root_Enet_Timer1, &rootCfg);
1540
1541 /* Configure ENET_TIMER2 using OSC_RC_48M_DIV2 */
1542 rootCfg.mux = kCLOCK_ENET_TIMER2_ClockRoot_MuxOscRc48MDiv2;
1543 rootCfg.div = 1;
1544 CLOCK_SetRootClock(kCLOCK_Root_Enet_Timer2, &rootCfg);
1545
1546 /* Configure ENET_TIMER3 using OSC_RC_48M_DIV2 */
1547 rootCfg.mux = kCLOCK_ENET_TIMER3_ClockRoot_MuxOscRc48MDiv2;
1548 rootCfg.div = 1;
1549 CLOCK_SetRootClock(kCLOCK_Root_Enet_Timer3, &rootCfg);
1550
1551 /* Configure USDHC1 using OSC_RC_48M_DIV2 */
1552 rootCfg.mux = kCLOCK_USDHC1_ClockRoot_MuxOscRc48MDiv2;
1553 rootCfg.div = 1;
1554 CLOCK_SetRootClock(kCLOCK_Root_Usdhc1, &rootCfg);
1555
1556 /* Configure USDHC2 using OSC_RC_48M_DIV2 */
1557 rootCfg.mux = kCLOCK_USDHC2_ClockRoot_MuxOscRc48MDiv2;
1558 rootCfg.div = 1;
1559 CLOCK_SetRootClock(kCLOCK_Root_Usdhc2, &rootCfg);
1560
1561 /* Configure ASRC using OSC_RC_48M_DIV2 */
1562 rootCfg.mux = kCLOCK_ASRC_ClockRoot_MuxOscRc48MDiv2;
1563 rootCfg.div = 1;
1564 CLOCK_SetRootClock(kCLOCK_Root_Asrc, &rootCfg);
1565
1566 /* Configure MQS using OSC_RC_48M_DIV2 */
1567 rootCfg.mux = kCLOCK_MQS_ClockRoot_MuxOscRc48MDiv2;
1568 rootCfg.div = 1;
1569 CLOCK_SetRootClock(kCLOCK_Root_Mqs, &rootCfg);
1570
1571 /* Configure MIC using OSC_RC_48M_DIV2 */
1572 rootCfg.mux = kCLOCK_MIC_ClockRoot_MuxOscRc48MDiv2;
1573 rootCfg.div = 1;
1574 CLOCK_SetRootClock(kCLOCK_Root_Mic, &rootCfg);
1575
1576 /* Configure SPDIF using OSC_RC_48M_DIV2 */
1577 rootCfg.mux = kCLOCK_SPDIF_ClockRoot_MuxOscRc48MDiv2;
1578 rootCfg.div = 1;
1579 CLOCK_SetRootClock(kCLOCK_Root_Spdif, &rootCfg);
1580
1581 /* Configure SAI1 using OSC_RC_48M_DIV2 */
1582 rootCfg.mux = kCLOCK_SAI1_ClockRoot_MuxOscRc48MDiv2;
1583 rootCfg.div = 1;
1584 CLOCK_SetRootClock(kCLOCK_Root_Sai1, &rootCfg);
1585
1586 /* Configure SAI2 using OSC_RC_48M_DIV2 */
1587 rootCfg.mux = kCLOCK_SAI2_ClockRoot_MuxOscRc48MDiv2;
1588 rootCfg.div = 1;
1589 CLOCK_SetRootClock(kCLOCK_Root_Sai2, &rootCfg);
1590
1591 /* Configure SAI3 using OSC_RC_48M_DIV2 */
1592 rootCfg.mux = kCLOCK_SAI3_ClockRoot_MuxOscRc48MDiv2;
1593 rootCfg.div = 1;
1594 CLOCK_SetRootClock(kCLOCK_Root_Sai3, &rootCfg);
1595
1596 /* Configure SAI4 using OSC_RC_48M_DIV2 */
1597 rootCfg.mux = kCLOCK_SAI4_ClockRoot_MuxOscRc48MDiv2;
1598 rootCfg.div = 1;
1599 CLOCK_SetRootClock(kCLOCK_Root_Sai4, &rootCfg);
1600
1601 /* Configure GC355 using PLL_VIDEO_CLK */
1602 rootCfg.mux = kCLOCK_GC355_ClockRoot_MuxVideoPllOut;
1603 rootCfg.div = 2;
1604 CLOCK_SetRootClock(kCLOCK_Root_Gc355, &rootCfg);
1605
1606 /* Configure LCDIF using OSC_RC_48M_DIV2 */
1607 rootCfg.mux = kCLOCK_LCDIF_ClockRoot_MuxOscRc48MDiv2;
1608 rootCfg.div = 1;
1609 CLOCK_SetRootClock(kCLOCK_Root_Lcdif, &rootCfg);
1610
1611 /* Configure LCDIFV2 using OSC_RC_48M_DIV2 */
1612 rootCfg.mux = kCLOCK_LCDIFV2_ClockRoot_MuxOscRc48MDiv2;
1613 rootCfg.div = 1;
1614 CLOCK_SetRootClock(kCLOCK_Root_Lcdifv2, &rootCfg);
1615
1616 /* Configure MIPI_REF using OSC_RC_48M_DIV2 */
1617 rootCfg.mux = kCLOCK_MIPI_REF_ClockRoot_MuxOscRc48MDiv2;
1618 rootCfg.div = 1;
1619 CLOCK_SetRootClock(kCLOCK_Root_Mipi_Ref, &rootCfg);
1620
1621 /* Configure MIPI_ESC using OSC_RC_48M_DIV2 */
1622 rootCfg.mux = kCLOCK_MIPI_ESC_ClockRoot_MuxOscRc48MDiv2;
1623 rootCfg.div = 1;
1624 CLOCK_SetRootClock(kCLOCK_Root_Mipi_Esc, &rootCfg);
1625
1626 /* Configure CSI2 using OSC_RC_48M_DIV2 */
1627 rootCfg.mux = kCLOCK_CSI2_ClockRoot_MuxOscRc48MDiv2;
1628 rootCfg.div = 1;
1629 CLOCK_SetRootClock(kCLOCK_Root_Csi2, &rootCfg);
1630
1631 /* Configure CSI2_ESC using OSC_RC_48M_DIV2 */
1632 rootCfg.mux = kCLOCK_CSI2_ESC_ClockRoot_MuxOscRc48MDiv2;
1633 rootCfg.div = 1;
1634 CLOCK_SetRootClock(kCLOCK_Root_Csi2_Esc, &rootCfg);
1635
1636 /* Configure CSI2_UI using OSC_RC_48M_DIV2 */
1637 rootCfg.mux = kCLOCK_CSI2_UI_ClockRoot_MuxOscRc48MDiv2;
1638 rootCfg.div = 1;
1639 CLOCK_SetRootClock(kCLOCK_Root_Csi2_Ui, &rootCfg);
1640
1641 /* Configure CSI using OSC_RC_48M_DIV2 */
1642 rootCfg.mux = kCLOCK_CSI_ClockRoot_MuxOscRc48MDiv2;
1643 rootCfg.div = 1;
1644 CLOCK_SetRootClock(kCLOCK_Root_Csi, &rootCfg);
1645
1646 /* Configure CKO1 using OSC_RC_48M_DIV2 */
1647 rootCfg.mux = kCLOCK_CKO1_ClockRoot_MuxOscRc48MDiv2;
1648 rootCfg.div = 1;
1649 CLOCK_SetRootClock(kCLOCK_Root_Cko1, &rootCfg);
1650
1651 /* Configure CKO2 using OSC_RC_48M_DIV2 */
1652 rootCfg.mux = kCLOCK_CKO2_ClockRoot_MuxOscRc48MDiv2;
1653 rootCfg.div = 1;
1654 CLOCK_SetRootClock(kCLOCK_Root_Cko2, &rootCfg);
1655
1656 /* Set SAI1 MCLK1 clock source. */
1657 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
1658 /* Set SAI1 MCLK2 clock source. */
1659 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 3);
1660 /* Set SAI1 MCLK3 clock source. */
1661 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
1662 /* Set SAI2 MCLK3 clock source. */
1663 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
1664 /* Set SAI3 MCLK3 clock source. */
1665 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
1666
1667 /* Set MQS configuration. */
1668 IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
1669 /* Set ENET Ref clock source. */
1670 IOMUXC_GPR->GPR4 &= ~IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_MASK;
1671 /* Set ENET_1G Tx clock source. */
1672 IOMUXC_GPR->GPR5 = ((IOMUXC_GPR->GPR5 & ~IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_MASK) | IOMUXC_GPR_GPR5_ENET1G_RGMII_EN_MASK);
1673 /* Set ENET_1G Ref clock source. */
1674 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_MASK;
1675 /* Set ENET_QOS Tx clock source. */
1676 IOMUXC_GPR->GPR6 &= ~IOMUXC_GPR_GPR6_ENET_QOS_RGMII_EN_MASK;
1677 /* Set ENET_QOS Ref clock source. */
1678 IOMUXC_GPR->GPR6 &= ~IOMUXC_GPR_GPR6_ENET_QOS_REF_CLK_DIR_MASK;
1679 /* Set GPT1 High frequency reference clock source. */
1680 IOMUXC_GPR->GPR22 &= ~IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1_MASK;
1681 /* Set GPT2 High frequency reference clock source. */
1682 IOMUXC_GPR->GPR23 &= ~IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2_MASK;
1683 /* Set GPT3 High frequency reference clock source. */
1684 IOMUXC_GPR->GPR24 &= ~IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3_MASK;
1685 /* Set GPT4 High frequency reference clock source. */
1686 IOMUXC_GPR->GPR25 &= ~IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4_MASK;
1687 /* Set GPT5 High frequency reference clock source. */
1688 IOMUXC_GPR->GPR26 &= ~IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5_MASK;
1689 /* Set GPT6 High frequency reference clock source. */
1690 IOMUXC_GPR->GPR27 &= ~IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6_MASK;
1691
1692 #if __CORTEX_M == 7
1693 SystemCoreClock = CLOCK_GetRootClockFreq(kCLOCK_Root_M7);
1694 #else
1695 SystemCoreClock = CLOCK_GetRootClockFreq(kCLOCK_Root_M4);
1696 #endif
1697 }
1698
