1 /*
2 * Copyright 2021-2022 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include "fsl_common.h"
9 #include "fsl_debug_console.h"
10 #include "board.h"
11 #if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
12 #include "fsl_lpi2c.h"
13 #endif /* SDK_I2C_BASED_COMPONENT_USED */
14 #include "fsl_iomuxc.h"
15
16 /*******************************************************************************
17 * Variables
18 ******************************************************************************/
19 /*******************************************************************************
20 * Code
21 ******************************************************************************/
22
23 /* Get debug console frequency. */
BOARD_DebugConsoleSrcFreq(void)24 uint32_t BOARD_DebugConsoleSrcFreq(void)
25 {
26 #if DEBUG_CONSOLE_UART_INDEX == 1
27 return CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart1);
28 #elif DEBUG_CONSOLE_UART_INDEX == 12
29 return CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart12);
30 #else
31 return CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart2);
32 #endif
33 }
34
35 /* Initialize debug console. */
BOARD_InitDebugConsole(void)36 void BOARD_InitDebugConsole(void)
37 {
38 uint32_t uartClkSrcFreq = BOARD_DebugConsoleSrcFreq();
39 DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
40 }
41
42 #if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
BOARD_LPI2C_Init(LPI2C_Type * base,uint32_t clkSrc_Hz)43 void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz)
44 {
45 lpi2c_master_config_t lpi2cConfig = {0};
46
47 /*
48 * lpi2cConfig.debugEnable = false;
49 * lpi2cConfig.ignoreAck = false;
50 * lpi2cConfig.pinConfig = kLPI2C_2PinOpenDrain;
51 * lpi2cConfig.baudRate_Hz = 100000U;
52 * lpi2cConfig.busIdleTimeout_ns = 0;
53 * lpi2cConfig.pinLowTimeout_ns = 0;
54 * lpi2cConfig.sdaGlitchFilterWidth_ns = 0;
55 * lpi2cConfig.sclGlitchFilterWidth_ns = 0;
56 */
57 LPI2C_MasterGetDefaultConfig(&lpi2cConfig);
58 LPI2C_MasterInit(base, &lpi2cConfig, clkSrc_Hz);
59 }
60
BOARD_LPI2C_Send(LPI2C_Type * base,uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,uint8_t * txBuff,uint8_t txBuffSize)61 status_t BOARD_LPI2C_Send(LPI2C_Type *base,
62 uint8_t deviceAddress,
63 uint32_t subAddress,
64 uint8_t subAddressSize,
65 uint8_t *txBuff,
66 uint8_t txBuffSize)
67 {
68 lpi2c_master_transfer_t xfer;
69
70 xfer.flags = kLPI2C_TransferDefaultFlag;
71 xfer.slaveAddress = deviceAddress;
72 xfer.direction = kLPI2C_Write;
73 xfer.subaddress = subAddress;
74 xfer.subaddressSize = subAddressSize;
75 xfer.data = txBuff;
76 xfer.dataSize = txBuffSize;
77
78 return LPI2C_MasterTransferBlocking(base, &xfer);
79 }
80
BOARD_LPI2C_Receive(LPI2C_Type * base,uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,uint8_t * rxBuff,uint8_t rxBuffSize)81 status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
82 uint8_t deviceAddress,
83 uint32_t subAddress,
84 uint8_t subAddressSize,
85 uint8_t *rxBuff,
86 uint8_t rxBuffSize)
87 {
88 lpi2c_master_transfer_t xfer;
89
90 xfer.flags = kLPI2C_TransferDefaultFlag;
91 xfer.slaveAddress = deviceAddress;
92 xfer.direction = kLPI2C_Read;
93 xfer.subaddress = subAddress;
94 xfer.subaddressSize = subAddressSize;
95 xfer.data = rxBuff;
96 xfer.dataSize = rxBuffSize;
97
98 return LPI2C_MasterTransferBlocking(base, &xfer);
99 }
100
BOARD_LPI2C_SendSCCB(LPI2C_Type * base,uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,uint8_t * txBuff,uint8_t txBuffSize)101 status_t BOARD_LPI2C_SendSCCB(LPI2C_Type *base,
102 uint8_t deviceAddress,
103 uint32_t subAddress,
104 uint8_t subAddressSize,
105 uint8_t *txBuff,
106 uint8_t txBuffSize)
107 {
108 lpi2c_master_transfer_t xfer;
109
110 xfer.flags = kLPI2C_TransferDefaultFlag;
111 xfer.slaveAddress = deviceAddress;
112 xfer.direction = kLPI2C_Write;
113 xfer.subaddress = subAddress;
114 xfer.subaddressSize = subAddressSize;
115 xfer.data = txBuff;
116 xfer.dataSize = txBuffSize;
117
118 return LPI2C_MasterTransferBlocking(base, &xfer);
119 }
120
BOARD_LPI2C_ReceiveSCCB(LPI2C_Type * base,uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,uint8_t * rxBuff,uint8_t rxBuffSize)121 status_t BOARD_LPI2C_ReceiveSCCB(LPI2C_Type *base,
122 uint8_t deviceAddress,
123 uint32_t subAddress,
124 uint8_t subAddressSize,
125 uint8_t *rxBuff,
126 uint8_t rxBuffSize)
127 {
128 status_t status;
129 lpi2c_master_transfer_t xfer;
130
131 xfer.flags = kLPI2C_TransferDefaultFlag;
132 xfer.slaveAddress = deviceAddress;
133 xfer.direction = kLPI2C_Write;
134 xfer.subaddress = subAddress;
135 xfer.subaddressSize = subAddressSize;
136 xfer.data = NULL;
137 xfer.dataSize = 0;
138
139 status = LPI2C_MasterTransferBlocking(base, &xfer);
140
141 if (kStatus_Success == status)
142 {
143 xfer.subaddressSize = 0;
144 xfer.direction = kLPI2C_Read;
145 xfer.data = rxBuff;
146 xfer.dataSize = rxBuffSize;
147
148 status = LPI2C_MasterTransferBlocking(base, &xfer);
149 }
150
151 return status;
152 }
153
BOARD_Accel_I2C_Init(void)154 void BOARD_Accel_I2C_Init(void)
155 {
156 BOARD_LPI2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
157 }
158
BOARD_Accel_I2C_Send(uint8_t deviceAddress,uint32_t subAddress,uint8_t subaddressSize,uint32_t txBuff)159 status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)
160 {
161 uint8_t data = (uint8_t)txBuff;
162
163 return BOARD_LPI2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);
164 }
165
BOARD_Accel_I2C_Receive(uint8_t deviceAddress,uint32_t subAddress,uint8_t subaddressSize,uint8_t * rxBuff,uint8_t rxBuffSize)166 status_t BOARD_Accel_I2C_Receive(
167 uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
168 {
169 return BOARD_LPI2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);
170 }
171
BOARD_Codec_I2C_Init(void)172 void BOARD_Codec_I2C_Init(void)
173 {
174 BOARD_LPI2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
175 }
176
BOARD_Codec_I2C_Send(uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,const uint8_t * txBuff,uint8_t txBuffSize)177 status_t BOARD_Codec_I2C_Send(
178 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
179 {
180 return BOARD_LPI2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
181 txBuffSize);
182 }
183
BOARD_Codec_I2C_Receive(uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,uint8_t * rxBuff,uint8_t rxBuffSize)184 status_t BOARD_Codec_I2C_Receive(
185 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
186 {
187 return BOARD_LPI2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
188 }
189
BOARD_Camera_I2C_Init(void)190 void BOARD_Camera_I2C_Init(void)
191 {
192 const clock_root_config_t lpi2cClockConfig = {
193 .clockOff = false,
194 .mux = BOARD_CAMERA_I2C_CLOCK_SOURCE,
195 .div = BOARD_CAMERA_I2C_CLOCK_DIVIDER,
196 };
197
198 CLOCK_SetRootClock(BOARD_CAMERA_I2C_CLOCK_ROOT, &lpi2cClockConfig);
199
200 BOARD_LPI2C_Init(BOARD_CAMERA_I2C_BASEADDR, CLOCK_GetRootClockFreq(BOARD_CAMERA_I2C_CLOCK_ROOT));
201 }
202
BOARD_Camera_I2C_Send(uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,const uint8_t * txBuff,uint8_t txBuffSize)203 status_t BOARD_Camera_I2C_Send(
204 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
205 {
206 return BOARD_LPI2C_Send(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
207 txBuffSize);
208 }
209
BOARD_Camera_I2C_Receive(uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,uint8_t * rxBuff,uint8_t rxBuffSize)210 status_t BOARD_Camera_I2C_Receive(
211 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
212 {
213 return BOARD_LPI2C_Receive(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff,
214 rxBuffSize);
215 }
216
BOARD_Camera_I2C_SendSCCB(uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,const uint8_t * txBuff,uint8_t txBuffSize)217 status_t BOARD_Camera_I2C_SendSCCB(
218 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
219 {
220 return BOARD_LPI2C_SendSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
221 txBuffSize);
222 }
223
BOARD_Camera_I2C_ReceiveSCCB(uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,uint8_t * rxBuff,uint8_t rxBuffSize)224 status_t BOARD_Camera_I2C_ReceiveSCCB(
225 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
226 {
227 return BOARD_LPI2C_ReceiveSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff,
228 rxBuffSize);
229 }
230
BOARD_MIPIPanelTouch_I2C_Init(void)231 void BOARD_MIPIPanelTouch_I2C_Init(void)
232 {
233 const clock_root_config_t lpi2cClockConfig = {
234 .clockOff = false,
235 .mux = BOARD_MIPI_PANEL_TOUCH_I2C_CLOCK_SOURCE,
236 .div = BOARD_MIPI_PANEL_TOUCH_I2C_CLOCK_DIVIDER,
237 };
238
239 CLOCK_SetRootClock(BOARD_MIPI_PANEL_TOUCH_I2C_CLOCK_ROOT, &lpi2cClockConfig);
240
241 BOARD_LPI2C_Init(BOARD_MIPI_PANEL_TOUCH_I2C_BASEADDR,
242 CLOCK_GetRootClockFreq(BOARD_MIPI_PANEL_TOUCH_I2C_CLOCK_ROOT));
243 }
244
BOARD_MIPIPanelTouch_I2C_Send(uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,const uint8_t * txBuff,uint8_t txBuffSize)245 status_t BOARD_MIPIPanelTouch_I2C_Send(
246 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
247 {
248 return BOARD_LPI2C_Send(BOARD_MIPI_PANEL_TOUCH_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize,
249 (uint8_t *)txBuff, txBuffSize);
250 }
251
BOARD_MIPIPanelTouch_I2C_Receive(uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,uint8_t * rxBuff,uint8_t rxBuffSize)252 status_t BOARD_MIPIPanelTouch_I2C_Receive(
253 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
254 {
255 return BOARD_LPI2C_Receive(BOARD_MIPI_PANEL_TOUCH_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff,
256 rxBuffSize);
257 }
258 #endif /* SDK_I2C_BASED_COMPONENT_USED */
259
260 /* MPU configuration. */
261 #if __CORTEX_M == 7
BOARD_ConfigMPU(void)262 void BOARD_ConfigMPU(void)
263 {
264 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
265 extern uint32_t Image$$RW_m_ncache$$Base[];
266 /* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */
267 extern uint32_t Image$$RW_m_ncache_unused$$Base[];
268 extern uint32_t Image$$RW_m_ncache_unused$$ZI$$Limit[];
269 uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base;
270 uint32_t size = ((uint32_t)Image$$RW_m_ncache_unused$$Base == nonCacheStart) ?
271 0 :
272 ((uint32_t)Image$$RW_m_ncache_unused$$ZI$$Limit - nonCacheStart);
273 #elif defined(__MCUXPRESSO)
274 #if defined(__USE_SHMEM)
275 extern uint32_t __base_rpmsg_sh_mem;
276 extern uint32_t __top_rpmsg_sh_mem;
277 uint32_t nonCacheStart = (uint32_t)(&__base_rpmsg_sh_mem);
278 uint32_t size = (uint32_t)(&__top_rpmsg_sh_mem) - nonCacheStart;
279 #else
280 extern uint32_t __base_NCACHE_REGION;
281 extern uint32_t __top_NCACHE_REGION;
282 uint32_t nonCacheStart = (uint32_t)(&__base_NCACHE_REGION);
283 uint32_t size = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart;
284 #endif
285 #elif defined(__ICCARM__) || defined(__GNUC__)
286 extern uint32_t __NCACHE_REGION_START[];
287 extern uint32_t __NCACHE_REGION_SIZE[];
288 uint32_t nonCacheStart = (uint32_t)__NCACHE_REGION_START;
289 uint32_t size = (uint32_t)__NCACHE_REGION_SIZE;
290 #endif
291 volatile uint32_t i = 0;
292
293 #if defined(__ICACHE_PRESENT) && __ICACHE_PRESENT
294 /* Disable I cache and D cache */
295 if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR))
296 {
297 SCB_DisableICache();
298 }
299 #endif
300 #if defined(__DCACHE_PRESENT) && __DCACHE_PRESENT
301 if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR))
302 {
303 SCB_DisableDCache();
304 }
305 #endif
306
307 /* Disable MPU */
308 ARM_MPU_Disable();
309
310 /* MPU configure:
311 * Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable,
312 * SubRegionDisable, Size)
313 * API in mpu_armv7.h.
314 * param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches
315 * disabled.
316 * param AccessPermission Data access permissions, allows you to configure read/write access for User and
317 * Privileged mode.
318 * Use MACROS defined in mpu_armv7.h:
319 * ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
320 * Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes.
321 * TypeExtField IsShareable IsCacheable IsBufferable Memory Attribute Shareability Cache
322 * 0 x 0 0 Strongly Ordered shareable
323 * 0 x 0 1 Device shareable
324 * 0 0 1 0 Normal not shareable Outer and inner write
325 * through no write allocate
326 * 0 0 1 1 Normal not shareable Outer and inner write
327 * back no write allocate
328 * 0 1 1 0 Normal shareable Outer and inner write
329 * through no write allocate
330 * 0 1 1 1 Normal shareable Outer and inner write
331 * back no write allocate
332 * 1 0 0 0 Normal not shareable outer and inner
333 * noncache
334 * 1 1 0 0 Normal shareable outer and inner
335 * noncache
336 * 1 0 1 1 Normal not shareable outer and inner write
337 * back write/read acllocate
338 * 1 1 1 1 Normal shareable outer and inner write
339 * back write/read acllocate
340 * 2 x 0 0 Device not shareable
341 * Above are normal use settings, if your want to see more details or want to config different inner/outter cache
342 * policy.
343 * please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide <dui0646b_cortex_m7_dgug.pdf>
344 * param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled.
345 * param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in
346 * mpu_armv7.h.
347 */
348
349 /*
350 * Add default region to deny access to whole address space to workaround speculative prefetch.
351 * Refer to Arm errata 1013783-B for more details.
352 *
353 */
354 /* Region 0 setting: Instruction access disabled, No data access permission. */
355 MPU->RBAR = ARM_MPU_RBAR(0, 0x00000000U);
356 MPU->RASR = ARM_MPU_RASR(1, ARM_MPU_AP_NONE, 0, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4GB);
357
358 /* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */
359 MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
360 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
361
362 /* Region 2 setting: Memory with Device type, not shareable, non-cacheable. */
363 MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
364 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
365
366 /* Region 3 setting: Memory with Device type, not shareable, non-cacheable. */
367 MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U);
368 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
369
370 /* Region 4 setting: Memory with Normal type, not shareable, outer/inner write back */
371 MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
372 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
373
374 /* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */
375 MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U);
376 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
377
378 #if defined(CACHE_MODE_WRITE_THROUGH) && CACHE_MODE_WRITE_THROUGH
379 /* Region 6 setting: Memory with Normal type, not shareable, write through */
380 MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U);
381 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_1MB);
382
383 /* Region 7 setting: Memory with Normal type, not shareable, write trough */
384 MPU->RBAR = ARM_MPU_RBAR(7, 0x20300000U);
385 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_512KB);
386 #else
387 /* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */
388 MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U);
389 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_1MB);
390
391 /* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */
392 MPU->RBAR = ARM_MPU_RBAR(7, 0x20300000U);
393 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_512KB);
394 #endif
395
396 #if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
397 /* Region 8 setting: Memory with Normal type, not shareable, outer/inner write back. */
398 MPU->RBAR = ARM_MPU_RBAR(8, 0x30000000U);
399 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_16MB);
400 #endif
401
402 #ifdef USE_SDRAM
403 #if defined(CACHE_MODE_WRITE_THROUGH) && CACHE_MODE_WRITE_THROUGH
404 /* Region 9 setting: Memory with Normal type, not shareable, write trough */
405 MPU->RBAR = ARM_MPU_RBAR(9, 0x80000000U);
406 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_64MB);
407 #else
408 /* Region 9 setting: Memory with Normal type, not shareable, outer/inner write back */
409 MPU->RBAR = ARM_MPU_RBAR(9, 0x80000000U);
410 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64MB);
411 #endif
412 #endif
413
414 while ((size >> i) > 0x1U)
415 {
416 i++;
417 }
418
419 if (i != 0)
420 {
421 /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
422 assert(!(nonCacheStart % size));
423 assert(size == (uint32_t)(1 << i));
424 assert(i >= 5);
425
426 /* Region 10 setting: Memory with Normal type, not shareable, non-cacheable */
427 MPU->RBAR = ARM_MPU_RBAR(10, nonCacheStart);
428 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, i - 1);
429 }
430
431 /* Region 11 setting: Memory with Device type, not shareable, non-cacheable */
432 MPU->RBAR = ARM_MPU_RBAR(11, 0x40000000);
433 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_16MB);
434
435 /* Region 12 setting: Memory with Device type, not shareable, non-cacheable */
436 MPU->RBAR = ARM_MPU_RBAR(12, 0x41000000);
437 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB);
438
439 /* Region 13 setting: Memory with Device type, not shareable, non-cacheable */
440 MPU->RBAR = ARM_MPU_RBAR(13, 0x41400000);
441 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1MB);
442
443 /* Region 14 setting: Memory with Device type, not shareable, non-cacheable */
444 MPU->RBAR = ARM_MPU_RBAR(14, 0x41800000);
445 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB);
446
447 /* Region 15 setting: Memory with Device type, not shareable, non-cacheable */
448 MPU->RBAR = ARM_MPU_RBAR(15, 0x42000000);
449 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1MB);
450
451 /* Enable MPU */
452 ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk);
453
454 /* Enable I cache and D cache */
455 #if defined(__DCACHE_PRESENT) && __DCACHE_PRESENT
456 SCB_EnableDCache();
457 #endif
458 #if defined(__ICACHE_PRESENT) && __ICACHE_PRESENT
459 SCB_EnableICache();
460 #endif
461 }
462 #elif __CORTEX_M == 4
BOARD_ConfigMPU(void)463 void BOARD_ConfigMPU(void)
464 {
465 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
466 extern uint32_t Image$$RW_m_ncache$$Base[];
467 /* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */
468 extern uint32_t Image$$RW_m_ncache_unused$$Base[];
469 extern uint32_t Image$$RW_m_ncache_unused$$ZI$$Limit[];
470 uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base;
471 uint32_t nonCacheSize = ((uint32_t)Image$$RW_m_ncache_unused$$Base == nonCacheStart) ?
472 0 :
473 ((uint32_t)Image$$RW_m_ncache_unused$$ZI$$Limit - nonCacheStart);
474 #elif defined(__MCUXPRESSO)
475 extern uint32_t __base_NCACHE_REGION;
476 extern uint32_t __top_NCACHE_REGION;
477 uint32_t nonCacheStart = (uint32_t)(&__base_NCACHE_REGION);
478 uint32_t nonCacheSize = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart;
479 #elif defined(__ICCARM__) || defined(__GNUC__)
480 extern uint32_t __NCACHE_REGION_START[];
481 extern uint32_t __NCACHE_REGION_SIZE[];
482 uint32_t nonCacheStart = (uint32_t)__NCACHE_REGION_START;
483 uint32_t nonCacheSize = (uint32_t)__NCACHE_REGION_SIZE;
484 #endif
485 #if defined(__USE_SHMEM)
486 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
487 extern uint32_t Image$$RPMSG_SH_MEM$$Base[];
488 /* RPMSG_SH_MEM_unused is a auxiliary region which is used to get the whole size of RPMSG_SH_MEM section */
489 extern uint32_t Image$$RPMSG_SH_MEM_unused$$Base[];
490 extern uint32_t Image$$RPMSG_SH_MEM_unused$$ZI$$Limit[];
491 uint32_t rpmsgShmemStart = (uint32_t)Image$$RPMSG_SH_MEM$$Base;
492 uint32_t rpmsgShmemSize = (uint32_t)Image$$RPMSG_SH_MEM_unused$$ZI$$Limit - rpmsgShmemStart;
493 #elif defined(__MCUXPRESSO)
494 extern uint32_t __base_rpmsg_sh_mem;
495 extern uint32_t __top_rpmsg_sh_mem;
496 uint32_t rpmsgShmemStart = (uint32_t)(&__base_rpmsg_sh_mem);
497 uint32_t rpmsgShmemSize = (uint32_t)(&__top_rpmsg_sh_mem) - rpmsgShmemStart;
498 #elif defined(__ICCARM__) || defined(__GNUC__)
499 extern uint32_t __RPMSG_SH_MEM_START[];
500 extern uint32_t __RPMSG_SH_MEM_SIZE[];
501 uint32_t rpmsgShmemStart = (uint32_t)__RPMSG_SH_MEM_START;
502 uint32_t rpmsgShmemSize = (uint32_t)__RPMSG_SH_MEM_SIZE;
503 #endif
504 #endif
505 uint32_t i = 0;
506
507 /* Only config non-cacheable region on system bus */
508 assert(nonCacheStart >= 0x20000000);
509
510 /* Disable code bus cache */
511 if (LMEM_PCCCR_ENCACHE_MASK == (LMEM_PCCCR_ENCACHE_MASK & LMEM->PCCCR))
512 {
513 /* Enable the processor code bus to push all modified lines. */
514 LMEM->PCCCR |= LMEM_PCCCR_PUSHW0_MASK | LMEM_PCCCR_PUSHW1_MASK | LMEM_PCCCR_GO_MASK;
515 /* Wait until the cache command completes. */
516 while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0U)
517 {
518 }
519 /* As a precaution clear the bits to avoid inadvertently re-running this command. */
520 LMEM->PCCCR &= ~(LMEM_PCCCR_PUSHW0_MASK | LMEM_PCCCR_PUSHW1_MASK);
521 /* Now disable the cache. */
522 LMEM->PCCCR &= ~LMEM_PCCCR_ENCACHE_MASK;
523 }
524
525 /* Disable system bus cache */
526 if (LMEM_PSCCR_ENCACHE_MASK == (LMEM_PSCCR_ENCACHE_MASK & LMEM->PSCCR))
527 {
528 /* Enable the processor system bus to push all modified lines. */
529 LMEM->PSCCR |= LMEM_PSCCR_PUSHW0_MASK | LMEM_PSCCR_PUSHW1_MASK | LMEM_PSCCR_GO_MASK;
530 /* Wait until the cache command completes. */
531 while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0U)
532 {
533 }
534 /* As a precaution clear the bits to avoid inadvertently re-running this command. */
535 LMEM->PSCCR &= ~(LMEM_PSCCR_PUSHW0_MASK | LMEM_PSCCR_PUSHW1_MASK);
536 /* Now disable the cache. */
537 LMEM->PSCCR &= ~LMEM_PSCCR_ENCACHE_MASK;
538 }
539
540 /* Disable MPU */
541 ARM_MPU_Disable();
542
543 #if defined(CACHE_MODE_WRITE_THROUGH) && CACHE_MODE_WRITE_THROUGH
544 /* Region 0 setting: Memory with Normal type, not shareable, write trough */
545 MPU->RBAR = ARM_MPU_RBAR(0, 0x20200000U);
546 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_1MB);
547
548 /* Region 1 setting: Memory with Normal type, not shareable, write through */
549 MPU->RBAR = ARM_MPU_RBAR(1, 0x20300000U);
550 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_512KB);
551
552 /* Region 2 setting: Memory with Normal type, not shareable, write through */
553 MPU->RBAR = ARM_MPU_RBAR(2, 0x80000000U);
554 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_64MB);
555
556 while ((nonCacheSize >> i) > 0x1U)
557 {
558 i++;
559 }
560
561 if (i != 0)
562 {
563 /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
564 assert(!(nonCacheStart % nonCacheSize));
565 assert(nonCacheSize == (uint32_t)(1 << i));
566 assert(i >= 5);
567
568 /* Region 3 setting: Memory with device type, not shareable, non-cacheable */
569 MPU->RBAR = ARM_MPU_RBAR(3, nonCacheStart);
570 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, i - 1);
571 }
572
573 #if defined(__USE_SHMEM)
574 i = 0;
575
576 while ((rpmsgShmemSize >> i) > 0x1U)
577 {
578 i++;
579 }
580
581 if (i != 0)
582 {
583 /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
584 assert(!(rpmsgShmemStart % rpmsgShmemSize));
585 assert(rpmsgShmemSize == (uint32_t)(1 << i));
586 assert(i >= 5);
587
588 /* Region 4 setting: Memory with device type, not shareable, non-cacheable */
589 MPU->RBAR = ARM_MPU_RBAR(4, rpmsgShmemStart);
590 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, i - 1);
591 }
592 #endif
593 #else
594 while ((nonCacheSize >> i) > 0x1U)
595 {
596 i++;
597 }
598
599 if (i != 0)
600 {
601 /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
602 assert(!(nonCacheStart % nonCacheSize));
603 assert(nonCacheSize == (uint32_t)(1 << i));
604 assert(i >= 5);
605
606 /* Region 0 setting: Memory with device type, not shareable, non-cacheable */
607 MPU->RBAR = ARM_MPU_RBAR(0, nonCacheStart);
608 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, i - 1);
609 }
610
611 #if defined(__USE_SHMEM)
612 i = 0;
613
614 while ((rpmsgShmemSize >> i) > 0x1U)
615 {
616 i++;
617 }
618
619 if (i != 0)
620 {
621 /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
622 assert(!(rpmsgShmemStart % rpmsgShmemSize));
623 assert(rpmsgShmemSize == (uint32_t)(1 << i));
624 assert(i >= 5);
625
626 /* Region 1 setting: Memory with device type, not shareable, non-cacheable */
627 MPU->RBAR = ARM_MPU_RBAR(1, rpmsgShmemStart);
628 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, i - 1);
629 }
630 #endif
631 #endif
632
633 /* Enable MPU */
634 ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk);
635
636 /* Enables the processor system bus to invalidate all lines in both ways.
637 and Initiate the processor system bus cache command. */
638 LMEM->PSCCR |= LMEM_PSCCR_INVW0_MASK | LMEM_PSCCR_INVW1_MASK | LMEM_PSCCR_GO_MASK;
639 /* Wait until the cache command completes */
640 while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0U)
641 {
642 }
643 /* As a precaution clear the bits to avoid inadvertently re-running this command. */
644 LMEM->PSCCR &= ~(LMEM_PSCCR_INVW0_MASK | LMEM_PSCCR_INVW1_MASK);
645 /* Now enable the system bus cache. */
646 LMEM->PSCCR |= LMEM_PSCCR_ENCACHE_MASK;
647
648 /* Enables the processor code bus to invalidate all lines in both ways.
649 and Initiate the processor code bus code cache command. */
650 LMEM->PCCCR |= LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_GO_MASK;
651 /* Wait until the cache command completes. */
652 while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0U)
653 {
654 }
655 /* As a precaution clear the bits to avoid inadvertently re-running this command. */
656 LMEM->PCCCR &= ~(LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_INVW1_MASK);
657 /* Now enable the code bus cache. */
658 LMEM->PCCCR |= LMEM_PCCCR_ENCACHE_MASK;
659 }
660 #endif
661
BOARD_SD_Pin_Config(uint32_t speed,uint32_t strength)662 void BOARD_SD_Pin_Config(uint32_t speed, uint32_t strength)
663 {
664 }
665
BOARD_MMC_Pin_Config(uint32_t speed,uint32_t strength)666 void BOARD_MMC_Pin_Config(uint32_t speed, uint32_t strength)
667 {
668 }
669
