1 /*
2 * Copyright 2018-2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include "fsl_common.h"
9 #include "fsl_debug_console.h"
10 #include "board.h"
11 #if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
12 #include "fsl_lpi2c.h"
13 #endif /* SDK_I2C_BASED_COMPONENT_USED */
14 #include "fsl_iomuxc.h"
15
16 /*******************************************************************************
17 * Variables
18 ******************************************************************************/
19
20 /*******************************************************************************
21 * Code
22 ******************************************************************************/
23
24 /* Get debug console frequency. */
BOARD_DebugConsoleSrcFreq(void)25 uint32_t BOARD_DebugConsoleSrcFreq(void)
26 {
27 uint32_t freq;
28
29 /* To make it simple, we assume default PLL and divider settings, and the only variable
30 from application is use PLL3 source or OSC source */
31 if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */
32 {
33 freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
34 }
35 else
36 {
37 freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
38 }
39
40 return freq;
41 }
42
43 /* Initialize debug console. */
BOARD_InitDebugConsole(void)44 void BOARD_InitDebugConsole(void)
45 {
46 uint32_t uartClkSrcFreq = BOARD_DebugConsoleSrcFreq();
47
48 DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
49 }
50
51 #if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
BOARD_LPI2C_Init(LPI2C_Type * base,uint32_t clkSrc_Hz)52 void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz)
53 {
54 lpi2c_master_config_t lpi2cConfig = {0};
55
56 /*
57 * lpi2cConfig.debugEnable = false;
58 * lpi2cConfig.ignoreAck = false;
59 * lpi2cConfig.pinConfig = kLPI2C_2PinOpenDrain;
60 * lpi2cConfig.baudRate_Hz = 100000U;
61 * lpi2cConfig.busIdleTimeout_ns = 0;
62 * lpi2cConfig.pinLowTimeout_ns = 0;
63 * lpi2cConfig.sdaGlitchFilterWidth_ns = 0;
64 * lpi2cConfig.sclGlitchFilterWidth_ns = 0;
65 */
66 LPI2C_MasterGetDefaultConfig(&lpi2cConfig);
67 LPI2C_MasterInit(base, &lpi2cConfig, clkSrc_Hz);
68 }
69
BOARD_LPI2C_Send(LPI2C_Type * base,uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,uint8_t * txBuff,uint8_t txBuffSize)70 status_t BOARD_LPI2C_Send(LPI2C_Type *base,
71 uint8_t deviceAddress,
72 uint32_t subAddress,
73 uint8_t subAddressSize,
74 uint8_t *txBuff,
75 uint8_t txBuffSize)
76 {
77 lpi2c_master_transfer_t xfer;
78
79 xfer.flags = kLPI2C_TransferDefaultFlag;
80 xfer.slaveAddress = deviceAddress;
81 xfer.direction = kLPI2C_Write;
82 xfer.subaddress = subAddress;
83 xfer.subaddressSize = subAddressSize;
84 xfer.data = txBuff;
85 xfer.dataSize = txBuffSize;
86
87 return LPI2C_MasterTransferBlocking(base, &xfer);
88 }
89
BOARD_LPI2C_Receive(LPI2C_Type * base,uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,uint8_t * rxBuff,uint8_t rxBuffSize)90 status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
91 uint8_t deviceAddress,
92 uint32_t subAddress,
93 uint8_t subAddressSize,
94 uint8_t *rxBuff,
95 uint8_t rxBuffSize)
96 {
97 lpi2c_master_transfer_t xfer;
98
99 xfer.flags = kLPI2C_TransferDefaultFlag;
100 xfer.slaveAddress = deviceAddress;
101 xfer.direction = kLPI2C_Read;
102 xfer.subaddress = subAddress;
103 xfer.subaddressSize = subAddressSize;
104 xfer.data = rxBuff;
105 xfer.dataSize = rxBuffSize;
106
107 return LPI2C_MasterTransferBlocking(base, &xfer);
108 }
109
BOARD_LPI2C_SendSCCB(LPI2C_Type * base,uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,uint8_t * txBuff,uint8_t txBuffSize)110 status_t BOARD_LPI2C_SendSCCB(LPI2C_Type *base,
111 uint8_t deviceAddress,
112 uint32_t subAddress,
113 uint8_t subAddressSize,
114 uint8_t *txBuff,
115 uint8_t txBuffSize)
116 {
117 lpi2c_master_transfer_t xfer;
118
119 xfer.flags = kLPI2C_TransferDefaultFlag;
120 xfer.slaveAddress = deviceAddress;
121 xfer.direction = kLPI2C_Write;
122 xfer.subaddress = subAddress;
123 xfer.subaddressSize = subAddressSize;
124 xfer.data = txBuff;
125 xfer.dataSize = txBuffSize;
126
127 return LPI2C_MasterTransferBlocking(base, &xfer);
128 }
129
BOARD_LPI2C_ReceiveSCCB(LPI2C_Type * base,uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,uint8_t * rxBuff,uint8_t rxBuffSize)130 status_t BOARD_LPI2C_ReceiveSCCB(LPI2C_Type *base,
131 uint8_t deviceAddress,
132 uint32_t subAddress,
133 uint8_t subAddressSize,
134 uint8_t *rxBuff,
135 uint8_t rxBuffSize)
136 {
137 status_t status;
138 lpi2c_master_transfer_t xfer;
139
140 xfer.flags = kLPI2C_TransferDefaultFlag;
141 xfer.slaveAddress = deviceAddress;
142 xfer.direction = kLPI2C_Write;
143 xfer.subaddress = subAddress;
144 xfer.subaddressSize = subAddressSize;
145 xfer.data = NULL;
146 xfer.dataSize = 0;
147
148 status = LPI2C_MasterTransferBlocking(base, &xfer);
149
150 if (kStatus_Success == status)
151 {
152 xfer.subaddressSize = 0;
153 xfer.direction = kLPI2C_Read;
154 xfer.data = rxBuff;
155 xfer.dataSize = rxBuffSize;
156
157 status = LPI2C_MasterTransferBlocking(base, &xfer);
158 }
159
160 return status;
161 }
162
BOARD_Accel_I2C_Init(void)163 void BOARD_Accel_I2C_Init(void)
164 {
165 BOARD_LPI2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
166 }
167
BOARD_Accel_I2C_Send(uint8_t deviceAddress,uint32_t subAddress,uint8_t subaddressSize,uint32_t txBuff)168 status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)
169 {
170 uint8_t data = (uint8_t)txBuff;
171
172 return BOARD_LPI2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);
173 }
174
BOARD_Accel_I2C_Receive(uint8_t deviceAddress,uint32_t subAddress,uint8_t subaddressSize,uint8_t * rxBuff,uint8_t rxBuffSize)175 status_t BOARD_Accel_I2C_Receive(
176 uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
177 {
178 return BOARD_LPI2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);
179 }
180
BOARD_Codec_I2C_Init(void)181 void BOARD_Codec_I2C_Init(void)
182 {
183 BOARD_LPI2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
184 }
185
BOARD_Codec_I2C_Send(uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,const uint8_t * txBuff,uint8_t txBuffSize)186 status_t BOARD_Codec_I2C_Send(
187 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
188 {
189 return BOARD_LPI2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
190 txBuffSize);
191 }
192
BOARD_Codec_I2C_Receive(uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,uint8_t * rxBuff,uint8_t rxBuffSize)193 status_t BOARD_Codec_I2C_Receive(
194 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
195 {
196 return BOARD_LPI2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
197 }
198
BOARD_Camera_I2C_Init(void)199 void BOARD_Camera_I2C_Init(void)
200 {
201 CLOCK_SetMux(kCLOCK_Lpi2cMux, BOARD_CAMERA_I2C_CLOCK_SOURCE_SELECT);
202 CLOCK_SetDiv(kCLOCK_Lpi2cDiv, BOARD_CAMERA_I2C_CLOCK_SOURCE_DIVIDER);
203 BOARD_LPI2C_Init(BOARD_CAMERA_I2C_BASEADDR, BOARD_CAMERA_I2C_CLOCK_FREQ);
204 }
205
BOARD_Camera_I2C_Send(uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,const uint8_t * txBuff,uint8_t txBuffSize)206 status_t BOARD_Camera_I2C_Send(
207 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
208 {
209 return BOARD_LPI2C_Send(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
210 txBuffSize);
211 }
212
BOARD_Camera_I2C_Receive(uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,uint8_t * rxBuff,uint8_t rxBuffSize)213 status_t BOARD_Camera_I2C_Receive(
214 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
215 {
216 return BOARD_LPI2C_Receive(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff,
217 rxBuffSize);
218 }
219
BOARD_Camera_I2C_SendSCCB(uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,const uint8_t * txBuff,uint8_t txBuffSize)220 status_t BOARD_Camera_I2C_SendSCCB(
221 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
222 {
223 return BOARD_LPI2C_SendSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
224 txBuffSize);
225 }
226
BOARD_Camera_I2C_ReceiveSCCB(uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,uint8_t * rxBuff,uint8_t rxBuffSize)227 status_t BOARD_Camera_I2C_ReceiveSCCB(
228 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
229 {
230 return BOARD_LPI2C_ReceiveSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff,
231 rxBuffSize);
232 }
233
BOARD_Touch_I2C_Send(uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,const uint8_t * txBuff,uint8_t txBuffSize)234 status_t BOARD_Touch_I2C_Send(
235 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
236 {
237 return BOARD_LPI2C_Send(BOARD_TOUCH_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
238 txBuffSize);
239 }
240
BOARD_Touch_I2C_Receive(uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,uint8_t * rxBuff,uint8_t rxBuffSize)241 status_t BOARD_Touch_I2C_Receive(
242 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
243 {
244 return BOARD_LPI2C_Receive(BOARD_TOUCH_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
245 }
246 #endif /* SDK_I2C_BASED_COMPONENT_USED */
247
248 /* MPU configuration. */
BOARD_ConfigMPU(void)249 void BOARD_ConfigMPU(void)
250 {
251 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
252 extern uint32_t Image$$RW_m_ncache$$Base[];
253 /* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */
254 extern uint32_t Image$$RW_m_ncache_unused$$Base[];
255 extern uint32_t Image$$RW_m_ncache_unused$$ZI$$Limit[];
256 uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base;
257 uint32_t size = ((uint32_t)Image$$RW_m_ncache_unused$$Base == nonCacheStart) ?
258 0 :
259 ((uint32_t)Image$$RW_m_ncache_unused$$ZI$$Limit - nonCacheStart);
260 #elif defined(__MCUXPRESSO)
261 extern uint32_t __base_NCACHE_REGION;
262 extern uint32_t __top_NCACHE_REGION;
263 uint32_t nonCacheStart = (uint32_t)(&__base_NCACHE_REGION);
264 uint32_t size = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart;
265 #elif defined(__ICCARM__) || defined(__GNUC__)
266 extern uint32_t __NCACHE_REGION_START[];
267 extern uint32_t __NCACHE_REGION_SIZE[];
268 uint32_t nonCacheStart = (uint32_t)__NCACHE_REGION_START;
269 uint32_t size = (uint32_t)__NCACHE_REGION_SIZE;
270 #endif
271 volatile uint32_t i = 0;
272
273 /* Disable I cache and D cache */
274 if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR))
275 {
276 SCB_DisableICache();
277 }
278 if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR))
279 {
280 SCB_DisableDCache();
281 }
282
283 /* Disable MPU */
284 ARM_MPU_Disable();
285
286 /* MPU configure:
287 * Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable,
288 * SubRegionDisable, Size)
289 * API in mpu_armv7.h.
290 * param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches
291 * disabled.
292 * param AccessPermission Data access permissions, allows you to configure read/write access for User and
293 * Privileged mode.
294 * Use MACROS defined in mpu_armv7.h:
295 * ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
296 * Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes.
297 * TypeExtField IsShareable IsCacheable IsBufferable Memory Attribute Shareability Cache
298 * 0 x 0 0 Strongly Ordered shareable
299 * 0 x 0 1 Device shareable
300 * 0 0 1 0 Normal not shareable Outer and inner write
301 * through no write allocate
302 * 0 0 1 1 Normal not shareable Outer and inner write
303 * back no write allocate
304 * 0 1 1 0 Normal shareable Outer and inner write
305 * through no write allocate
306 * 0 1 1 1 Normal shareable Outer and inner write
307 * back no write allocate
308 * 1 0 0 0 Normal not shareable outer and inner
309 * noncache
310 * 1 1 0 0 Normal shareable outer and inner
311 * noncache
312 * 1 0 1 1 Normal not shareable outer and inner write
313 * back write/read acllocate
314 * 1 1 1 1 Normal shareable outer and inner write
315 * back write/read acllocate
316 * 2 x 0 0 Device not shareable
317 * Above are normal use settings, if your want to see more details or want to config different inner/outter cache
318 * policy.
319 * please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide <dui0646b_cortex_m7_dgug.pdf>
320 * param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled.
321 * param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in
322 * mpu_armv7.h.
323 */
324 /*
325 * Add default region to deny access to whole address space to workaround speculative prefetch.
326 * Refer to Arm errata 1013783-B for more details.
327 *
328 */
329 /* Region 0 setting: Instruction access disabled, No data access permission. */
330 MPU->RBAR = ARM_MPU_RBAR(0, 0x00000000U);
331 MPU->RASR = ARM_MPU_RASR(1, ARM_MPU_AP_NONE, 0, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4GB);
332
333 /* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */
334 MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
335 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
336
337 /* Region 2 setting: Memory with Device type, not shareable, non-cacheable. */
338 MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
339 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
340
341 #if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
342 /* Region 3 setting: Memory with Normal type, not shareable, outer/inner write back. */
343 MPU->RBAR = ARM_MPU_RBAR(3, 0x70000000U);
344 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_4MB);
345 #endif
346
347 /* Region 4 setting: Memory with Device type, not shareable, non-cacheable. */
348 MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
349 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
350
351 /* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */
352 MPU->RBAR = ARM_MPU_RBAR(5, 0x00000000U);
353 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
354
355 /* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */
356 MPU->RBAR = ARM_MPU_RBAR(6, 0x20000000U);
357 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
358
359 /* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */
360 MPU->RBAR = ARM_MPU_RBAR(7, 0x20200000U);
361 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_512KB);
362
363 /* Region 8 setting: Memory with Normal type, not shareable, outer/inner write back */
364 MPU->RBAR = ARM_MPU_RBAR(8, 0x20280000U);
365 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
366
367 /* Region 9 setting: Memory with Normal type, not shareable, outer/inner write back */
368 MPU->RBAR = ARM_MPU_RBAR(9, 0x80000000U);
369 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
370
371 while ((size >> i) > 0x1U)
372 {
373 i++;
374 }
375
376 if (i != 0)
377 {
378 /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
379 assert(!(nonCacheStart % size));
380 assert(size == (uint32_t)(1 << i));
381 assert(i >= 5);
382
383 /* Region 10 setting: Memory with Normal type, not shareable, non-cacheable */
384 MPU->RBAR = ARM_MPU_RBAR(10, nonCacheStart);
385 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, i - 1);
386 }
387
388 /* Region 11 setting: Memory with Device type, not shareable, non-cacheable */
389 MPU->RBAR = ARM_MPU_RBAR(11, 0x40000000);
390 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4MB);
391
392 /* Region 12 setting: Memory with Device type, not shareable, non-cacheable */
393 MPU->RBAR = ARM_MPU_RBAR(12, 0x42000000);
394 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1MB);
395
396 /* Enable MPU */
397 ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk);
398
399 /* Enable I cache and D cache */
400 SCB_EnableDCache();
401 SCB_EnableICache();
402 }
403
