1 /*
2 * Copyright 2022 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 /*
9 * How to setup clock using clock driver functions:
10 *
11 * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
12 *
13 * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
14 *
15 * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
16 *
17 * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
18 *
19 * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
20 *
21 */
22
23 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
24 !!GlobalInfo
25 product: Clocks v10.0
26 processor: MIMXRT1062xxxxA
27 package_id: MIMXRT1062DVL6A
28 mcu_data: ksdk2_0
29 processor_version: 0.12.9
30 board: MIMXRT1060-EVK
31 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
32
33 #include "clock_config.h"
34 #include "fsl_iomuxc.h"
35
36 /*******************************************************************************
37 * Definitions
38 ******************************************************************************/
39
40 /*******************************************************************************
41 * Variables
42 ******************************************************************************/
43
44 /*******************************************************************************
45 ************************ BOARD_InitBootClocks function ************************
46 ******************************************************************************/
BOARD_InitBootClocks(void)47 void BOARD_InitBootClocks(void)
48 {
49 BOARD_BootClockRUN();
50 }
51
52 /*******************************************************************************
53 ********************** Configuration BOARD_BootClockRUN ***********************
54 ******************************************************************************/
55 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
56 !!Configuration
57 name: BOARD_BootClockRUN
58 called_from_default_init: true
59 outputs:
60 - {id: AHB_CLK_ROOT.outFreq, value: 600 MHz}
61 - {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
62 - {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
63 - {id: CLK_1M.outFreq, value: 1 MHz}
64 - {id: CLK_24M.outFreq, value: 24 MHz}
65 - {id: CSI_CLK_ROOT.outFreq, value: 12 MHz}
66 - {id: ENET2_125M_CLK.outFreq, value: 1.2 MHz}
67 - {id: ENET_125M_CLK.outFreq, value: 2.4 MHz}
68 - {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
69 - {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
70 - {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz}
71 - {id: FLEXSPI2_CLK_ROOT.outFreq, value: 1440/11 MHz}
72 - {id: FLEXSPI_CLK_ROOT.outFreq, value: 1440/11 MHz}
73 - {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz}
74 - {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz}
75 - {id: IPG_CLK_ROOT.outFreq, value: 150 MHz}
76 - {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz}
77 - {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
78 - {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
79 - {id: LVDS1_CLK.outFreq, value: 1.2 GHz}
80 - {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
81 - {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz}
82 - {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz}
83 - {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
84 - {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
85 - {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
86 - {id: SAI1_MCLK3.outFreq, value: 30 MHz}
87 - {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
88 - {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
89 - {id: SAI2_MCLK3.outFreq, value: 30 MHz}
90 - {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
91 - {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
92 - {id: SAI3_MCLK3.outFreq, value: 30 MHz}
93 - {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz}
94 - {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
95 - {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
96 - {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
97 - {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz}
98 - {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz}
99 settings:
100 - {id: CCM.AHB_PODF.scale, value: '1', locked: true}
101 - {id: CCM.ARM_PODF.scale, value: '2', locked: true}
102 - {id: CCM.FLEXSPI2_PODF.scale, value: '2', locked: true}
103 - {id: CCM.FLEXSPI2_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
104 - {id: CCM.FLEXSPI_PODF.scale, value: '2', locked: true}
105 - {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
106 - {id: CCM.LCDIF_PODF.scale, value: '4', locked: true}
107 - {id: CCM.LCDIF_PRED.scale, value: '2', locked: true}
108 - {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
109 - {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
110 - {id: CCM.SEMC_PODF.scale, value: '8'}
111 - {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
112 - {id: CCM.TRACE_PODF.scale, value: '4', locked: true}
113 - {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
114 - {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
115 - {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true}
116 - {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
117 - {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
118 - {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
119 - {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
120 - {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
121 - {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
122 - {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
123 - {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
124 - {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
125 - {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true}
126 - {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
127 - {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
128 - {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
129 - {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
130 - {id: CCM_ANALOG.PLL4.denom, value: '50'}
131 - {id: CCM_ANALOG.PLL4.div, value: '47'}
132 - {id: CCM_ANALOG.PLL5.denom, value: '1'}
133 - {id: CCM_ANALOG.PLL5.div, value: '31', locked: true}
134 - {id: CCM_ANALOG.PLL5.num, value: '0'}
135 - {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV}
136 - {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2', locked: true}
137 - {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4', locked: true}
138 - {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'}
139 - {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
140 - {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'}
141 sources:
142 - {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
143 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
144
145 /*******************************************************************************
146 * Variables for BOARD_BootClockRUN configuration
147 ******************************************************************************/
148 const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN =
149 {
150 .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */
151 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
152 };
153 const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
154 {
155 .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
156 .numerator = 0, /* 30 bit numerator of fractional loop divider */
157 .denominator = 1, /* 30 bit denominator of fractional loop divider */
158 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
159 };
160 const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
161 {
162 .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
163 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
164 };
165 const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN =
166 {
167 .loopDivider = 31, /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
168 .postDivider = 8, /* Divider after PLL */
169 .numerator = 0, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
170 .denominator = 1, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
171 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
172 };
173 /*******************************************************************************
174 * Code for BOARD_BootClockRUN configuration
175 ******************************************************************************/
BOARD_BootClockRUN(void)176 void BOARD_BootClockRUN(void)
177 {
178 /* Init RTC OSC clock frequency. */
179 CLOCK_SetRtcXtalFreq(32768U);
180 /* Enable 1MHz clock output. */
181 XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
182 /* Use free 1MHz clock output. */
183 XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
184 /* Set XTAL 24MHz clock frequency. */
185 CLOCK_SetXtalFreq(24000000U);
186 /* Enable XTAL 24MHz clock source. */
187 CLOCK_InitExternalClk(0);
188 /* Enable internal RC. */
189 CLOCK_InitRcOsc24M();
190 /* Switch clock source to external OSC. */
191 CLOCK_SwitchOsc(kCLOCK_XtalOsc);
192 /* Set Oscillator ready counter value. */
193 CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
194 /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
195 CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
196 CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
197 /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */
198 DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13);
199 /* Waiting for DCDC_STS_DC_OK bit is asserted */
200 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
201 {
202 }
203 /* Set AHB_PODF. */
204 CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
205 /* Disable IPG clock gate. */
206 CLOCK_DisableClock(kCLOCK_Adc1);
207 CLOCK_DisableClock(kCLOCK_Adc2);
208 CLOCK_DisableClock(kCLOCK_Xbar1);
209 CLOCK_DisableClock(kCLOCK_Xbar2);
210 CLOCK_DisableClock(kCLOCK_Xbar3);
211 /* Set IPG_PODF. */
212 CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
213 /* Set ARM_PODF. */
214 CLOCK_SetDiv(kCLOCK_ArmDiv, 1);
215 /* Set PERIPH_CLK2_PODF. */
216 CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
217 /* Disable PERCLK clock gate. */
218 CLOCK_DisableClock(kCLOCK_Gpt1);
219 CLOCK_DisableClock(kCLOCK_Gpt1S);
220 CLOCK_DisableClock(kCLOCK_Gpt2);
221 CLOCK_DisableClock(kCLOCK_Gpt2S);
222 CLOCK_DisableClock(kCLOCK_Pit);
223 /* Set PERCLK_PODF. */
224 CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
225 /* Disable USDHC1 clock gate. */
226 CLOCK_DisableClock(kCLOCK_Usdhc1);
227 /* Set USDHC1_PODF. */
228 CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1);
229 /* Set Usdhc1 clock source. */
230 CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
231 /* Disable USDHC2 clock gate. */
232 CLOCK_DisableClock(kCLOCK_Usdhc2);
233 /* Set USDHC2_PODF. */
234 CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
235 /* Set Usdhc2 clock source. */
236 CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
237 /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
238 * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
239 * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
240 #ifndef SKIP_SYSCLK_INIT
241 /* Disable Semc clock gate. */
242 CLOCK_DisableClock(kCLOCK_Semc);
243 /* Set SEMC_PODF. */
244 CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
245 /* Set Semc alt clock source. */
246 CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
247 /* Set Semc clock source. */
248 CLOCK_SetMux(kCLOCK_SemcMux, 0);
249 #endif
250 /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
251 * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
252 * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
253 #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
254 /* Disable Flexspi clock gate. */
255 CLOCK_DisableClock(kCLOCK_FlexSpi);
256 /* Set FLEXSPI_PODF. */
257 CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1);
258 /* Set Flexspi clock source. */
259 CLOCK_SetMux(kCLOCK_FlexspiMux, 3);
260 #endif
261 /* Disable Flexspi2 clock gate. */
262 CLOCK_DisableClock(kCLOCK_FlexSpi2);
263 /* Set FLEXSPI2_PODF. */
264 CLOCK_SetDiv(kCLOCK_Flexspi2Div, 1);
265 /* Set Flexspi2 clock source. */
266 CLOCK_SetMux(kCLOCK_Flexspi2Mux, 1);
267 /* Disable CSI clock gate. */
268 CLOCK_DisableClock(kCLOCK_Csi);
269 /* Set CSI_PODF. */
270 CLOCK_SetDiv(kCLOCK_CsiDiv, 1);
271 /* Set Csi clock source. */
272 CLOCK_SetMux(kCLOCK_CsiMux, 0);
273 /* Disable LPSPI clock gate. */
274 CLOCK_DisableClock(kCLOCK_Lpspi1);
275 CLOCK_DisableClock(kCLOCK_Lpspi2);
276 CLOCK_DisableClock(kCLOCK_Lpspi3);
277 CLOCK_DisableClock(kCLOCK_Lpspi4);
278 /* Set LPSPI_PODF. */
279 CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
280 /* Set Lpspi clock source. */
281 CLOCK_SetMux(kCLOCK_LpspiMux, 2);
282 /* Disable TRACE clock gate. */
283 CLOCK_DisableClock(kCLOCK_Trace);
284 /* Set TRACE_PODF. */
285 CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
286 /* Set Trace clock source. */
287 CLOCK_SetMux(kCLOCK_TraceMux, 0);
288 /* Disable SAI1 clock gate. */
289 CLOCK_DisableClock(kCLOCK_Sai1);
290 /* Set SAI1_CLK_PRED. */
291 CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
292 /* Set SAI1_CLK_PODF. */
293 CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
294 /* Set Sai1 clock source. */
295 CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
296 /* Disable SAI2 clock gate. */
297 CLOCK_DisableClock(kCLOCK_Sai2);
298 /* Set SAI2_CLK_PRED. */
299 CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
300 /* Set SAI2_CLK_PODF. */
301 CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
302 /* Set Sai2 clock source. */
303 CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
304 /* Disable SAI3 clock gate. */
305 CLOCK_DisableClock(kCLOCK_Sai3);
306 /* Set SAI3_CLK_PRED. */
307 CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
308 /* Set SAI3_CLK_PODF. */
309 CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
310 /* Set Sai3 clock source. */
311 CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
312 /* Disable Lpi2c clock gate. */
313 CLOCK_DisableClock(kCLOCK_Lpi2c1);
314 CLOCK_DisableClock(kCLOCK_Lpi2c2);
315 CLOCK_DisableClock(kCLOCK_Lpi2c3);
316 /* Set LPI2C_CLK_PODF. */
317 CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
318 /* Set Lpi2c clock source. */
319 CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
320 /* Disable CAN clock gate. */
321 CLOCK_DisableClock(kCLOCK_Can1);
322 CLOCK_DisableClock(kCLOCK_Can2);
323 CLOCK_DisableClock(kCLOCK_Can3);
324 CLOCK_DisableClock(kCLOCK_Can1S);
325 CLOCK_DisableClock(kCLOCK_Can2S);
326 CLOCK_DisableClock(kCLOCK_Can3S);
327 /* Set CAN_CLK_PODF. */
328 CLOCK_SetDiv(kCLOCK_CanDiv, 1);
329 /* Set Can clock source. */
330 CLOCK_SetMux(kCLOCK_CanMux, 2);
331 /* Disable UART clock gate. */
332 CLOCK_DisableClock(kCLOCK_Lpuart1);
333 CLOCK_DisableClock(kCLOCK_Lpuart2);
334 CLOCK_DisableClock(kCLOCK_Lpuart3);
335 CLOCK_DisableClock(kCLOCK_Lpuart4);
336 CLOCK_DisableClock(kCLOCK_Lpuart5);
337 CLOCK_DisableClock(kCLOCK_Lpuart6);
338 CLOCK_DisableClock(kCLOCK_Lpuart7);
339 CLOCK_DisableClock(kCLOCK_Lpuart8);
340 /* Set UART_CLK_PODF. */
341 CLOCK_SetDiv(kCLOCK_UartDiv, 0);
342 /* Set Uart clock source. */
343 CLOCK_SetMux(kCLOCK_UartMux, 0);
344 /* Disable LCDIF clock gate. */
345 CLOCK_DisableClock(kCLOCK_LcdPixel);
346 /* Set LCDIF_PRED. */
347 CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1);
348 /* Set LCDIF_CLK_PODF. */
349 CLOCK_SetDiv(kCLOCK_LcdifDiv, 3);
350 /* Set Lcdif pre clock source. */
351 CLOCK_SetMux(kCLOCK_LcdifPreMux, 5);
352 /* Disable SPDIF clock gate. */
353 CLOCK_DisableClock(kCLOCK_Spdif);
354 /* Set SPDIF0_CLK_PRED. */
355 CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
356 /* Set SPDIF0_CLK_PODF. */
357 CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
358 /* Set Spdif clock source. */
359 CLOCK_SetMux(kCLOCK_SpdifMux, 3);
360 /* Disable Flexio1 clock gate. */
361 CLOCK_DisableClock(kCLOCK_Flexio1);
362 /* Set FLEXIO1_CLK_PRED. */
363 CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
364 /* Set FLEXIO1_CLK_PODF. */
365 CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
366 /* Set Flexio1 clock source. */
367 CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
368 /* Disable Flexio2 clock gate. */
369 CLOCK_DisableClock(kCLOCK_Flexio2);
370 /* Set FLEXIO2_CLK_PRED. */
371 CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1);
372 /* Set FLEXIO2_CLK_PODF. */
373 CLOCK_SetDiv(kCLOCK_Flexio2Div, 7);
374 /* Set Flexio2 clock source. */
375 CLOCK_SetMux(kCLOCK_Flexio2Mux, 3);
376 /* Set Pll3 sw clock source. */
377 CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
378 /* Init ARM PLL. */
379 CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
380 /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
381 * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
382 * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
383 #ifndef SKIP_SYSCLK_INIT
384 #if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
385 #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
386 #endif
387 /* Init System PLL. */
388 CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
389 /* Init System pfd0. */
390 CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
391 /* Init System pfd1. */
392 CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
393 /* Init System pfd2. */
394 CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
395 /* Init System pfd3. */
396 CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
397 #endif
398 /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
399 * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
400 * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
401 #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
402 /* Init Usb1 PLL. */
403 CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
404 /* Init Usb1 pfd0. */
405 CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33);
406 /* Init Usb1 pfd1. */
407 CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
408 /* Init Usb1 pfd2. */
409 CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
410 /* Init Usb1 pfd3. */
411 CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19);
412 /* Disable Usb1 PLL output for USBPHY1. */
413 CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
414 #endif
415 /* DeInit Audio PLL. */
416 CLOCK_DeinitAudioPll();
417 /* Bypass Audio PLL. */
418 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
419 /* Set divider for Audio PLL. */
420 CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
421 CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
422 /* Enable Audio PLL output. */
423 CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
424 /* Init Video PLL. */
425 uint32_t pllVideo;
426 /* Disable Video PLL output before initial Video PLL. */
427 CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
428 /* Bypass PLL first */
429 CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) |
430 CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0);
431 CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0);
432 CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1);
433 pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) |
434 CCM_ANALOG_PLL_VIDEO_ENABLE_MASK |CCM_ANALOG_PLL_VIDEO_DIV_SELECT(31);
435 pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1);
436 CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3);
437 CCM_ANALOG->PLL_VIDEO = pllVideo;
438 while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0)
439 {
440 }
441 /* Disable bypass for Video PLL. */
442 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0);
443 /* DeInit Enet PLL. */
444 CLOCK_DeinitEnetPll();
445 /* Bypass Enet PLL. */
446 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1);
447 /* Set Enet output divider. */
448 CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
449 /* Enable Enet output. */
450 CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
451 /* Set Enet2 output divider. */
452 CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(0);
453 /* Enable Enet2 output. */
454 CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK;
455 /* Enable Enet25M output. */
456 CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
457 /* DeInit Usb2 PLL. */
458 CLOCK_DeinitUsb2Pll();
459 /* Bypass Usb2 PLL. */
460 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1);
461 /* Enable Usb2 PLL output. */
462 CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK;
463 /* Set preperiph clock source. */
464 CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
465 /* Set periph clock source. */
466 CLOCK_SetMux(kCLOCK_PeriphMux, 0);
467 /* Set periph clock2 clock source. */
468 CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
469 /* Set per clock source. */
470 CLOCK_SetMux(kCLOCK_PerclkMux, 0);
471 /* Set lvds1 clock source. */
472 CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
473 /* Set clock out1 divider. */
474 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
475 /* Set clock out1 source. */
476 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
477 /* Set clock out2 divider. */
478 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
479 /* Set clock out2 source. */
480 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
481 /* Set clock out1 drives clock out1. */
482 CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
483 /* Disable clock out1. */
484 CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
485 /* Disable clock out2. */
486 CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
487 /* Set SAI1 MCLK1 clock source. */
488 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
489 /* Set SAI1 MCLK2 clock source. */
490 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
491 /* Set SAI1 MCLK3 clock source. */
492 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
493 /* Set SAI2 MCLK3 clock source. */
494 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
495 /* Set SAI3 MCLK3 clock source. */
496 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
497 /* Set MQS configuration. */
498 IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
499 /* Set ENET Ref clock source. */
500 IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK;
501 /* Set ENET2 Ref clock source. */
502 IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK;
503 /* Set GPT1 High frequency reference clock source. */
504 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
505 /* Set GPT2 High frequency reference clock source. */
506 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
507 /* Set SystemCoreClock variable. */
508 SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
509 }
510
511 /*******************************************************************************
512 ******************* Configuration BOARD_BootClockRUN_528M *********************
513 ******************************************************************************/
514 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
515 !!Configuration
516 name: BOARD_BootClockRUN_528M
517 outputs:
518 - {id: AHB_CLK_ROOT.outFreq, value: 528 MHz}
519 - {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
520 - {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
521 - {id: CLK_1M.outFreq, value: 1 MHz}
522 - {id: CLK_24M.outFreq, value: 24 MHz}
523 - {id: CSI_CLK_ROOT.outFreq, value: 12 MHz}
524 - {id: ENET2_125M_CLK.outFreq, value: 1.2 MHz}
525 - {id: ENET_125M_CLK.outFreq, value: 2.4 MHz}
526 - {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
527 - {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
528 - {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz}
529 - {id: FLEXSPI2_CLK_ROOT.outFreq, value: 1440/11 MHz}
530 - {id: FLEXSPI_CLK_ROOT.outFreq, value: 1440/11 MHz}
531 - {id: GPT1_ipg_clk_highfreq.outFreq, value: 66 MHz}
532 - {id: GPT2_ipg_clk_highfreq.outFreq, value: 66 MHz}
533 - {id: IPG_CLK_ROOT.outFreq, value: 132 MHz}
534 - {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz}
535 - {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
536 - {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
537 - {id: LVDS1_CLK.outFreq, value: 1.2 GHz}
538 - {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
539 - {id: PERCLK_CLK_ROOT.outFreq, value: 66 MHz}
540 - {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz}
541 - {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
542 - {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
543 - {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
544 - {id: SAI1_MCLK3.outFreq, value: 30 MHz}
545 - {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
546 - {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
547 - {id: SAI2_MCLK3.outFreq, value: 30 MHz}
548 - {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
549 - {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
550 - {id: SAI3_MCLK3.outFreq, value: 30 MHz}
551 - {id: SEMC_CLK_ROOT.outFreq, value: 66 MHz}
552 - {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
553 - {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
554 - {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
555 - {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz}
556 - {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz}
557 settings:
558 - {id: CCM.AHB_PODF.scale, value: '1', locked: true}
559 - {id: CCM.ARM_PODF.scale, value: '2', locked: true}
560 - {id: CCM.FLEXSPI2_PODF.scale, value: '2', locked: true}
561 - {id: CCM.FLEXSPI2_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
562 - {id: CCM.FLEXSPI_PODF.scale, value: '2', locked: true}
563 - {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
564 - {id: CCM.LCDIF_PODF.scale, value: '4', locked: true}
565 - {id: CCM.LCDIF_PRED.scale, value: '2', locked: true}
566 - {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
567 - {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
568 - {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
569 - {id: CCM.SEMC_PODF.scale, value: '8'}
570 - {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
571 - {id: CCM.TRACE_PODF.scale, value: '4', locked: true}
572 - {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
573 - {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
574 - {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true}
575 - {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
576 - {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
577 - {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
578 - {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
579 - {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
580 - {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
581 - {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
582 - {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
583 - {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
584 - {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true}
585 - {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
586 - {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
587 - {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
588 - {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
589 - {id: CCM_ANALOG.PLL4.denom, value: '50'}
590 - {id: CCM_ANALOG.PLL4.div, value: '47'}
591 - {id: CCM_ANALOG.PLL5.denom, value: '1'}
592 - {id: CCM_ANALOG.PLL5.div, value: '31', locked: true}
593 - {id: CCM_ANALOG.PLL5.num, value: '0'}
594 - {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV}
595 - {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2', locked: true}
596 - {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4', locked: true}
597 - {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'}
598 - {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
599 - {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'}
600 sources:
601 - {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
602 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
603
604 /*******************************************************************************
605 * Variables for BOARD_BootClockRUN_528M configuration
606 ******************************************************************************/
607 const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN_528M =
608 {
609 .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */
610 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
611 };
612 const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN_528M =
613 {
614 .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
615 .numerator = 0, /* 30 bit numerator of fractional loop divider */
616 .denominator = 1, /* 30 bit denominator of fractional loop divider */
617 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
618 };
619 const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN_528M =
620 {
621 .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
622 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
623 };
624 const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN_528M =
625 {
626 .loopDivider = 31, /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
627 .postDivider = 8, /* Divider after PLL */
628 .numerator = 0, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
629 .denominator = 1, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
630 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
631 };
632 /*******************************************************************************
633 * Code for BOARD_BootClockRUN_528M configuration
634 ******************************************************************************/
BOARD_BootClockRUN_528M(void)635 void BOARD_BootClockRUN_528M(void)
636 {
637 /* Init RTC OSC clock frequency. */
638 CLOCK_SetRtcXtalFreq(32768U);
639 /* Enable 1MHz clock output. */
640 XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
641 /* Use free 1MHz clock output. */
642 XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
643 /* Set XTAL 24MHz clock frequency. */
644 CLOCK_SetXtalFreq(24000000U);
645 /* Enable XTAL 24MHz clock source. */
646 CLOCK_InitExternalClk(0);
647 /* Enable internal RC. */
648 CLOCK_InitRcOsc24M();
649 /* Switch clock source to external OSC. */
650 CLOCK_SwitchOsc(kCLOCK_XtalOsc);
651 /* Set Oscillator ready counter value. */
652 CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
653 /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
654 CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
655 CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
656 /* Set AHB_PODF. */
657 CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
658 /* Disable IPG clock gate. */
659 CLOCK_DisableClock(kCLOCK_Adc1);
660 CLOCK_DisableClock(kCLOCK_Adc2);
661 CLOCK_DisableClock(kCLOCK_Xbar1);
662 CLOCK_DisableClock(kCLOCK_Xbar2);
663 CLOCK_DisableClock(kCLOCK_Xbar3);
664 /* Set IPG_PODF. */
665 CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
666 /* Set ARM_PODF. */
667 CLOCK_SetDiv(kCLOCK_ArmDiv, 1);
668 /* Set PERIPH_CLK2_PODF. */
669 CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
670 /* Disable PERCLK clock gate. */
671 CLOCK_DisableClock(kCLOCK_Gpt1);
672 CLOCK_DisableClock(kCLOCK_Gpt1S);
673 CLOCK_DisableClock(kCLOCK_Gpt2);
674 CLOCK_DisableClock(kCLOCK_Gpt2S);
675 CLOCK_DisableClock(kCLOCK_Pit);
676 /* Set PERCLK_PODF. */
677 CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
678 /* Disable USDHC1 clock gate. */
679 CLOCK_DisableClock(kCLOCK_Usdhc1);
680 /* Set USDHC1_PODF. */
681 CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1);
682 /* Set Usdhc1 clock source. */
683 CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
684 /* Disable USDHC2 clock gate. */
685 CLOCK_DisableClock(kCLOCK_Usdhc2);
686 /* Set USDHC2_PODF. */
687 CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
688 /* Set Usdhc2 clock source. */
689 CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
690 /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
691 * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
692 * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
693 #ifndef SKIP_SYSCLK_INIT
694 /* Disable Semc clock gate. */
695 CLOCK_DisableClock(kCLOCK_Semc);
696 /* Set SEMC_PODF. */
697 CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
698 /* Set Semc alt clock source. */
699 CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
700 /* Set Semc clock source. */
701 CLOCK_SetMux(kCLOCK_SemcMux, 0);
702 #endif
703 /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
704 * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
705 * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
706 #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
707 /* Disable Flexspi clock gate. */
708 CLOCK_DisableClock(kCLOCK_FlexSpi);
709 /* Set FLEXSPI_PODF. */
710 CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1);
711 /* Set Flexspi clock source. */
712 CLOCK_SetMux(kCLOCK_FlexspiMux, 3);
713 #endif
714 /* Disable Flexspi2 clock gate. */
715 CLOCK_DisableClock(kCLOCK_FlexSpi2);
716 /* Set FLEXSPI2_PODF. */
717 CLOCK_SetDiv(kCLOCK_Flexspi2Div, 1);
718 /* Set Flexspi2 clock source. */
719 CLOCK_SetMux(kCLOCK_Flexspi2Mux, 1);
720 /* Disable CSI clock gate. */
721 CLOCK_DisableClock(kCLOCK_Csi);
722 /* Set CSI_PODF. */
723 CLOCK_SetDiv(kCLOCK_CsiDiv, 1);
724 /* Set Csi clock source. */
725 CLOCK_SetMux(kCLOCK_CsiMux, 0);
726 /* Disable LPSPI clock gate. */
727 CLOCK_DisableClock(kCLOCK_Lpspi1);
728 CLOCK_DisableClock(kCLOCK_Lpspi2);
729 CLOCK_DisableClock(kCLOCK_Lpspi3);
730 CLOCK_DisableClock(kCLOCK_Lpspi4);
731 /* Set LPSPI_PODF. */
732 CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
733 /* Set Lpspi clock source. */
734 CLOCK_SetMux(kCLOCK_LpspiMux, 2);
735 /* Disable TRACE clock gate. */
736 CLOCK_DisableClock(kCLOCK_Trace);
737 /* Set TRACE_PODF. */
738 CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
739 /* Set Trace clock source. */
740 CLOCK_SetMux(kCLOCK_TraceMux, 0);
741 /* Disable SAI1 clock gate. */
742 CLOCK_DisableClock(kCLOCK_Sai1);
743 /* Set SAI1_CLK_PRED. */
744 CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
745 /* Set SAI1_CLK_PODF. */
746 CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
747 /* Set Sai1 clock source. */
748 CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
749 /* Disable SAI2 clock gate. */
750 CLOCK_DisableClock(kCLOCK_Sai2);
751 /* Set SAI2_CLK_PRED. */
752 CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
753 /* Set SAI2_CLK_PODF. */
754 CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
755 /* Set Sai2 clock source. */
756 CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
757 /* Disable SAI3 clock gate. */
758 CLOCK_DisableClock(kCLOCK_Sai3);
759 /* Set SAI3_CLK_PRED. */
760 CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
761 /* Set SAI3_CLK_PODF. */
762 CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
763 /* Set Sai3 clock source. */
764 CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
765 /* Disable Lpi2c clock gate. */
766 CLOCK_DisableClock(kCLOCK_Lpi2c1);
767 CLOCK_DisableClock(kCLOCK_Lpi2c2);
768 CLOCK_DisableClock(kCLOCK_Lpi2c3);
769 /* Set LPI2C_CLK_PODF. */
770 CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
771 /* Set Lpi2c clock source. */
772 CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
773 /* Disable CAN clock gate. */
774 CLOCK_DisableClock(kCLOCK_Can1);
775 CLOCK_DisableClock(kCLOCK_Can2);
776 CLOCK_DisableClock(kCLOCK_Can3);
777 CLOCK_DisableClock(kCLOCK_Can1S);
778 CLOCK_DisableClock(kCLOCK_Can2S);
779 CLOCK_DisableClock(kCLOCK_Can3S);
780 /* Set CAN_CLK_PODF. */
781 CLOCK_SetDiv(kCLOCK_CanDiv, 1);
782 /* Set Can clock source. */
783 CLOCK_SetMux(kCLOCK_CanMux, 2);
784 /* Disable UART clock gate. */
785 CLOCK_DisableClock(kCLOCK_Lpuart1);
786 CLOCK_DisableClock(kCLOCK_Lpuart2);
787 CLOCK_DisableClock(kCLOCK_Lpuart3);
788 CLOCK_DisableClock(kCLOCK_Lpuart4);
789 CLOCK_DisableClock(kCLOCK_Lpuart5);
790 CLOCK_DisableClock(kCLOCK_Lpuart6);
791 CLOCK_DisableClock(kCLOCK_Lpuart7);
792 CLOCK_DisableClock(kCLOCK_Lpuart8);
793 /* Set UART_CLK_PODF. */
794 CLOCK_SetDiv(kCLOCK_UartDiv, 0);
795 /* Set Uart clock source. */
796 CLOCK_SetMux(kCLOCK_UartMux, 0);
797 /* Disable LCDIF clock gate. */
798 CLOCK_DisableClock(kCLOCK_LcdPixel);
799 /* Set LCDIF_PRED. */
800 CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1);
801 /* Set LCDIF_CLK_PODF. */
802 CLOCK_SetDiv(kCLOCK_LcdifDiv, 3);
803 /* Set Lcdif pre clock source. */
804 CLOCK_SetMux(kCLOCK_LcdifPreMux, 5);
805 /* Disable SPDIF clock gate. */
806 CLOCK_DisableClock(kCLOCK_Spdif);
807 /* Set SPDIF0_CLK_PRED. */
808 CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
809 /* Set SPDIF0_CLK_PODF. */
810 CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
811 /* Set Spdif clock source. */
812 CLOCK_SetMux(kCLOCK_SpdifMux, 3);
813 /* Disable Flexio1 clock gate. */
814 CLOCK_DisableClock(kCLOCK_Flexio1);
815 /* Set FLEXIO1_CLK_PRED. */
816 CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
817 /* Set FLEXIO1_CLK_PODF. */
818 CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
819 /* Set Flexio1 clock source. */
820 CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
821 /* Disable Flexio2 clock gate. */
822 CLOCK_DisableClock(kCLOCK_Flexio2);
823 /* Set FLEXIO2_CLK_PRED. */
824 CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1);
825 /* Set FLEXIO2_CLK_PODF. */
826 CLOCK_SetDiv(kCLOCK_Flexio2Div, 7);
827 /* Set Flexio2 clock source. */
828 CLOCK_SetMux(kCLOCK_Flexio2Mux, 3);
829 /* Set Pll3 sw clock source. */
830 CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
831 /* Init ARM PLL. */
832 CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN_528M);
833 /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
834 * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
835 * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
836 #ifndef SKIP_SYSCLK_INIT
837 #if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
838 #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
839 #endif
840 /* Init System PLL. */
841 CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN_528M);
842 /* Init System pfd0. */
843 CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
844 /* Init System pfd1. */
845 CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
846 /* Init System pfd2. */
847 CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
848 /* Init System pfd3. */
849 CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
850 #endif
851 /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
852 * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
853 * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
854 #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
855 /* Init Usb1 PLL. */
856 CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN_528M);
857 /* Init Usb1 pfd0. */
858 CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33);
859 /* Init Usb1 pfd1. */
860 CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
861 /* Init Usb1 pfd2. */
862 CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
863 /* Init Usb1 pfd3. */
864 CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19);
865 /* Disable Usb1 PLL output for USBPHY1. */
866 CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
867 #endif
868 /* DeInit Audio PLL. */
869 CLOCK_DeinitAudioPll();
870 /* Bypass Audio PLL. */
871 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
872 /* Set divider for Audio PLL. */
873 CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
874 CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
875 /* Enable Audio PLL output. */
876 CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
877 /* Init Video PLL. */
878 uint32_t pllVideo;
879 /* Disable Video PLL output before initial Video PLL. */
880 CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
881 /* Bypass PLL first */
882 CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) |
883 CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0);
884 CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0);
885 CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1);
886 pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) |
887 CCM_ANALOG_PLL_VIDEO_ENABLE_MASK |CCM_ANALOG_PLL_VIDEO_DIV_SELECT(31);
888 pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1);
889 CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3);
890 CCM_ANALOG->PLL_VIDEO = pllVideo;
891 while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0)
892 {
893 }
894 /* Disable bypass for Video PLL. */
895 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0);
896 /* DeInit Enet PLL. */
897 CLOCK_DeinitEnetPll();
898 /* Bypass Enet PLL. */
899 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1);
900 /* Set Enet output divider. */
901 CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
902 /* Enable Enet output. */
903 CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
904 /* Set Enet2 output divider. */
905 CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(0);
906 /* Enable Enet2 output. */
907 CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK;
908 /* Enable Enet25M output. */
909 CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
910 /* DeInit Usb2 PLL. */
911 CLOCK_DeinitUsb2Pll();
912 /* Bypass Usb2 PLL. */
913 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1);
914 /* Enable Usb2 PLL output. */
915 CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK;
916 /* Set preperiph clock source. */
917 CLOCK_SetMux(kCLOCK_PrePeriphMux, 0);
918 /* Set periph clock source. */
919 CLOCK_SetMux(kCLOCK_PeriphMux, 0);
920 /* Set periph clock2 clock source. */
921 CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
922 /* Set per clock source. */
923 CLOCK_SetMux(kCLOCK_PerclkMux, 0);
924 /* Set lvds1 clock source. */
925 CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
926 /* Set clock out1 divider. */
927 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
928 /* Set clock out1 source. */
929 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
930 /* Set clock out2 divider. */
931 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
932 /* Set clock out2 source. */
933 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
934 /* Set clock out1 drives clock out1. */
935 CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
936 /* Disable clock out1. */
937 CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
938 /* Disable clock out2. */
939 CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
940 /* Set SAI1 MCLK1 clock source. */
941 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
942 /* Set SAI1 MCLK2 clock source. */
943 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
944 /* Set SAI1 MCLK3 clock source. */
945 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
946 /* Set SAI2 MCLK3 clock source. */
947 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
948 /* Set SAI3 MCLK3 clock source. */
949 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
950 /* Set MQS configuration. */
951 IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
952 /* Set ENET Ref clock source. */
953 IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK;
954 /* Set ENET2 Ref clock source. */
955 IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK;
956 /* Set GPT1 High frequency reference clock source. */
957 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
958 /* Set GPT2 High frequency reference clock source. */
959 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
960 /* Set SystemCoreClock variable. */
961 SystemCoreClock = BOARD_BOOTCLOCKRUN_528M_CORE_CLOCK;
962 }
963
964
