1 /* 2 * Copyright 2022 NXP 3 * All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef _CLOCK_CONFIG_H_ 9 #define _CLOCK_CONFIG_H_ 10 11 #include "fsl_common.h" 12 13 /******************************************************************************* 14 * Definitions 15 ******************************************************************************/ 16 #define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ 17 18 #define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ 19 /******************************************************************************* 20 ************************ BOARD_InitBootClocks function ************************ 21 ******************************************************************************/ 22 23 #if defined(__cplusplus) 24 extern "C" { 25 #endif /* __cplusplus*/ 26 27 /*! 28 * @brief This function executes default configuration of clocks. 29 * 30 */ 31 void BOARD_InitBootClocks(void); 32 33 #if defined(__cplusplus) 34 } 35 #endif /* __cplusplus*/ 36 37 /******************************************************************************* 38 ********************** Configuration BOARD_BootClockRUN *********************** 39 ******************************************************************************/ 40 /******************************************************************************* 41 * Definitions for BOARD_BootClockRUN configuration 42 ******************************************************************************/ 43 #define BOARD_BOOTCLOCKRUN_CORE_CLOCK 528000000U /*!< Core clock frequency: 528000000Hz */ 44 45 /* Clock outputs (values are in Hz): */ 46 #define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 528000000UL 47 #define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL 48 #define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL 49 #define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL 50 #define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL 51 #define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL 52 #define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL 53 #define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL 54 #define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL 55 #define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL 56 #define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL 57 #define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL 58 #define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL 59 #define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 130909090UL 60 #define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 130909090UL 61 #define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 66000000UL 62 #define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 66000000UL 63 #define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 132000000UL 64 #define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 67500000UL 65 #define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL 66 #define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL 67 #define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL 68 #define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL 69 #define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 66000000UL 70 #define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL 71 #define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL 72 #define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL 73 #define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL 74 #define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL 75 #define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL 76 #define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL 77 #define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL 78 #define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL 79 #define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL 80 #define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL 81 #define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL 82 #define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 66000000UL 83 #define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL 84 #define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL 85 #define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL 86 #define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL 87 #define BOARD_BOOTCLOCKRUN_USBPHY_CLK 0UL 88 #define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL 89 #define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL 90 91 /*! @brief Arm PLL set for BOARD_BootClockRUN configuration. 92 */ 93 extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN; 94 /*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration. 95 */ 96 extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN; 97 /*! @brief Sys PLL for BOARD_BootClockRUN configuration. 98 */ 99 extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN; 100 /*! @brief Video PLL set for BOARD_BootClockRUN configuration. 101 */ 102 extern const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN; 103 104 /******************************************************************************* 105 * API for BOARD_BootClockRUN configuration 106 ******************************************************************************/ 107 #if defined(__cplusplus) 108 extern "C" { 109 #endif /* __cplusplus*/ 110 111 /*! 112 * @brief This function executes configuration of clocks. 113 * 114 */ 115 void BOARD_BootClockRUN(void); 116 117 #if defined(__cplusplus) 118 } 119 #endif /* __cplusplus*/ 120 121 /******************************************************************************* 122 ******************* Configuration BOARD_BootClockRUN_600M ********************* 123 ******************************************************************************/ 124 /******************************************************************************* 125 * Definitions for BOARD_BootClockRUN_600M configuration 126 ******************************************************************************/ 127 #define BOARD_BOOTCLOCKRUN_600M_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */ 128 129 /* Clock outputs (values are in Hz): */ 130 #define BOARD_BOOTCLOCKRUN_600M_AHB_CLK_ROOT 600000000UL 131 #define BOARD_BOOTCLOCKRUN_600M_CAN_CLK_ROOT 40000000UL 132 #define BOARD_BOOTCLOCKRUN_600M_CKIL_SYNC_CLK_ROOT 32768UL 133 #define BOARD_BOOTCLOCKRUN_600M_CLKO1_CLK 0UL 134 #define BOARD_BOOTCLOCKRUN_600M_CLKO2_CLK 0UL 135 #define BOARD_BOOTCLOCKRUN_600M_CLK_1M 1000000UL 136 #define BOARD_BOOTCLOCKRUN_600M_CLK_24M 24000000UL 137 #define BOARD_BOOTCLOCKRUN_600M_ENET_125M_CLK 2400000UL 138 #define BOARD_BOOTCLOCKRUN_600M_ENET_25M_REF_CLK 1200000UL 139 #define BOARD_BOOTCLOCKRUN_600M_ENET_REF_CLK 0UL 140 #define BOARD_BOOTCLOCKRUN_600M_ENET_TX_CLK 0UL 141 #define BOARD_BOOTCLOCKRUN_600M_FLEXIO1_CLK_ROOT 30000000UL 142 #define BOARD_BOOTCLOCKRUN_600M_FLEXIO2_CLK_ROOT 30000000UL 143 #define BOARD_BOOTCLOCKRUN_600M_FLEXSPI2_CLK_ROOT 130909090UL 144 #define BOARD_BOOTCLOCKRUN_600M_FLEXSPI_CLK_ROOT 130909090UL 145 #define BOARD_BOOTCLOCKRUN_600M_GPT1_IPG_CLK_HIGHFREQ 75000000UL 146 #define BOARD_BOOTCLOCKRUN_600M_GPT2_IPG_CLK_HIGHFREQ 75000000UL 147 #define BOARD_BOOTCLOCKRUN_600M_IPG_CLK_ROOT 150000000UL 148 #define BOARD_BOOTCLOCKRUN_600M_LCDIF_CLK_ROOT 67500000UL 149 #define BOARD_BOOTCLOCKRUN_600M_LPI2C_CLK_ROOT 60000000UL 150 #define BOARD_BOOTCLOCKRUN_600M_LPSPI_CLK_ROOT 105600000UL 151 #define BOARD_BOOTCLOCKRUN_600M_LVDS1_CLK 1200000000UL 152 #define BOARD_BOOTCLOCKRUN_600M_MQS_MCLK 63529411UL 153 #define BOARD_BOOTCLOCKRUN_600M_PERCLK_CLK_ROOT 75000000UL 154 #define BOARD_BOOTCLOCKRUN_600M_SAI1_CLK_ROOT 63529411UL 155 #define BOARD_BOOTCLOCKRUN_600M_SAI1_MCLK1 63529411UL 156 #define BOARD_BOOTCLOCKRUN_600M_SAI1_MCLK2 63529411UL 157 #define BOARD_BOOTCLOCKRUN_600M_SAI1_MCLK3 30000000UL 158 #define BOARD_BOOTCLOCKRUN_600M_SAI2_CLK_ROOT 63529411UL 159 #define BOARD_BOOTCLOCKRUN_600M_SAI2_MCLK1 63529411UL 160 #define BOARD_BOOTCLOCKRUN_600M_SAI2_MCLK2 0UL 161 #define BOARD_BOOTCLOCKRUN_600M_SAI2_MCLK3 30000000UL 162 #define BOARD_BOOTCLOCKRUN_600M_SAI3_CLK_ROOT 63529411UL 163 #define BOARD_BOOTCLOCKRUN_600M_SAI3_MCLK1 63529411UL 164 #define BOARD_BOOTCLOCKRUN_600M_SAI3_MCLK2 0UL 165 #define BOARD_BOOTCLOCKRUN_600M_SAI3_MCLK3 30000000UL 166 #define BOARD_BOOTCLOCKRUN_600M_SEMC_CLK_ROOT 75000000UL 167 #define BOARD_BOOTCLOCKRUN_600M_SPDIF0_CLK_ROOT 30000000UL 168 #define BOARD_BOOTCLOCKRUN_600M_SPDIF0_EXTCLK_OUT 0UL 169 #define BOARD_BOOTCLOCKRUN_600M_TRACE_CLK_ROOT 132000000UL 170 #define BOARD_BOOTCLOCKRUN_600M_UART_CLK_ROOT 80000000UL 171 #define BOARD_BOOTCLOCKRUN_600M_USBPHY_CLK 0UL 172 #define BOARD_BOOTCLOCKRUN_600M_USDHC1_CLK_ROOT 198000000UL 173 #define BOARD_BOOTCLOCKRUN_600M_USDHC2_CLK_ROOT 198000000UL 174 175 /*! @brief Arm PLL set for BOARD_BootClockRUN_600M configuration. 176 */ 177 extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN_600M; 178 /*! @brief Usb1 PLL set for BOARD_BootClockRUN_600M configuration. 179 */ 180 extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN_600M; 181 /*! @brief Sys PLL for BOARD_BootClockRUN_600M configuration. 182 */ 183 extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN_600M; 184 /*! @brief Video PLL set for BOARD_BootClockRUN_600M configuration. 185 */ 186 extern const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN_600M; 187 188 /******************************************************************************* 189 * API for BOARD_BootClockRUN_600M configuration 190 ******************************************************************************/ 191 #if defined(__cplusplus) 192 extern "C" { 193 #endif /* __cplusplus*/ 194 195 /*! 196 * @brief This function executes configuration of clocks. 197 * 198 */ 199 void BOARD_BootClockRUN_600M(void); 200 201 #if defined(__cplusplus) 202 } 203 #endif /* __cplusplus*/ 204 205 #endif /* _CLOCK_CONFIG_H_ */ 206 207
