1 /*
2  * Copyright 2020-2021 NXP
3  * All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 /***********************************************************************************************************************
9  * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10  * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11  **********************************************************************************************************************/
12 
13 /*
14  * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
15 !!GlobalInfo
16 product: Pins v9.0
17 processor: MIMXRT1176xxxxx
18 package_id: MIMXRT1176DVMAA
19 mcu_data: ksdk2_0
20 processor_version: 0.9.6
21  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
22  */
23 
24 #include "fsl_common.h"
25 #include "fsl_iomuxc.h"
26 #include "pin_mux.h"
27 
28 /* FUNCTION ************************************************************************************************************
29  *
30  * Function Name : BOARD_InitBootPins
31  * Description   : Calls initialization functions.
32  *
33  * END ****************************************************************************************************************/
BOARD_InitBootPins(void)34 void BOARD_InitBootPins(void) {
35     BOARD_InitPins();
36 }
37 
38 /*
39  * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
40 BOARD_InitPins:
41 - options: {callFromInitBoot: 'true', coreID: cm7, enableClock: 'true'}
42 - pin_list:
43   - {pin_num: M15, peripheral: LPUART1, signal: RXD, pin_signal: GPIO_AD_25, software_input_on: Disable, pull_up_down_config: Pull_Down, pull_keeper_select: Keeper,
44     open_drain: Disable, drive_strength: High, slew_rate: Slow}
45   - {pin_num: L13, peripheral: LPUART1, signal: TXD, pin_signal: GPIO_AD_24, software_input_on: Disable, pull_up_down_config: Pull_Down, pull_keeper_select: Keeper,
46     open_drain: Disable, drive_strength: High, slew_rate: Slow}
47  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
48  */
49 
50 /* FUNCTION ************************************************************************************************************
51  *
52  * Function Name : BOARD_InitPins, assigned for the Cortex-M7F core.
53  * Description   : Configures pin routing and optionally pin electrical features.
54  *
55  * END ****************************************************************************************************************/
BOARD_InitPins(void)56 void BOARD_InitPins(void) {
57   CLOCK_EnableClock(kCLOCK_Iomuxc);           /* LPCG on: LPCG is ON. */
58 
59   IOMUXC_SetPinMux(
60       IOMUXC_GPIO_AD_24_LPUART1_TXD,          /* GPIO_AD_24 is configured as LPUART1_TXD */
61       0U);                                    /* Software Input On Field: Input Path is determined by functionality */
62   IOMUXC_SetPinMux(
63       IOMUXC_GPIO_AD_25_LPUART1_RXD,          /* GPIO_AD_25 is configured as LPUART1_RXD */
64       0U);                                    /* Software Input On Field: Input Path is determined by functionality */
65   IOMUXC_SetPinConfig(
66       IOMUXC_GPIO_AD_24_LPUART1_TXD,          /* GPIO_AD_24 PAD functional properties : */
67       0x02U);                                 /* Slew Rate Field: Slow Slew Rate
68                                                  Drive Strength Field: high drive strength
69                                                  Pull / Keep Select Field: Pull Disable, Highz
70                                                  Pull Up / Down Config. Field: Weak pull down
71                                                  Open Drain Field: Disabled
72                                                  Domain write protection: Both cores are allowed
73                                                  Domain write protection lock: Neither of DWP bits is locked */
74   IOMUXC_SetPinConfig(
75       IOMUXC_GPIO_AD_25_LPUART1_RXD,          /* GPIO_AD_25 PAD functional properties : */
76       0x02U);                                 /* Slew Rate Field: Slow Slew Rate
77                                                  Drive Strength Field: high drive strength
78                                                  Pull / Keep Select Field: Pull Disable, Highz
79                                                  Pull Up / Down Config. Field: Weak pull down
80                                                  Open Drain Field: Disabled
81                                                  Domain write protection: Both cores are allowed
82                                                  Domain write protection lock: Neither of DWP bits is locked */
83 }
84 
85 /***********************************************************************************************************************
86  * EOF
87  **********************************************************************************************************************/
88