1 /* 2 * Copyright 2022 NXP 3 * All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef _CLOCK_CONFIG_H_ 9 #define _CLOCK_CONFIG_H_ 10 11 #include "fsl_common.h" 12 13 /******************************************************************************* 14 * Definitions 15 ******************************************************************************/ 16 17 #define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ 18 19 #define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ 20 21 /******************************************************************************* 22 ************************ BOARD_InitBootClocks function ************************ 23 ******************************************************************************/ 24 25 #if defined(__cplusplus) 26 extern "C" { 27 #endif /* __cplusplus*/ 28 29 /*! 30 * @brief This function executes default configuration of clocks. 31 * 32 */ 33 void BOARD_InitBootClocks(void); 34 35 #if defined(__cplusplus) 36 } 37 #endif /* __cplusplus*/ 38 39 /******************************************************************************* 40 ********************** Configuration BOARD_BootClockRUN *********************** 41 ******************************************************************************/ 42 /******************************************************************************* 43 * Definitions for BOARD_BootClockRUN configuration 44 ******************************************************************************/ 45 #if __CORTEX_M == 7 46 #define BOARD_BOOTCLOCKRUN_CORE_CLOCK 996000000UL /*!< CM7 Core clock frequency: 996000000Hz */ 47 #else 48 #define BOARD_BOOTCLOCKRUN_CORE_CLOCK 392727272UL /*!< CM4 Core clock frequency: 392727272Hz */ 49 #endif 50 51 /* Clock outputs (values are in Hz): */ 52 #define BOARD_BOOTCLOCKRUN_ACMP_CLK_ROOT 24000000UL 53 #define BOARD_BOOTCLOCKRUN_ADC1_CLK_ROOT 24000000UL 54 #define BOARD_BOOTCLOCKRUN_ADC2_CLK_ROOT 24000000UL 55 #define BOARD_BOOTCLOCKRUN_ARM_PLL_CLK 996000000UL 56 #define BOARD_BOOTCLOCKRUN_ASRC_CLK_ROOT 24000000UL 57 #define BOARD_BOOTCLOCKRUN_AXI_CLK_ROOT 996000000UL 58 #define BOARD_BOOTCLOCKRUN_BUS_CLK_ROOT 240000000UL 59 #define BOARD_BOOTCLOCKRUN_BUS_LPSR_CLK_ROOT 160000000UL 60 #define BOARD_BOOTCLOCKRUN_CAN1_CLK_ROOT 24000000UL 61 #define BOARD_BOOTCLOCKRUN_CAN2_CLK_ROOT 24000000UL 62 #define BOARD_BOOTCLOCKRUN_CAN3_CLK_ROOT 24000000UL 63 #define BOARD_BOOTCLOCKRUN_CCM_CLKO1_CLK_ROOT 24000000UL 64 #define BOARD_BOOTCLOCKRUN_CCM_CLKO2_CLK_ROOT 24000000UL 65 #define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL 66 #define BOARD_BOOTCLOCKRUN_CSI2_CLK_ROOT 24000000UL 67 #define BOARD_BOOTCLOCKRUN_CSI2_ESC_CLK_ROOT 24000000UL 68 #define BOARD_BOOTCLOCKRUN_CSI2_UI_CLK_ROOT 24000000UL 69 #define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 24000000UL 70 #define BOARD_BOOTCLOCKRUN_CSSYS_CLK_ROOT 24000000UL 71 #define BOARD_BOOTCLOCKRUN_CSTRACE_CLK_ROOT 132000000UL 72 #define BOARD_BOOTCLOCKRUN_ELCDIF_CLK_ROOT 24000000UL 73 #define BOARD_BOOTCLOCKRUN_EMV1_CLK_ROOT 24000000UL 74 #define BOARD_BOOTCLOCKRUN_EMV2_CLK_ROOT 24000000UL 75 #define BOARD_BOOTCLOCKRUN_ENET1_CLK_ROOT 24000000UL 76 #define BOARD_BOOTCLOCKRUN_ENET2_CLK_ROOT 24000000UL 77 #define BOARD_BOOTCLOCKRUN_ENET_1G_REF_CLK 0UL 78 #define BOARD_BOOTCLOCKRUN_ENET_1G_TX_CLK 24000000UL 79 #define BOARD_BOOTCLOCKRUN_ENET_25M_CLK_ROOT 24000000UL 80 #define BOARD_BOOTCLOCKRUN_ENET_QOS_CLK_ROOT 24000000UL 81 #define BOARD_BOOTCLOCKRUN_ENET_QOS_REF_CLK 0UL 82 #define BOARD_BOOTCLOCKRUN_ENET_QOS_TX_CLK 0UL 83 #define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL 84 #define BOARD_BOOTCLOCKRUN_ENET_TIMER1_CLK_ROOT 24000000UL 85 #define BOARD_BOOTCLOCKRUN_ENET_TIMER2_CLK_ROOT 24000000UL 86 #define BOARD_BOOTCLOCKRUN_ENET_TIMER3_CLK_ROOT 24000000UL 87 #define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL 88 #define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 24000000UL 89 #define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 24000000UL 90 #define BOARD_BOOTCLOCKRUN_FLEXSPI1_CLK_ROOT 24000000UL 91 #define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 24000000UL 92 #define BOARD_BOOTCLOCKRUN_GC355_CLK_ROOT 492000012UL 93 #define BOARD_BOOTCLOCKRUN_GPT1_CLK_ROOT 24000000UL 94 #define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 24000000UL 95 #define BOARD_BOOTCLOCKRUN_GPT2_CLK_ROOT 24000000UL 96 #define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 24000000UL 97 #define BOARD_BOOTCLOCKRUN_GPT3_CLK_ROOT 24000000UL 98 #define BOARD_BOOTCLOCKRUN_GPT3_IPG_CLK_HIGHFREQ 24000000UL 99 #define BOARD_BOOTCLOCKRUN_GPT4_CLK_ROOT 24000000UL 100 #define BOARD_BOOTCLOCKRUN_GPT4_IPG_CLK_HIGHFREQ 24000000UL 101 #define BOARD_BOOTCLOCKRUN_GPT5_CLK_ROOT 24000000UL 102 #define BOARD_BOOTCLOCKRUN_GPT5_IPG_CLK_HIGHFREQ 24000000UL 103 #define BOARD_BOOTCLOCKRUN_GPT6_CLK_ROOT 24000000UL 104 #define BOARD_BOOTCLOCKRUN_GPT6_IPG_CLK_HIGHFREQ 24000000UL 105 #define BOARD_BOOTCLOCKRUN_LCDIFV2_CLK_ROOT 24000000UL 106 #define BOARD_BOOTCLOCKRUN_LPI2C1_CLK_ROOT 24000000UL 107 #define BOARD_BOOTCLOCKRUN_LPI2C2_CLK_ROOT 24000000UL 108 #define BOARD_BOOTCLOCKRUN_LPI2C3_CLK_ROOT 24000000UL 109 #define BOARD_BOOTCLOCKRUN_LPI2C4_CLK_ROOT 24000000UL 110 #define BOARD_BOOTCLOCKRUN_LPI2C5_CLK_ROOT 24000000UL 111 #define BOARD_BOOTCLOCKRUN_LPI2C6_CLK_ROOT 24000000UL 112 #define BOARD_BOOTCLOCKRUN_LPSPI1_CLK_ROOT 24000000UL 113 #define BOARD_BOOTCLOCKRUN_LPSPI2_CLK_ROOT 24000000UL 114 #define BOARD_BOOTCLOCKRUN_LPSPI3_CLK_ROOT 24000000UL 115 #define BOARD_BOOTCLOCKRUN_LPSPI4_CLK_ROOT 24000000UL 116 #define BOARD_BOOTCLOCKRUN_LPSPI5_CLK_ROOT 24000000UL 117 #define BOARD_BOOTCLOCKRUN_LPSPI6_CLK_ROOT 24000000UL 118 #define BOARD_BOOTCLOCKRUN_LPUART10_CLK_ROOT 24000000UL 119 #define BOARD_BOOTCLOCKRUN_LPUART11_CLK_ROOT 24000000UL 120 #define BOARD_BOOTCLOCKRUN_LPUART12_CLK_ROOT 24000000UL 121 #define BOARD_BOOTCLOCKRUN_LPUART1_CLK_ROOT 24000000UL 122 #define BOARD_BOOTCLOCKRUN_LPUART2_CLK_ROOT 24000000UL 123 #define BOARD_BOOTCLOCKRUN_LPUART3_CLK_ROOT 24000000UL 124 #define BOARD_BOOTCLOCKRUN_LPUART4_CLK_ROOT 24000000UL 125 #define BOARD_BOOTCLOCKRUN_LPUART5_CLK_ROOT 24000000UL 126 #define BOARD_BOOTCLOCKRUN_LPUART6_CLK_ROOT 24000000UL 127 #define BOARD_BOOTCLOCKRUN_LPUART7_CLK_ROOT 24000000UL 128 #define BOARD_BOOTCLOCKRUN_LPUART8_CLK_ROOT 24000000UL 129 #define BOARD_BOOTCLOCKRUN_LPUART9_CLK_ROOT 24000000UL 130 #define BOARD_BOOTCLOCKRUN_M4_CLK_ROOT 392727272UL 131 #define BOARD_BOOTCLOCKRUN_M4_SYSTICK_CLK_ROOT 24000000UL 132 #define BOARD_BOOTCLOCKRUN_M7_CLK_ROOT 996000000UL 133 #define BOARD_BOOTCLOCKRUN_M7_SYSTICK_CLK_ROOT 100000UL 134 #define BOARD_BOOTCLOCKRUN_MIC_CLK_ROOT 24000000UL 135 #define BOARD_BOOTCLOCKRUN_MIPI_DSI_TX_CLK_ESC_ROOT 24000000UL 136 #define BOARD_BOOTCLOCKRUN_MIPI_ESC_CLK_ROOT 24000000UL 137 #define BOARD_BOOTCLOCKRUN_MIPI_REF_CLK_ROOT 24000000UL 138 #define BOARD_BOOTCLOCKRUN_MQS_CLK_ROOT 24000000UL 139 #define BOARD_BOOTCLOCKRUN_MQS_MCLK 24000000UL 140 #define BOARD_BOOTCLOCKRUN_OSC_24M 24000000UL 141 #define BOARD_BOOTCLOCKRUN_OSC_32K 32768UL 142 #define BOARD_BOOTCLOCKRUN_OSC_RC_16M 16000000UL 143 #define BOARD_BOOTCLOCKRUN_OSC_RC_400M 400000000UL 144 #define BOARD_BOOTCLOCKRUN_OSC_RC_48M 48000000UL 145 #define BOARD_BOOTCLOCKRUN_OSC_RC_48M_DIV2 24000000UL 146 #define BOARD_BOOTCLOCKRUN_PLL_AUDIO_CLK 0UL 147 #define BOARD_BOOTCLOCKRUN_PLL_AUDIO_SS_MODULATION 0UL 148 #define BOARD_BOOTCLOCKRUN_PLL_AUDIO_SS_RANGE 0UL 149 #define BOARD_BOOTCLOCKRUN_PLL_VIDEO_CLK 984000025UL 150 #define BOARD_BOOTCLOCKRUN_PLL_VIDEO_SS_MODULATION 0UL 151 #define BOARD_BOOTCLOCKRUN_PLL_VIDEO_SS_RANGE 0UL 152 #define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 24000000UL 153 #define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 24000000UL 154 #define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 0UL 155 #define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 24000000UL 156 #define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 24000000UL 157 #define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 24000000UL 158 #define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL 159 #define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 24000000UL 160 #define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 24000000UL 161 #define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 24000000UL 162 #define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL 163 #define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 24000000UL 164 #define BOARD_BOOTCLOCKRUN_SAI4_CLK_ROOT 24000000UL 165 #define BOARD_BOOTCLOCKRUN_SAI4_MCLK1 24000000UL 166 #define BOARD_BOOTCLOCKRUN_SAI4_MCLK2 0UL 167 #define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 198000000UL 168 #define BOARD_BOOTCLOCKRUN_SPDIF_CLK_ROOT 24000000UL 169 #define BOARD_BOOTCLOCKRUN_SPDIF_EXTCLK_OUT 0UL 170 #define BOARD_BOOTCLOCKRUN_SYS_PLL1_CLK 0UL 171 #define BOARD_BOOTCLOCKRUN_SYS_PLL1_DIV2_CLK 0UL 172 #define BOARD_BOOTCLOCKRUN_SYS_PLL1_DIV5_CLK 0UL 173 #define BOARD_BOOTCLOCKRUN_SYS_PLL1_SS_MODULATION 0UL 174 #define BOARD_BOOTCLOCKRUN_SYS_PLL1_SS_RANGE 0UL 175 #define BOARD_BOOTCLOCKRUN_SYS_PLL2_CLK 528000000UL 176 #define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD0_CLK 352000000UL 177 #define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD1_CLK 594000000UL 178 #define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD2_CLK 396000000UL 179 #define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD3_CLK 297000000UL 180 #define BOARD_BOOTCLOCKRUN_SYS_PLL2_SS_MODULATION 0UL 181 #define BOARD_BOOTCLOCKRUN_SYS_PLL2_SS_RANGE 0UL 182 #define BOARD_BOOTCLOCKRUN_SYS_PLL3_CLK 480000000UL 183 #define BOARD_BOOTCLOCKRUN_SYS_PLL3_DIV2_CLK 240000000UL 184 #define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD0_CLK 664615384UL 185 #define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD1_CLK 508235294UL 186 #define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD2_CLK 270000000UL 187 #define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD3_CLK 392727272UL 188 #define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 24000000UL 189 #define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 24000000UL 190 191 192 /******************************************************************************* 193 * API for BOARD_BootClockRUN configuration 194 ******************************************************************************/ 195 #if defined(__cplusplus) 196 extern "C" { 197 #endif /* __cplusplus*/ 198 199 /*! 200 * @brief This function executes configuration of clocks. 201 * 202 */ 203 void BOARD_BootClockRUN(void); 204 205 #if defined(__cplusplus) 206 } 207 #endif /* __cplusplus*/ 208 209 /******************************************************************************* 210 ******************* Configuration BOARD_BootClockRUN_800M ********************* 211 ******************************************************************************/ 212 /******************************************************************************* 213 * Definitions for BOARD_BootClockRUN_800M configuration 214 ******************************************************************************/ 215 #if __CORTEX_M == 7 216 #define BOARD_BOOTCLOCKRUN_800M_CORE_CLOCK 800000000UL /*!< CM7 Core clock frequency: 800000000Hz */ 217 #else 218 #define BOARD_BOOTCLOCKRUN_800M_CORE_CLOCK 392727272UL /*!< CM4 Core clock frequency: 392727272Hz */ 219 #endif 220 221 /* Clock outputs (values are in Hz): */ 222 #define BOARD_BOOTCLOCKRUN_800M_ACMP_CLK_ROOT 24000000UL 223 #define BOARD_BOOTCLOCKRUN_800M_ADC1_CLK_ROOT 24000000UL 224 #define BOARD_BOOTCLOCKRUN_800M_ADC2_CLK_ROOT 24000000UL 225 #define BOARD_BOOTCLOCKRUN_800M_ARM_PLL_CLK 2400000000UL 226 #define BOARD_BOOTCLOCKRUN_800M_ASRC_CLK_ROOT 24000000UL 227 #define BOARD_BOOTCLOCKRUN_800M_AXI_CLK_ROOT 800000000UL 228 #define BOARD_BOOTCLOCKRUN_800M_BUS_CLK_ROOT 240000000UL 229 #define BOARD_BOOTCLOCKRUN_800M_BUS_LPSR_CLK_ROOT 160000000UL 230 #define BOARD_BOOTCLOCKRUN_800M_CAN1_CLK_ROOT 24000000UL 231 #define BOARD_BOOTCLOCKRUN_800M_CAN2_CLK_ROOT 24000000UL 232 #define BOARD_BOOTCLOCKRUN_800M_CAN3_CLK_ROOT 24000000UL 233 #define BOARD_BOOTCLOCKRUN_800M_CCM_CLKO1_CLK_ROOT 24000000UL 234 #define BOARD_BOOTCLOCKRUN_800M_CCM_CLKO2_CLK_ROOT 24000000UL 235 #define BOARD_BOOTCLOCKRUN_800M_CLK_1M 1000000UL 236 #define BOARD_BOOTCLOCKRUN_800M_CSI2_CLK_ROOT 24000000UL 237 #define BOARD_BOOTCLOCKRUN_800M_CSI2_ESC_CLK_ROOT 24000000UL 238 #define BOARD_BOOTCLOCKRUN_800M_CSI2_UI_CLK_ROOT 24000000UL 239 #define BOARD_BOOTCLOCKRUN_800M_CSI_CLK_ROOT 24000000UL 240 #define BOARD_BOOTCLOCKRUN_800M_CSSYS_CLK_ROOT 24000000UL 241 #define BOARD_BOOTCLOCKRUN_800M_CSTRACE_CLK_ROOT 132000000UL 242 #define BOARD_BOOTCLOCKRUN_800M_ELCDIF_CLK_ROOT 24000000UL 243 #define BOARD_BOOTCLOCKRUN_800M_EMV1_CLK_ROOT 24000000UL 244 #define BOARD_BOOTCLOCKRUN_800M_EMV2_CLK_ROOT 24000000UL 245 #define BOARD_BOOTCLOCKRUN_800M_ENET1_CLK_ROOT 24000000UL 246 #define BOARD_BOOTCLOCKRUN_800M_ENET2_CLK_ROOT 24000000UL 247 #define BOARD_BOOTCLOCKRUN_800M_ENET_1G_REF_CLK 0UL 248 #define BOARD_BOOTCLOCKRUN_800M_ENET_1G_TX_CLK 24000000UL 249 #define BOARD_BOOTCLOCKRUN_800M_ENET_25M_CLK_ROOT 24000000UL 250 #define BOARD_BOOTCLOCKRUN_800M_ENET_QOS_CLK_ROOT 24000000UL 251 #define BOARD_BOOTCLOCKRUN_800M_ENET_QOS_REF_CLK 0UL 252 #define BOARD_BOOTCLOCKRUN_800M_ENET_QOS_TX_CLK 0UL 253 #define BOARD_BOOTCLOCKRUN_800M_ENET_REF_CLK 0UL 254 #define BOARD_BOOTCLOCKRUN_800M_ENET_TIMER1_CLK_ROOT 24000000UL 255 #define BOARD_BOOTCLOCKRUN_800M_ENET_TIMER2_CLK_ROOT 24000000UL 256 #define BOARD_BOOTCLOCKRUN_800M_ENET_TIMER3_CLK_ROOT 24000000UL 257 #define BOARD_BOOTCLOCKRUN_800M_ENET_TX_CLK 0UL 258 #define BOARD_BOOTCLOCKRUN_800M_FLEXIO1_CLK_ROOT 24000000UL 259 #define BOARD_BOOTCLOCKRUN_800M_FLEXIO2_CLK_ROOT 24000000UL 260 #define BOARD_BOOTCLOCKRUN_800M_FLEXSPI1_CLK_ROOT 24000000UL 261 #define BOARD_BOOTCLOCKRUN_800M_FLEXSPI2_CLK_ROOT 24000000UL 262 #define BOARD_BOOTCLOCKRUN_800M_GC355_CLK_ROOT 492000012UL 263 #define BOARD_BOOTCLOCKRUN_800M_GPT1_CLK_ROOT 24000000UL 264 #define BOARD_BOOTCLOCKRUN_800M_GPT1_IPG_CLK_HIGHFREQ 24000000UL 265 #define BOARD_BOOTCLOCKRUN_800M_GPT2_CLK_ROOT 24000000UL 266 #define BOARD_BOOTCLOCKRUN_800M_GPT2_IPG_CLK_HIGHFREQ 24000000UL 267 #define BOARD_BOOTCLOCKRUN_800M_GPT3_CLK_ROOT 24000000UL 268 #define BOARD_BOOTCLOCKRUN_800M_GPT3_IPG_CLK_HIGHFREQ 24000000UL 269 #define BOARD_BOOTCLOCKRUN_800M_GPT4_CLK_ROOT 24000000UL 270 #define BOARD_BOOTCLOCKRUN_800M_GPT4_IPG_CLK_HIGHFREQ 24000000UL 271 #define BOARD_BOOTCLOCKRUN_800M_GPT5_CLK_ROOT 24000000UL 272 #define BOARD_BOOTCLOCKRUN_800M_GPT5_IPG_CLK_HIGHFREQ 24000000UL 273 #define BOARD_BOOTCLOCKRUN_800M_GPT6_CLK_ROOT 24000000UL 274 #define BOARD_BOOTCLOCKRUN_800M_GPT6_IPG_CLK_HIGHFREQ 24000000UL 275 #define BOARD_BOOTCLOCKRUN_800M_LCDIFV2_CLK_ROOT 24000000UL 276 #define BOARD_BOOTCLOCKRUN_800M_LPI2C1_CLK_ROOT 24000000UL 277 #define BOARD_BOOTCLOCKRUN_800M_LPI2C2_CLK_ROOT 24000000UL 278 #define BOARD_BOOTCLOCKRUN_800M_LPI2C3_CLK_ROOT 24000000UL 279 #define BOARD_BOOTCLOCKRUN_800M_LPI2C4_CLK_ROOT 24000000UL 280 #define BOARD_BOOTCLOCKRUN_800M_LPI2C5_CLK_ROOT 24000000UL 281 #define BOARD_BOOTCLOCKRUN_800M_LPI2C6_CLK_ROOT 24000000UL 282 #define BOARD_BOOTCLOCKRUN_800M_LPSPI1_CLK_ROOT 24000000UL 283 #define BOARD_BOOTCLOCKRUN_800M_LPSPI2_CLK_ROOT 24000000UL 284 #define BOARD_BOOTCLOCKRUN_800M_LPSPI3_CLK_ROOT 24000000UL 285 #define BOARD_BOOTCLOCKRUN_800M_LPSPI4_CLK_ROOT 24000000UL 286 #define BOARD_BOOTCLOCKRUN_800M_LPSPI5_CLK_ROOT 24000000UL 287 #define BOARD_BOOTCLOCKRUN_800M_LPSPI6_CLK_ROOT 24000000UL 288 #define BOARD_BOOTCLOCKRUN_800M_LPUART10_CLK_ROOT 24000000UL 289 #define BOARD_BOOTCLOCKRUN_800M_LPUART11_CLK_ROOT 24000000UL 290 #define BOARD_BOOTCLOCKRUN_800M_LPUART12_CLK_ROOT 24000000UL 291 #define BOARD_BOOTCLOCKRUN_800M_LPUART1_CLK_ROOT 24000000UL 292 #define BOARD_BOOTCLOCKRUN_800M_LPUART2_CLK_ROOT 24000000UL 293 #define BOARD_BOOTCLOCKRUN_800M_LPUART3_CLK_ROOT 24000000UL 294 #define BOARD_BOOTCLOCKRUN_800M_LPUART4_CLK_ROOT 24000000UL 295 #define BOARD_BOOTCLOCKRUN_800M_LPUART5_CLK_ROOT 24000000UL 296 #define BOARD_BOOTCLOCKRUN_800M_LPUART6_CLK_ROOT 24000000UL 297 #define BOARD_BOOTCLOCKRUN_800M_LPUART7_CLK_ROOT 24000000UL 298 #define BOARD_BOOTCLOCKRUN_800M_LPUART8_CLK_ROOT 24000000UL 299 #define BOARD_BOOTCLOCKRUN_800M_LPUART9_CLK_ROOT 24000000UL 300 #define BOARD_BOOTCLOCKRUN_800M_M4_CLK_ROOT 392727272UL 301 #define BOARD_BOOTCLOCKRUN_800M_M4_SYSTICK_CLK_ROOT 24000000UL 302 #define BOARD_BOOTCLOCKRUN_800M_M7_CLK_ROOT 800000000UL 303 #define BOARD_BOOTCLOCKRUN_800M_M7_SYSTICK_CLK_ROOT 100000UL 304 #define BOARD_BOOTCLOCKRUN_800M_MIC_CLK_ROOT 24000000UL 305 #define BOARD_BOOTCLOCKRUN_800M_MIPI_DSI_TX_CLK_ESC_ROOT24000000UL 306 #define BOARD_BOOTCLOCKRUN_800M_MIPI_ESC_CLK_ROOT 24000000UL 307 #define BOARD_BOOTCLOCKRUN_800M_MIPI_REF_CLK_ROOT 24000000UL 308 #define BOARD_BOOTCLOCKRUN_800M_MQS_CLK_ROOT 24000000UL 309 #define BOARD_BOOTCLOCKRUN_800M_MQS_MCLK 24000000UL 310 #define BOARD_BOOTCLOCKRUN_800M_OSC_24M 24000000UL 311 #define BOARD_BOOTCLOCKRUN_800M_OSC_32K 32768UL 312 #define BOARD_BOOTCLOCKRUN_800M_OSC_RC_16M 16000000UL 313 #define BOARD_BOOTCLOCKRUN_800M_OSC_RC_400M 400000000UL 314 #define BOARD_BOOTCLOCKRUN_800M_OSC_RC_48M 48000000UL 315 #define BOARD_BOOTCLOCKRUN_800M_OSC_RC_48M_DIV2 24000000UL 316 #define BOARD_BOOTCLOCKRUN_800M_PLL_AUDIO_CLK 0UL 317 #define BOARD_BOOTCLOCKRUN_800M_PLL_AUDIO_SS_MODULATION0UL 318 #define BOARD_BOOTCLOCKRUN_800M_PLL_AUDIO_SS_RANGE 0UL 319 #define BOARD_BOOTCLOCKRUN_800M_PLL_VIDEO_CLK 984000025UL 320 #define BOARD_BOOTCLOCKRUN_800M_PLL_VIDEO_SS_MODULATION0UL 321 #define BOARD_BOOTCLOCKRUN_800M_PLL_VIDEO_SS_RANGE 0UL 322 #define BOARD_BOOTCLOCKRUN_800M_SAI1_CLK_ROOT 24000000UL 323 #define BOARD_BOOTCLOCKRUN_800M_SAI1_MCLK1 24000000UL 324 #define BOARD_BOOTCLOCKRUN_800M_SAI1_MCLK2 0UL 325 #define BOARD_BOOTCLOCKRUN_800M_SAI1_MCLK3 24000000UL 326 #define BOARD_BOOTCLOCKRUN_800M_SAI2_CLK_ROOT 24000000UL 327 #define BOARD_BOOTCLOCKRUN_800M_SAI2_MCLK1 24000000UL 328 #define BOARD_BOOTCLOCKRUN_800M_SAI2_MCLK2 0UL 329 #define BOARD_BOOTCLOCKRUN_800M_SAI2_MCLK3 24000000UL 330 #define BOARD_BOOTCLOCKRUN_800M_SAI3_CLK_ROOT 24000000UL 331 #define BOARD_BOOTCLOCKRUN_800M_SAI3_MCLK1 24000000UL 332 #define BOARD_BOOTCLOCKRUN_800M_SAI3_MCLK2 0UL 333 #define BOARD_BOOTCLOCKRUN_800M_SAI3_MCLK3 24000000UL 334 #define BOARD_BOOTCLOCKRUN_800M_SAI4_CLK_ROOT 24000000UL 335 #define BOARD_BOOTCLOCKRUN_800M_SAI4_MCLK1 24000000UL 336 #define BOARD_BOOTCLOCKRUN_800M_SAI4_MCLK2 0UL 337 #define BOARD_BOOTCLOCKRUN_800M_SEMC_CLK_ROOT 198000000UL 338 #define BOARD_BOOTCLOCKRUN_800M_SPDIF_CLK_ROOT 24000000UL 339 #define BOARD_BOOTCLOCKRUN_800M_SPDIF_EXTCLK_OUT 0UL 340 #define BOARD_BOOTCLOCKRUN_800M_SYS_PLL1_CLK 0UL 341 #define BOARD_BOOTCLOCKRUN_800M_SYS_PLL1_DIV2_CLK 0UL 342 #define BOARD_BOOTCLOCKRUN_800M_SYS_PLL1_DIV5_CLK 0UL 343 #define BOARD_BOOTCLOCKRUN_800M_SYS_PLL1_SS_MODULATION0UL 344 #define BOARD_BOOTCLOCKRUN_800M_SYS_PLL1_SS_RANGE 0UL 345 #define BOARD_BOOTCLOCKRUN_800M_SYS_PLL2_CLK 528000000UL 346 #define BOARD_BOOTCLOCKRUN_800M_SYS_PLL2_PFD0_CLK 352000000UL 347 #define BOARD_BOOTCLOCKRUN_800M_SYS_PLL2_PFD1_CLK 594000000UL 348 #define BOARD_BOOTCLOCKRUN_800M_SYS_PLL2_PFD2_CLK 396000000UL 349 #define BOARD_BOOTCLOCKRUN_800M_SYS_PLL2_PFD3_CLK 297000000UL 350 #define BOARD_BOOTCLOCKRUN_800M_SYS_PLL2_SS_MODULATION0UL 351 #define BOARD_BOOTCLOCKRUN_800M_SYS_PLL2_SS_RANGE 0UL 352 #define BOARD_BOOTCLOCKRUN_800M_SYS_PLL3_CLK 480000000UL 353 #define BOARD_BOOTCLOCKRUN_800M_SYS_PLL3_DIV2_CLK 240000000UL 354 #define BOARD_BOOTCLOCKRUN_800M_SYS_PLL3_PFD0_CLK 664615384UL 355 #define BOARD_BOOTCLOCKRUN_800M_SYS_PLL3_PFD1_CLK 508235294UL 356 #define BOARD_BOOTCLOCKRUN_800M_SYS_PLL3_PFD2_CLK 270000000UL 357 #define BOARD_BOOTCLOCKRUN_800M_SYS_PLL3_PFD3_CLK 392727272UL 358 #define BOARD_BOOTCLOCKRUN_800M_USDHC1_CLK_ROOT 24000000UL 359 #define BOARD_BOOTCLOCKRUN_800M_USDHC2_CLK_ROOT 24000000UL 360 361 362 /******************************************************************************* 363 * API for BOARD_BootClockRUN_800M configuration 364 ******************************************************************************/ 365 #if defined(__cplusplus) 366 extern "C" { 367 #endif /* __cplusplus*/ 368 369 /*! 370 * @brief This function executes configuration of clocks. 371 * 372 */ 373 void BOARD_BootClockRUN_800M(void); 374 375 #if defined(__cplusplus) 376 } 377 #endif /* __cplusplus*/ 378 379 #endif /* _CLOCK_CONFIG_H_ */ 380 381
