1 /* 2 * Copyright 2022 NXP 3 * All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef _CLOCK_CONFIG_H_ 9 #define _CLOCK_CONFIG_H_ 10 11 #include "fsl_common.h" 12 13 /******************************************************************************* 14 * Definitions 15 ******************************************************************************/ 16 #define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ 17 18 #define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ 19 /******************************************************************************* 20 ************************ BOARD_InitBootClocks function ************************ 21 ******************************************************************************/ 22 23 #if defined(__cplusplus) 24 extern "C" { 25 #endif /* __cplusplus*/ 26 27 /*! 28 * @brief This function executes default configuration of clocks. 29 * 30 */ 31 void BOARD_InitBootClocks(void); 32 33 #if defined(__cplusplus) 34 } 35 #endif /* __cplusplus*/ 36 37 /******************************************************************************* 38 ********************** Configuration BOARD_BootClockRUN *********************** 39 ******************************************************************************/ 40 /******************************************************************************* 41 * Definitions for BOARD_BootClockRUN configuration 42 ******************************************************************************/ 43 #define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */ 44 45 /* Clock outputs (values are in Hz): */ 46 #define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL 47 #define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL 48 #define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL 49 #define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL 50 #define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL 51 #define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL 52 #define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL 53 #define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL 54 #define BOARD_BOOTCLOCKRUN_ENET2_125M_CLK 1200000UL 55 #define BOARD_BOOTCLOCKRUN_ENET2_REF_CLK 0UL 56 #define BOARD_BOOTCLOCKRUN_ENET2_TX_CLK 0UL 57 #define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL 58 #define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL 59 #define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL 60 #define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL 61 #define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL 62 #define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL 63 #define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 130909090UL 64 #define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 130909090UL 65 #define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL 66 #define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL 67 #define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL 68 #define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 67500000UL 69 #define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL 70 #define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL 71 #define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL 72 #define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL 73 #define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL 74 #define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 24000000UL 75 #define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL 76 #define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL 77 #define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL 78 #define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL 79 #define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL 80 #define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL 81 #define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL 82 #define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL 83 #define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL 84 #define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL 85 #define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL 86 #define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL 87 #define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL 88 #define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL 89 #define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL 90 #define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL 91 #define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL 92 #define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 0UL 93 #define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 0UL 94 #define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL 95 #define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL 96 97 /*! @brief Arm PLL set for BOARD_BootClockRUN configuration. 98 */ 99 extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN; 100 /*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration. 101 */ 102 extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN; 103 /*! @brief Sys PLL for BOARD_BootClockRUN configuration. 104 */ 105 extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN; 106 /*! @brief Video PLL set for BOARD_BootClockRUN configuration. 107 */ 108 extern const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN; 109 110 /******************************************************************************* 111 * API for BOARD_BootClockRUN configuration 112 ******************************************************************************/ 113 #if defined(__cplusplus) 114 extern "C" { 115 #endif /* __cplusplus*/ 116 117 /*! 118 * @brief This function executes configuration of clocks. 119 * 120 */ 121 void BOARD_BootClockRUN(void); 122 123 #if defined(__cplusplus) 124 } 125 #endif /* __cplusplus*/ 126 127 /******************************************************************************* 128 ******************* Configuration BOARD_BootClockRUN_528M ********************* 129 ******************************************************************************/ 130 /******************************************************************************* 131 * Definitions for BOARD_BootClockRUN_528M configuration 132 ******************************************************************************/ 133 #define BOARD_BOOTCLOCKRUN_528M_CORE_CLOCK 528000000U /*!< Core clock frequency: 528000000Hz */ 134 135 /* Clock outputs (values are in Hz): */ 136 #define BOARD_BOOTCLOCKRUN_528M_AHB_CLK_ROOT 528000000UL 137 #define BOARD_BOOTCLOCKRUN_528M_CAN_CLK_ROOT 40000000UL 138 #define BOARD_BOOTCLOCKRUN_528M_CKIL_SYNC_CLK_ROOT 32768UL 139 #define BOARD_BOOTCLOCKRUN_528M_CLKO1_CLK 0UL 140 #define BOARD_BOOTCLOCKRUN_528M_CLKO2_CLK 0UL 141 #define BOARD_BOOTCLOCKRUN_528M_CLK_1M 1000000UL 142 #define BOARD_BOOTCLOCKRUN_528M_CLK_24M 24000000UL 143 #define BOARD_BOOTCLOCKRUN_528M_CSI_CLK_ROOT 12000000UL 144 #define BOARD_BOOTCLOCKRUN_528M_ENET2_125M_CLK 1200000UL 145 #define BOARD_BOOTCLOCKRUN_528M_ENET2_REF_CLK 0UL 146 #define BOARD_BOOTCLOCKRUN_528M_ENET2_TX_CLK 0UL 147 #define BOARD_BOOTCLOCKRUN_528M_ENET_125M_CLK 2400000UL 148 #define BOARD_BOOTCLOCKRUN_528M_ENET_25M_REF_CLK 1200000UL 149 #define BOARD_BOOTCLOCKRUN_528M_ENET_REF_CLK 0UL 150 #define BOARD_BOOTCLOCKRUN_528M_ENET_TX_CLK 0UL 151 #define BOARD_BOOTCLOCKRUN_528M_FLEXIO1_CLK_ROOT 30000000UL 152 #define BOARD_BOOTCLOCKRUN_528M_FLEXIO2_CLK_ROOT 30000000UL 153 #define BOARD_BOOTCLOCKRUN_528M_FLEXSPI2_CLK_ROOT 130909090UL 154 #define BOARD_BOOTCLOCKRUN_528M_FLEXSPI_CLK_ROOT 130909090UL 155 #define BOARD_BOOTCLOCKRUN_528M_GPT1_IPG_CLK_HIGHFREQ 66000000UL 156 #define BOARD_BOOTCLOCKRUN_528M_GPT2_IPG_CLK_HIGHFREQ 66000000UL 157 #define BOARD_BOOTCLOCKRUN_528M_IPG_CLK_ROOT 132000000UL 158 #define BOARD_BOOTCLOCKRUN_528M_LCDIF_CLK_ROOT 67500000UL 159 #define BOARD_BOOTCLOCKRUN_528M_LPI2C_CLK_ROOT 60000000UL 160 #define BOARD_BOOTCLOCKRUN_528M_LPSPI_CLK_ROOT 105600000UL 161 #define BOARD_BOOTCLOCKRUN_528M_LVDS1_CLK 1200000000UL 162 #define BOARD_BOOTCLOCKRUN_528M_MQS_MCLK 63529411UL 163 #define BOARD_BOOTCLOCKRUN_528M_PERCLK_CLK_ROOT 66000000UL 164 #define BOARD_BOOTCLOCKRUN_528M_PLL7_MAIN_CLK 24000000UL 165 #define BOARD_BOOTCLOCKRUN_528M_SAI1_CLK_ROOT 63529411UL 166 #define BOARD_BOOTCLOCKRUN_528M_SAI1_MCLK1 63529411UL 167 #define BOARD_BOOTCLOCKRUN_528M_SAI1_MCLK2 63529411UL 168 #define BOARD_BOOTCLOCKRUN_528M_SAI1_MCLK3 30000000UL 169 #define BOARD_BOOTCLOCKRUN_528M_SAI2_CLK_ROOT 63529411UL 170 #define BOARD_BOOTCLOCKRUN_528M_SAI2_MCLK1 63529411UL 171 #define BOARD_BOOTCLOCKRUN_528M_SAI2_MCLK2 0UL 172 #define BOARD_BOOTCLOCKRUN_528M_SAI2_MCLK3 30000000UL 173 #define BOARD_BOOTCLOCKRUN_528M_SAI3_CLK_ROOT 63529411UL 174 #define BOARD_BOOTCLOCKRUN_528M_SAI3_MCLK1 63529411UL 175 #define BOARD_BOOTCLOCKRUN_528M_SAI3_MCLK2 0UL 176 #define BOARD_BOOTCLOCKRUN_528M_SAI3_MCLK3 30000000UL 177 #define BOARD_BOOTCLOCKRUN_528M_SEMC_CLK_ROOT 66000000UL 178 #define BOARD_BOOTCLOCKRUN_528M_SPDIF0_CLK_ROOT 30000000UL 179 #define BOARD_BOOTCLOCKRUN_528M_SPDIF0_EXTCLK_OUT 0UL 180 #define BOARD_BOOTCLOCKRUN_528M_TRACE_CLK_ROOT 132000000UL 181 #define BOARD_BOOTCLOCKRUN_528M_UART_CLK_ROOT 80000000UL 182 #define BOARD_BOOTCLOCKRUN_528M_USBPHY1_CLK 0UL 183 #define BOARD_BOOTCLOCKRUN_528M_USBPHY2_CLK 0UL 184 #define BOARD_BOOTCLOCKRUN_528M_USDHC1_CLK_ROOT 198000000UL 185 #define BOARD_BOOTCLOCKRUN_528M_USDHC2_CLK_ROOT 198000000UL 186 187 /*! @brief Arm PLL set for BOARD_BootClockRUN_528M configuration. 188 */ 189 extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN_528M; 190 /*! @brief Usb1 PLL set for BOARD_BootClockRUN_528M configuration. 191 */ 192 extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN_528M; 193 /*! @brief Sys PLL for BOARD_BootClockRUN_528M configuration. 194 */ 195 extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN_528M; 196 /*! @brief Video PLL set for BOARD_BootClockRUN_528M configuration. 197 */ 198 extern const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN_528M; 199 200 /******************************************************************************* 201 * API for BOARD_BootClockRUN_528M configuration 202 ******************************************************************************/ 203 #if defined(__cplusplus) 204 extern "C" { 205 #endif /* __cplusplus*/ 206 207 /*! 208 * @brief This function executes configuration of clocks. 209 * 210 */ 211 void BOARD_BootClockRUN_528M(void); 212 213 #if defined(__cplusplus) 214 } 215 #endif /* __cplusplus*/ 216 217 #endif /* _CLOCK_CONFIG_H_ */ 218 219
