1 /*
2 * Copyright 2017-2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include "fsl_common.h"
9 #include "fsl_debug_console.h"
10 #include "board.h"
11 #if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
12 #include "fsl_lpi2c.h"
13 #endif /* SDK_I2C_BASED_COMPONENT_USED */
14 #include "fsl_iomuxc.h"
15 /*******************************************************************************
16 * Variables
17 ******************************************************************************/
18
19 /*******************************************************************************
20 * Code
21 ******************************************************************************/
22
23 /* Get debug console frequency. */
BOARD_DebugConsoleSrcFreq(void)24 uint32_t BOARD_DebugConsoleSrcFreq(void)
25 {
26 uint32_t freq;
27
28 /* To make it simple, we assume default PLL and divider settings, and the only variable
29 from application is use PLL3 source or OSC source */
30 if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */
31 {
32 freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
33 }
34 else
35 {
36 freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
37 }
38
39 return freq;
40 }
41
42 /* Initialize debug console. */
BOARD_InitDebugConsole(void)43 void BOARD_InitDebugConsole(void)
44 {
45 uint32_t uartClkSrcFreq = BOARD_DebugConsoleSrcFreq();
46
47 DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
48 }
49
50 #if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
BOARD_LPI2C_Init(LPI2C_Type * base,uint32_t clkSrc_Hz)51 void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz)
52 {
53 lpi2c_master_config_t lpi2cConfig = {0};
54
55 /*
56 * lpi2cConfig.debugEnable = false;
57 * lpi2cConfig.ignoreAck = false;
58 * lpi2cConfig.pinConfig = kLPI2C_2PinOpenDrain;
59 * lpi2cConfig.baudRate_Hz = 100000U;
60 * lpi2cConfig.busIdleTimeout_ns = 0;
61 * lpi2cConfig.pinLowTimeout_ns = 0;
62 * lpi2cConfig.sdaGlitchFilterWidth_ns = 0;
63 * lpi2cConfig.sclGlitchFilterWidth_ns = 0;
64 */
65 LPI2C_MasterGetDefaultConfig(&lpi2cConfig);
66 LPI2C_MasterInit(base, &lpi2cConfig, clkSrc_Hz);
67 }
68
BOARD_LPI2C_Send(LPI2C_Type * base,uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,uint8_t * txBuff,uint8_t txBuffSize)69 status_t BOARD_LPI2C_Send(LPI2C_Type *base,
70 uint8_t deviceAddress,
71 uint32_t subAddress,
72 uint8_t subAddressSize,
73 uint8_t *txBuff,
74 uint8_t txBuffSize)
75 {
76 lpi2c_master_transfer_t xfer;
77
78 xfer.flags = kLPI2C_TransferDefaultFlag;
79 xfer.slaveAddress = deviceAddress;
80 xfer.direction = kLPI2C_Write;
81 xfer.subaddress = subAddress;
82 xfer.subaddressSize = subAddressSize;
83 xfer.data = txBuff;
84 xfer.dataSize = txBuffSize;
85
86 return LPI2C_MasterTransferBlocking(base, &xfer);
87 }
88
BOARD_LPI2C_Receive(LPI2C_Type * base,uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,uint8_t * rxBuff,uint8_t rxBuffSize)89 status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
90 uint8_t deviceAddress,
91 uint32_t subAddress,
92 uint8_t subAddressSize,
93 uint8_t *rxBuff,
94 uint8_t rxBuffSize)
95 {
96 lpi2c_master_transfer_t xfer;
97
98 xfer.flags = kLPI2C_TransferDefaultFlag;
99 xfer.slaveAddress = deviceAddress;
100 xfer.direction = kLPI2C_Read;
101 xfer.subaddress = subAddress;
102 xfer.subaddressSize = subAddressSize;
103 xfer.data = rxBuff;
104 xfer.dataSize = rxBuffSize;
105
106 return LPI2C_MasterTransferBlocking(base, &xfer);
107 }
108
BOARD_LPI2C_SendSCCB(LPI2C_Type * base,uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,uint8_t * txBuff,uint8_t txBuffSize)109 status_t BOARD_LPI2C_SendSCCB(LPI2C_Type *base,
110 uint8_t deviceAddress,
111 uint32_t subAddress,
112 uint8_t subAddressSize,
113 uint8_t *txBuff,
114 uint8_t txBuffSize)
115 {
116 lpi2c_master_transfer_t xfer;
117
118 xfer.flags = kLPI2C_TransferDefaultFlag;
119 xfer.slaveAddress = deviceAddress;
120 xfer.direction = kLPI2C_Write;
121 xfer.subaddress = subAddress;
122 xfer.subaddressSize = subAddressSize;
123 xfer.data = txBuff;
124 xfer.dataSize = txBuffSize;
125
126 return LPI2C_MasterTransferBlocking(base, &xfer);
127 }
128
BOARD_LPI2C_ReceiveSCCB(LPI2C_Type * base,uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,uint8_t * rxBuff,uint8_t rxBuffSize)129 status_t BOARD_LPI2C_ReceiveSCCB(LPI2C_Type *base,
130 uint8_t deviceAddress,
131 uint32_t subAddress,
132 uint8_t subAddressSize,
133 uint8_t *rxBuff,
134 uint8_t rxBuffSize)
135 {
136 status_t status;
137 lpi2c_master_transfer_t xfer;
138
139 xfer.flags = kLPI2C_TransferDefaultFlag;
140 xfer.slaveAddress = deviceAddress;
141 xfer.direction = kLPI2C_Write;
142 xfer.subaddress = subAddress;
143 xfer.subaddressSize = subAddressSize;
144 xfer.data = NULL;
145 xfer.dataSize = 0;
146
147 status = LPI2C_MasterTransferBlocking(base, &xfer);
148
149 if (kStatus_Success == status)
150 {
151 xfer.subaddressSize = 0;
152 xfer.direction = kLPI2C_Read;
153 xfer.data = rxBuff;
154 xfer.dataSize = rxBuffSize;
155
156 status = LPI2C_MasterTransferBlocking(base, &xfer);
157 }
158
159 return status;
160 }
161
BOARD_Accel_I2C_Init(void)162 void BOARD_Accel_I2C_Init(void)
163 {
164 BOARD_LPI2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
165 }
166
BOARD_Accel_I2C_Send(uint8_t deviceAddress,uint32_t subAddress,uint8_t subaddressSize,uint32_t txBuff)167 status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)
168 {
169 uint8_t data = (uint8_t)txBuff;
170
171 return BOARD_LPI2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);
172 }
173
BOARD_Accel_I2C_Receive(uint8_t deviceAddress,uint32_t subAddress,uint8_t subaddressSize,uint8_t * rxBuff,uint8_t rxBuffSize)174 status_t BOARD_Accel_I2C_Receive(
175 uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
176 {
177 return BOARD_LPI2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);
178 }
179
BOARD_Codec_I2C_Init(void)180 void BOARD_Codec_I2C_Init(void)
181 {
182 BOARD_LPI2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
183 }
184
BOARD_Codec_I2C_Send(uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,const uint8_t * txBuff,uint8_t txBuffSize)185 status_t BOARD_Codec_I2C_Send(
186 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
187 {
188 return BOARD_LPI2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
189 txBuffSize);
190 }
191
BOARD_Codec_I2C_Receive(uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,uint8_t * rxBuff,uint8_t rxBuffSize)192 status_t BOARD_Codec_I2C_Receive(
193 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
194 {
195 return BOARD_LPI2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
196 }
197
BOARD_Camera_I2C_Init(void)198 void BOARD_Camera_I2C_Init(void)
199 {
200 CLOCK_SetMux(kCLOCK_Lpi2cMux, BOARD_CAMERA_I2C_CLOCK_SOURCE_SELECT);
201 CLOCK_SetDiv(kCLOCK_Lpi2cDiv, BOARD_CAMERA_I2C_CLOCK_SOURCE_DIVIDER);
202 BOARD_LPI2C_Init(BOARD_CAMERA_I2C_BASEADDR, BOARD_CAMERA_I2C_CLOCK_FREQ);
203 }
204
BOARD_Camera_I2C_Send(uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,const uint8_t * txBuff,uint8_t txBuffSize)205 status_t BOARD_Camera_I2C_Send(
206 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
207 {
208 return BOARD_LPI2C_Send(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
209 txBuffSize);
210 }
211
BOARD_Camera_I2C_Receive(uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,uint8_t * rxBuff,uint8_t rxBuffSize)212 status_t BOARD_Camera_I2C_Receive(
213 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
214 {
215 return BOARD_LPI2C_Receive(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff,
216 rxBuffSize);
217 }
218
BOARD_Camera_I2C_SendSCCB(uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,const uint8_t * txBuff,uint8_t txBuffSize)219 status_t BOARD_Camera_I2C_SendSCCB(
220 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
221 {
222 return BOARD_LPI2C_SendSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
223 txBuffSize);
224 }
225
BOARD_Camera_I2C_ReceiveSCCB(uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,uint8_t * rxBuff,uint8_t rxBuffSize)226 status_t BOARD_Camera_I2C_ReceiveSCCB(
227 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
228 {
229 return BOARD_LPI2C_ReceiveSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff,
230 rxBuffSize);
231 }
232
BOARD_Touch_I2C_Send(uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,const uint8_t * txBuff,uint8_t txBuffSize)233 status_t BOARD_Touch_I2C_Send(
234 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
235 {
236 return BOARD_LPI2C_Send(BOARD_TOUCH_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
237 txBuffSize);
238 }
239
BOARD_Touch_I2C_Receive(uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,uint8_t * rxBuff,uint8_t rxBuffSize)240 status_t BOARD_Touch_I2C_Receive(
241 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
242 {
243 return BOARD_LPI2C_Receive(BOARD_TOUCH_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
244 }
245 #endif /* SDK_I2C_BASED_COMPONENT_USED */
246
247 /* MPU configuration. */
BOARD_ConfigMPU(void)248 void BOARD_ConfigMPU(void)
249 {
250 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
251 extern uint32_t Image$$RW_m_ncache$$Base[];
252 /* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */
253 extern uint32_t Image$$RW_m_ncache_unused$$Base[];
254 extern uint32_t Image$$RW_m_ncache_unused$$ZI$$Limit[];
255 uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base;
256 uint32_t size = ((uint32_t)Image$$RW_m_ncache_unused$$Base == nonCacheStart) ?
257 0 :
258 ((uint32_t)Image$$RW_m_ncache_unused$$ZI$$Limit - nonCacheStart);
259 #elif defined(__MCUXPRESSO)
260 extern uint32_t __base_NCACHE_REGION;
261 extern uint32_t __top_NCACHE_REGION;
262 uint32_t nonCacheStart = (uint32_t)(&__base_NCACHE_REGION);
263 uint32_t size = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart;
264 #elif defined(__ICCARM__) || defined(__GNUC__)
265 extern uint32_t __NCACHE_REGION_START[];
266 extern uint32_t __NCACHE_REGION_SIZE[];
267 uint32_t nonCacheStart = (uint32_t)__NCACHE_REGION_START;
268 uint32_t size = (uint32_t)__NCACHE_REGION_SIZE;
269 #endif
270 volatile uint32_t i = 0;
271
272 /* Disable I cache and D cache */
273 if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR))
274 {
275 SCB_DisableICache();
276 }
277 if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR))
278 {
279 SCB_DisableDCache();
280 }
281
282 /* Disable MPU */
283 ARM_MPU_Disable();
284
285 /* MPU configure:
286 * Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable,
287 * SubRegionDisable, Size)
288 * API in mpu_armv7.h.
289 * param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches
290 * disabled.
291 * param AccessPermission Data access permissions, allows you to configure read/write access for User and
292 * Privileged mode.
293 * Use MACROS defined in mpu_armv7.h:
294 * ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
295 * Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes.
296 * TypeExtField IsShareable IsCacheable IsBufferable Memory Attribute Shareability Cache
297 * 0 x 0 0 Strongly Ordered shareable
298 * 0 x 0 1 Device shareable
299 * 0 0 1 0 Normal not shareable Outer and inner write
300 * through no write allocate
301 * 0 0 1 1 Normal not shareable Outer and inner write
302 * back no write allocate
303 * 0 1 1 0 Normal shareable Outer and inner write
304 * through no write allocate
305 * 0 1 1 1 Normal shareable Outer and inner write
306 * back no write allocate
307 * 1 0 0 0 Normal not shareable outer and inner
308 * noncache
309 * 1 1 0 0 Normal shareable outer and inner
310 * noncache
311 * 1 0 1 1 Normal not shareable outer and inner write
312 * back write/read acllocate
313 * 1 1 1 1 Normal shareable outer and inner write
314 * back write/read acllocate
315 * 2 x 0 0 Device not shareable
316 * Above are normal use settings, if your want to see more details or want to config different inner/outter cache
317 * policy.
318 * please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide <dui0646b_cortex_m7_dgug.pdf>
319 * param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled.
320 * param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in
321 * mpu_armv7.h.
322 */
323
324 /*
325 * Add default region to deny access to whole address space to workaround speculative prefetch.
326 * Refer to Arm errata 1013783-B for more details.
327 *
328 */
329 /* Region 0 setting: Instruction access disabled, No data access permission. */
330 MPU->RBAR = ARM_MPU_RBAR(0, 0x00000000U);
331 MPU->RASR = ARM_MPU_RASR(1, ARM_MPU_AP_NONE, 0, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4GB);
332
333 /* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */
334 MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
335 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
336
337 /* Region 2 setting: Memory with Device type, not shareable, non-cacheable. */
338 MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
339 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
340
341 #if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
342 /* Region 3 setting: Memory with Normal type, not shareable, outer/inner write back. */
343 MPU->RBAR = ARM_MPU_RBAR(3, 0x60000000U);
344 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64MB);
345 #endif
346
347 /* Region 4 setting: Memory with Device type, not shareable, non-cacheable. */
348 MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
349 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
350
351 /* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */
352 MPU->RBAR = ARM_MPU_RBAR(5, 0x00000000U);
353 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
354
355 /* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */
356 MPU->RBAR = ARM_MPU_RBAR(6, 0x20000000U);
357 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
358
359 /* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */
360 MPU->RBAR = ARM_MPU_RBAR(7, 0x20200000U);
361 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
362
363 /* Region 8 setting: Memory with Normal type, not shareable, outer/inner write back */
364 MPU->RBAR = ARM_MPU_RBAR(8, 0x80000000U);
365 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
366
367 while ((size >> i) > 0x1U)
368 {
369 i++;
370 }
371
372 if (i != 0)
373 {
374 /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
375 assert(!(nonCacheStart % size));
376 assert(size == (uint32_t)(1 << i));
377 assert(i >= 5);
378
379 /* Region 9 setting: Memory with Normal type, not shareable, non-cacheable */
380 MPU->RBAR = ARM_MPU_RBAR(9, nonCacheStart);
381 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, i - 1);
382 }
383
384 /* Region 10 setting: Memory with Device type, not shareable, non-cacheable */
385 MPU->RBAR = ARM_MPU_RBAR(10, 0x40000000);
386 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4MB);
387
388 /* Enable MPU */
389 ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk);
390
391 /* Enable I cache and D cache */
392 SCB_EnableDCache();
393 SCB_EnableICache();
394 }
395
