1 /* 2 * Copyright (c) 2016, Freescale Semiconductor, Inc. 3 * Copyright 2016,2019 NXP 4 * All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef __USB_HOST_OHCI_H__ 10 #define __USB_HOST_OHCI_H__ 11 12 /******************************************************************************* 13 * Definitions 14 ******************************************************************************/ 15 16 /*! device not responding transfer error workaround enable or not 17 * The controller has "device not responding" error sometimes when connecting to LS device. 18 * when it is enabled, the SW will notify error to application only when the error occurs 19 * USB_HOST_OHCI_DEVICE_NOT_RESPONDING_WORKAROUND_CONSEQUENT_COUNT consecutively. 20 */ 21 #define USB_HOST_OHCI_DEVICE_NOT_RESPONDING_WORKAROUND (1U) 22 23 /*! The error counsts */ 24 #define USB_HOST_OHCI_DEVICE_NOT_RESPONDING_WORKAROUND_CONSEQUENT_COUNT (3U) 25 26 /*! HcRevision Register */ 27 #define USB_HOST_OHCI_REVISION_MASK (0xFFU) 28 29 /*! HcControl Register */ 30 #define USB_HOST_OHCI_CONTROL_CBSR_MASK (0x03U) 31 #define USB_HOST_OHCI_CONTROL_CBSR_C1_B1 (0U) 32 #define USB_HOST_OHCI_CONTROL_CBSR_C2_B1 (1U) 33 #define USB_HOST_OHCI_CONTROL_CBSR_C3_B1 (2U) 34 #define USB_HOST_OHCI_CONTROL_CBSR_C4_B1 (3U) 35 #define USB_HOST_OHCI_CONTROL_CBSR(n) ((n)&USB_HOST_OHCI_CONTROL_CBSR_MASK) 36 #define USB_HOST_OHCI_CONTROL_PLE_MASK (0x04U) 37 #define USB_HOST_OHCI_CONTROL_IE_MASK (0x08U) 38 #define USB_HOST_OHCI_CONTROL_CLE_MASK (0x10U) 39 #define USB_HOST_OHCI_CONTROL_BLE_MASK (0x20U) 40 #define USB_HOST_OHCI_CONTROL_HCFS_MASK (0xC0U) 41 #define USB_HOST_OHCI_CONTROL_HCFS_SHIFT (0x06U) 42 #define USB_HOST_OHCI_CONTROL_HCFS_RESET (0x00U) 43 #define USB_HOST_OHCI_CONTROL_HCFS_RESUME (0x01U) 44 #define USB_HOST_OHCI_CONTROL_HCFS_OPERATIONAL (0x02U) 45 #define USB_HOST_OHCI_CONTROL_HCFS_SUSPEND (0x03U) 46 #define USB_HOST_OHCI_CONTROL_HCFS(n) (((n) << USB_HOST_OHCI_CONTROL_HCFS_SHIFT) & USB_HOST_OHCI_CONTROL_HCFS_MASK) 47 #define USB_HOST_OHCI_CONTROL_IR_MASK (0x100U) 48 #define USB_HOST_OHCI_CONTROL_RWC_MASK (0x200U) 49 #define USB_HOST_OHCI_CONTROL_RWE_MASK (0x400U) 50 51 /*! HcCommandStatus Register */ 52 #define USB_HOST_OHCI_COMMAND_STATUS_HCR_MASK (0x01U) 53 #define USB_HOST_OHCI_COMMAND_STATUS_CLF_MASK (0x02U) 54 #define USB_HOST_OHCI_COMMAND_STATUS_BLF_MASK (0x04U) 55 #define USB_HOST_OHCI_COMMAND_STATUS_OCR_MASK (0x08U) 56 #define USB_HOST_OHCI_COMMAND_STATUS_SOC_MASK (0x30000U) 57 58 /*! HcInterruptStatus Register */ 59 #define USB_HOST_OHCI_INTERRUPT_STATUS_SO_MASK (0x01U) 60 #define USB_HOST_OHCI_INTERRUPT_STATUS_WDH_MASK (0x02U) 61 #define USB_HOST_OHCI_INTERRUPT_STATUS_SF_MASK (0x04U) 62 #define USB_HOST_OHCI_INTERRUPT_STATUS_RD_MASK (0x08U) 63 #define USB_HOST_OHCI_INTERRUPT_STATUS_UE_MASK (0x10U) 64 #define USB_HOST_OHCI_INTERRUPT_STATUS_FNO_MASK (0x20U) 65 #define USB_HOST_OHCI_INTERRUPT_STATUS_RHSC_MASK (0x40U) 66 #define USB_HOST_OHCI_INTERRUPT_STATUS_OC_MASK (0x40000000U) 67 #define USB_HOST_OHCI_INTERRUPT_STATUS_MASK (0x4000007FU) 68 69 /*! HcInterruptEnable Register */ 70 #define USB_HOST_OHCI_INTERRUPT_ENABLE_SO_MASK (0x01U) 71 #define USB_HOST_OHCI_INTERRUPT_ENABLE_WDH_MASK (0x02U) 72 #define USB_HOST_OHCI_INTERRUPT_ENABLE_SF_MASK (0x04U) 73 #define USB_HOST_OHCI_INTERRUPT_ENABLE_RD_MASK (0x08U) 74 #define USB_HOST_OHCI_INTERRUPT_ENABLE_UE_MASK (0x10U) 75 #define USB_HOST_OHCI_INTERRUPT_ENABLE_FNO_MASK (0x20U) 76 #define USB_HOST_OHCI_INTERRUPT_ENABLE_RHSC_MASK (0x40U) 77 #define USB_HOST_OHCI_INTERRUPT_ENABLE_OC_MASK (0x40000000U) 78 #define USB_HOST_OHCI_INTERRUPT_ENABLE_MIE_MASK (0x80000000U) 79 #define USB_HOST_OHCI_INTERRUPT_ENABLE_MASK (0x8000007FU) 80 81 /*! HcInterruptDisable Register */ 82 #define USB_HOST_OHCI_INTERRUPT_DISABLE_SO_MASK (0x01U) 83 #define USB_HOST_OHCI_INTERRUPT_DISABLE_WDH_MASK (0x02U) 84 #define USB_HOST_OHCI_INTERRUPT_DISABLE_SF_MASK (0x04U) 85 #define USB_HOST_OHCI_INTERRUPT_DISABLE_RD_MASK (0x08U) 86 #define USB_HOST_OHCI_INTERRUPT_DISABLE_UE_MASK (0x10U) 87 #define USB_HOST_OHCI_INTERRUPT_DISABLE_FNO_MASK (0x20U) 88 #define USB_HOST_OHCI_INTERRUPT_DISABLE_RHSC_MASK (0x40U) 89 #define USB_HOST_OHCI_INTERRUPT_DISABLE_OC_MASK (0x40000000U) 90 #define USB_HOST_OHCI_INTERRUPT_DISABLE_MIE_MASK (0x80000000U) 91 #define USB_HOST_OHCI_INTERRUPT_DISABLE_MASK (0xC000007FU) 92 93 /*! HcHCCA Register */ 94 #define USB_HOST_OHCI_HCCA_MASK (0xFFFFFF00U) 95 #define USB_HOST_OHCI_HCCA_SIZE (32U) 96 97 /*! HcPeriodCurrentED Register */ 98 #define USB_HOST_OHCI_PCED_MASK (0xFFFFFFF0U) 99 100 /*! HcControlHeadED Register */ 101 #define USB_HOST_OHCI_CHED_MASK (0xFFFFFFF0U) 102 103 /*! HcControlCurrentED Register */ 104 #define USB_HOST_OHCI_CCED_MASK (0xFFFFFFF0U) 105 106 /*! HcBulkHeadED Register */ 107 #define USB_HOST_OHCI_BHED_MASK (0xFFFFFFF0U) 108 109 /*! HcBulkCurrentED Register */ 110 #define USB_HOST_OHCI_BCED_MASK (0xFFFFFFF0U) 111 112 /*! HcDoneHead Register */ 113 #define USB_HOST_OHCI_HD_MASK (0xFFFFFFF0U) 114 115 /*! HcFmInterval Register */ 116 #define USB_HOST_OHCI_SOF_INTERVAL (11999UL) 117 #define USB_HOST_OHCI_FMINTERVAL_FI_MASK (0x3FFFU) 118 #define USB_HOST_OHCI_FMINTERVAL_FI(n) ((n)&USB_HOST_OHCI_FMINTERVAL_FI_MASK) 119 #define USB_HOST_OHCI_FMINTERVAL_FSMPS_MASK (0x7FFF0000U) 120 #define USB_HOST_OHCI_FMINTERVAL_FSMPS_SHIFT (16U) 121 #define USB_HOST_OHCI_FMINTERVAL_FSMPS(n) \ 122 (((n) << USB_HOST_OHCI_FMINTERVAL_FSMPS_SHIFT) & USB_HOST_OHCI_FMINTERVAL_FSMPS_MASK) 123 #define USB_HOST_OHCI_FMINTERVAL_FIT_MASK (0x80000000U) 124 125 /*! HcFmRemaining Register */ 126 #define USB_HOST_OHCI_FMREMAINING_FR_MASK (0x3FFFU) 127 #define USB_HOST_OHCI_FMREMAINING_FR(n) ((n)&USB_HOST_OHCI_FMINTERVAL_FR_MASK) 128 #define USB_HOST_OHCI_FMREMAINING_FRT_MASK (0x80000000U) 129 130 /*! HcFmNumber Register */ 131 #define USB_HOST_OHCI_FMNUMBER_FN_MASK (0xFFFFU) 132 133 /*! HcPeriodicStart Register */ 134 #define USB_HOST_OHCI_PERIODIC_START_PS_MASK (0x3FFFU) 135 #define USB_HOST_OHCI_PERIODIC_START_PS(n) ((n)&USB_HOST_OHCI_PERIODIC_START_PS_MASK) 136 137 /*! HcLSThreshold Register */ 138 #define USB_HOST_OHCI_LSTHRESHOLD_LST_MASK (0xFFFU) 139 #define USB_HOST_OHCI_LSTHRESHOLD_LST(n) ((n)&USB_HOST_OHCI_LSTHRESHOLD_LST_MASK) 140 141 /*! HcRhDescriptorA Register */ 142 #define USB_HOST_OHCI_RHDESCRIPTORA_NDP_MASK (0xFFU) 143 #define USB_HOST_OHCI_RHDESCRIPTORA_PSM_MASK (0x100U) 144 #define USB_HOST_OHCI_RHDESCRIPTORA_NPS_MASK (0x200U) 145 #define USB_HOST_OHCI_RHDESCRIPTORA_DT_MASK (0x400U) 146 #define USB_HOST_OHCI_RHDESCRIPTORA_OCPM_MASK (0x800U) 147 #define USB_HOST_OHCI_RHDESCRIPTORA_NOCP_MASK (0x1000U) 148 #define USB_HOST_OHCI_RHDESCRIPTORA_POTPGT_MASK (0xFF000000U) 149 #define USB_HOST_OHCI_RHDESCRIPTORA_POTPGT_SHIFT (24U) 150 #define USB_HOST_OHCI_RHDESCRIPTORA_POTPGT(n) \ 151 (((n) << USB_HOST_OHCI_RHDESCRIPTORA_POTPGT_SHIFT) & USB_HOST_OHCI_RHDESCRIPTORA_POTPGT_MASK) 152 153 /*! HcRhDescriptorB Register */ 154 #define USB_HOST_OHCI_RHDESCRIPTORB_DR_MASK (0xFFFFU) 155 #define USB_HOST_OHCI_RHDESCRIPTORB_DR(n) ((n)&USB_HOST_OHCI_RHDESCRIPTORB_DR_MASK) 156 #define USB_HOST_OHCI_RHDESCRIPTORB_PPCM_MASK (0xFFFF0000U) 157 #define USB_HOST_OHCI_RHDESCRIPTORB_PPCM_SHIFT (16U) 158 #define USB_HOST_OHCI_RHDESCRIPTORB_PPCM(n) \ 159 (((n) << USB_HOST_OHCI_RHDESCRIPTORB_PPCM_SHIFT) & USB_HOST_OHCI_RHDESCRIPTORB_PPCM_MASK) 160 161 /*! HcRhStatus Register */ 162 #define USB_HOST_OHCI_RHSTATUS_LPS_MASK (0x01U) 163 #define USB_HOST_OHCI_RHSTATUS_OCI_MASK (0x02U) 164 #define USB_HOST_OHCI_RHSTATUS_DRWE_MASK (0x8000U) 165 #define USB_HOST_OHCI_RHSTATUS_LPSC_MASK (0x10000U) 166 #define USB_HOST_OHCI_RHSTATUS_OCIC_MASK (0x20000U) 167 #define USB_HOST_OHCI_RHSTATUS_CRWE_MASK (0x80000000U) 168 169 /*! HcRhPortStatus[1:NDP] Register */ 170 #define USB_HOST_OHCI_RHPORTSTATUS_CCS_MASK (0x01U) 171 #define USB_HOST_OHCI_RHPORTSTATUS_PES_MASK (0x02U) 172 #define USB_HOST_OHCI_RHPORTSTATUS_PSS_MASK (0x04U) 173 #define USB_HOST_OHCI_RHPORTSTATUS_POCI_MASK (0x08U) 174 #define USB_HOST_OHCI_RHPORTSTATUS_PRS_MASK (0x10U) 175 #define USB_HOST_OHCI_RHPORTSTATUS_PPS_MASK (0x100U) 176 #define USB_HOST_OHCI_RHPORTSTATUS_LSDA_MASK (0x200U) 177 #define USB_HOST_OHCI_RHPORTSTATUS_CSC_MASK (0x10000U) 178 #define USB_HOST_OHCI_RHPORTSTATUS_PESC_MASK (0x20000U) 179 #define USB_HOST_OHCI_RHPORTSTATUS_PSSC_MASK (0x40000U) 180 #define USB_HOST_OHCI_RHPORTSTATUS_OCIC_MASK (0x80000U) 181 #define USB_HOST_OHCI_RHPORTSTATUS_PRSC_MASK (0x100000U) 182 #define USB_HOST_OHCI_RHPORTSTATUS_WIC (0x1F0000U) 183 184 /*! PortMode Register */ 185 #define USB_HOST_OHCI_PORTMODE_ID_MASK (0x01U) 186 #define USB_HOST_OHCI_PORTMODE_ID_EN_MASK (0x100U) 187 #define USB_HOST_OHCI_PORTMODE_DEV_ENABLE_MASK (0x10000U) 188 189 /*! Completion Codes */ 190 #define USB_HOST_OHCI_CC_NO_ERROR (0U) 191 #define USB_HOST_OHCI_CC_CRC (1U) 192 #define USB_HOST_OHCI_CC_BIT_STUFFING (2U) 193 #define USB_HOST_OHCI_CC_DATA_TOGGLE_MISMATCH (3U) 194 #define USB_HOST_OHCI_CC_STALL (4U) 195 #define USB_HOST_OHCI_CC_DEVICE_NOT_RESPONDING (5U) 196 #define USB_HOST_OHCI_CC_PID_CHECK_FAILURE (6U) 197 #define USB_HOST_OHCI_CC_UNEXPECTED_PID (7U) 198 #define USB_HOST_OHCI_CC_DATA_OVERRUN (8U) 199 #define USB_HOST_OHCI_CC_DATA_UNDERRUN (9U) 200 #define USB_HOST_OHCI_CC_BUFFER_OVERRUN (12U) 201 #define USB_HOST_OHCI_CC_BUFFER_UNDERRUN (13U) 202 #define USB_HOST_OHCI_CC_NOT_ACCESSED (14U) 203 204 #define USB_HOST_OHCI_ED_HEADP_HALT_MASK (0x00000001U) /*!< Stopped bit */ 205 #define USB_HOST_OHCI_ED_HEADP_CARRY_MASK (0x00000002U) /*!< Toggle carry bit */ 206 #define USB_HOST_OHCI_ED_HEADP_MASK (0xFFFFFFF0U) 207 #define USB_HOST_OHCI_ED_TAILP_MASK (0xFFFFFFF0U) 208 209 #define USB_HOST_OHCI_GTD_DP_SETUP (0U) 210 #define USB_HOST_OHCI_GTD_DP_OUT (1U) 211 #define USB_HOST_OHCI_GTD_DP_IN (2U) 212 #define USB_HOST_OHCI_GTD_DI_NO_INTERRUPT (7U) 213 214 #define USB_HOST_OHCI_ITD_BP0_MASK (0xFFFFF000U) 215 #define USB_HOST_OHCI_ITD_TRANSFER_SIZE_MASK (0x00000FFFU) 216 #define USB_HOST_OHCI_ITD_CONDITION_CODE_MASK (0x0000F000U) 217 #define USB_HOST_OHCI_ITD_CONDITION_CODE_SHIFT (12U) 218 /*! 219 * @addtogroup usb_host_controller_ohci 220 * @{ 221 */ 222 /*! @brief OHCI Endpoint Descriptor */ 223 typedef struct _usb_host_ohci_endpoint_descritpor_struct 224 { 225 union 226 { 227 uint32_t state; 228 struct 229 { 230 uint32_t FA : 7U; /*!< FunctionAddress */ 231 uint32_t EN : 4U; /*!< EndpointNumber */ 232 uint32_t D : 2U; /*!< Direction: 00,11 - Get dir from TD, 01 - OUT, 10 - IN. */ 233 uint32_t S : 1U; /*!< Speed: 0 - full speed, 1 - low speed. */ 234 uint32_t K : 1U; /*!< Skip */ 235 uint32_t F : 1U; /*!< Format: 0 - Control, Bulk, or Interrupt Endpoint, 1 - ISO Endpoint. */ 236 volatile uint32_t MPS : 11U; /*!< MaximumPacketSize */ 237 uint32_t reserved1 : 5U; /*!< Reserved */ 238 } stateBitField; 239 } stateUnion; 240 volatile uint32_t TailP; /*!< TDQueueTailPointer */ 241 volatile uint32_t HeadP; /*!< TDQueueHeadPointer */ 242 volatile uint32_t NextED; /*!< NextED */ 243 struct _usb_host_ohci_pipe_struct *pipe; /*!< Pipe handle for the ED */ 244 usb_host_transfer_t *trListHead; 245 usb_host_transfer_t *trListTail; 246 usb_host_transfer_t *dealTr; 247 } usb_host_ohci_endpoint_descritpor_struct_t; 248 249 /*! @brief OHCI General Transfer Descriptor */ 250 typedef struct _usb_host_ohci_general_transfer_descritpor_struct 251 { 252 union 253 { 254 uint32_t state; 255 struct 256 { 257 uint32_t reserved1 : 18U; /*!< Reserved */ 258 volatile uint32_t R : 1U; /*!< bufferRounding */ 259 volatile uint32_t DP : 2U; /*!< Direction/PID */ 260 volatile uint32_t DI : 3U; /*!< DelayInterrupt */ 261 volatile uint32_t T : 2U; /*!< DataToggle */ 262 volatile uint32_t EC : 2U; /*!< ErrorCount */ 263 volatile uint32_t CC : 4U; /*!< ConditionCode */ 264 } stateBitField; 265 } stateUnion; 266 uint32_t CBP; /*!< CurrentBufferPointer */ 267 volatile uint32_t NextTD; /*!< NextTD */ 268 uint32_t BE; /*!< BufferEnd */ 269 struct _usb_host_ohci_pipe_struct *pipe; /*!< Pipe handle for the GTD */ 270 usb_host_transfer_t *tr; 271 struct _usb_host_ohci_general_transfer_descritpor_struct *nextGtd; 272 uint32_t length; 273 } usb_host_ohci_general_transfer_descritpor_struct_t; 274 275 /*! @brief OHCI Isochronous Transfer Descriptor */ 276 typedef struct _usb_host_ohci_isochronous_transfer_descritpor_struct 277 { 278 union 279 { 280 uint32_t state; 281 struct 282 { 283 volatile uint32_t SF : 16U; /*!< StartingFrame */ 284 uint32_t reserved1 : 5U; /*!< Reserved */ 285 volatile uint32_t DI : 3U; /*!< DelayInterrupt */ 286 volatile uint32_t FC : 3U; /*!< FrameCount */ 287 uint32_t reserved2 : 1U; /*!< Reserved */ 288 volatile uint32_t CC : 4U; /*!< ConditionCode */ 289 } stateBitField; 290 } stateUnion; 291 uint32_t BP0; /*!< BufferPage0 */ 292 volatile uint32_t NextTD; /*!< NextTD */ 293 uint32_t BE; /*!< BufferEnd */ 294 volatile uint16_t OffsetPSW[8]; /*!< Offest or PacketStatusWord */ 295 struct _usb_host_ohci_pipe_struct *pipe; /*!< Pipe handle for the ITD */ 296 usb_host_transfer_t *tr; 297 struct _usb_host_ohci_isochronous_transfer_descritpor_struct *nextItd; 298 uint32_t length; 299 uint32_t reserved[4]; 300 } usb_host_ohci_isochronous_transfer_descritpor_struct_t; 301 302 /*! @brief OHCI Host Controller Communications Area */ 303 typedef struct _usb_host_ohci_hcca_struct 304 { 305 volatile uint32_t 306 HccaInterrruptTable[USB_HOST_OHCI_HCCA_SIZE]; /*!< These 32 Dwords are pointers to interrupt EDs */ 307 volatile uint16_t HccaFrameNumber; /*!< Contains the current frame number */ 308 uint16_t HccaPad1; /*!< When the HC updates HccaFrameNumber, it sets this word to 0 */ 309 volatile uint32_t HccaDoneHead; /*!< Hcca done head */ 310 uint32_t reserved[30]; /*!< Reserved for use by HC */ 311 } usb_host_ohci_hcca_struct_t; 312 313 #if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) 314 typedef enum _bus_ohci_suspend_request_state 315 { 316 kBus_OhciIdle = 0U, 317 kBus_OhciStartSuspend, 318 kBus_OhciSuspended, 319 kBus_OhciStartResume, 320 } bus_ohci_suspend_request_state_t; 321 #endif 322 323 #define USB_HOST_OHCI_CONTROL_ED_DUMMY (0U) 324 #define USB_HOST_OHCI_BULK_ED_DUMMY (1U) 325 #define USB_HOST_OHCI_PERIODIC_ED_DUMMY (2U) 326 327 #define USB_HOST_OHCI_TIME_DELAY (3500U) 328 #define USB_HOST_OHCI_HUB_LS_SETUP_TIME_DELAY (333U) 329 330 #define USB_HOST_OHCI_PERIODIC_BANDWIDTH_PERCENT ((float)80U / (float)100U) 331 #define USB_HOST_OHCI_PERIODIC_BANDWIDTH (((float)1000U) * USB_HOST_OHCI_PERIODIC_BANDWIDTH_PERCENT) 332 333 #define USB_HOST_OHCI_GTD_MAX_LENGTH (0x2000U) 334 #define USB_HOST_OHCI_GTD_BUFFER_ALIGN_MASK (0x0FFFU) 335 336 typedef struct _usb_host_ohci_td_struct 337 { 338 #if (defined(USB_HOST_CONFIG_OHCI_MAX_ITD) && (USB_HOST_CONFIG_OHCI_MAX_ITD > 0U)) 339 usb_host_ohci_isochronous_transfer_descritpor_struct_t itd[USB_HOST_CONFIG_OHCI_MAX_ITD]; 340 #endif 341 #if (defined(USB_HOST_CONFIG_OHCI_MAX_GTD) && (USB_HOST_CONFIG_OHCI_MAX_GTD > 0U)) 342 usb_host_ohci_general_transfer_descritpor_struct_t gtd[USB_HOST_CONFIG_OHCI_MAX_GTD]; 343 #endif 344 usb_host_ohci_endpoint_descritpor_struct_t ed[USB_HOST_CONFIG_OHCI_MAX_ED + 3U]; 345 } usb_host_ohci_td_struct_t; 346 347 /*! @brief task event */ 348 #define USB_HOST_OHCI_EVENT_ATTACH (0x01U) 349 #define USB_HOST_OHCI_EVENT_DETACH (0x02U) 350 #define USB_HOST_OHCI_EVENT_PORT_CHANGE (0x04U) 351 #define USB_HOST_OHCI_EVENT_TOKEN_DONE (0x08U) 352 #define USB_HOST_OHCI_EVENT_SOF (0x10U) 353 354 /*! @brief Check the port connect state delay if the state is unstable */ 355 #define USB_HOST_OHCI_PORT_CONNECT_DEBOUNCE_DELAY (101U) 356 357 #define USB_HOST_OHCI_PIPE_QUEUE_TYPE_IDLE (0U) 358 #define USB_HOST_OHCI_PIPE_QUEUE_TYPE_INUSING (1U) 359 360 #define USB_HOST_OHCI_ISO_TRANSFER_GAP (3U) 361 362 /*! @brief Transfer scan interval (ms)*/ 363 #define USB_HOST_OHCI_TRANSFER_SCAN_INTERVAL (10U) 364 /*! @brief Time out gap for each transfer (USB_HOST_OHCI_TRANSFER_SCAN_INTERVAL * 1ms) */ 365 #define USB_HOST_OHCI_TRANSFER_TIMEOUT_GAP (5000U / USB_HOST_OHCI_TRANSFER_SCAN_INTERVAL) 366 367 /*! @brief USB host OHCI lock */ 368 #define USB_HostOhciLock() (void)OSA_MutexLock(usbHostState->mutex, USB_OSA_WAIT_TIMEOUT) 369 /*! @brief USB host OHCI unlock */ 370 #define USB_HostOhciUnlock() (void)OSA_MutexUnlock(usbHostState->mutex) 371 372 /*! @brief OHCI Host Controller Operational Registers */ 373 typedef struct _usb_host_ohci_hcor_struct 374 { 375 __I uint32_t HcRevision; /* Offset 0x00 */ 376 __IO uint32_t HcControl; /* Offset 0x04 */ 377 __IO uint32_t HcCommandStatus; /* Offset 0x08 */ 378 __IO uint32_t HcInterruptStatus; /* Offset 0x0C */ 379 __IO uint32_t HcInterruptEnable; /* Offset 0x10 */ 380 __IO uint32_t HcInterruptDisable; /* Offset 0x14 */ 381 __IO uint32_t HcHCCA; /* Offset 0x18 */ 382 __I uint32_t HcPeriodCurrentED; /* Offset 0x1C */ 383 __IO uint32_t HcControlHeadED; /* Offset 0x20 */ 384 __IO uint32_t HcControlCurrentED; /* Offset 0x24 */ 385 __IO uint32_t HcBulkHeadED; /* Offset 0x28 */ 386 __IO uint32_t HcBulkCurrentED; /* Offset 0x2C */ 387 __I uint32_t HcDoneHead; /* Offset 0x30 */ 388 __IO uint32_t HcFmInterval; /* Offset 0x34 */ 389 __I uint32_t HcFmRemaining; /* Offset 0x38 */ 390 __I uint32_t HcFmNumber; /* Offset 0x3C */ 391 __IO uint32_t HcPeriodicStart; /* Offset 0x40 */ 392 __IO uint32_t HcLSThreshold; /* Offset 0x44 */ 393 __IO uint32_t HcRhDescriptorA; /* Offset 0x48 */ 394 __IO uint32_t HcRhDescriptorB; /* Offset 0x4C */ 395 __IO uint32_t HcRhStatus; /* Offset 0x50 */ 396 __IO uint32_t HcRhPortStatus[2]; /* Offset 0x54 - 0x58 */ 397 __IO uint32_t PortMode; /* Offset 0x5C */ 398 } usb_host_ohci_hcor_struct_t; 399 400 /*! @brief Port state for device attachment/detachment. */ 401 typedef enum _usb_host_ohci_port_state 402 { 403 kUSB_DeviceOhciPortDetached = 0U, /*!< Port is detached and de-initialized */ 404 kUSB_DeviceOhciPortPhyDetached, /*!< Port is physically detached */ 405 kUSB_DeviceOhciPortPhyAttached, /*!< Port is physically attached */ 406 kUSB_DeviceOhciPortAttached, /*!< Port is attached and initialized */ 407 } usb_host_ohci_port_state_t; 408 409 typedef struct _usb_host_ohci_port_state_struct 410 { 411 uint8_t portSpeed; /*!< Port speed */ 412 uint8_t portStatus; /*!< Port status */ 413 } usb_host_ohci_port_state_struct_t; 414 415 typedef struct _usb_host_ohci_pipe_struct 416 { 417 usb_host_pipe_t pipeCommon; /*!< Common pipe information */ 418 usb_host_ohci_endpoint_descritpor_struct_t *ed; 419 usb_host_transfer_t *currentTr; 420 uint32_t cutOffTime; 421 volatile uint32_t startWriteBackCount; 422 uint16_t busTime; 423 uint16_t startFrame; 424 #if (defined(USB_HOST_OHCI_DEVICE_NOT_RESPONDING_WORKAROUND) && (USB_HOST_OHCI_DEVICE_NOT_RESPONDING_WORKAROUND)) 425 uint16_t deviceNotRespondingCount; 426 uint16_t endpointInterval; 427 #endif 428 volatile uint8_t isBusy; 429 volatile uint8_t isDone; 430 volatile uint8_t isCanceling; 431 } usb_host_ohci_pipe_struct_t; 432 433 typedef enum _usb_host_ohci_transfer_status 434 { 435 kStatus_UsbHostOhci_Idle = 0, 436 kStatus_UsbHostOhci_Setup, 437 kStatus_UsbHostOhci_Data, 438 kStatus_UsbHostOhci_State, 439 } usb_host_ohci_transfer_status_t; 440 441 /*! @brief OHCI controller driver instance structure */ 442 typedef struct _usb_host_ohci_state_struct 443 { 444 volatile usb_host_ohci_hcor_struct_t *usbRegBase; /*!< The base address of the register */ 445 void *hostHandle; /*!< Related host handle*/ 446 usb_host_ohci_port_state_struct_t *portState; 447 usb_host_ohci_pipe_struct_t *pipeList; 448 usb_host_ohci_pipe_struct_t *pipeListInUsing; 449 volatile uint32_t writeBackCount; 450 volatile usb_host_ohci_general_transfer_descritpor_struct_t *tdDoneListHead; 451 volatile usb_host_ohci_general_transfer_descritpor_struct_t *tdDoneListTail; 452 #if (defined(USB_HOST_CONFIG_OHCI_MAX_GTD) && (USB_HOST_CONFIG_OHCI_MAX_GTD > 0U)) 453 usb_host_ohci_general_transfer_descritpor_struct_t *gtdList; 454 #endif 455 #if (defined(USB_HOST_CONFIG_OHCI_MAX_ITD) && (USB_HOST_CONFIG_OHCI_MAX_ITD > 0U)) 456 usb_host_ohci_isochronous_transfer_descritpor_struct_t *itdList; 457 #endif 458 459 #if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) 460 uint64_t matchTick; 461 #endif 462 osa_event_handle_t ohciEvent; /*!< OHCI event*/ 463 uint32_t taskEventHandleBuffer[(OSA_EVENT_HANDLE_SIZE + 3) / 4]; /*!< task event handle buffer*/ 464 osa_mutex_handle_t mutex; /*!< OHCI layer mutex*/ 465 uint32_t mutexBuffer[(OSA_MUTEX_HANDLE_SIZE + 3) / 4]; 466 usb_host_ohci_pipe_struct_t pipePool[USB_HOST_CONFIG_OHCI_MAX_ED]; 467 uint8_t controllerId; /*!< Controller id */ 468 uint8_t portNumber; /*!< Port count */ 469 uint8_t isrNumber; /*!< ISR Number */ 470 volatile uint8_t gtdCount; /*!< Gtd count */ 471 volatile uint8_t itdCount; /*!< Itd count */ 472 volatile uint8_t controlIsBusy; /*!< Is handling control transfer */ 473 volatile uint8_t isrLevel; /*!< The disable deep of the ISR */ 474 475 #if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) 476 volatile bus_ohci_suspend_request_state_t busSuspendStatus; /*!< Bus Suspend Status*/ 477 #endif 478 } usb_host_ohci_state_struct_t; 479 480 /******************************************************************************* 481 * API 482 ******************************************************************************/ 483 484 #ifdef __cplusplus 485 extern "C" { 486 #endif 487 /*! 488 * @name USB host OHCI APIs 489 * @{ 490 */ 491 492 /*! 493 * @brief Creates the USB host OHCI instance. 494 * 495 * This function initializes the USB host OHCI controller driver. 496 * 497 * @param controllerId The controller ID of the USB IP. See the enumeration usb_controller_index_t. 498 * @param hostHandle The host level handle. 499 * @param controllerHandle Returns the controller instance handle. 500 * 501 * @retval kStatus_USB_Success The host is initialized successfully. 502 * @retval kStatus_USB_AllocFail Allocates memory failed. 503 * @retval kStatus_USB_Error Host mutex create failed, OHCI mutex or OHCI event create failed. 504 * Or, OHCI IP initialize failed. 505 */ 506 extern usb_status_t USB_HostOhciCreate(uint8_t controllerId, 507 usb_host_handle hostHandle, 508 usb_host_controller_handle *controllerHandle); 509 510 /*! 511 * @brief Destroys the USB host OHCI instance. 512 * 513 * This function deinitializes the USB host OHCI controller driver. 514 * 515 * @param controllerHandle The controller handle. 516 * 517 * @retval kStatus_USB_Success The host is initialized successfully. 518 */ 519 extern usb_status_t USB_HostOhciDestory(usb_host_controller_handle controllerHandle); 520 521 /*! 522 * @brief Opens the USB host pipe. 523 * 524 * This function opens a pipe according to the pipe_init_ptr parameter. 525 * 526 * @param controllerHandle The controller handle. 527 * @param pipeHandle The pipe handle pointer used to return the pipe handle. 528 * @param pipeInit It is used to initialize the pipe. 529 * 530 * @retval kStatus_USB_Success The host is initialized successfully. 531 * @retval kStatus_USB_Error There is no idle pipe. 532 * 533 */ 534 extern usb_status_t USB_HostOhciOpenPipe(usb_host_controller_handle controllerHandle, 535 usb_host_pipe_handle *pipeHandle, 536 usb_host_pipe_init_t *pipeInit); 537 538 /*! 539 * @brief Closes the USB host pipe. 540 * 541 * This function closes a pipe and frees the related resources. 542 * 543 * @param controllerHandle The controller handle. 544 * @param pipeHandle The closing pipe handle. 545 * 546 * @retval kStatus_USB_Success The host is initialized successfully. 547 */ 548 extern usb_status_t USB_HostOhciClosePipe(usb_host_controller_handle controllerHandle, usb_host_pipe_handle pipeHandle); 549 550 /*! 551 * @brief Sends data to the pipe. 552 * 553 * This function requests to send the transfer to the specified pipe. 554 * 555 * @param controllerHandle The controller handle. 556 * @param pipeHandle The sending pipe handle. 557 * @param transfer The transfer information. 558 * 559 * @retval kStatus_USB_Success Send successful. 560 * @retval kStatus_USB_LackSwapBuffer There is no swap buffer for OHCI. 561 */ 562 extern usb_status_t USB_HostOhciWritePipe(usb_host_controller_handle controllerHandle, 563 usb_host_pipe_handle pipeHandle, 564 usb_host_transfer_t *transfer); 565 566 /*! 567 * @brief Receives data from the pipe. 568 * 569 * This function requests to receive the transfer from the specified pipe. 570 * 571 * @param controllerHandle The controller handle. 572 * @param pipeHandle The receiving pipe handle. 573 * @param transfer The transfer information. 574 * 575 * @retval kStatus_USB_Success Receive successful. 576 * @retval kStatus_USB_LackSwapBuffer There is no swap buffer for OHCI. 577 */ 578 extern usb_status_t USB_HostOhciReadPipe(usb_host_controller_handle controllerHandle, 579 usb_host_pipe_handle pipeHandle, 580 usb_host_transfer_t *transfer); 581 582 /*! 583 * @brief Controls the OHCI. 584 * 585 * This function controls the OHCI. 586 * 587 * @param controllerHandle The controller handle. 588 * @param ioctlEvent See the enumeration host_bus_control_t. 589 * @param ioctlParam The control parameter. 590 * 591 * @retval kStatus_USB_Success Cancel successful. 592 * @retval kStatus_USB_InvalidHandle The controllerHandle is a NULL pointer. 593 */ 594 extern usb_status_t USB_HostOhciIoctl(usb_host_controller_handle controllerHandle, 595 uint32_t ioctlEvent, 596 void *ioctlParam); 597 598 /*! @}*/ 599 #ifdef __cplusplus 600 } 601 #endif 602 /*! @}*/ 603 #endif /* __USB_HOST_OHCI_H__ */ 604
