1 /*
2  * Copyright (c) 2015, Freescale Semiconductor, Inc.
3  * Copyright 2016-2019 NXP
4  * All rights reserved.
5  *
6  * SPDX-License-Identifier: BSD-3-Clause
7  */
8 
9 #include "fsl_flexbus.h"
10 
11 /* Component ID definition, used by tools. */
12 #ifndef FSL_COMPONENT_ID
13 #define FSL_COMPONENT_ID "platform.drivers.flexbus"
14 #endif
15 
16 /*******************************************************************************
17  * Prototypes
18  ******************************************************************************/
19 
20 /*!
21  * @brief Gets the instance from the base address
22  *
23  * @param base FLEXBUS peripheral base address
24  *
25  * @return The FLEXBUS instance
26  */
27 static uint32_t FLEXBUS_GetInstance(FB_Type *base);
28 
29 /*******************************************************************************
30  * Variables
31  ******************************************************************************/
32 
33 /*! @brief Pointers to FLEXBUS bases for each instance. */
34 static FB_Type *const s_flexbusBases[] = FB_BASE_PTRS;
35 
36 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
37 /*! @brief Pointers to FLEXBUS clocks for each instance. */
38 static const clock_ip_name_t s_flexbusClocks[] = FLEXBUS_CLOCKS;
39 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
40 
41 /*******************************************************************************
42  * Code
43  ******************************************************************************/
44 
FLEXBUS_GetInstance(FB_Type * base)45 static uint32_t FLEXBUS_GetInstance(FB_Type *base)
46 {
47     uint32_t instance;
48 
49     /* Find the instance index from base address mappings. */
50     for (instance = 0; instance < ARRAY_SIZE(s_flexbusBases); instance++)
51     {
52         if (s_flexbusBases[instance] == base)
53         {
54             break;
55         }
56     }
57 
58     assert(instance < ARRAY_SIZE(s_flexbusBases));
59 
60     return instance;
61 }
62 
63 /*!
64  * brief Initializes and configures the FlexBus module.
65  *
66  * This function enables the clock gate for FlexBus module.
67  * Only chip 0 is validated and set to known values. Other chips are disabled.
68  * Note that in this function, certain parameters, depending on external memories,  must
69  * be set before using the FLEXBUS_Init() function.
70  * This example shows how to set up the uart_state_t and the
71  * flexbus_config_t parameters and how to call the FLEXBUS_Init function by passing
72  * in these parameters.
73    code
74     flexbus_config_t flexbusConfig;
75     FLEXBUS_GetDefaultConfig(&flexbusConfig);
76     flexbusConfig.waitStates            = 2U;
77     flexbusConfig.chipBaseAddress       = 0x60000000U;
78     flexbusConfig.chipBaseAddressMask   = 7U;
79     FLEXBUS_Init(FB, &flexbusConfig);
80    endcode
81  *
82  * param base FlexBus peripheral address.
83  * param config Pointer to the configuration structure
84 */
FLEXBUS_Init(FB_Type * base,const flexbus_config_t * config)85 void FLEXBUS_Init(FB_Type *base, const flexbus_config_t *config)
86 {
87     assert(config != NULL);
88     assert(config->chip < FB_CSAR_COUNT);
89     assert(config->waitStates <= 0x3FU);
90     assert(config->secondaryWaitStates <= 0x3FU);
91 
92     uint32_t chip      = config->chip;
93     uint32_t reg_value = 0;
94 
95 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
96     /* Ungate clock for FLEXBUS */
97     CLOCK_EnableClock(s_flexbusClocks[FLEXBUS_GetInstance(base)]);
98 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
99 
100     /* Reset the associated register to default state */
101     /* Set CSMR register, all chips not valid (disabled) */
102     base->CS[chip].CSMR = 0x0000U;
103     /* Set default base address */
104     base->CS[chip].CSAR &= (~FB_CSAR_BA_MASK);
105     /* Reset FB_CSCRx register */
106     base->CS[chip].CSCR = 0x0000U;
107 
108     /* Set FB_CSPMCR register */
109     /* FlexBus signal group 1 multiplex control */
110     reg_value |= (uint32_t)kFLEXBUS_MultiplexGroup1_FB_ALE << FB_CSPMCR_GROUP1_SHIFT;
111     /* FlexBus signal group 2 multiplex control */
112     reg_value |= (uint32_t)kFLEXBUS_MultiplexGroup2_FB_CS4 << FB_CSPMCR_GROUP2_SHIFT;
113     /* FlexBus signal group 3 multiplex control */
114     reg_value |= (uint32_t)kFLEXBUS_MultiplexGroup3_FB_CS5 << FB_CSPMCR_GROUP3_SHIFT;
115     /* FlexBus signal group 4 multiplex control */
116     reg_value |= (uint32_t)kFLEXBUS_MultiplexGroup4_FB_TBST << FB_CSPMCR_GROUP4_SHIFT;
117     /* FlexBus signal group 5 multiplex control */
118     reg_value |= (uint32_t)kFLEXBUS_MultiplexGroup5_FB_TA << FB_CSPMCR_GROUP5_SHIFT;
119     /* Write to CSPMCR register */
120     base->CSPMCR = reg_value;
121 
122     /* Base address */
123     reg_value = config->chipBaseAddress;
124     /* Write to CSAR register */
125     base->CS[chip].CSAR = reg_value;
126 
127     /* Chip-select validation */
128     reg_value = 0x1U << FB_CSMR_V_SHIFT;
129     /* Write protect */
130     reg_value |= ((uint32_t)config->writeProtect) << FB_CSMR_WP_SHIFT;
131     /* Base address mask */
132     reg_value |= config->chipBaseAddressMask << FB_CSMR_BAM_SHIFT;
133     /* Write to CSMR register */
134     base->CS[chip].CSMR = reg_value;
135 
136     /* Burst write */
137     reg_value = ((uint32_t)config->burstWrite) << FB_CSCR_BSTW_SHIFT;
138     /* Burst read */
139     reg_value |= ((uint32_t)config->burstRead) << FB_CSCR_BSTR_SHIFT;
140     /* Byte-enable mode */
141     reg_value |= ((uint32_t)config->byteEnableMode) << FB_CSCR_BEM_SHIFT;
142     /* Port size */
143     reg_value |= (uint32_t)config->portSize << FB_CSCR_PS_SHIFT;
144     /* The internal transfer acknowledge for accesses */
145     reg_value |= ((uint32_t)config->autoAcknowledge) << FB_CSCR_AA_SHIFT;
146     /* Byte-Lane shift */
147     reg_value |= (uint32_t)config->byteLaneShift << FB_CSCR_BLS_SHIFT;
148     /* The number of wait states */
149     reg_value |= (uint32_t)config->waitStates << FB_CSCR_WS_SHIFT;
150     /* Write address hold or deselect */
151     reg_value |= (uint32_t)config->writeAddressHold << FB_CSCR_WRAH_SHIFT;
152     /* Read address hold or deselect */
153     reg_value |= (uint32_t)config->readAddressHold << FB_CSCR_RDAH_SHIFT;
154     /* Address setup */
155     reg_value |= (uint32_t)config->addressSetup << FB_CSCR_ASET_SHIFT;
156     /* Extended transfer start/extended address latch */
157     reg_value |= ((uint32_t)config->extendTransferAddress) << FB_CSCR_EXTS_SHIFT;
158     /* Secondary wait state */
159     if (config->secondaryWaitStatesEnable)
160     {
161         reg_value |= FB_CSCR_SWSEN_MASK;
162         reg_value |= (uint32_t)(config->secondaryWaitStates) << FB_CSCR_SWS_SHIFT;
163     }
164     /* Write to CSCR register */
165     base->CS[chip].CSCR = reg_value;
166 
167     /* FlexBus signal group 1 multiplex control */
168     reg_value = (uint32_t)config->group1MultiplexControl << FB_CSPMCR_GROUP1_SHIFT;
169     /* FlexBus signal group 2 multiplex control */
170     reg_value |= (uint32_t)config->group2MultiplexControl << FB_CSPMCR_GROUP2_SHIFT;
171     /* FlexBus signal group 3 multiplex control */
172     reg_value |= (uint32_t)config->group3MultiplexControl << FB_CSPMCR_GROUP3_SHIFT;
173     /* FlexBus signal group 4 multiplex control */
174     reg_value |= (uint32_t)config->group4MultiplexControl << FB_CSPMCR_GROUP4_SHIFT;
175     /* FlexBus signal group 5 multiplex control */
176     reg_value |= (uint32_t)config->group5MultiplexControl << FB_CSPMCR_GROUP5_SHIFT;
177     /* Write to CSPMCR register */
178     base->CSPMCR = reg_value;
179 
180     /* Enable CSPMCR0[V] to make all chip select registers take effect. */
181     if (chip != 0UL)
182     {
183         base->CS[0].CSMR |= FB_CSMR_V_MASK;
184     }
185 }
186 
187 /*!
188  * brief De-initializes a FlexBus instance.
189  *
190  * This function disables the clock gate of the FlexBus module clock.
191  *
192  * param base FlexBus peripheral address.
193  */
FLEXBUS_Deinit(FB_Type * base)194 void FLEXBUS_Deinit(FB_Type *base)
195 {
196 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
197     /* Gate clock for FLEXBUS */
198     CLOCK_DisableClock(s_flexbusClocks[FLEXBUS_GetInstance(base)]);
199 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
200 }
201 
202 /*!
203  * brief Initializes the FlexBus configuration structure.
204  *
205  * This function initializes the FlexBus configuration structure to default value. The default
206  * values are.
207    code
208    fbConfig->chip                         = 0;
209    fbConfig->writeProtect                 = false;
210    fbConfig->burstWrite                   = false;
211    fbConfig->burstRead                    = false;
212    fbConfig->byteEnableMode               = false;
213    fbConfig->autoAcknowledge              = true;
214    fbConfig->extendTransferAddress        = false;
215    fbConfig->secondaryWaitStatesEnable    = false;
216    fbConfig->byteLaneShift                = kFLEXBUS_NotShifted;
217    fbConfig->writeAddressHold             = kFLEXBUS_Hold1Cycle;
218    fbConfig->readAddressHold              = kFLEXBUS_Hold1Or0Cycles;
219    fbConfig->addressSetup                 = kFLEXBUS_FirstRisingEdge;
220    fbConfig->portSize                     = kFLEXBUS_1Byte;
221    fbConfig->group1MultiplexControl       = kFLEXBUS_MultiplexGroup1_FB_ALE;
222    fbConfig->group2MultiplexControl       = kFLEXBUS_MultiplexGroup2_FB_CS4 ;
223    fbConfig->group3MultiplexControl       = kFLEXBUS_MultiplexGroup3_FB_CS5;
224    fbConfig->group4MultiplexControl       = kFLEXBUS_MultiplexGroup4_FB_TBST;
225    fbConfig->group5MultiplexControl       = kFLEXBUS_MultiplexGroup5_FB_TA;
226    endcode
227  * param config Pointer to the initialization structure.
228  * see FLEXBUS_Init
229  */
FLEXBUS_GetDefaultConfig(flexbus_config_t * config)230 void FLEXBUS_GetDefaultConfig(flexbus_config_t *config)
231 {
232     /* Initializes the configure structure to zero. */
233     (void)memset(config, 0, sizeof(*config));
234 
235     config->chip                      = 0;                   /* Chip 0 FlexBus for validation */
236     config->writeProtect              = false;               /* Write accesses are allowed */
237     config->burstWrite                = false;               /* Burst-Write disable */
238     config->burstRead                 = false;               /* Burst-Read disable */
239     config->byteEnableMode            = false;               /* Byte-Enable mode is asserted for data write only */
240     config->autoAcknowledge           = true;                /* Auto-Acknowledge enable */
241     config->extendTransferAddress     = false;               /* Extend transfer start/extend address latch disable */
242     config->secondaryWaitStatesEnable = false;               /* Secondary wait state disable */
243     config->byteLaneShift             = kFLEXBUS_NotShifted; /* Byte-Lane shift disable */
244     config->writeAddressHold          = kFLEXBUS_Hold1Cycle; /* Write address hold 1 cycles */
245     config->readAddressHold           = kFLEXBUS_Hold1Or0Cycles; /* Read address hold 0 cycles */
246     config->addressSetup =
247         kFLEXBUS_FirstRisingEdge; /* Assert ~FB_CSn on the first rising clock edge after the address is asserted */
248     config->portSize               = kFLEXBUS_1Byte;                   /* 1 byte port size of transfer */
249     config->group1MultiplexControl = kFLEXBUS_MultiplexGroup1_FB_ALE;  /* FB_ALE */
250     config->group2MultiplexControl = kFLEXBUS_MultiplexGroup2_FB_CS4;  /* FB_CS4 */
251     config->group3MultiplexControl = kFLEXBUS_MultiplexGroup3_FB_CS5;  /* FB_CS5 */
252     config->group4MultiplexControl = kFLEXBUS_MultiplexGroup4_FB_TBST; /* FB_TBST */
253     config->group5MultiplexControl = kFLEXBUS_MultiplexGroup5_FB_TA;   /* FB_TA */
254 }
255