1 /*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016-2020 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #ifndef _FSL_DMIC_H_
10 #define _FSL_DMIC_H_
11
12 #include "fsl_common.h"
13
14 /*!
15 * @addtogroup dmic_driver
16 * @{
17 */
18
19 /*! @file*/
20
21 /*******************************************************************************
22 * Definitions
23 ******************************************************************************/
24
25 /*!
26 * @name DMIC version
27 * @{
28 */
29
30 /*! @brief DMIC driver version 2.3.1. */
31 #define FSL_DMIC_DRIVER_VERSION (MAKE_VERSION(2, 3, 1))
32 /*@}*/
33
34 /*! @brief _dmic_status DMIC transfer status.*/
35 enum
36 {
37 kStatus_DMIC_Busy = MAKE_STATUS(kStatusGroup_DMIC, 0), /*!< DMIC is busy */
38 kStatus_DMIC_Idle = MAKE_STATUS(kStatusGroup_DMIC, 1), /*!< DMIC is idle */
39 kStatus_DMIC_OverRunError = MAKE_STATUS(kStatusGroup_DMIC, 2), /*!< DMIC over run Error */
40 kStatus_DMIC_UnderRunError = MAKE_STATUS(kStatusGroup_DMIC, 3), /*!< DMIC under run Error */
41 };
42
43 /*! @brief DMIC different operation modes. */
44 typedef enum _operation_mode
45 {
46 kDMIC_OperationModeInterrupt = 1U, /*!< Interrupt mode */
47 kDMIC_OperationModeDma = 2U, /*!< DMA mode */
48 } operation_mode_t;
49
50 /*! @brief DMIC left/right values. */
51 typedef enum _stereo_side
52 {
53 kDMIC_Left = 0U, /*!< Left Stereo channel */
54 kDMIC_Right = 1U, /*!< Right Stereo channel */
55 } stereo_side_t;
56
57 /*! @brief DMIC Clock pre-divider values. */
58 typedef enum
59 {
60 kDMIC_PdmDiv1 = 0U, /*!< DMIC pre-divider set in divide by 1 */
61 kDMIC_PdmDiv2 = 1U, /*!< DMIC pre-divider set in divide by 2 */
62 kDMIC_PdmDiv3 = 2U, /*!< DMIC pre-divider set in divide by 3 */
63 kDMIC_PdmDiv4 = 3U, /*!< DMIC pre-divider set in divide by 4 */
64 kDMIC_PdmDiv6 = 4U, /*!< DMIC pre-divider set in divide by 6 */
65 kDMIC_PdmDiv8 = 5U, /*!< DMIC pre-divider set in divide by 8 */
66 kDMIC_PdmDiv12 = 6U, /*!< DMIC pre-divider set in divide by 12 */
67 kDMIC_PdmDiv16 = 7U, /*!< DMIC pre-divider set in divide by 16*/
68 kDMIC_PdmDiv24 = 8U, /*!< DMIC pre-divider set in divide by 24*/
69 kDMIC_PdmDiv32 = 9U, /*!< DMIC pre-divider set in divide by 32 */
70 kDMIC_PdmDiv48 = 10U, /*!< DMIC pre-divider set in divide by 48 */
71 kDMIC_PdmDiv64 = 11U, /*!< DMIC pre-divider set in divide by 64*/
72 kDMIC_PdmDiv96 = 12U, /*!< DMIC pre-divider set in divide by 96*/
73 kDMIC_PdmDiv128 = 13U, /*!< DMIC pre-divider set in divide by 128 */
74 } pdm_div_t;
75
76 /*! @brief Pre-emphasis Filter coefficient value for 2FS and 4FS modes. */
77 typedef enum _compensation
78 {
79 kDMIC_CompValueZero = 0U, /*!< Compensation 0 */
80 kDMIC_CompValueNegativePoint16 = 1U, /*!< Compensation -0.16 */
81 kDMIC_CompValueNegativePoint15 = 2U, /*!< Compensation -0.15 */
82 kDMIC_CompValueNegativePoint13 = 3U, /*!< Compensation -0.13 */
83 } compensation_t;
84
85 /*! @brief DMIC DC filter control values. */
86 typedef enum _dc_removal
87 {
88 kDMIC_DcNoRemove = 0U, /*!< Flat response no filter */
89 kDMIC_DcCut155 = 1U, /*!< Cut off Frequency is 155 Hz */
90 kDMIC_DcCut78 = 2U, /*!< Cut off Frequency is 78 Hz */
91 kDMIC_DcCut39 = 3U, /*!< Cut off Frequency is 39 Hz */
92 } dc_removal_t;
93
94 #if !(defined(FSL_FEATURE_DMIC_HAS_NO_IOCFG) && FSL_FEATURE_DMIC_HAS_NO_IOCFG)
95 /*! @brief DMIC IO configiration. */
96 typedef enum _dmic_io
97 {
98 kDMIC_PdmDual = 0, /*!< Two separate pairs of PDM wires */
99 kDMIC_PdmStereo = 4, /*!< Stereo data0 */
100
101 #if !(defined(FSL_FEATURE_DMIC_IO_HAS_NO_BYPASS) && (FSL_FEATURE_DMIC_IO_HAS_NO_BYPASS))
102 kDMIC_PdmBypass = 3, /*!< Clk Bypass clocks both channels */
103 kDMIC_PdmBypassClk0 = 1, /*!< Clk Bypass clocks only channel0 */
104 kDMIC_PdmBypassClk1 = 2, /*!< Clk Bypas clocks only channel1 */
105 #endif
106
107 #if defined(FSL_FEATURE_DMIC_IO_HAS_STEREO_2_4_6) && (FSL_FEATURE_DMIC_IO_HAS_STEREO_2_4_6)
108 kDMIC_PdmStereo2 = 8, /*!< Stereo data2 */
109 kDMIC_PdmStereo4 = 16, /*!< Stereo data4 */
110 kDMIC_PdmStereo6 = 32, /*!< Stereo data6 */
111 #endif
112 } dmic_io_t;
113 #endif
114
115 /*! @brief DMIC Channel number. */
116 typedef enum _dmic_channel
117 {
118 kDMIC_Channel0 = 0U, /*!< DMIC channel 0 */
119 kDMIC_Channel1 = 1U, /*!< DMIC channel 1 */
120 #if defined(FSL_FEATURE_DMIC_CHANNEL_NUM) && (FSL_FEATURE_DMIC_CHANNEL_NUM == 8U)
121 kDMIC_Channel2 = 2U, /*!< DMIC channel 2 */
122 kDMIC_Channel3 = 3U, /*!< DMIC channel 3 */
123 kDMIC_Channel4 = 4U, /*!< DMIC channel 4 */
124 kDMIC_Channel5 = 5U, /*!< DMIC channel 5 */
125 kDMIC_Channel6 = 6U, /*!< DMIC channel 6 */
126 kDMIC_Channel7 = 7U, /*!< DMIC channel 7 */
127 #endif
128 } dmic_channel_t;
129
130 /*! @brief _dmic_channel_mask DMIC Channel mask. */
131 enum
132 {
133 kDMIC_EnableChannel0 = 1 << 0U, /*!< DMIC channel 0 mask */
134 kDMIC_EnableChannel1 = 1 << 1U, /*!< DMIC channel 1 mask */
135 #if defined(FSL_FEATURE_DMIC_CHANNEL_NUM) && (FSL_FEATURE_DMIC_CHANNEL_NUM == 8U)
136 kDMIC_EnableChannel2 = 1 << 2U, /*!< DMIC channel 2 mask */
137 kDMIC_EnableChannel3 = 1 << 3U, /*!< DMIC channel 3 mask */
138 kDMIC_EnableChannel4 = 1 << 4U, /*!< DMIC channel 4 mask */
139 kDMIC_EnableChannel5 = 1 << 5U, /*!< DMIC channel 5 mask */
140 kDMIC_EnableChannel6 = 1 << 6U, /*!< DMIC channel 6 mask */
141 kDMIC_EnableChannel7 = 1 << 7U, /*!< DMIC channel 7 mask */
142 #endif
143 };
144
145 /*! @brief DMIC and decimator sample rates. */
146 typedef enum _dmic_phy_sample_rate
147 {
148 kDMIC_PhyFullSpeed = 0U, /*!< Decimator gets one sample per each chosen clock edge of PDM interface */
149 kDMIC_PhyHalfSpeed = 1U, /*!< PDM clock to Microphone is halved, decimator receives each sample twice */
150 } dmic_phy_sample_rate_t;
151
152 /*! @brief DMIC Channel configuration structure. */
153 typedef struct _dmic_channel_config
154 {
155 pdm_div_t divhfclk; /*!< DMIC Clock pre-divider values */
156 uint32_t osr; /*!< oversampling rate(CIC decimation rate) for PCM */
157 int32_t gainshft; /*!< 4FS PCM data gain control */
158 compensation_t preac2coef; /*!< Pre-emphasis Filter coefficient value for 2FS */
159 compensation_t preac4coef; /*!< Pre-emphasis Filter coefficient value for 4FS */
160 dc_removal_t dc_cut_level; /*!< DMIC DC filter control values. */
161 uint32_t post_dc_gain_reduce; /*!< Fine gain adjustment in the form of a number of bits to downshift */
162 dmic_phy_sample_rate_t sample_rate; /*!< DMIC and decimator sample rates */
163 bool saturate16bit; /*!< Selects 16-bit saturation. 0 means results roll over if out range and do not saturate.
164 1 means if the result overflows, it saturates at 0xFFFF for positive overflow and
165 0x8000 for negative overflow.*/
166 #if defined(FSL_FEATURE_DMIC_CHANNEL_HAS_SIGNEXTEND) && (FSL_FEATURE_DMIC_CHANNEL_HAS_SIGNEXTEND)
167 bool enableSignExtend; /*!< sign extend feature which allows processing of 24bit audio data on 32bit machine */
168 #endif
169 } dmic_channel_config_t;
170
171 /*! @brief DMIC Callback function. */
172 typedef void (*dmic_callback_t)(void);
173
174 /*! @brief HWVAD Callback function. */
175 typedef void (*dmic_hwvad_callback_t)(void);
176
177 /*******************************************************************************
178 * API
179 ******************************************************************************/
180 #ifdef __cplusplus
181 extern "C" {
182 #endif
183
184 /*!
185 * @name Initialization and deinitialization
186 * @{
187 */
188
189 /*!
190 * @brief Get the DMIC instance from peripheral base address.
191 *
192 * @param base DMIC peripheral base address.
193 * @return DMIC instance.
194 */
195 uint32_t DMIC_GetInstance(DMIC_Type *base);
196
197 /*!
198 * @brief Turns DMIC Clock on
199 * @param base : DMIC base
200 * @return Nothing
201 */
202 void DMIC_Init(DMIC_Type *base);
203
204 /*!
205 * @brief Turns DMIC Clock off
206 * @param base : DMIC base
207 * @return Nothing
208 */
209 void DMIC_DeInit(DMIC_Type *base);
210
211 #if !(defined(FSL_FEATURE_DMIC_HAS_NO_IOCFG) && FSL_FEATURE_DMIC_HAS_NO_IOCFG)
212 /*!
213 * @brief Configure DMIC io
214 * @deprecated Do not use this function. It has been superceded by @ref DMIC_SetIOCFG
215 * @param base : The base address of DMIC interface
216 * @param config : DMIC io configuration
217 * @return Nothing
218 */
219 void DMIC_ConfigIO(DMIC_Type *base, dmic_io_t config);
220
221 /*!
222 * @brief Stereo PDM select.
223 * @param base : The base address of DMIC interface
224 * @param sel : Reference dmic_io_t, can be a single or combination value of dmic_io_t.
225 * @return Nothing
226 */
DMIC_SetIOCFG(DMIC_Type * base,uint32_t sel)227 static inline void DMIC_SetIOCFG(DMIC_Type *base, uint32_t sel)
228 {
229 base->IOCFG = sel;
230 }
231 #endif
232
233 /*!
234 * @brief Set DMIC operating mode
235 * @deprecated Do not use this function. It has been superceded by
236 * @ref DMIC_EnableChannelInterrupt, @ref DMIC_EnableChannelDma.
237 * @param base : The base address of DMIC interface
238 * @param mode : DMIC mode
239 * @return Nothing
240 */
241 void DMIC_SetOperationMode(DMIC_Type *base, operation_mode_t mode);
242
243 /*!
244 * @brief Configure Clock scaling
245 * @param base : The base address of DMIC interface
246 * @param use2fs : clock scaling
247 * @return Nothing
248 */
249 void DMIC_Use2fs(DMIC_Type *base, bool use2fs);
250
251 /*! @} */
252
253 /*!
254 * @name Channel configuration
255 * @{
256 */
257
258 /*!
259 * @brief Configure DMIC channel
260 * @param base : The base address of DMIC interface
261 * @param channel : DMIC channel
262 * @param dc_cut_level : dc_removal_t, Cut off Frequency
263 * @param post_dc_gain_reduce : Fine gain adjustment in the form of a number of bits to downshift.
264 * @param saturate16bit : If selects 16-bit saturation.
265 */
266 void DMIC_CfgChannelDc(DMIC_Type *base,
267 dmic_channel_t channel,
268 dc_removal_t dc_cut_level,
269 uint32_t post_dc_gain_reduce,
270 bool saturate16bit);
271
272 #if defined(FSL_FEATURE_DMIC_CHANNEL_HAS_SIGNEXTEND) && (FSL_FEATURE_DMIC_CHANNEL_HAS_SIGNEXTEND)
273 /*!
274 * @brief Enbale channel sign extend which allows processing of 24bit audio data on 32bit machines.
275 * @param base : The base address of DMIC interface
276 * @param channel : DMIC channel
277 * @param enable : true is enable sign extend, false is disable sign extend
278 */
DMIC_EnableChannelSignExtend(DMIC_Type * base,dmic_channel_t channel,bool enable)279 static inline void DMIC_EnableChannelSignExtend(DMIC_Type *base, dmic_channel_t channel, bool enable)
280 {
281 if (enable)
282 {
283 base->CHANNEL[channel].DC_CTRL |= DMIC_CHANNEL_DC_CTRL_SIGNEXTEND_MASK;
284 }
285 else
286 {
287 base->CHANNEL[channel].DC_CTRL &= ~DMIC_CHANNEL_DC_CTRL_SIGNEXTEND_MASK;
288 }
289 }
290 #endif
291
292 /*!
293 * @brief Configure DMIC channel
294 *
295 * @param base : The base address of DMIC interface
296 * @param channel : DMIC channel
297 * @param side : stereo_side_t, choice of left or right
298 * @param channel_config : Channel configuration
299 * @return Nothing
300 */
301 void DMIC_ConfigChannel(DMIC_Type *base,
302 dmic_channel_t channel,
303 stereo_side_t side,
304 dmic_channel_config_t *channel_config);
305
306 /*!
307 * @brief Enable a particualr channel
308 * @param base : The base address of DMIC interface
309 * @param channelmask reference _dmic_channel_mask
310 * @return Nothing
311 */
312 void DMIC_EnableChannnel(DMIC_Type *base, uint32_t channelmask);
313
314 /*!
315 * @brief Configure fifo settings for DMIC channel
316 * @param base : The base address of DMIC interface
317 * @param channel : DMIC channel
318 * @param trig_level : FIFO trigger level
319 * @param enable : FIFO level
320 * @param resetn : FIFO reset
321 * @return Nothing
322 */
323 void DMIC_FifoChannel(DMIC_Type *base, uint32_t channel, uint32_t trig_level, uint32_t enable, uint32_t resetn);
324
325 /*!
326 * @brief Enable a particualr channel interrupt request.
327 * @param base : The base address of DMIC interface
328 * @param channel : Channel selection
329 * @param enable : true is enable, false is disable
330 */
DMIC_EnableChannelInterrupt(DMIC_Type * base,dmic_channel_t channel,bool enable)331 static inline void DMIC_EnableChannelInterrupt(DMIC_Type *base, dmic_channel_t channel, bool enable)
332 {
333 if (enable)
334 {
335 base->CHANNEL[channel].FIFO_CTRL |= DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK;
336 }
337 else
338 {
339 base->CHANNEL[channel].FIFO_CTRL &= ~DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK;
340 }
341 }
342
343 /*!
344 * @brief Enable a particualr channel dma request.
345 * @param base : The base address of DMIC interface
346 * @param channel : Channel selection
347 * @param enable : true is enable, false is disable
348 */
DMIC_EnableChannelDma(DMIC_Type * base,dmic_channel_t channel,bool enable)349 static inline void DMIC_EnableChannelDma(DMIC_Type *base, dmic_channel_t channel, bool enable)
350 {
351 if (enable)
352 {
353 base->CHANNEL[channel].FIFO_CTRL |= DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK;
354 }
355 else
356 {
357 base->CHANNEL[channel].FIFO_CTRL &= ~DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK;
358 }
359 }
360
361 /*!
362 * @brief Enable a particualr channel fifo.
363 * @param base : The base address of DMIC interface
364 * @param channel : Channel selection
365 * @param enable : true is enable, false is disable
366 */
DMIC_EnableChannelFifo(DMIC_Type * base,dmic_channel_t channel,bool enable)367 static inline void DMIC_EnableChannelFifo(DMIC_Type *base, dmic_channel_t channel, bool enable)
368 {
369 if (enable)
370 {
371 base->CHANNEL[channel].FIFO_CTRL |= DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK;
372 }
373 else
374 {
375 base->CHANNEL[channel].FIFO_CTRL &= ~DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK;
376 }
377 }
378
379 /*!
380 * @brief Channel fifo reset.
381 * @param base : The base address of DMIC interface
382 * @param channel : Channel selection
383 */
DMIC_DoFifoReset(DMIC_Type * base,dmic_channel_t channel)384 static inline void DMIC_DoFifoReset(DMIC_Type *base, dmic_channel_t channel)
385 {
386 /* reset FIFO */
387 base->CHANNEL[channel].FIFO_CTRL &= ~DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK;
388 /* normal operation */
389 base->CHANNEL[channel].FIFO_CTRL |= DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK;
390 }
391
392 /*!
393 * @brief Get FIFO status
394 * @param base : The base address of DMIC interface
395 * @param channel : DMIC channel
396 * @return FIFO status
397 */
DMIC_FifoGetStatus(DMIC_Type * base,uint32_t channel)398 static inline uint32_t DMIC_FifoGetStatus(DMIC_Type *base, uint32_t channel)
399 {
400 return base->CHANNEL[channel].FIFO_STATUS;
401 }
402
403 /*!
404 * @brief Clear FIFO status
405 * @param base : The base address of DMIC interface
406 * @param channel : DMIC channel
407 * @param mask : Bits to be cleared
408 * @return FIFO status
409 */
DMIC_FifoClearStatus(DMIC_Type * base,uint32_t channel,uint32_t mask)410 static inline void DMIC_FifoClearStatus(DMIC_Type *base, uint32_t channel, uint32_t mask)
411 {
412 base->CHANNEL[channel].FIFO_STATUS = mask;
413 }
414
415 /*!
416 * @brief Get FIFO data
417 * @param base : The base address of DMIC interface
418 * @param channel : DMIC channel
419 * @return FIFO data
420 */
DMIC_FifoGetData(DMIC_Type * base,uint32_t channel)421 static inline uint32_t DMIC_FifoGetData(DMIC_Type *base, uint32_t channel)
422 {
423 return base->CHANNEL[channel].FIFO_DATA;
424 }
425
426 /*!
427 * @brief Get FIFO address
428 * @param base : The base address of DMIC interface
429 * @param channel : DMIC channel
430 * @return FIFO data
431 */
DMIC_FifoGetAddress(DMIC_Type * base,uint32_t channel)432 static inline uint32_t DMIC_FifoGetAddress(DMIC_Type *base, uint32_t channel)
433 {
434 return (uint32_t)(&(base->CHANNEL[channel].FIFO_DATA));
435 }
436
437 #if defined(FSL_FEATURE_DMIC_HAS_DECIMATOR_RESET_FUNC) && FSL_FEATURE_DMIC_HAS_DECIMATOR_RESET_FUNC
438 /*!
439 * @brief DMIC channel Decimator reset
440 * @param base : The base address of DMIC interface
441 * @param channelMask : DMIC channel mask, reference _dmic_channel_mask
442 * @param reset : true is reset decimator, false is release decimator.
443 */
444 void DMIC_ResetChannelDecimator(DMIC_Type *base, uint32_t channelMask, bool reset);
445 #endif
446
447 #if defined(FSL_FEATURE_DMIC_HAS_GLOBAL_SYNC_FUNC) && FSL_FEATURE_DMIC_HAS_GLOBAL_SYNC_FUNC
448 /*!
449 * @brief Enable DMIC channel global sync function.
450 * @param base : The base address of DMIC interface
451 * @param channelMask : DMIC channel mask, reference _dmic_channel_mask
452 * @param syncCounter :sync counter will trigger a pulse whenever count reaches CCOUNTVAL. If CCOUNTVAL is set to 0,
453 * there will be a pulse on every cycle
454 */
DMIC_EnableChannelGlobalSync(DMIC_Type * base,uint32_t channelMask,uint32_t syncCounter)455 static inline void DMIC_EnableChannelGlobalSync(DMIC_Type *base, uint32_t channelMask, uint32_t syncCounter)
456 {
457 base->GLOBAL_COUNT_VAL = syncCounter;
458 base->GLOBAL_SYNC_EN = channelMask;
459 }
460
461 /*!
462 * @brief Disbale DMIC channel global sync function.
463 * @param base : The base address of DMIC interface
464 * @param channelMask : DMIC channel mask, reference _dmic_channel_mask
465 */
DMIC_DisableChannelGlobalSync(DMIC_Type * base,uint32_t channelMask)466 static inline void DMIC_DisableChannelGlobalSync(DMIC_Type *base, uint32_t channelMask)
467 {
468 base->GLOBAL_SYNC_EN &= ~channelMask;
469 }
470 #endif
471
472 /*! @} */
473
474 /*!
475 * @name Register callback.
476 * @{
477 */
478
479 /*!
480 * @brief Enable callback.
481
482 * This function enables the interrupt for the selected DMIC peripheral.
483 * The callback function is not enabled until this function is called.
484 *
485 * @param base Base address of the DMIC peripheral.
486 * @param cb callback Pointer to store callback function.
487 * @retval None.
488 */
489 void DMIC_EnableIntCallback(DMIC_Type *base, dmic_callback_t cb);
490
491 /*!
492 * @brief Disable callback.
493
494 * This function disables the interrupt for the selected DMIC peripheral.
495 *
496 * @param base Base address of the DMIC peripheral.
497 * @param cb callback Pointer to store callback function..
498 * @retval None.
499 */
500 void DMIC_DisableIntCallback(DMIC_Type *base, dmic_callback_t cb);
501 /*! @} */
502
503 /*!
504 * @name HWVAD
505 * @{
506 */
507
508 /*!
509 * @brief Sets the gain value for the noise estimator.
510 *
511 * @param base DMIC base pointer
512 * @param value gain value for the noise estimator.
513 * @retval None.
514 */
DMIC_SetGainNoiseEstHwvad(DMIC_Type * base,uint32_t value)515 static inline void DMIC_SetGainNoiseEstHwvad(DMIC_Type *base, uint32_t value)
516 {
517 assert(NULL != base);
518 base->HWVADTHGN = value & 0xFUL;
519 }
520
521 /*!
522 * @brief Sets the gain value for the signal estimator.
523 *
524 * @param base DMIC base pointer
525 * @param value gain value for the signal estimator.
526 * @retval None.
527 */
DMIC_SetGainSignalEstHwvad(DMIC_Type * base,uint32_t value)528 static inline void DMIC_SetGainSignalEstHwvad(DMIC_Type *base, uint32_t value)
529 {
530 assert(NULL != base);
531 base->HWVADTHGS = value & 0xFUL;
532 }
533
534 /*!
535 * @brief Sets the hwvad filter cutoff frequency parameter.
536 *
537 * @param base DMIC base pointer
538 * @param value cut off frequency value.
539 * @retval None.
540 */
DMIC_SetFilterCtrlHwvad(DMIC_Type * base,uint32_t value)541 static inline void DMIC_SetFilterCtrlHwvad(DMIC_Type *base, uint32_t value)
542 {
543 assert(NULL != base);
544 base->HWVADHPFS = value & 0x3UL;
545 }
546
547 /*!
548 * @brief Sets the input gain of hwvad.
549 *
550 * @param base DMIC base pointer
551 * @param value input gain value for hwvad.
552 * @retval None.
553 */
DMIC_SetInputGainHwvad(DMIC_Type * base,uint32_t value)554 static inline void DMIC_SetInputGainHwvad(DMIC_Type *base, uint32_t value)
555 {
556 assert(NULL != base);
557 base->HWVADGAIN = value & 0xFUL;
558 }
559
560 /*!
561 * @brief Clears hwvad internal interrupt flag.
562 *
563 * @param base DMIC base pointer
564 * @param st10 bit value.
565 * @retval None.
566 */
DMIC_CtrlClrIntrHwvad(DMIC_Type * base,bool st10)567 static inline void DMIC_CtrlClrIntrHwvad(DMIC_Type *base, bool st10)
568 {
569 assert(NULL != base);
570 base->HWVADST10 = (st10) ? 0x1UL : 0x0UL;
571 }
572
573 /*!
574 * @brief Resets hwvad filters.
575 *
576 * @param base DMIC base pointer
577 * @param rstt Reset bit value.
578 * @retval None.
579 */
DMIC_FilterResetHwvad(DMIC_Type * base,bool rstt)580 static inline void DMIC_FilterResetHwvad(DMIC_Type *base, bool rstt)
581 {
582 assert(NULL != base);
583 base->HWVADRSTT = (rstt) ? 0x1UL : 0x0UL;
584 }
585
586 /*!
587 * @brief Gets the value from output of the filter z7.
588 *
589 * @param base DMIC base pointer
590 * @retval output of filter z7.
591 */
DMIC_GetNoiseEnvlpEst(DMIC_Type * base)592 static inline uint16_t DMIC_GetNoiseEnvlpEst(DMIC_Type *base)
593 {
594 assert(NULL != base);
595 return (uint16_t)(base->HWVADLOWZ & 0xFFFFU);
596 }
597
598 /*!
599 * @brief Enable hwvad callback.
600
601 * This function enables the hwvad interrupt for the selected DMIC peripheral.
602 * The callback function is not enabled until this function is called.
603 *
604 * @param base Base address of the DMIC peripheral.
605 * @param vadcb callback Pointer to store callback function.
606 * @retval None.
607 */
608 void DMIC_HwvadEnableIntCallback(DMIC_Type *base, dmic_hwvad_callback_t vadcb);
609
610 /*!
611 * @brief Disable callback.
612
613 * This function disables the hwvad interrupt for the selected DMIC peripheral.
614 *
615 * @param base Base address of the DMIC peripheral.
616 * @param vadcb callback Pointer to store callback function..
617 * @retval None.
618 */
619 void DMIC_HwvadDisableIntCallback(DMIC_Type *base, dmic_hwvad_callback_t vadcb);
620
621 /*! @} */
622
623 #ifdef __cplusplus
624 }
625 #endif
626
627 /*! @}*/
628
629 #endif /* __FSL_DMIC_H */
630
