1 /*
2 ** ###################################################################
3 **     Processors:          MKW41Z256VHT4
4 **                          MKW41Z512CAT4
5 **                          MKW41Z512VHT4
6 **
7 **     Compilers:           Keil ARM C/C++ Compiler
8 **                          GNU C Compiler
9 **                          IAR ANSI C/C++ Compiler for ARM
10 **                          MCUXpresso Compiler
11 **
12 **     Reference manual:    MKW41Z512RM Rev. 0.1, 04/2016
13 **     Version:             rev. 1.0, 2015-09-23
14 **     Build:               b170213
15 **
16 **     Abstract:
17 **         CMSIS Peripheral Access Layer for MKW41Z4
18 **
19 **     Copyright 1997-2016 Freescale Semiconductor, Inc.
20 **     Copyright 2016-2017 NXP
21 **     Redistribution and use in source and binary forms, with or without modification,
22 **     are permitted provided that the following conditions are met:
23 **
24 **     o Redistributions of source code must retain the above copyright notice, this list
25 **       of conditions and the following disclaimer.
26 **
27 **     o Redistributions in binary form must reproduce the above copyright notice, this
28 **       list of conditions and the following disclaimer in the documentation and/or
29 **       other materials provided with the distribution.
30 **
31 **     o Neither the name of the copyright holder nor the names of its
32 **       contributors may be used to endorse or promote products derived from this
33 **       software without specific prior written permission.
34 **
35 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
36 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
37 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
38 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
39 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
40 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
41 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
42 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
43 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
44 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
45 **
46 **     http:                 www.nxp.com
47 **     mail:                 support@nxp.com
48 **
49 **     Revisions:
50 **     - rev. 1.0 (2015-09-23)
51 **         Initial version.
52 **
53 ** ###################################################################
54 */
55 
56 /*!
57  * @file MKW41Z4.h
58  * @version 1.0
59  * @date 2015-09-23
60  * @brief CMSIS Peripheral Access Layer for MKW41Z4
61  *
62  * CMSIS Peripheral Access Layer for MKW41Z4
63  */
64 
65 #ifndef _MKW41Z4_H_
66 #define _MKW41Z4_H_                              /**< Symbol preventing repeated inclusion */
67 
68 /** Memory map major version (memory maps with equal major version number are
69  * compatible) */
70 #define MCU_MEM_MAP_VERSION 0x0100U
71 /** Memory map minor version */
72 #define MCU_MEM_MAP_VERSION_MINOR 0x0000U
73 
74 
75 /* ----------------------------------------------------------------------------
76    -- Interrupt vector numbers
77    ---------------------------------------------------------------------------- */
78 
79 /*!
80  * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
81  * @{
82  */
83 
84 /** Interrupt Number Definitions */
85 #define NUMBER_OF_INT_VECTORS 48                 /**< Number of interrupts in the Vector table */
86 
87 typedef enum IRQn {
88   /* Auxiliary constants */
89   NotAvail_IRQn                = -128,             /**< Not available device specific interrupt */
90 
91   /* Core interrupts */
92   NonMaskableInt_IRQn          = -14,              /**< Non Maskable Interrupt */
93   HardFault_IRQn               = -13,              /**< Cortex-M0 SV Hard Fault Interrupt */
94   SVCall_IRQn                  = -5,               /**< Cortex-M0 SV Call Interrupt */
95   PendSV_IRQn                  = -2,               /**< Cortex-M0 Pend SV Interrupt */
96   SysTick_IRQn                 = -1,               /**< Cortex-M0 System Tick Interrupt */
97 
98   /* Device specific interrupts */
99   DMA0_IRQn                    = 0,                /**< DMA channel 0 transfer complete */
100   DMA1_IRQn                    = 1,                /**< DMA channel 1 transfer complete */
101   DMA2_IRQn                    = 2,                /**< DMA channel 2 transfer complete */
102   DMA3_IRQn                    = 3,                /**< DMA channel 3 transfer complete */
103   Reserved20_IRQn              = 4,                /**< Reserved interrupt */
104   FTFA_IRQn                    = 5,                /**< Command complete and read collision */
105   LVD_LVW_DCDC_IRQn            = 6,                /**< Low-voltage detect, low-voltage warning, DCDC */
106   LLWU_IRQn                    = 7,                /**< Low leakage wakeup Unit */
107   I2C0_IRQn                    = 8,                /**< I2C0 interrupt */
108   I2C1_IRQn                    = 9,                /**< I2C1 interrupt */
109   SPI0_IRQn                    = 10,               /**< SPI0 single interrupt vector for all sources */
110   TSI0_IRQn                    = 11,               /**< TSI0 single interrupt vector for all sources */
111   LPUART0_IRQn                 = 12,               /**< LPUART0 status and error */
112   TRNG0_IRQn                   = 13,               /**< TRNG0 interrupt */
113   CMT_IRQn                     = 14,               /**< CMT interrupt */
114   ADC0_IRQn                    = 15,               /**< ADC0 interrupt */
115   CMP0_IRQn                    = 16,               /**< CMP0 interrupt */
116   TPM0_IRQn                    = 17,               /**< TPM0 single interrupt vector for all sources */
117   TPM1_IRQn                    = 18,               /**< TPM1 single interrupt vector for all sources */
118   TPM2_IRQn                    = 19,               /**< TPM2 single interrupt vector for all sources */
119   RTC_IRQn                     = 20,               /**< RTC alarm */
120   RTC_Seconds_IRQn             = 21,               /**< RTC seconds */
121   PIT_IRQn                     = 22,               /**< PIT interrupt */
122   LTC0_IRQn                    = 23,               /**< LTC0 interrupt */
123   Radio_0_IRQn                 = 24,               /**< BTLE, ZIGBEE, ANT, GENFSK interrupt 0 */
124   DAC0_IRQn                    = 25,               /**< DAC0 interrupt */
125   Radio_1_IRQn                 = 26,               /**< BTLE, ZIGBEE, ANT, GENFSK interrupt 1 */
126   MCG_IRQn                     = 27,               /**< MCG interrupt */
127   LPTMR0_IRQn                  = 28,               /**< LPTMR0 interrupt */
128   SPI1_IRQn                    = 29,               /**< SPI1 single interrupt vector for all sources */
129   PORTA_IRQn                   = 30,               /**< PORTA Pin detect */
130   PORTB_PORTC_IRQn             = 31                /**< PORTB and PORTC Pin detect */
131 } IRQn_Type;
132 
133 /*!
134  * @}
135  */ /* end of group Interrupt_vector_numbers */
136 
137 
138 /* ----------------------------------------------------------------------------
139    -- Cortex M0 Core Configuration
140    ---------------------------------------------------------------------------- */
141 
142 /*!
143  * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
144  * @{
145  */
146 
147 #define __CM0PLUS_REV                  0x0000    /**< Core revision r0p0 */
148 #define __MPU_PRESENT                  0         /**< Defines if an MPU is present or not */
149 #define __VTOR_PRESENT                 1         /**< Defines if VTOR is present or not */
150 #define __NVIC_PRIO_BITS               2         /**< Number of priority bits implemented in the NVIC */
151 #define __Vendor_SysTickConfig         0         /**< Vendor specific implementation of SysTickConfig is defined */
152 
153 #include "core_cm0plus.h"              /* Core Peripheral Access Layer */
154 #include "system_MKW41Z4.h"            /* Device specific configuration file */
155 
156 /*!
157  * @}
158  */ /* end of group Cortex_Core_Configuration */
159 
160 
161 /* ----------------------------------------------------------------------------
162    -- Mapping Information
163    ---------------------------------------------------------------------------- */
164 
165 /*!
166  * @addtogroup Mapping_Information Mapping Information
167  * @{
168  */
169 
170 /** Mapping Information */
171 /*!
172  * @addtogroup edma_request
173  * @{
174  */
175 
176 /*******************************************************************************
177  * Definitions
178  ******************************************************************************/
179 
180 /*!
181  * @brief Structure for the DMA hardware request
182  *
183  * Defines the structure for the DMA hardware request collections. The user can configure the
184  * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index
185  * of the hardware request varies according  to the to SoC.
186  */
187 typedef enum _dma_request_source
188 {
189     kDmaRequestMux0Disable          = 0|0x100U,    /**< DMAMUX TriggerDisabled. */
190     kDmaRequestMux0Reserved1        = 1|0x100U,    /**< Reserved1 */
191     kDmaRequestMux0LPUART0Rx        = 2|0x100U,    /**< LPUART0 Receive. */
192     kDmaRequestMux0LPUART0Tx        = 3|0x100U,    /**< LPUART0 Transmit. */
193     kDmaRequestMux0Reserved4        = 4|0x100U,    /**< Reserved4 */
194     kDmaRequestMux0Reserved5        = 5|0x100U,    /**< Reserved5 */
195     kDmaRequestMux0Reserved6        = 6|0x100U,    /**< Reserved6 */
196     kDmaRequestMux0Reserved7        = 7|0x100U,    /**< Reserved7 */
197     kDmaRequestMux0Reserved8        = 8|0x100U,    /**< Reserved8 */
198     kDmaRequestMux0Reserved9        = 9|0x100U,    /**< Reserved9 */
199     kDmaRequestMux0Reserved10       = 10|0x100U,   /**< Reserved10 */
200     kDmaRequestMux0Reserved11       = 11|0x100U,   /**< Reserved11 */
201     kDmaRequestMux0Reserved12       = 12|0x100U,   /**< Reserved12 */
202     kDmaRequestMux0Reserved13       = 13|0x100U,   /**< Reserved13 */
203     kDmaRequestMux0Reserved14       = 14|0x100U,   /**< Reserved14 */
204     kDmaRequestMux0Reserved15       = 15|0x100U,   /**< Reserved15 */
205     kDmaRequestMux0SPI0Rx           = 16|0x100U,   /**< SPI0 Receive. */
206     kDmaRequestMux0SPI0Tx           = 17|0x100U,   /**< SPI0 Transmit. */
207     kDmaRequestMux0SPI1Rx           = 18|0x100U,   /**< SPI1 Receive. */
208     kDmaRequestMux0SPI1Tx           = 19|0x100U,   /**< SPI1 Transmit. */
209     kDmaRequestMux0LTC0InputFIFO    = 20|0x100U,   /**< LTC0 Input FIFO. */
210     kDmaRequestMux0LTC0OutputFIFO   = 21|0x100U,   /**< LTC0 Output FIFO. */
211     kDmaRequestMux0I2C0             = 22|0x100U,   /**< I2C0. */
212     kDmaRequestMux0I2C1             = 23|0x100U,   /**< I2C1. */
213     kDmaRequestMux0TPM0Channel0     = 24|0x100U,   /**< TPM0 C0V. */
214     kDmaRequestMux0TPM0Channel1     = 25|0x100U,   /**< TPM0 C1V. */
215     kDmaRequestMux0TPM0Channel2     = 26|0x100U,   /**< TPM0 C2V. */
216     kDmaRequestMux0TPM0Channel3     = 27|0x100U,   /**< TPM0 C3V. */
217     kDmaRequestMux0Reserved28       = 28|0x100U,   /**< Reserved28 */
218     kDmaRequestMux0Reserved29       = 29|0x100U,   /**< Reserved29 */
219     kDmaRequestMux0Reserved30       = 30|0x100U,   /**< Reserved30 */
220     kDmaRequestMux0Reserved31       = 31|0x100U,   /**< Reserved31 */
221     kDmaRequestMux0TPM1Channel0     = 32|0x100U,   /**< TPM1 C0V. */
222     kDmaRequestMux0TPM1Channel1     = 33|0x100U,   /**< TPM1 C1V. */
223     kDmaRequestMux0TPM2Channel0     = 34|0x100U,   /**< TPM2 C0V. */
224     kDmaRequestMux0TPM2Channel1     = 35|0x100U,   /**< TPM2 C1V. */
225     kDmaRequestMux0Reserved36       = 36|0x100U,   /**< Reserved36 */
226     kDmaRequestMux0Reserved37       = 37|0x100U,   /**< Reserved37 */
227     kDmaRequestMux0Reserved38       = 38|0x100U,   /**< Reserved38 */
228     kDmaRequestMux0Reserved39       = 39|0x100U,   /**< Reserved39 */
229     kDmaRequestMux0ADC0             = 40|0x100U,   /**< ADC0. */
230     kDmaRequestMux0Reserved41       = 41|0x100U,   /**< Reserved41 */
231     kDmaRequestMux0CMP0             = 42|0x100U,   /**< CMP0. */
232     kDmaRequestMux0Reserved43       = 43|0x100U,   /**< Reserved43 */
233     kDmaRequestMux0Reserved44       = 44|0x100U,   /**< Reserved44 */
234     kDmaRequestMux0DAC0             = 45|0x100U,   /**< DAC0. */
235     kDmaRequestMux0Reserved46       = 46|0x100U,   /**< Reserved46 */
236     kDmaRequestMux0CMT              = 47|0x100U,   /**< CMT. */
237     kDmaRequestMux0Reserved48       = 48|0x100U,   /**< Reserved48 */
238     kDmaRequestMux0PortA            = 49|0x100U,   /**< PTA. */
239     kDmaRequestMux0PortB            = 50|0x100U,   /**< PTB. */
240     kDmaRequestMux0PortC            = 51|0x100U,   /**< PTC. */
241     kDmaRequestMux0Reserved52       = 52|0x100U,   /**< Reserved52 */
242     kDmaRequestMux0Reserved53       = 53|0x100U,   /**< Reserved53 */
243     kDmaRequestMux0TPM0Overflow     = 54|0x100U,   /**< TPM0. */
244     kDmaRequestMux0TPM1Overflow     = 55|0x100U,   /**< TPM1. */
245     kDmaRequestMux0TPM2Overflow     = 56|0x100U,   /**< TPM2. */
246     kDmaRequestMux0TSI0             = 57|0x100U,   /**< TSI0. */
247     kDmaRequestMux0Reserved58       = 58|0x100U,   /**< Reserved58 */
248     kDmaRequestMux0Reserved59       = 59|0x100U,   /**< Reserved59 */
249     kDmaRequestMux0AlwaysOn60       = 60|0x100U,   /**< DMAMUX Always Enabled slot. */
250     kDmaRequestMux0AlwaysOn61       = 61|0x100U,   /**< DMAMUX Always Enabled slot. */
251     kDmaRequestMux0AlwaysOn62       = 62|0x100U,   /**< DMAMUX Always Enabled slot. */
252     kDmaRequestMux0AlwaysOn63       = 63|0x100U,   /**< DMAMUX Always Enabled slot. */
253 } dma_request_source_t;
254 
255 /* @} */
256 
257 
258 /*!
259  * @}
260  */ /* end of group Mapping_Information */
261 
262 
263 /* ----------------------------------------------------------------------------
264    -- Device Peripheral Access Layer
265    ---------------------------------------------------------------------------- */
266 
267 /*!
268  * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
269  * @{
270  */
271 
272 
273 /*
274 ** Start of section using anonymous unions
275 */
276 
277 #if defined(__ARMCC_VERSION)
278   #pragma push
279   #pragma anon_unions
280 #elif defined(__GNUC__)
281   /* anonymous unions are enabled by default */
282 #elif defined(__IAR_SYSTEMS_ICC__)
283   #pragma language=extended
284 #else
285   #error Not supported compiler type
286 #endif
287 
288 /* ----------------------------------------------------------------------------
289    -- ADC Peripheral Access Layer
290    ---------------------------------------------------------------------------- */
291 
292 /*!
293  * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
294  * @{
295  */
296 
297 /** ADC - Register Layout Typedef */
298 typedef struct {
299   __IO uint32_t SC1[2];                            /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
300   __IO uint32_t CFG1;                              /**< ADC Configuration Register 1, offset: 0x8 */
301   __IO uint32_t CFG2;                              /**< ADC Configuration Register 2, offset: 0xC */
302   __I  uint32_t R[2];                              /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
303   __IO uint32_t CV1;                               /**< Compare Value Registers, offset: 0x18 */
304   __IO uint32_t CV2;                               /**< Compare Value Registers, offset: 0x1C */
305   __IO uint32_t SC2;                               /**< Status and Control Register 2, offset: 0x20 */
306   __IO uint32_t SC3;                               /**< Status and Control Register 3, offset: 0x24 */
307   __IO uint32_t OFS;                               /**< ADC Offset Correction Register, offset: 0x28 */
308   __IO uint32_t PG;                                /**< ADC Plus-Side Gain Register, offset: 0x2C */
309   __IO uint32_t MG;                                /**< ADC Minus-Side Gain Register, offset: 0x30 */
310   __IO uint32_t CLPD;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
311   __IO uint32_t CLPS;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
312   __IO uint32_t CLP4;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
313   __IO uint32_t CLP3;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
314   __IO uint32_t CLP2;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
315   __IO uint32_t CLP1;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
316   __IO uint32_t CLP0;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
317        uint8_t RESERVED_0[4];
318   __IO uint32_t CLMD;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
319   __IO uint32_t CLMS;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
320   __IO uint32_t CLM4;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
321   __IO uint32_t CLM3;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
322   __IO uint32_t CLM2;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
323   __IO uint32_t CLM1;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
324   __IO uint32_t CLM0;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
325 } ADC_Type;
326 
327 /* ----------------------------------------------------------------------------
328    -- ADC Register Masks
329    ---------------------------------------------------------------------------- */
330 
331 /*!
332  * @addtogroup ADC_Register_Masks ADC Register Masks
333  * @{
334  */
335 
336 /*! @name SC1 - ADC Status and Control Registers 1 */
337 #define ADC_SC1_ADCH_MASK                        (0x1FU)
338 #define ADC_SC1_ADCH_SHIFT                       (0U)
339 #define ADC_SC1_ADCH(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
340 #define ADC_SC1_DIFF_MASK                        (0x20U)
341 #define ADC_SC1_DIFF_SHIFT                       (5U)
342 #define ADC_SC1_DIFF(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK)
343 #define ADC_SC1_AIEN_MASK                        (0x40U)
344 #define ADC_SC1_AIEN_SHIFT                       (6U)
345 #define ADC_SC1_AIEN(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK)
346 #define ADC_SC1_COCO_MASK                        (0x80U)
347 #define ADC_SC1_COCO_SHIFT                       (7U)
348 #define ADC_SC1_COCO(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK)
349 
350 /* The count of ADC_SC1 */
351 #define ADC_SC1_COUNT                            (2U)
352 
353 /*! @name CFG1 - ADC Configuration Register 1 */
354 #define ADC_CFG1_ADICLK_MASK                     (0x3U)
355 #define ADC_CFG1_ADICLK_SHIFT                    (0U)
356 #define ADC_CFG1_ADICLK(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK)
357 #define ADC_CFG1_MODE_MASK                       (0xCU)
358 #define ADC_CFG1_MODE_SHIFT                      (2U)
359 #define ADC_CFG1_MODE(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK)
360 #define ADC_CFG1_ADLSMP_MASK                     (0x10U)
361 #define ADC_CFG1_ADLSMP_SHIFT                    (4U)
362 #define ADC_CFG1_ADLSMP(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK)
363 #define ADC_CFG1_ADIV_MASK                       (0x60U)
364 #define ADC_CFG1_ADIV_SHIFT                      (5U)
365 #define ADC_CFG1_ADIV(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
366 #define ADC_CFG1_ADLPC_MASK                      (0x80U)
367 #define ADC_CFG1_ADLPC_SHIFT                     (7U)
368 #define ADC_CFG1_ADLPC(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK)
369 
370 /*! @name CFG2 - ADC Configuration Register 2 */
371 #define ADC_CFG2_ADLSTS_MASK                     (0x3U)
372 #define ADC_CFG2_ADLSTS_SHIFT                    (0U)
373 #define ADC_CFG2_ADLSTS(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK)
374 #define ADC_CFG2_ADHSC_MASK                      (0x4U)
375 #define ADC_CFG2_ADHSC_SHIFT                     (2U)
376 #define ADC_CFG2_ADHSC(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK)
377 #define ADC_CFG2_ADACKEN_MASK                    (0x8U)
378 #define ADC_CFG2_ADACKEN_SHIFT                   (3U)
379 #define ADC_CFG2_ADACKEN(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK)
380 #define ADC_CFG2_MUXSEL_MASK                     (0x10U)
381 #define ADC_CFG2_MUXSEL_SHIFT                    (4U)
382 #define ADC_CFG2_MUXSEL(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK)
383 
384 /*! @name R - ADC Data Result Register */
385 #define ADC_R_D_MASK                             (0xFFFFU)
386 #define ADC_R_D_SHIFT                            (0U)
387 #define ADC_R_D(x)                               (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK)
388 
389 /* The count of ADC_R */
390 #define ADC_R_COUNT                              (2U)
391 
392 /*! @name CV1 - Compare Value Registers */
393 #define ADC_CV1_CV_MASK                          (0xFFFFU)
394 #define ADC_CV1_CV_SHIFT                         (0U)
395 #define ADC_CV1_CV(x)                            (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK)
396 
397 /*! @name CV2 - Compare Value Registers */
398 #define ADC_CV2_CV_MASK                          (0xFFFFU)
399 #define ADC_CV2_CV_SHIFT                         (0U)
400 #define ADC_CV2_CV(x)                            (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK)
401 
402 /*! @name SC2 - Status and Control Register 2 */
403 #define ADC_SC2_REFSEL_MASK                      (0x3U)
404 #define ADC_SC2_REFSEL_SHIFT                     (0U)
405 #define ADC_SC2_REFSEL(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK)
406 #define ADC_SC2_DMAEN_MASK                       (0x4U)
407 #define ADC_SC2_DMAEN_SHIFT                      (2U)
408 #define ADC_SC2_DMAEN(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK)
409 #define ADC_SC2_ACREN_MASK                       (0x8U)
410 #define ADC_SC2_ACREN_SHIFT                      (3U)
411 #define ADC_SC2_ACREN(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK)
412 #define ADC_SC2_ACFGT_MASK                       (0x10U)
413 #define ADC_SC2_ACFGT_SHIFT                      (4U)
414 #define ADC_SC2_ACFGT(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK)
415 #define ADC_SC2_ACFE_MASK                        (0x20U)
416 #define ADC_SC2_ACFE_SHIFT                       (5U)
417 #define ADC_SC2_ACFE(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK)
418 #define ADC_SC2_ADTRG_MASK                       (0x40U)
419 #define ADC_SC2_ADTRG_SHIFT                      (6U)
420 #define ADC_SC2_ADTRG(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK)
421 #define ADC_SC2_ADACT_MASK                       (0x80U)
422 #define ADC_SC2_ADACT_SHIFT                      (7U)
423 #define ADC_SC2_ADACT(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK)
424 
425 /*! @name SC3 - Status and Control Register 3 */
426 #define ADC_SC3_AVGS_MASK                        (0x3U)
427 #define ADC_SC3_AVGS_SHIFT                       (0U)
428 #define ADC_SC3_AVGS(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK)
429 #define ADC_SC3_AVGE_MASK                        (0x4U)
430 #define ADC_SC3_AVGE_SHIFT                       (2U)
431 #define ADC_SC3_AVGE(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK)
432 #define ADC_SC3_ADCO_MASK                        (0x8U)
433 #define ADC_SC3_ADCO_SHIFT                       (3U)
434 #define ADC_SC3_ADCO(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK)
435 #define ADC_SC3_CALF_MASK                        (0x40U)
436 #define ADC_SC3_CALF_SHIFT                       (6U)
437 #define ADC_SC3_CALF(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK)
438 #define ADC_SC3_CAL_MASK                         (0x80U)
439 #define ADC_SC3_CAL_SHIFT                        (7U)
440 #define ADC_SC3_CAL(x)                           (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK)
441 
442 /*! @name OFS - ADC Offset Correction Register */
443 #define ADC_OFS_OFS_MASK                         (0xFFFFU)
444 #define ADC_OFS_OFS_SHIFT                        (0U)
445 #define ADC_OFS_OFS(x)                           (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
446 
447 /*! @name PG - ADC Plus-Side Gain Register */
448 #define ADC_PG_PG_MASK                           (0xFFFFU)
449 #define ADC_PG_PG_SHIFT                          (0U)
450 #define ADC_PG_PG(x)                             (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK)
451 
452 /*! @name MG - ADC Minus-Side Gain Register */
453 #define ADC_MG_MG_MASK                           (0xFFFFU)
454 #define ADC_MG_MG_SHIFT                          (0U)
455 #define ADC_MG_MG(x)                             (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK)
456 
457 /*! @name CLPD - ADC Plus-Side General Calibration Value Register */
458 #define ADC_CLPD_CLPD_MASK                       (0x3FU)
459 #define ADC_CLPD_CLPD_SHIFT                      (0U)
460 #define ADC_CLPD_CLPD(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK)
461 
462 /*! @name CLPS - ADC Plus-Side General Calibration Value Register */
463 #define ADC_CLPS_CLPS_MASK                       (0x3FU)
464 #define ADC_CLPS_CLPS_SHIFT                      (0U)
465 #define ADC_CLPS_CLPS(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK)
466 
467 /*! @name CLP4 - ADC Plus-Side General Calibration Value Register */
468 #define ADC_CLP4_CLP4_MASK                       (0x3FFU)
469 #define ADC_CLP4_CLP4_SHIFT                      (0U)
470 #define ADC_CLP4_CLP4(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK)
471 
472 /*! @name CLP3 - ADC Plus-Side General Calibration Value Register */
473 #define ADC_CLP3_CLP3_MASK                       (0x1FFU)
474 #define ADC_CLP3_CLP3_SHIFT                      (0U)
475 #define ADC_CLP3_CLP3(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK)
476 
477 /*! @name CLP2 - ADC Plus-Side General Calibration Value Register */
478 #define ADC_CLP2_CLP2_MASK                       (0xFFU)
479 #define ADC_CLP2_CLP2_SHIFT                      (0U)
480 #define ADC_CLP2_CLP2(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK)
481 
482 /*! @name CLP1 - ADC Plus-Side General Calibration Value Register */
483 #define ADC_CLP1_CLP1_MASK                       (0x7FU)
484 #define ADC_CLP1_CLP1_SHIFT                      (0U)
485 #define ADC_CLP1_CLP1(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
486 
487 /*! @name CLP0 - ADC Plus-Side General Calibration Value Register */
488 #define ADC_CLP0_CLP0_MASK                       (0x3FU)
489 #define ADC_CLP0_CLP0_SHIFT                      (0U)
490 #define ADC_CLP0_CLP0(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
491 
492 /*! @name CLMD - ADC Minus-Side General Calibration Value Register */
493 #define ADC_CLMD_CLMD_MASK                       (0x3FU)
494 #define ADC_CLMD_CLMD_SHIFT                      (0U)
495 #define ADC_CLMD_CLMD(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK)
496 
497 /*! @name CLMS - ADC Minus-Side General Calibration Value Register */
498 #define ADC_CLMS_CLMS_MASK                       (0x3FU)
499 #define ADC_CLMS_CLMS_SHIFT                      (0U)
500 #define ADC_CLMS_CLMS(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK)
501 
502 /*! @name CLM4 - ADC Minus-Side General Calibration Value Register */
503 #define ADC_CLM4_CLM4_MASK                       (0x3FFU)
504 #define ADC_CLM4_CLM4_SHIFT                      (0U)
505 #define ADC_CLM4_CLM4(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK)
506 
507 /*! @name CLM3 - ADC Minus-Side General Calibration Value Register */
508 #define ADC_CLM3_CLM3_MASK                       (0x1FFU)
509 #define ADC_CLM3_CLM3_SHIFT                      (0U)
510 #define ADC_CLM3_CLM3(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK)
511 
512 /*! @name CLM2 - ADC Minus-Side General Calibration Value Register */
513 #define ADC_CLM2_CLM2_MASK                       (0xFFU)
514 #define ADC_CLM2_CLM2_SHIFT                      (0U)
515 #define ADC_CLM2_CLM2(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK)
516 
517 /*! @name CLM1 - ADC Minus-Side General Calibration Value Register */
518 #define ADC_CLM1_CLM1_MASK                       (0x7FU)
519 #define ADC_CLM1_CLM1_SHIFT                      (0U)
520 #define ADC_CLM1_CLM1(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK)
521 
522 /*! @name CLM0 - ADC Minus-Side General Calibration Value Register */
523 #define ADC_CLM0_CLM0_MASK                       (0x3FU)
524 #define ADC_CLM0_CLM0_SHIFT                      (0U)
525 #define ADC_CLM0_CLM0(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK)
526 
527 
528 /*!
529  * @}
530  */ /* end of group ADC_Register_Masks */
531 
532 
533 /* ADC - Peripheral instance base addresses */
534 /** Peripheral ADC0 base address */
535 #define ADC0_BASE                                (0x4003B000u)
536 /** Peripheral ADC0 base pointer */
537 #define ADC0                                     ((ADC_Type *)ADC0_BASE)
538 /** Array initializer of ADC peripheral base addresses */
539 #define ADC_BASE_ADDRS                           { ADC0_BASE }
540 /** Array initializer of ADC peripheral base pointers */
541 #define ADC_BASE_PTRS                            { ADC0 }
542 /** Interrupt vectors for the ADC peripheral type */
543 #define ADC_IRQS                                 { ADC0_IRQn }
544 
545 /*!
546  * @}
547  */ /* end of group ADC_Peripheral_Access_Layer */
548 
549 
550 /* ----------------------------------------------------------------------------
551    -- ANT Peripheral Access Layer
552    ---------------------------------------------------------------------------- */
553 
554 /*!
555  * @addtogroup ANT_Peripheral_Access_Layer ANT Peripheral Access Layer
556  * @{
557  */
558 
559 /** ANT - Register Layout Typedef */
560 typedef struct {
561   __IO uint32_t IRQ_CTRL;                          /**< IRQ CONTROL, offset: 0x0 */
562   __IO uint32_t EVENT_TMR;                         /**< EVENT TIMER, offset: 0x4 */
563   __IO uint32_t T1_CMP;                            /**< T1 COMPARE, offset: 0x8 */
564   __IO uint32_t T2_CMP;                            /**< T2 COMPARE, offset: 0xC */
565   __I  uint32_t TIMESTAMP;                         /**< TIMESTAMP, offset: 0x10 */
566   __IO uint32_t XCVR_CTRL;                         /**< TRANSCEIVER CONTROL, offset: 0x14 */
567   __I  uint32_t XCVR_STS;                          /**< TRANSCEIVER STATUS, offset: 0x18 */
568   __IO uint32_t XCVR_CFG;                          /**< TRANSCEIVER CONFIGURATION, offset: 0x1C */
569   __IO uint32_t CHANNEL_NUM;                       /**< CHANNEL NUMBER, offset: 0x20 */
570   __IO uint32_t TX_POWER;                          /**< TRANSMIT POWER, offset: 0x24 */
571   __IO uint32_t NTW_ADR_CTRL;                      /**< NETWORK ADDRESS CONTROL, offset: 0x28 */
572   __IO uint32_t NTW_ADR_0;                         /**< NETWORK ADDRESS 0, offset: 0x2C */
573   __IO uint32_t NTW_ADR_1;                         /**< NETWORK ADDRESS 1, offset: 0x30 */
574   __IO uint32_t NTW_ADR_2;                         /**< NETWORK ADDRESS 2, offset: 0x34 */
575   __IO uint32_t NTW_ADR_3;                         /**< NETWORK ADDRESS 3, offset: 0x38 */
576   __IO uint32_t RX_WATERMARK;                      /**< RX WATERMARK, offset: 0x3C */
577   __IO uint32_t DSM_CTRL;                          /**< DSM CONTROL, offset: 0x40 */
578   __I  uint32_t PART_ID;                           /**< PART ID, offset: 0x44 */
579        uint8_t RESERVED_0[184];
580   __IO uint16_t PACKET_BUFFER[64];                 /**< PACKET BUFFER, array offset: 0x100, array step: 0x2 */
581 } ANT_Type;
582 
583 /* ----------------------------------------------------------------------------
584    -- ANT Register Masks
585    ---------------------------------------------------------------------------- */
586 
587 /*!
588  * @addtogroup ANT_Register_Masks ANT Register Masks
589  * @{
590  */
591 
592 /*! @name IRQ_CTRL - IRQ CONTROL */
593 #define ANT_IRQ_CTRL_SEQ_END_IRQ_MASK            (0x1U)
594 #define ANT_IRQ_CTRL_SEQ_END_IRQ_SHIFT           (0U)
595 #define ANT_IRQ_CTRL_SEQ_END_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_SEQ_END_IRQ_SHIFT)) & ANT_IRQ_CTRL_SEQ_END_IRQ_MASK)
596 #define ANT_IRQ_CTRL_TX_IRQ_MASK                 (0x2U)
597 #define ANT_IRQ_CTRL_TX_IRQ_SHIFT                (1U)
598 #define ANT_IRQ_CTRL_TX_IRQ(x)                   (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_TX_IRQ_SHIFT)) & ANT_IRQ_CTRL_TX_IRQ_MASK)
599 #define ANT_IRQ_CTRL_RX_IRQ_MASK                 (0x4U)
600 #define ANT_IRQ_CTRL_RX_IRQ_SHIFT                (2U)
601 #define ANT_IRQ_CTRL_RX_IRQ(x)                   (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_RX_IRQ_SHIFT)) & ANT_IRQ_CTRL_RX_IRQ_MASK)
602 #define ANT_IRQ_CTRL_NTW_ADR_IRQ_MASK            (0x8U)
603 #define ANT_IRQ_CTRL_NTW_ADR_IRQ_SHIFT           (3U)
604 #define ANT_IRQ_CTRL_NTW_ADR_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_NTW_ADR_IRQ_SHIFT)) & ANT_IRQ_CTRL_NTW_ADR_IRQ_MASK)
605 #define ANT_IRQ_CTRL_T1_IRQ_MASK                 (0x10U)
606 #define ANT_IRQ_CTRL_T1_IRQ_SHIFT                (4U)
607 #define ANT_IRQ_CTRL_T1_IRQ(x)                   (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_T1_IRQ_SHIFT)) & ANT_IRQ_CTRL_T1_IRQ_MASK)
608 #define ANT_IRQ_CTRL_T2_IRQ_MASK                 (0x20U)
609 #define ANT_IRQ_CTRL_T2_IRQ_SHIFT                (5U)
610 #define ANT_IRQ_CTRL_T2_IRQ(x)                   (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_T2_IRQ_SHIFT)) & ANT_IRQ_CTRL_T2_IRQ_MASK)
611 #define ANT_IRQ_CTRL_PLL_UNLOCK_IRQ_MASK         (0x40U)
612 #define ANT_IRQ_CTRL_PLL_UNLOCK_IRQ_SHIFT        (6U)
613 #define ANT_IRQ_CTRL_PLL_UNLOCK_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_PLL_UNLOCK_IRQ_SHIFT)) & ANT_IRQ_CTRL_PLL_UNLOCK_IRQ_MASK)
614 #define ANT_IRQ_CTRL_WAKE_IRQ_MASK               (0x80U)
615 #define ANT_IRQ_CTRL_WAKE_IRQ_SHIFT              (7U)
616 #define ANT_IRQ_CTRL_WAKE_IRQ(x)                 (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_WAKE_IRQ_SHIFT)) & ANT_IRQ_CTRL_WAKE_IRQ_MASK)
617 #define ANT_IRQ_CTRL_RX_WATERMARK_IRQ_MASK       (0x100U)
618 #define ANT_IRQ_CTRL_RX_WATERMARK_IRQ_SHIFT      (8U)
619 #define ANT_IRQ_CTRL_RX_WATERMARK_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_RX_WATERMARK_IRQ_SHIFT)) & ANT_IRQ_CTRL_RX_WATERMARK_IRQ_MASK)
620 #define ANT_IRQ_CTRL_TSM_IRQ_MASK                (0x200U)
621 #define ANT_IRQ_CTRL_TSM_IRQ_SHIFT               (9U)
622 #define ANT_IRQ_CTRL_TSM_IRQ(x)                  (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_TSM_IRQ_SHIFT)) & ANT_IRQ_CTRL_TSM_IRQ_MASK)
623 #define ANT_IRQ_CTRL_SEQ_END_IRQ_EN_MASK         (0x10000U)
624 #define ANT_IRQ_CTRL_SEQ_END_IRQ_EN_SHIFT        (16U)
625 #define ANT_IRQ_CTRL_SEQ_END_IRQ_EN(x)           (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_SEQ_END_IRQ_EN_SHIFT)) & ANT_IRQ_CTRL_SEQ_END_IRQ_EN_MASK)
626 #define ANT_IRQ_CTRL_TX_IRQ_EN_MASK              (0x20000U)
627 #define ANT_IRQ_CTRL_TX_IRQ_EN_SHIFT             (17U)
628 #define ANT_IRQ_CTRL_TX_IRQ_EN(x)                (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_TX_IRQ_EN_SHIFT)) & ANT_IRQ_CTRL_TX_IRQ_EN_MASK)
629 #define ANT_IRQ_CTRL_RX_IRQ_EN_MASK              (0x40000U)
630 #define ANT_IRQ_CTRL_RX_IRQ_EN_SHIFT             (18U)
631 #define ANT_IRQ_CTRL_RX_IRQ_EN(x)                (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_RX_IRQ_EN_SHIFT)) & ANT_IRQ_CTRL_RX_IRQ_EN_MASK)
632 #define ANT_IRQ_CTRL_NTW_ADR_IRQ_EN_MASK         (0x80000U)
633 #define ANT_IRQ_CTRL_NTW_ADR_IRQ_EN_SHIFT        (19U)
634 #define ANT_IRQ_CTRL_NTW_ADR_IRQ_EN(x)           (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_NTW_ADR_IRQ_EN_SHIFT)) & ANT_IRQ_CTRL_NTW_ADR_IRQ_EN_MASK)
635 #define ANT_IRQ_CTRL_T1_IRQ_EN_MASK              (0x100000U)
636 #define ANT_IRQ_CTRL_T1_IRQ_EN_SHIFT             (20U)
637 #define ANT_IRQ_CTRL_T1_IRQ_EN(x)                (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_T1_IRQ_EN_SHIFT)) & ANT_IRQ_CTRL_T1_IRQ_EN_MASK)
638 #define ANT_IRQ_CTRL_T2_IRQ_EN_MASK              (0x200000U)
639 #define ANT_IRQ_CTRL_T2_IRQ_EN_SHIFT             (21U)
640 #define ANT_IRQ_CTRL_T2_IRQ_EN(x)                (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_T2_IRQ_EN_SHIFT)) & ANT_IRQ_CTRL_T2_IRQ_EN_MASK)
641 #define ANT_IRQ_CTRL_PLL_UNLOCK_IRQ_EN_MASK      (0x400000U)
642 #define ANT_IRQ_CTRL_PLL_UNLOCK_IRQ_EN_SHIFT     (22U)
643 #define ANT_IRQ_CTRL_PLL_UNLOCK_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_PLL_UNLOCK_IRQ_EN_SHIFT)) & ANT_IRQ_CTRL_PLL_UNLOCK_IRQ_EN_MASK)
644 #define ANT_IRQ_CTRL_WAKE_IRQ_EN_MASK            (0x800000U)
645 #define ANT_IRQ_CTRL_WAKE_IRQ_EN_SHIFT           (23U)
646 #define ANT_IRQ_CTRL_WAKE_IRQ_EN(x)              (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_WAKE_IRQ_EN_SHIFT)) & ANT_IRQ_CTRL_WAKE_IRQ_EN_MASK)
647 #define ANT_IRQ_CTRL_RX_WATERMARK_IRQ_EN_MASK    (0x1000000U)
648 #define ANT_IRQ_CTRL_RX_WATERMARK_IRQ_EN_SHIFT   (24U)
649 #define ANT_IRQ_CTRL_RX_WATERMARK_IRQ_EN(x)      (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_RX_WATERMARK_IRQ_EN_SHIFT)) & ANT_IRQ_CTRL_RX_WATERMARK_IRQ_EN_MASK)
650 #define ANT_IRQ_CTRL_TSM_IRQ_EN_MASK             (0x2000000U)
651 #define ANT_IRQ_CTRL_TSM_IRQ_EN_SHIFT            (25U)
652 #define ANT_IRQ_CTRL_TSM_IRQ_EN(x)               (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_TSM_IRQ_EN_SHIFT)) & ANT_IRQ_CTRL_TSM_IRQ_EN_MASK)
653 #define ANT_IRQ_CTRL_ANT_IRQ_EN_MASK             (0x4000000U)
654 #define ANT_IRQ_CTRL_ANT_IRQ_EN_SHIFT            (26U)
655 #define ANT_IRQ_CTRL_ANT_IRQ_EN(x)               (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_ANT_IRQ_EN_SHIFT)) & ANT_IRQ_CTRL_ANT_IRQ_EN_MASK)
656 #define ANT_IRQ_CTRL_CRC_IGNORE_MASK             (0x8000000U)
657 #define ANT_IRQ_CTRL_CRC_IGNORE_SHIFT            (27U)
658 #define ANT_IRQ_CTRL_CRC_IGNORE(x)               (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_CRC_IGNORE_SHIFT)) & ANT_IRQ_CTRL_CRC_IGNORE_MASK)
659 #define ANT_IRQ_CTRL_CRC_VALID_MASK              (0x80000000U)
660 #define ANT_IRQ_CTRL_CRC_VALID_SHIFT             (31U)
661 #define ANT_IRQ_CTRL_CRC_VALID(x)                (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_CRC_VALID_SHIFT)) & ANT_IRQ_CTRL_CRC_VALID_MASK)
662 
663 /*! @name EVENT_TMR - EVENT TIMER */
664 #define ANT_EVENT_TMR_EVENT_TMR_MASK             (0xFFFFFFU)
665 #define ANT_EVENT_TMR_EVENT_TMR_SHIFT            (0U)
666 #define ANT_EVENT_TMR_EVENT_TMR(x)               (((uint32_t)(((uint32_t)(x)) << ANT_EVENT_TMR_EVENT_TMR_SHIFT)) & ANT_EVENT_TMR_EVENT_TMR_MASK)
667 #define ANT_EVENT_TMR_EVENT_TMR_LD_MASK          (0x1000000U)
668 #define ANT_EVENT_TMR_EVENT_TMR_LD_SHIFT         (24U)
669 #define ANT_EVENT_TMR_EVENT_TMR_LD(x)            (((uint32_t)(((uint32_t)(x)) << ANT_EVENT_TMR_EVENT_TMR_LD_SHIFT)) & ANT_EVENT_TMR_EVENT_TMR_LD_MASK)
670 #define ANT_EVENT_TMR_EVENT_TMR_ADD_MASK         (0x2000000U)
671 #define ANT_EVENT_TMR_EVENT_TMR_ADD_SHIFT        (25U)
672 #define ANT_EVENT_TMR_EVENT_TMR_ADD(x)           (((uint32_t)(((uint32_t)(x)) << ANT_EVENT_TMR_EVENT_TMR_ADD_SHIFT)) & ANT_EVENT_TMR_EVENT_TMR_ADD_MASK)
673 
674 /*! @name T1_CMP - T1 COMPARE */
675 #define ANT_T1_CMP_T1_CMP_MASK                   (0xFFFFFFU)
676 #define ANT_T1_CMP_T1_CMP_SHIFT                  (0U)
677 #define ANT_T1_CMP_T1_CMP(x)                     (((uint32_t)(((uint32_t)(x)) << ANT_T1_CMP_T1_CMP_SHIFT)) & ANT_T1_CMP_T1_CMP_MASK)
678 #define ANT_T1_CMP_T1_CMP_EN_MASK                (0x1000000U)
679 #define ANT_T1_CMP_T1_CMP_EN_SHIFT               (24U)
680 #define ANT_T1_CMP_T1_CMP_EN(x)                  (((uint32_t)(((uint32_t)(x)) << ANT_T1_CMP_T1_CMP_EN_SHIFT)) & ANT_T1_CMP_T1_CMP_EN_MASK)
681 
682 /*! @name T2_CMP - T2 COMPARE */
683 #define ANT_T2_CMP_T2_CMP_MASK                   (0xFFFFFFU)
684 #define ANT_T2_CMP_T2_CMP_SHIFT                  (0U)
685 #define ANT_T2_CMP_T2_CMP(x)                     (((uint32_t)(((uint32_t)(x)) << ANT_T2_CMP_T2_CMP_SHIFT)) & ANT_T2_CMP_T2_CMP_MASK)
686 #define ANT_T2_CMP_T2_CMP_EN_MASK                (0x1000000U)
687 #define ANT_T2_CMP_T2_CMP_EN_SHIFT               (24U)
688 #define ANT_T2_CMP_T2_CMP_EN(x)                  (((uint32_t)(((uint32_t)(x)) << ANT_T2_CMP_T2_CMP_EN_SHIFT)) & ANT_T2_CMP_T2_CMP_EN_MASK)
689 
690 /*! @name TIMESTAMP - TIMESTAMP */
691 #define ANT_TIMESTAMP_TIMESTAMP_MASK             (0xFFFFFFU)
692 #define ANT_TIMESTAMP_TIMESTAMP_SHIFT            (0U)
693 #define ANT_TIMESTAMP_TIMESTAMP(x)               (((uint32_t)(((uint32_t)(x)) << ANT_TIMESTAMP_TIMESTAMP_SHIFT)) & ANT_TIMESTAMP_TIMESTAMP_MASK)
694 
695 /*! @name XCVR_CTRL - TRANSCEIVER CONTROL */
696 #define ANT_XCVR_CTRL_SEQCMD_MASK                (0xFU)
697 #define ANT_XCVR_CTRL_SEQCMD_SHIFT               (0U)
698 #define ANT_XCVR_CTRL_SEQCMD(x)                  (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_CTRL_SEQCMD_SHIFT)) & ANT_XCVR_CTRL_SEQCMD_MASK)
699 #define ANT_XCVR_CTRL_TX_PKT_LENGTH_MASK         (0x3F00U)
700 #define ANT_XCVR_CTRL_TX_PKT_LENGTH_SHIFT        (8U)
701 #define ANT_XCVR_CTRL_TX_PKT_LENGTH(x)           (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_CTRL_TX_PKT_LENGTH_SHIFT)) & ANT_XCVR_CTRL_TX_PKT_LENGTH_MASK)
702 #define ANT_XCVR_CTRL_RX_PKT_LENGTH_MASK         (0x3F0000U)
703 #define ANT_XCVR_CTRL_RX_PKT_LENGTH_SHIFT        (16U)
704 #define ANT_XCVR_CTRL_RX_PKT_LENGTH(x)           (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_CTRL_RX_PKT_LENGTH_SHIFT)) & ANT_XCVR_CTRL_RX_PKT_LENGTH_MASK)
705 #define ANT_XCVR_CTRL_CMDDEC_CS_MASK             (0x7000000U)
706 #define ANT_XCVR_CTRL_CMDDEC_CS_SHIFT            (24U)
707 #define ANT_XCVR_CTRL_CMDDEC_CS(x)               (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_CTRL_CMDDEC_CS_SHIFT)) & ANT_XCVR_CTRL_CMDDEC_CS_MASK)
708 #define ANT_XCVR_CTRL_XCVR_BUSY_MASK             (0x80000000U)
709 #define ANT_XCVR_CTRL_XCVR_BUSY_SHIFT            (31U)
710 #define ANT_XCVR_CTRL_XCVR_BUSY(x)               (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_CTRL_XCVR_BUSY_SHIFT)) & ANT_XCVR_CTRL_XCVR_BUSY_MASK)
711 
712 /*! @name XCVR_STS - TRANSCEIVER STATUS */
713 #define ANT_XCVR_STS_TX_START_T1_PEND_MASK       (0x1U)
714 #define ANT_XCVR_STS_TX_START_T1_PEND_SHIFT      (0U)
715 #define ANT_XCVR_STS_TX_START_T1_PEND(x)         (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_STS_TX_START_T1_PEND_SHIFT)) & ANT_XCVR_STS_TX_START_T1_PEND_MASK)
716 #define ANT_XCVR_STS_TX_START_T2_PEND_MASK       (0x2U)
717 #define ANT_XCVR_STS_TX_START_T2_PEND_SHIFT      (1U)
718 #define ANT_XCVR_STS_TX_START_T2_PEND(x)         (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_STS_TX_START_T2_PEND_SHIFT)) & ANT_XCVR_STS_TX_START_T2_PEND_MASK)
719 #define ANT_XCVR_STS_TX_IN_WARMUP_MASK           (0x4U)
720 #define ANT_XCVR_STS_TX_IN_WARMUP_SHIFT          (2U)
721 #define ANT_XCVR_STS_TX_IN_WARMUP(x)             (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_STS_TX_IN_WARMUP_SHIFT)) & ANT_XCVR_STS_TX_IN_WARMUP_MASK)
722 #define ANT_XCVR_STS_TX_IN_PROGRESS_MASK         (0x8U)
723 #define ANT_XCVR_STS_TX_IN_PROGRESS_SHIFT        (3U)
724 #define ANT_XCVR_STS_TX_IN_PROGRESS(x)           (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_STS_TX_IN_PROGRESS_SHIFT)) & ANT_XCVR_STS_TX_IN_PROGRESS_MASK)
725 #define ANT_XCVR_STS_TX_IN_WARMDN_MASK           (0x10U)
726 #define ANT_XCVR_STS_TX_IN_WARMDN_SHIFT          (4U)
727 #define ANT_XCVR_STS_TX_IN_WARMDN(x)             (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_STS_TX_IN_WARMDN_SHIFT)) & ANT_XCVR_STS_TX_IN_WARMDN_MASK)
728 #define ANT_XCVR_STS_RX_START_T1_PEND_MASK       (0x20U)
729 #define ANT_XCVR_STS_RX_START_T1_PEND_SHIFT      (5U)
730 #define ANT_XCVR_STS_RX_START_T1_PEND(x)         (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_STS_RX_START_T1_PEND_SHIFT)) & ANT_XCVR_STS_RX_START_T1_PEND_MASK)
731 #define ANT_XCVR_STS_RX_START_T2_PEND_MASK       (0x40U)
732 #define ANT_XCVR_STS_RX_START_T2_PEND_SHIFT      (6U)
733 #define ANT_XCVR_STS_RX_START_T2_PEND(x)         (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_STS_RX_START_T2_PEND_SHIFT)) & ANT_XCVR_STS_RX_START_T2_PEND_MASK)
734 #define ANT_XCVR_STS_RX_STOP_T1_PEND_MASK        (0x80U)
735 #define ANT_XCVR_STS_RX_STOP_T1_PEND_SHIFT       (7U)
736 #define ANT_XCVR_STS_RX_STOP_T1_PEND(x)          (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_STS_RX_STOP_T1_PEND_SHIFT)) & ANT_XCVR_STS_RX_STOP_T1_PEND_MASK)
737 #define ANT_XCVR_STS_RX_STOP_T2_PEND_MASK        (0x100U)
738 #define ANT_XCVR_STS_RX_STOP_T2_PEND_SHIFT       (8U)
739 #define ANT_XCVR_STS_RX_STOP_T2_PEND(x)          (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_STS_RX_STOP_T2_PEND_SHIFT)) & ANT_XCVR_STS_RX_STOP_T2_PEND_MASK)
740 #define ANT_XCVR_STS_RX_IN_WARMUP_MASK           (0x200U)
741 #define ANT_XCVR_STS_RX_IN_WARMUP_SHIFT          (9U)
742 #define ANT_XCVR_STS_RX_IN_WARMUP(x)             (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_STS_RX_IN_WARMUP_SHIFT)) & ANT_XCVR_STS_RX_IN_WARMUP_MASK)
743 #define ANT_XCVR_STS_RX_IN_SEARCH_MASK           (0x400U)
744 #define ANT_XCVR_STS_RX_IN_SEARCH_SHIFT          (10U)
745 #define ANT_XCVR_STS_RX_IN_SEARCH(x)             (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_STS_RX_IN_SEARCH_SHIFT)) & ANT_XCVR_STS_RX_IN_SEARCH_MASK)
746 #define ANT_XCVR_STS_RX_IN_PROGRESS_MASK         (0x800U)
747 #define ANT_XCVR_STS_RX_IN_PROGRESS_SHIFT        (11U)
748 #define ANT_XCVR_STS_RX_IN_PROGRESS(x)           (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_STS_RX_IN_PROGRESS_SHIFT)) & ANT_XCVR_STS_RX_IN_PROGRESS_MASK)
749 #define ANT_XCVR_STS_RX_IN_WARMDN_MASK           (0x1000U)
750 #define ANT_XCVR_STS_RX_IN_WARMDN_SHIFT          (12U)
751 #define ANT_XCVR_STS_RX_IN_WARMDN(x)             (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_STS_RX_IN_WARMDN_SHIFT)) & ANT_XCVR_STS_RX_IN_WARMDN_MASK)
752 #define ANT_XCVR_STS_CRC_VALID_MASK              (0x8000U)
753 #define ANT_XCVR_STS_CRC_VALID_SHIFT             (15U)
754 #define ANT_XCVR_STS_CRC_VALID(x)                (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_STS_CRC_VALID_SHIFT)) & ANT_XCVR_STS_CRC_VALID_MASK)
755 #define ANT_XCVR_STS_RSSI_MASK                   (0xFF0000U)
756 #define ANT_XCVR_STS_RSSI_SHIFT                  (16U)
757 #define ANT_XCVR_STS_RSSI(x)                     (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_STS_RSSI_SHIFT)) & ANT_XCVR_STS_RSSI_MASK)
758 
759 /*! @name XCVR_CFG - TRANSCEIVER CONFIGURATION */
760 #define ANT_XCVR_CFG_TX_WHITEN_DIS_MASK          (0x1U)
761 #define ANT_XCVR_CFG_TX_WHITEN_DIS_SHIFT         (0U)
762 #define ANT_XCVR_CFG_TX_WHITEN_DIS(x)            (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_CFG_TX_WHITEN_DIS_SHIFT)) & ANT_XCVR_CFG_TX_WHITEN_DIS_MASK)
763 #define ANT_XCVR_CFG_RX_DEWHITEN_DIS_MASK        (0x2U)
764 #define ANT_XCVR_CFG_RX_DEWHITEN_DIS_SHIFT       (1U)
765 #define ANT_XCVR_CFG_RX_DEWHITEN_DIS(x)          (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_CFG_RX_DEWHITEN_DIS_SHIFT)) & ANT_XCVR_CFG_RX_DEWHITEN_DIS_MASK)
766 #define ANT_XCVR_CFG_SW_CRC_EN_MASK              (0x4U)
767 #define ANT_XCVR_CFG_SW_CRC_EN_SHIFT             (2U)
768 #define ANT_XCVR_CFG_SW_CRC_EN(x)                (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_CFG_SW_CRC_EN_SHIFT)) & ANT_XCVR_CFG_SW_CRC_EN_MASK)
769 #define ANT_XCVR_CFG_PREAMBLE_SZ_MASK            (0x30U)
770 #define ANT_XCVR_CFG_PREAMBLE_SZ_SHIFT           (4U)
771 #define ANT_XCVR_CFG_PREAMBLE_SZ(x)              (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_CFG_PREAMBLE_SZ_SHIFT)) & ANT_XCVR_CFG_PREAMBLE_SZ_MASK)
772 #define ANT_XCVR_CFG_TX_WARMUP_MASK              (0xFF00U)
773 #define ANT_XCVR_CFG_TX_WARMUP_SHIFT             (8U)
774 #define ANT_XCVR_CFG_TX_WARMUP(x)                (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_CFG_TX_WARMUP_SHIFT)) & ANT_XCVR_CFG_TX_WARMUP_MASK)
775 #define ANT_XCVR_CFG_RX_WARMUP_MASK              (0xFF0000U)
776 #define ANT_XCVR_CFG_RX_WARMUP_SHIFT             (16U)
777 #define ANT_XCVR_CFG_RX_WARMUP(x)                (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_CFG_RX_WARMUP_SHIFT)) & ANT_XCVR_CFG_RX_WARMUP_MASK)
778 
779 /*! @name CHANNEL_NUM - CHANNEL NUMBER */
780 #define ANT_CHANNEL_NUM_CHANNEL_NUM_MASK         (0x7FU)
781 #define ANT_CHANNEL_NUM_CHANNEL_NUM_SHIFT        (0U)
782 #define ANT_CHANNEL_NUM_CHANNEL_NUM(x)           (((uint32_t)(((uint32_t)(x)) << ANT_CHANNEL_NUM_CHANNEL_NUM_SHIFT)) & ANT_CHANNEL_NUM_CHANNEL_NUM_MASK)
783 
784 /*! @name TX_POWER - TRANSMIT POWER */
785 #define ANT_TX_POWER_TX_POWER_MASK               (0x3FU)
786 #define ANT_TX_POWER_TX_POWER_SHIFT              (0U)
787 #define ANT_TX_POWER_TX_POWER(x)                 (((uint32_t)(((uint32_t)(x)) << ANT_TX_POWER_TX_POWER_SHIFT)) & ANT_TX_POWER_TX_POWER_MASK)
788 
789 /*! @name NTW_ADR_CTRL - NETWORK ADDRESS CONTROL */
790 #define ANT_NTW_ADR_CTRL_NTW_ADR_EN_MASK         (0xFU)
791 #define ANT_NTW_ADR_CTRL_NTW_ADR_EN_SHIFT        (0U)
792 #define ANT_NTW_ADR_CTRL_NTW_ADR_EN(x)           (((uint32_t)(((uint32_t)(x)) << ANT_NTW_ADR_CTRL_NTW_ADR_EN_SHIFT)) & ANT_NTW_ADR_CTRL_NTW_ADR_EN_MASK)
793 #define ANT_NTW_ADR_CTRL_NTW_ADR_MCH_MASK        (0xF0U)
794 #define ANT_NTW_ADR_CTRL_NTW_ADR_MCH_SHIFT       (4U)
795 #define ANT_NTW_ADR_CTRL_NTW_ADR_MCH(x)          (((uint32_t)(((uint32_t)(x)) << ANT_NTW_ADR_CTRL_NTW_ADR_MCH_SHIFT)) & ANT_NTW_ADR_CTRL_NTW_ADR_MCH_MASK)
796 #define ANT_NTW_ADR_CTRL_NTW_ADR0_SZ_MASK        (0x300U)
797 #define ANT_NTW_ADR_CTRL_NTW_ADR0_SZ_SHIFT       (8U)
798 #define ANT_NTW_ADR_CTRL_NTW_ADR0_SZ(x)          (((uint32_t)(((uint32_t)(x)) << ANT_NTW_ADR_CTRL_NTW_ADR0_SZ_SHIFT)) & ANT_NTW_ADR_CTRL_NTW_ADR0_SZ_MASK)
799 #define ANT_NTW_ADR_CTRL_NTW_ADR1_SZ_MASK        (0xC00U)
800 #define ANT_NTW_ADR_CTRL_NTW_ADR1_SZ_SHIFT       (10U)
801 #define ANT_NTW_ADR_CTRL_NTW_ADR1_SZ(x)          (((uint32_t)(((uint32_t)(x)) << ANT_NTW_ADR_CTRL_NTW_ADR1_SZ_SHIFT)) & ANT_NTW_ADR_CTRL_NTW_ADR1_SZ_MASK)
802 #define ANT_NTW_ADR_CTRL_NTW_ADR2_SZ_MASK        (0x3000U)
803 #define ANT_NTW_ADR_CTRL_NTW_ADR2_SZ_SHIFT       (12U)
804 #define ANT_NTW_ADR_CTRL_NTW_ADR2_SZ(x)          (((uint32_t)(((uint32_t)(x)) << ANT_NTW_ADR_CTRL_NTW_ADR2_SZ_SHIFT)) & ANT_NTW_ADR_CTRL_NTW_ADR2_SZ_MASK)
805 #define ANT_NTW_ADR_CTRL_NTW_ADR3_SZ_MASK        (0xC000U)
806 #define ANT_NTW_ADR_CTRL_NTW_ADR3_SZ_SHIFT       (14U)
807 #define ANT_NTW_ADR_CTRL_NTW_ADR3_SZ(x)          (((uint32_t)(((uint32_t)(x)) << ANT_NTW_ADR_CTRL_NTW_ADR3_SZ_SHIFT)) & ANT_NTW_ADR_CTRL_NTW_ADR3_SZ_MASK)
808 #define ANT_NTW_ADR_CTRL_NTW_ADR_THR0_MASK       (0x70000U)
809 #define ANT_NTW_ADR_CTRL_NTW_ADR_THR0_SHIFT      (16U)
810 #define ANT_NTW_ADR_CTRL_NTW_ADR_THR0(x)         (((uint32_t)(((uint32_t)(x)) << ANT_NTW_ADR_CTRL_NTW_ADR_THR0_SHIFT)) & ANT_NTW_ADR_CTRL_NTW_ADR_THR0_MASK)
811 #define ANT_NTW_ADR_CTRL_NTW_ADR_THR1_MASK       (0x700000U)
812 #define ANT_NTW_ADR_CTRL_NTW_ADR_THR1_SHIFT      (20U)
813 #define ANT_NTW_ADR_CTRL_NTW_ADR_THR1(x)         (((uint32_t)(((uint32_t)(x)) << ANT_NTW_ADR_CTRL_NTW_ADR_THR1_SHIFT)) & ANT_NTW_ADR_CTRL_NTW_ADR_THR1_MASK)
814 #define ANT_NTW_ADR_CTRL_NTW_ADR_THR2_MASK       (0x7000000U)
815 #define ANT_NTW_ADR_CTRL_NTW_ADR_THR2_SHIFT      (24U)
816 #define ANT_NTW_ADR_CTRL_NTW_ADR_THR2(x)         (((uint32_t)(((uint32_t)(x)) << ANT_NTW_ADR_CTRL_NTW_ADR_THR2_SHIFT)) & ANT_NTW_ADR_CTRL_NTW_ADR_THR2_MASK)
817 #define ANT_NTW_ADR_CTRL_NTW_ADR_THR3_MASK       (0x70000000U)
818 #define ANT_NTW_ADR_CTRL_NTW_ADR_THR3_SHIFT      (28U)
819 #define ANT_NTW_ADR_CTRL_NTW_ADR_THR3(x)         (((uint32_t)(((uint32_t)(x)) << ANT_NTW_ADR_CTRL_NTW_ADR_THR3_SHIFT)) & ANT_NTW_ADR_CTRL_NTW_ADR_THR3_MASK)
820 
821 /*! @name NTW_ADR_0 - NETWORK ADDRESS 0 */
822 #define ANT_NTW_ADR_0_NTW_ADR_0_MASK             (0xFFFFFFFFU)
823 #define ANT_NTW_ADR_0_NTW_ADR_0_SHIFT            (0U)
824 #define ANT_NTW_ADR_0_NTW_ADR_0(x)               (((uint32_t)(((uint32_t)(x)) << ANT_NTW_ADR_0_NTW_ADR_0_SHIFT)) & ANT_NTW_ADR_0_NTW_ADR_0_MASK)
825 
826 /*! @name NTW_ADR_1 - NETWORK ADDRESS 1 */
827 #define ANT_NTW_ADR_1_NTW_ADR_1_MASK             (0xFFFFFFFFU)
828 #define ANT_NTW_ADR_1_NTW_ADR_1_SHIFT            (0U)
829 #define ANT_NTW_ADR_1_NTW_ADR_1(x)               (((uint32_t)(((uint32_t)(x)) << ANT_NTW_ADR_1_NTW_ADR_1_SHIFT)) & ANT_NTW_ADR_1_NTW_ADR_1_MASK)
830 
831 /*! @name NTW_ADR_2 - NETWORK ADDRESS 2 */
832 #define ANT_NTW_ADR_2_NTW_ADR_2_MASK             (0xFFFFFFFFU)
833 #define ANT_NTW_ADR_2_NTW_ADR_2_SHIFT            (0U)
834 #define ANT_NTW_ADR_2_NTW_ADR_2(x)               (((uint32_t)(((uint32_t)(x)) << ANT_NTW_ADR_2_NTW_ADR_2_SHIFT)) & ANT_NTW_ADR_2_NTW_ADR_2_MASK)
835 
836 /*! @name NTW_ADR_3 - NETWORK ADDRESS 3 */
837 #define ANT_NTW_ADR_3_NTW_ADR_3_MASK             (0xFFFFFFFFU)
838 #define ANT_NTW_ADR_3_NTW_ADR_3_SHIFT            (0U)
839 #define ANT_NTW_ADR_3_NTW_ADR_3(x)               (((uint32_t)(((uint32_t)(x)) << ANT_NTW_ADR_3_NTW_ADR_3_SHIFT)) & ANT_NTW_ADR_3_NTW_ADR_3_MASK)
840 
841 /*! @name RX_WATERMARK - RX WATERMARK */
842 #define ANT_RX_WATERMARK_RX_WATERMARK_MASK       (0x7FU)
843 #define ANT_RX_WATERMARK_RX_WATERMARK_SHIFT      (0U)
844 #define ANT_RX_WATERMARK_RX_WATERMARK(x)         (((uint32_t)(((uint32_t)(x)) << ANT_RX_WATERMARK_RX_WATERMARK_SHIFT)) & ANT_RX_WATERMARK_RX_WATERMARK_MASK)
845 #define ANT_RX_WATERMARK_BYTE_COUNTER_MASK       (0x7F0000U)
846 #define ANT_RX_WATERMARK_BYTE_COUNTER_SHIFT      (16U)
847 #define ANT_RX_WATERMARK_BYTE_COUNTER(x)         (((uint32_t)(((uint32_t)(x)) << ANT_RX_WATERMARK_BYTE_COUNTER_SHIFT)) & ANT_RX_WATERMARK_BYTE_COUNTER_MASK)
848 
849 /*! @name DSM_CTRL - DSM CONTROL */
850 #define ANT_DSM_CTRL_ANT_SLEEP_EN_MASK           (0x1U)
851 #define ANT_DSM_CTRL_ANT_SLEEP_EN_SHIFT          (0U)
852 #define ANT_DSM_CTRL_ANT_SLEEP_EN(x)             (((uint32_t)(((uint32_t)(x)) << ANT_DSM_CTRL_ANT_SLEEP_EN_SHIFT)) & ANT_DSM_CTRL_ANT_SLEEP_EN_MASK)
853 
854 /*! @name PART_ID - PART ID */
855 #define ANT_PART_ID_PART_ID_MASK                 (0xFFU)
856 #define ANT_PART_ID_PART_ID_SHIFT                (0U)
857 #define ANT_PART_ID_PART_ID(x)                   (((uint32_t)(((uint32_t)(x)) << ANT_PART_ID_PART_ID_SHIFT)) & ANT_PART_ID_PART_ID_MASK)
858 
859 /*! @name PACKET_BUFFER - PACKET BUFFER */
860 #define ANT_PACKET_BUFFER_PACKET_BUFFER_MASK     (0xFFFFU)
861 #define ANT_PACKET_BUFFER_PACKET_BUFFER_SHIFT    (0U)
862 #define ANT_PACKET_BUFFER_PACKET_BUFFER(x)       (((uint16_t)(((uint16_t)(x)) << ANT_PACKET_BUFFER_PACKET_BUFFER_SHIFT)) & ANT_PACKET_BUFFER_PACKET_BUFFER_MASK)
863 
864 /* The count of ANT_PACKET_BUFFER */
865 #define ANT_PACKET_BUFFER_COUNT                  (64U)
866 
867 
868 /*!
869  * @}
870  */ /* end of group ANT_Register_Masks */
871 
872 
873 /* ANT - Peripheral instance base addresses */
874 /** Peripheral ANT base address */
875 #define ANT_BASE                                 (0x4005E000u)
876 /** Peripheral ANT base pointer */
877 #define ANT                                      ((ANT_Type *)ANT_BASE)
878 /** Array initializer of ANT peripheral base addresses */
879 #define ANT_BASE_ADDRS                           { ANT_BASE }
880 /** Array initializer of ANT peripheral base pointers */
881 #define ANT_BASE_PTRS                            { ANT }
882 
883 /*!
884  * @}
885  */ /* end of group ANT_Peripheral_Access_Layer */
886 
887 
888 /* ----------------------------------------------------------------------------
889    -- BTLE_RF Peripheral Access Layer
890    ---------------------------------------------------------------------------- */
891 
892 /*!
893  * @addtogroup BTLE_RF_Peripheral_Access_Layer BTLE_RF Peripheral Access Layer
894  * @{
895  */
896 
897 /** BTLE_RF - Register Layout Typedef */
898 typedef struct {
899        uint8_t RESERVED_0[1536];
900   __I  uint16_t BLE_PART_ID;                       /**< BLUETOOTH LOW ENERGY PART ID, offset: 0x600 */
901        uint8_t RESERVED_1[2];
902   __I  uint16_t DSM_STATUS;                        /**< BLE DSM STATUS, offset: 0x604 */
903        uint8_t RESERVED_2[2];
904   __IO uint16_t MISC_CTRL;                         /**< BLUETOOTH LOW ENERGY MISCELLANEOUS CONTROL, offset: 0x608 */
905 } BTLE_RF_Type;
906 
907 /* ----------------------------------------------------------------------------
908    -- BTLE_RF Register Masks
909    ---------------------------------------------------------------------------- */
910 
911 /*!
912  * @addtogroup BTLE_RF_Register_Masks BTLE_RF Register Masks
913  * @{
914  */
915 
916 /*! @name BLE_PART_ID - BLUETOOTH LOW ENERGY PART ID */
917 #define BTLE_RF_BLE_PART_ID_BLE_PART_ID_MASK     (0xFFFFU)
918 #define BTLE_RF_BLE_PART_ID_BLE_PART_ID_SHIFT    (0U)
919 #define BTLE_RF_BLE_PART_ID_BLE_PART_ID(x)       (((uint16_t)(((uint16_t)(x)) << BTLE_RF_BLE_PART_ID_BLE_PART_ID_SHIFT)) & BTLE_RF_BLE_PART_ID_BLE_PART_ID_MASK)
920 
921 /*! @name DSM_STATUS - BLE DSM STATUS */
922 #define BTLE_RF_DSM_STATUS_ORF_SYSCLK_REQ_MASK   (0x1U)
923 #define BTLE_RF_DSM_STATUS_ORF_SYSCLK_REQ_SHIFT  (0U)
924 #define BTLE_RF_DSM_STATUS_ORF_SYSCLK_REQ(x)     (((uint16_t)(((uint16_t)(x)) << BTLE_RF_DSM_STATUS_ORF_SYSCLK_REQ_SHIFT)) & BTLE_RF_DSM_STATUS_ORF_SYSCLK_REQ_MASK)
925 #define BTLE_RF_DSM_STATUS_RIF_LL_ACTIVE_MASK    (0x2U)
926 #define BTLE_RF_DSM_STATUS_RIF_LL_ACTIVE_SHIFT   (1U)
927 #define BTLE_RF_DSM_STATUS_RIF_LL_ACTIVE(x)      (((uint16_t)(((uint16_t)(x)) << BTLE_RF_DSM_STATUS_RIF_LL_ACTIVE_SHIFT)) & BTLE_RF_DSM_STATUS_RIF_LL_ACTIVE_MASK)
928 #define BTLE_RF_DSM_STATUS_XCVR_BUSY_MASK        (0x4U)
929 #define BTLE_RF_DSM_STATUS_XCVR_BUSY_SHIFT       (2U)
930 #define BTLE_RF_DSM_STATUS_XCVR_BUSY(x)          (((uint16_t)(((uint16_t)(x)) << BTLE_RF_DSM_STATUS_XCVR_BUSY_SHIFT)) & BTLE_RF_DSM_STATUS_XCVR_BUSY_MASK)
931 
932 /*! @name MISC_CTRL - BLUETOOTH LOW ENERGY MISCELLANEOUS CONTROL */
933 #define BTLE_RF_MISC_CTRL_TSM_INTR_EN_MASK       (0x2U)
934 #define BTLE_RF_MISC_CTRL_TSM_INTR_EN_SHIFT      (1U)
935 #define BTLE_RF_MISC_CTRL_TSM_INTR_EN(x)         (((uint16_t)(((uint16_t)(x)) << BTLE_RF_MISC_CTRL_TSM_INTR_EN_SHIFT)) & BTLE_RF_MISC_CTRL_TSM_INTR_EN_MASK)
936 
937 
938 /*!
939  * @}
940  */ /* end of group BTLE_RF_Register_Masks */
941 
942 
943 /* BTLE_RF - Peripheral instance base addresses */
944 /** Peripheral BTLE_RF base address */
945 #define BTLE_RF_BASE                             (0x4005B000u)
946 /** Peripheral BTLE_RF base pointer */
947 #define BTLE_RF                                  ((BTLE_RF_Type *)BTLE_RF_BASE)
948 /** Array initializer of BTLE_RF peripheral base addresses */
949 #define BTLE_RF_BASE_ADDRS                       { BTLE_RF_BASE }
950 /** Array initializer of BTLE_RF peripheral base pointers */
951 #define BTLE_RF_BASE_PTRS                        { BTLE_RF }
952 
953 /*!
954  * @}
955  */ /* end of group BTLE_RF_Peripheral_Access_Layer */
956 
957 
958 /* ----------------------------------------------------------------------------
959    -- CMP Peripheral Access Layer
960    ---------------------------------------------------------------------------- */
961 
962 /*!
963  * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
964  * @{
965  */
966 
967 /** CMP - Register Layout Typedef */
968 typedef struct {
969   __IO uint8_t CR0;                                /**< CMP Control Register 0, offset: 0x0 */
970   __IO uint8_t CR1;                                /**< CMP Control Register 1, offset: 0x1 */
971   __IO uint8_t FPR;                                /**< CMP Filter Period Register, offset: 0x2 */
972   __IO uint8_t SCR;                                /**< CMP Status and Control Register, offset: 0x3 */
973   __IO uint8_t DACCR;                              /**< DAC Control Register, offset: 0x4 */
974   __IO uint8_t MUXCR;                              /**< MUX Control Register, offset: 0x5 */
975 } CMP_Type;
976 
977 /* ----------------------------------------------------------------------------
978    -- CMP Register Masks
979    ---------------------------------------------------------------------------- */
980 
981 /*!
982  * @addtogroup CMP_Register_Masks CMP Register Masks
983  * @{
984  */
985 
986 /*! @name CR0 - CMP Control Register 0 */
987 #define CMP_CR0_HYSTCTR_MASK                     (0x3U)
988 #define CMP_CR0_HYSTCTR_SHIFT                    (0U)
989 #define CMP_CR0_HYSTCTR(x)                       (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
990 #define CMP_CR0_FILTER_CNT_MASK                  (0x70U)
991 #define CMP_CR0_FILTER_CNT_SHIFT                 (4U)
992 #define CMP_CR0_FILTER_CNT(x)                    (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
993 
994 /*! @name CR1 - CMP Control Register 1 */
995 #define CMP_CR1_EN_MASK                          (0x1U)
996 #define CMP_CR1_EN_SHIFT                         (0U)
997 #define CMP_CR1_EN(x)                            (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)
998 #define CMP_CR1_OPE_MASK                         (0x2U)
999 #define CMP_CR1_OPE_SHIFT                        (1U)
1000 #define CMP_CR1_OPE(x)                           (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
1001 #define CMP_CR1_COS_MASK                         (0x4U)
1002 #define CMP_CR1_COS_SHIFT                        (2U)
1003 #define CMP_CR1_COS(x)                           (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)
1004 #define CMP_CR1_INV_MASK                         (0x8U)
1005 #define CMP_CR1_INV_SHIFT                        (3U)
1006 #define CMP_CR1_INV(x)                           (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
1007 #define CMP_CR1_PMODE_MASK                       (0x10U)
1008 #define CMP_CR1_PMODE_SHIFT                      (4U)
1009 #define CMP_CR1_PMODE(x)                         (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
1010 #define CMP_CR1_TRIGM_MASK                       (0x20U)
1011 #define CMP_CR1_TRIGM_SHIFT                      (5U)
1012 #define CMP_CR1_TRIGM(x)                         (((uint8_t)(((uint8_t)(x)) << CMP_CR1_TRIGM_SHIFT)) & CMP_CR1_TRIGM_MASK)
1013 #define CMP_CR1_WE_MASK                          (0x40U)
1014 #define CMP_CR1_WE_SHIFT                         (6U)
1015 #define CMP_CR1_WE(x)                            (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)
1016 #define CMP_CR1_SE_MASK                          (0x80U)
1017 #define CMP_CR1_SE_SHIFT                         (7U)
1018 #define CMP_CR1_SE(x)                            (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)
1019 
1020 /*! @name FPR - CMP Filter Period Register */
1021 #define CMP_FPR_FILT_PER_MASK                    (0xFFU)
1022 #define CMP_FPR_FILT_PER_SHIFT                   (0U)
1023 #define CMP_FPR_FILT_PER(x)                      (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)
1024 
1025 /*! @name SCR - CMP Status and Control Register */
1026 #define CMP_SCR_COUT_MASK                        (0x1U)
1027 #define CMP_SCR_COUT_SHIFT                       (0U)
1028 #define CMP_SCR_COUT(x)                          (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)
1029 #define CMP_SCR_CFF_MASK                         (0x2U)
1030 #define CMP_SCR_CFF_SHIFT                        (1U)
1031 #define CMP_SCR_CFF(x)                           (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
1032 #define CMP_SCR_CFR_MASK                         (0x4U)
1033 #define CMP_SCR_CFR_SHIFT                        (2U)
1034 #define CMP_SCR_CFR(x)                           (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
1035 #define CMP_SCR_IEF_MASK                         (0x8U)
1036 #define CMP_SCR_IEF_SHIFT                        (3U)
1037 #define CMP_SCR_IEF(x)                           (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)
1038 #define CMP_SCR_IER_MASK                         (0x10U)
1039 #define CMP_SCR_IER_SHIFT                        (4U)
1040 #define CMP_SCR_IER(x)                           (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)
1041 #define CMP_SCR_DMAEN_MASK                       (0x40U)
1042 #define CMP_SCR_DMAEN_SHIFT                      (6U)
1043 #define CMP_SCR_DMAEN(x)                         (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)
1044 
1045 /*! @name DACCR - DAC Control Register */
1046 #define CMP_DACCR_VOSEL_MASK                     (0x3FU)
1047 #define CMP_DACCR_VOSEL_SHIFT                    (0U)
1048 #define CMP_DACCR_VOSEL(x)                       (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
1049 #define CMP_DACCR_VRSEL_MASK                     (0x40U)
1050 #define CMP_DACCR_VRSEL_SHIFT                    (6U)
1051 #define CMP_DACCR_VRSEL(x)                       (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
1052 #define CMP_DACCR_DACEN_MASK                     (0x80U)
1053 #define CMP_DACCR_DACEN_SHIFT                    (7U)
1054 #define CMP_DACCR_DACEN(x)                       (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
1055 
1056 /*! @name MUXCR - MUX Control Register */
1057 #define CMP_MUXCR_MSEL_MASK                      (0x7U)
1058 #define CMP_MUXCR_MSEL_SHIFT                     (0U)
1059 #define CMP_MUXCR_MSEL(x)                        (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
1060 #define CMP_MUXCR_PSEL_MASK                      (0x38U)
1061 #define CMP_MUXCR_PSEL_SHIFT                     (3U)
1062 #define CMP_MUXCR_PSEL(x)                        (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)
1063 #define CMP_MUXCR_PSTM_MASK                      (0x80U)
1064 #define CMP_MUXCR_PSTM_SHIFT                     (7U)
1065 #define CMP_MUXCR_PSTM(x)                        (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSTM_SHIFT)) & CMP_MUXCR_PSTM_MASK)
1066 
1067 
1068 /*!
1069  * @}
1070  */ /* end of group CMP_Register_Masks */
1071 
1072 
1073 /* CMP - Peripheral instance base addresses */
1074 /** Peripheral CMP0 base address */
1075 #define CMP0_BASE                                (0x40073000u)
1076 /** Peripheral CMP0 base pointer */
1077 #define CMP0                                     ((CMP_Type *)CMP0_BASE)
1078 /** Array initializer of CMP peripheral base addresses */
1079 #define CMP_BASE_ADDRS                           { CMP0_BASE }
1080 /** Array initializer of CMP peripheral base pointers */
1081 #define CMP_BASE_PTRS                            { CMP0 }
1082 /** Interrupt vectors for the CMP peripheral type */
1083 #define CMP_IRQS                                 { CMP0_IRQn }
1084 
1085 /*!
1086  * @}
1087  */ /* end of group CMP_Peripheral_Access_Layer */
1088 
1089 
1090 /* ----------------------------------------------------------------------------
1091    -- CMT Peripheral Access Layer
1092    ---------------------------------------------------------------------------- */
1093 
1094 /*!
1095  * @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer
1096  * @{
1097  */
1098 
1099 /** CMT - Register Layout Typedef */
1100 typedef struct {
1101   __IO uint8_t CGH1;                               /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */
1102   __IO uint8_t CGL1;                               /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */
1103   __IO uint8_t CGH2;                               /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */
1104   __IO uint8_t CGL2;                               /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */
1105   __IO uint8_t OC;                                 /**< CMT Output Control Register, offset: 0x4 */
1106   __IO uint8_t MSC;                                /**< CMT Modulator Status and Control Register, offset: 0x5 */
1107   __IO uint8_t CMD1;                               /**< CMT Modulator Data Register Mark High, offset: 0x6 */
1108   __IO uint8_t CMD2;                               /**< CMT Modulator Data Register Mark Low, offset: 0x7 */
1109   __IO uint8_t CMD3;                               /**< CMT Modulator Data Register Space High, offset: 0x8 */
1110   __IO uint8_t CMD4;                               /**< CMT Modulator Data Register Space Low, offset: 0x9 */
1111   __IO uint8_t PPS;                                /**< CMT Primary Prescaler Register, offset: 0xA */
1112   __IO uint8_t DMA;                                /**< CMT Direct Memory Access Register, offset: 0xB */
1113 } CMT_Type;
1114 
1115 /* ----------------------------------------------------------------------------
1116    -- CMT Register Masks
1117    ---------------------------------------------------------------------------- */
1118 
1119 /*!
1120  * @addtogroup CMT_Register_Masks CMT Register Masks
1121  * @{
1122  */
1123 
1124 /*! @name CGH1 - CMT Carrier Generator High Data Register 1 */
1125 #define CMT_CGH1_PH_MASK                         (0xFFU)
1126 #define CMT_CGH1_PH_SHIFT                        (0U)
1127 #define CMT_CGH1_PH(x)                           (((uint8_t)(((uint8_t)(x)) << CMT_CGH1_PH_SHIFT)) & CMT_CGH1_PH_MASK)
1128 
1129 /*! @name CGL1 - CMT Carrier Generator Low Data Register 1 */
1130 #define CMT_CGL1_PL_MASK                         (0xFFU)
1131 #define CMT_CGL1_PL_SHIFT                        (0U)
1132 #define CMT_CGL1_PL(x)                           (((uint8_t)(((uint8_t)(x)) << CMT_CGL1_PL_SHIFT)) & CMT_CGL1_PL_MASK)
1133 
1134 /*! @name CGH2 - CMT Carrier Generator High Data Register 2 */
1135 #define CMT_CGH2_SH_MASK                         (0xFFU)
1136 #define CMT_CGH2_SH_SHIFT                        (0U)
1137 #define CMT_CGH2_SH(x)                           (((uint8_t)(((uint8_t)(x)) << CMT_CGH2_SH_SHIFT)) & CMT_CGH2_SH_MASK)
1138 
1139 /*! @name CGL2 - CMT Carrier Generator Low Data Register 2 */
1140 #define CMT_CGL2_SL_MASK                         (0xFFU)
1141 #define CMT_CGL2_SL_SHIFT                        (0U)
1142 #define CMT_CGL2_SL(x)                           (((uint8_t)(((uint8_t)(x)) << CMT_CGL2_SL_SHIFT)) & CMT_CGL2_SL_MASK)
1143 
1144 /*! @name OC - CMT Output Control Register */
1145 #define CMT_OC_IROPEN_MASK                       (0x20U)
1146 #define CMT_OC_IROPEN_SHIFT                      (5U)
1147 #define CMT_OC_IROPEN(x)                         (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROPEN_SHIFT)) & CMT_OC_IROPEN_MASK)
1148 #define CMT_OC_CMTPOL_MASK                       (0x40U)
1149 #define CMT_OC_CMTPOL_SHIFT                      (6U)
1150 #define CMT_OC_CMTPOL(x)                         (((uint8_t)(((uint8_t)(x)) << CMT_OC_CMTPOL_SHIFT)) & CMT_OC_CMTPOL_MASK)
1151 #define CMT_OC_IROL_MASK                         (0x80U)
1152 #define CMT_OC_IROL_SHIFT                        (7U)
1153 #define CMT_OC_IROL(x)                           (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROL_SHIFT)) & CMT_OC_IROL_MASK)
1154 
1155 /*! @name MSC - CMT Modulator Status and Control Register */
1156 #define CMT_MSC_MCGEN_MASK                       (0x1U)
1157 #define CMT_MSC_MCGEN_SHIFT                      (0U)
1158 #define CMT_MSC_MCGEN(x)                         (((uint8_t)(((uint8_t)(x)) << CMT_MSC_MCGEN_SHIFT)) & CMT_MSC_MCGEN_MASK)
1159 #define CMT_MSC_EOCIE_MASK                       (0x2U)
1160 #define CMT_MSC_EOCIE_SHIFT                      (1U)
1161 #define CMT_MSC_EOCIE(x)                         (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCIE_SHIFT)) & CMT_MSC_EOCIE_MASK)
1162 #define CMT_MSC_FSK_MASK                         (0x4U)
1163 #define CMT_MSC_FSK_SHIFT                        (2U)
1164 #define CMT_MSC_FSK(x)                           (((uint8_t)(((uint8_t)(x)) << CMT_MSC_FSK_SHIFT)) & CMT_MSC_FSK_MASK)
1165 #define CMT_MSC_BASE_MASK                        (0x8U)
1166 #define CMT_MSC_BASE_SHIFT                       (3U)
1167 #define CMT_MSC_BASE(x)                          (((uint8_t)(((uint8_t)(x)) << CMT_MSC_BASE_SHIFT)) & CMT_MSC_BASE_MASK)
1168 #define CMT_MSC_EXSPC_MASK                       (0x10U)
1169 #define CMT_MSC_EXSPC_SHIFT                      (4U)
1170 #define CMT_MSC_EXSPC(x)                         (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EXSPC_SHIFT)) & CMT_MSC_EXSPC_MASK)
1171 #define CMT_MSC_CMTDIV_MASK                      (0x60U)
1172 #define CMT_MSC_CMTDIV_SHIFT                     (5U)
1173 #define CMT_MSC_CMTDIV(x)                        (((uint8_t)(((uint8_t)(x)) << CMT_MSC_CMTDIV_SHIFT)) & CMT_MSC_CMTDIV_MASK)
1174 #define CMT_MSC_EOCF_MASK                        (0x80U)
1175 #define CMT_MSC_EOCF_SHIFT                       (7U)
1176 #define CMT_MSC_EOCF(x)                          (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCF_SHIFT)) & CMT_MSC_EOCF_MASK)
1177 
1178 /*! @name CMD1 - CMT Modulator Data Register Mark High */
1179 #define CMT_CMD1_MB_MASK                         (0xFFU)
1180 #define CMT_CMD1_MB_SHIFT                        (0U)
1181 #define CMT_CMD1_MB(x)                           (((uint8_t)(((uint8_t)(x)) << CMT_CMD1_MB_SHIFT)) & CMT_CMD1_MB_MASK)
1182 
1183 /*! @name CMD2 - CMT Modulator Data Register Mark Low */
1184 #define CMT_CMD2_MB_MASK                         (0xFFU)
1185 #define CMT_CMD2_MB_SHIFT                        (0U)
1186 #define CMT_CMD2_MB(x)                           (((uint8_t)(((uint8_t)(x)) << CMT_CMD2_MB_SHIFT)) & CMT_CMD2_MB_MASK)
1187 
1188 /*! @name CMD3 - CMT Modulator Data Register Space High */
1189 #define CMT_CMD3_SB_MASK                         (0xFFU)
1190 #define CMT_CMD3_SB_SHIFT                        (0U)
1191 #define CMT_CMD3_SB(x)                           (((uint8_t)(((uint8_t)(x)) << CMT_CMD3_SB_SHIFT)) & CMT_CMD3_SB_MASK)
1192 
1193 /*! @name CMD4 - CMT Modulator Data Register Space Low */
1194 #define CMT_CMD4_SB_MASK                         (0xFFU)
1195 #define CMT_CMD4_SB_SHIFT                        (0U)
1196 #define CMT_CMD4_SB(x)                           (((uint8_t)(((uint8_t)(x)) << CMT_CMD4_SB_SHIFT)) & CMT_CMD4_SB_MASK)
1197 
1198 /*! @name PPS - CMT Primary Prescaler Register */
1199 #define CMT_PPS_PPSDIV_MASK                      (0xFU)
1200 #define CMT_PPS_PPSDIV_SHIFT                     (0U)
1201 #define CMT_PPS_PPSDIV(x)                        (((uint8_t)(((uint8_t)(x)) << CMT_PPS_PPSDIV_SHIFT)) & CMT_PPS_PPSDIV_MASK)
1202 
1203 /*! @name DMA - CMT Direct Memory Access Register */
1204 #define CMT_DMA_DMA_MASK                         (0x1U)
1205 #define CMT_DMA_DMA_SHIFT                        (0U)
1206 #define CMT_DMA_DMA(x)                           (((uint8_t)(((uint8_t)(x)) << CMT_DMA_DMA_SHIFT)) & CMT_DMA_DMA_MASK)
1207 
1208 
1209 /*!
1210  * @}
1211  */ /* end of group CMT_Register_Masks */
1212 
1213 
1214 /* CMT - Peripheral instance base addresses */
1215 /** Peripheral CMT base address */
1216 #define CMT_BASE                                 (0x40062000u)
1217 /** Peripheral CMT base pointer */
1218 #define CMT                                      ((CMT_Type *)CMT_BASE)
1219 /** Array initializer of CMT peripheral base addresses */
1220 #define CMT_BASE_ADDRS                           { CMT_BASE }
1221 /** Array initializer of CMT peripheral base pointers */
1222 #define CMT_BASE_PTRS                            { CMT }
1223 /** Interrupt vectors for the CMT peripheral type */
1224 #define CMT_IRQS                                 { CMT_IRQn }
1225 
1226 /*!
1227  * @}
1228  */ /* end of group CMT_Peripheral_Access_Layer */
1229 
1230 
1231 /* ----------------------------------------------------------------------------
1232    -- DAC Peripheral Access Layer
1233    ---------------------------------------------------------------------------- */
1234 
1235 /*!
1236  * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
1237  * @{
1238  */
1239 
1240 /** DAC - Register Layout Typedef */
1241 typedef struct {
1242   struct {                                         /* offset: 0x0, array step: 0x2 */
1243     __IO uint8_t DATL;                               /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
1244     __IO uint8_t DATH;                               /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
1245   } DAT[2];
1246        uint8_t RESERVED_0[28];
1247   __IO uint8_t SR;                                 /**< DAC Status Register, offset: 0x20 */
1248   __IO uint8_t C0;                                 /**< DAC Control Register, offset: 0x21 */
1249   __IO uint8_t C1;                                 /**< DAC Control Register 1, offset: 0x22 */
1250   __IO uint8_t C2;                                 /**< DAC Control Register 2, offset: 0x23 */
1251 } DAC_Type;
1252 
1253 /* ----------------------------------------------------------------------------
1254    -- DAC Register Masks
1255    ---------------------------------------------------------------------------- */
1256 
1257 /*!
1258  * @addtogroup DAC_Register_Masks DAC Register Masks
1259  * @{
1260  */
1261 
1262 /*! @name DATL - DAC Data Low Register */
1263 #define DAC_DATL_DATA0_MASK                      (0xFFU)
1264 #define DAC_DATL_DATA0_SHIFT                     (0U)
1265 #define DAC_DATL_DATA0(x)                        (((uint8_t)(((uint8_t)(x)) << DAC_DATL_DATA0_SHIFT)) & DAC_DATL_DATA0_MASK)
1266 
1267 /* The count of DAC_DATL */
1268 #define DAC_DATL_COUNT                           (2U)
1269 
1270 /*! @name DATH - DAC Data High Register */
1271 #define DAC_DATH_DATA1_MASK                      (0xFU)
1272 #define DAC_DATH_DATA1_SHIFT                     (0U)
1273 #define DAC_DATH_DATA1(x)                        (((uint8_t)(((uint8_t)(x)) << DAC_DATH_DATA1_SHIFT)) & DAC_DATH_DATA1_MASK)
1274 
1275 /* The count of DAC_DATH */
1276 #define DAC_DATH_COUNT                           (2U)
1277 
1278 /*! @name SR - DAC Status Register */
1279 #define DAC_SR_DACBFRPBF_MASK                    (0x1U)
1280 #define DAC_SR_DACBFRPBF_SHIFT                   (0U)
1281 #define DAC_SR_DACBFRPBF(x)                      (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPBF_SHIFT)) & DAC_SR_DACBFRPBF_MASK)
1282 #define DAC_SR_DACBFRPTF_MASK                    (0x2U)
1283 #define DAC_SR_DACBFRPTF_SHIFT                   (1U)
1284 #define DAC_SR_DACBFRPTF(x)                      (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPTF_SHIFT)) & DAC_SR_DACBFRPTF_MASK)
1285 #define DAC_SR_DACBFWMF_MASK                     (0x4U)
1286 #define DAC_SR_DACBFWMF_SHIFT                    (2U)
1287 #define DAC_SR_DACBFWMF(x)                       (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFWMF_SHIFT)) & DAC_SR_DACBFWMF_MASK)
1288 
1289 /*! @name C0 - DAC Control Register */
1290 #define DAC_C0_DACBBIEN_MASK                     (0x1U)
1291 #define DAC_C0_DACBBIEN_SHIFT                    (0U)
1292 #define DAC_C0_DACBBIEN(x)                       (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBBIEN_SHIFT)) & DAC_C0_DACBBIEN_MASK)
1293 #define DAC_C0_DACBTIEN_MASK                     (0x2U)
1294 #define DAC_C0_DACBTIEN_SHIFT                    (1U)
1295 #define DAC_C0_DACBTIEN(x)                       (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBTIEN_SHIFT)) & DAC_C0_DACBTIEN_MASK)
1296 #define DAC_C0_DACBWIEN_MASK                     (0x4U)
1297 #define DAC_C0_DACBWIEN_SHIFT                    (2U)
1298 #define DAC_C0_DACBWIEN(x)                       (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBWIEN_SHIFT)) & DAC_C0_DACBWIEN_MASK)
1299 #define DAC_C0_LPEN_MASK                         (0x8U)
1300 #define DAC_C0_LPEN_SHIFT                        (3U)
1301 #define DAC_C0_LPEN(x)                           (((uint8_t)(((uint8_t)(x)) << DAC_C0_LPEN_SHIFT)) & DAC_C0_LPEN_MASK)
1302 #define DAC_C0_DACSWTRG_MASK                     (0x10U)
1303 #define DAC_C0_DACSWTRG_SHIFT                    (4U)
1304 #define DAC_C0_DACSWTRG(x)                       (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACSWTRG_SHIFT)) & DAC_C0_DACSWTRG_MASK)
1305 #define DAC_C0_DACTRGSEL_MASK                    (0x20U)
1306 #define DAC_C0_DACTRGSEL_SHIFT                   (5U)
1307 #define DAC_C0_DACTRGSEL(x)                      (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACTRGSEL_SHIFT)) & DAC_C0_DACTRGSEL_MASK)
1308 #define DAC_C0_DACRFS_MASK                       (0x40U)
1309 #define DAC_C0_DACRFS_SHIFT                      (6U)
1310 #define DAC_C0_DACRFS(x)                         (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACRFS_SHIFT)) & DAC_C0_DACRFS_MASK)
1311 #define DAC_C0_DACEN_MASK                        (0x80U)
1312 #define DAC_C0_DACEN_SHIFT                       (7U)
1313 #define DAC_C0_DACEN(x)                          (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACEN_SHIFT)) & DAC_C0_DACEN_MASK)
1314 
1315 /*! @name C1 - DAC Control Register 1 */
1316 #define DAC_C1_DACBFEN_MASK                      (0x1U)
1317 #define DAC_C1_DACBFEN_SHIFT                     (0U)
1318 #define DAC_C1_DACBFEN(x)                        (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFEN_SHIFT)) & DAC_C1_DACBFEN_MASK)
1319 #define DAC_C1_DACBFMD_MASK                      (0x4U)
1320 #define DAC_C1_DACBFMD_SHIFT                     (2U)
1321 #define DAC_C1_DACBFMD(x)                        (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFMD_SHIFT)) & DAC_C1_DACBFMD_MASK)
1322 #define DAC_C1_DACBFWM_MASK                      (0x18U)
1323 #define DAC_C1_DACBFWM_SHIFT                     (3U)
1324 #define DAC_C1_DACBFWM(x)                        (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFWM_SHIFT)) & DAC_C1_DACBFWM_MASK)
1325 #define DAC_C1_DMAEN_MASK                        (0x80U)
1326 #define DAC_C1_DMAEN_SHIFT                       (7U)
1327 #define DAC_C1_DMAEN(x)                          (((uint8_t)(((uint8_t)(x)) << DAC_C1_DMAEN_SHIFT)) & DAC_C1_DMAEN_MASK)
1328 
1329 /*! @name C2 - DAC Control Register 2 */
1330 #define DAC_C2_DACBFUP_MASK                      (0x1U)
1331 #define DAC_C2_DACBFUP_SHIFT                     (0U)
1332 #define DAC_C2_DACBFUP(x)                        (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFUP_SHIFT)) & DAC_C2_DACBFUP_MASK)
1333 #define DAC_C2_DACBFRP_MASK                      (0x10U)
1334 #define DAC_C2_DACBFRP_SHIFT                     (4U)
1335 #define DAC_C2_DACBFRP(x)                        (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFRP_SHIFT)) & DAC_C2_DACBFRP_MASK)
1336 
1337 
1338 /*!
1339  * @}
1340  */ /* end of group DAC_Register_Masks */
1341 
1342 
1343 /* DAC - Peripheral instance base addresses */
1344 /** Peripheral DAC0 base address */
1345 #define DAC0_BASE                                (0x4003F000u)
1346 /** Peripheral DAC0 base pointer */
1347 #define DAC0                                     ((DAC_Type *)DAC0_BASE)
1348 /** Array initializer of DAC peripheral base addresses */
1349 #define DAC_BASE_ADDRS                           { DAC0_BASE }
1350 /** Array initializer of DAC peripheral base pointers */
1351 #define DAC_BASE_PTRS                            { DAC0 }
1352 /** Interrupt vectors for the DAC peripheral type */
1353 #define DAC_IRQS                                 { DAC0_IRQn }
1354 
1355 /*!
1356  * @}
1357  */ /* end of group DAC_Peripheral_Access_Layer */
1358 
1359 
1360 /* ----------------------------------------------------------------------------
1361    -- DCDC Peripheral Access Layer
1362    ---------------------------------------------------------------------------- */
1363 
1364 /*!
1365  * @addtogroup DCDC_Peripheral_Access_Layer DCDC Peripheral Access Layer
1366  * @{
1367  */
1368 
1369 /** DCDC - Register Layout Typedef */
1370 typedef struct {
1371   __IO uint32_t REG0;                              /**< DCDC REGISTER 0, offset: 0x0 */
1372   __IO uint32_t REG1;                              /**< DCDC REGISTER 1, offset: 0x4 */
1373   __IO uint32_t REG2;                              /**< DCDC REGISTER 2, offset: 0x8 */
1374   __IO uint32_t REG3;                              /**< DCDC REGISTER 3, offset: 0xC */
1375   __IO uint32_t REG4;                              /**< DCDC REGISTER 4, offset: 0x10 */
1376        uint8_t RESERVED_0[4];
1377   __IO uint32_t REG6;                              /**< DCDC REGISTER 6, offset: 0x18 */
1378   __IO uint32_t REG7;                              /**< DCDC REGISTER 7, offset: 0x1C */
1379 } DCDC_Type;
1380 
1381 /* ----------------------------------------------------------------------------
1382    -- DCDC Register Masks
1383    ---------------------------------------------------------------------------- */
1384 
1385 /*!
1386  * @addtogroup DCDC_Register_Masks DCDC Register Masks
1387  * @{
1388  */
1389 
1390 /*! @name REG0 - DCDC REGISTER 0 */
1391 #define DCDC_REG0_DCDC_DISABLE_AUTO_CLK_SWITCH_MASK (0x2U)
1392 #define DCDC_REG0_DCDC_DISABLE_AUTO_CLK_SWITCH_SHIFT (1U)
1393 #define DCDC_REG0_DCDC_DISABLE_AUTO_CLK_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DCDC_DISABLE_AUTO_CLK_SWITCH_SHIFT)) & DCDC_REG0_DCDC_DISABLE_AUTO_CLK_SWITCH_MASK)
1394 #define DCDC_REG0_DCDC_SEL_CLK_MASK              (0x4U)
1395 #define DCDC_REG0_DCDC_SEL_CLK_SHIFT             (2U)
1396 #define DCDC_REG0_DCDC_SEL_CLK(x)                (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DCDC_SEL_CLK_SHIFT)) & DCDC_REG0_DCDC_SEL_CLK_MASK)
1397 #define DCDC_REG0_DCDC_PWD_OSC_INT_MASK          (0x8U)
1398 #define DCDC_REG0_DCDC_PWD_OSC_INT_SHIFT         (3U)
1399 #define DCDC_REG0_DCDC_PWD_OSC_INT(x)            (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DCDC_PWD_OSC_INT_SHIFT)) & DCDC_REG0_DCDC_PWD_OSC_INT_MASK)
1400 #define DCDC_REG0_DCDC_LP_DF_CMP_ENABLE_MASK     (0x200U)
1401 #define DCDC_REG0_DCDC_LP_DF_CMP_ENABLE_SHIFT    (9U)
1402 #define DCDC_REG0_DCDC_LP_DF_CMP_ENABLE(x)       (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DCDC_LP_DF_CMP_ENABLE_SHIFT)) & DCDC_REG0_DCDC_LP_DF_CMP_ENABLE_MASK)
1403 #define DCDC_REG0_DCDC_VBAT_DIV_CTRL_MASK        (0xC00U)
1404 #define DCDC_REG0_DCDC_VBAT_DIV_CTRL_SHIFT       (10U)
1405 #define DCDC_REG0_DCDC_VBAT_DIV_CTRL(x)          (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DCDC_VBAT_DIV_CTRL_SHIFT)) & DCDC_REG0_DCDC_VBAT_DIV_CTRL_MASK)
1406 #define DCDC_REG0_DCDC_LP_STATE_HYS_L_MASK       (0x60000U)
1407 #define DCDC_REG0_DCDC_LP_STATE_HYS_L_SHIFT      (17U)
1408 #define DCDC_REG0_DCDC_LP_STATE_HYS_L(x)         (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DCDC_LP_STATE_HYS_L_SHIFT)) & DCDC_REG0_DCDC_LP_STATE_HYS_L_MASK)
1409 #define DCDC_REG0_DCDC_LP_STATE_HYS_H_MASK       (0x180000U)
1410 #define DCDC_REG0_DCDC_LP_STATE_HYS_H_SHIFT      (19U)
1411 #define DCDC_REG0_DCDC_LP_STATE_HYS_H(x)         (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DCDC_LP_STATE_HYS_H_SHIFT)) & DCDC_REG0_DCDC_LP_STATE_HYS_H_MASK)
1412 #define DCDC_REG0_HYST_LP_COMP_ADJ_MASK          (0x200000U)
1413 #define DCDC_REG0_HYST_LP_COMP_ADJ_SHIFT         (21U)
1414 #define DCDC_REG0_HYST_LP_COMP_ADJ(x)            (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_HYST_LP_COMP_ADJ_SHIFT)) & DCDC_REG0_HYST_LP_COMP_ADJ_MASK)
1415 #define DCDC_REG0_HYST_LP_CMP_DISABLE_MASK       (0x400000U)
1416 #define DCDC_REG0_HYST_LP_CMP_DISABLE_SHIFT      (22U)
1417 #define DCDC_REG0_HYST_LP_CMP_DISABLE(x)         (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_HYST_LP_CMP_DISABLE_SHIFT)) & DCDC_REG0_HYST_LP_CMP_DISABLE_MASK)
1418 #define DCDC_REG0_OFFSET_RSNS_LP_ADJ_MASK        (0x800000U)
1419 #define DCDC_REG0_OFFSET_RSNS_LP_ADJ_SHIFT       (23U)
1420 #define DCDC_REG0_OFFSET_RSNS_LP_ADJ(x)          (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_OFFSET_RSNS_LP_ADJ_SHIFT)) & DCDC_REG0_OFFSET_RSNS_LP_ADJ_MASK)
1421 #define DCDC_REG0_OFFSET_RSNS_LP_DISABLE_MASK    (0x1000000U)
1422 #define DCDC_REG0_OFFSET_RSNS_LP_DISABLE_SHIFT   (24U)
1423 #define DCDC_REG0_OFFSET_RSNS_LP_DISABLE(x)      (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_OFFSET_RSNS_LP_DISABLE_SHIFT)) & DCDC_REG0_OFFSET_RSNS_LP_DISABLE_MASK)
1424 #define DCDC_REG0_DCDC_LESS_I_MASK               (0x2000000U)
1425 #define DCDC_REG0_DCDC_LESS_I_SHIFT              (25U)
1426 #define DCDC_REG0_DCDC_LESS_I(x)                 (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DCDC_LESS_I_SHIFT)) & DCDC_REG0_DCDC_LESS_I_MASK)
1427 #define DCDC_REG0_PWD_CMP_OFFSET_MASK            (0x4000000U)
1428 #define DCDC_REG0_PWD_CMP_OFFSET_SHIFT           (26U)
1429 #define DCDC_REG0_PWD_CMP_OFFSET(x)              (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_OFFSET_SHIFT)) & DCDC_REG0_PWD_CMP_OFFSET_MASK)
1430 #define DCDC_REG0_DCDC_XTALOK_DISABLE_MASK       (0x8000000U)
1431 #define DCDC_REG0_DCDC_XTALOK_DISABLE_SHIFT      (27U)
1432 #define DCDC_REG0_DCDC_XTALOK_DISABLE(x)         (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DCDC_XTALOK_DISABLE_SHIFT)) & DCDC_REG0_DCDC_XTALOK_DISABLE_MASK)
1433 #define DCDC_REG0_PSWITCH_STATUS_MASK            (0x10000000U)
1434 #define DCDC_REG0_PSWITCH_STATUS_SHIFT           (28U)
1435 #define DCDC_REG0_PSWITCH_STATUS(x)              (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PSWITCH_STATUS_SHIFT)) & DCDC_REG0_PSWITCH_STATUS_MASK)
1436 #define DCDC_REG0_VLPS_CONFIG_DCDC_HP_MASK       (0x20000000U)
1437 #define DCDC_REG0_VLPS_CONFIG_DCDC_HP_SHIFT      (29U)
1438 #define DCDC_REG0_VLPS_CONFIG_DCDC_HP(x)         (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_VLPS_CONFIG_DCDC_HP_SHIFT)) & DCDC_REG0_VLPS_CONFIG_DCDC_HP_MASK)
1439 #define DCDC_REG0_VLPR_VLPW_CONFIG_DCDC_HP_MASK  (0x40000000U)
1440 #define DCDC_REG0_VLPR_VLPW_CONFIG_DCDC_HP_SHIFT (30U)
1441 #define DCDC_REG0_VLPR_VLPW_CONFIG_DCDC_HP(x)    (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_VLPR_VLPW_CONFIG_DCDC_HP_SHIFT)) & DCDC_REG0_VLPR_VLPW_CONFIG_DCDC_HP_MASK)
1442 #define DCDC_REG0_DCDC_STS_DC_OK_MASK            (0x80000000U)
1443 #define DCDC_REG0_DCDC_STS_DC_OK_SHIFT           (31U)
1444 #define DCDC_REG0_DCDC_STS_DC_OK(x)              (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DCDC_STS_DC_OK_SHIFT)) & DCDC_REG0_DCDC_STS_DC_OK_MASK)
1445 
1446 /*! @name REG1 - DCDC REGISTER 1 */
1447 #define DCDC_REG1_POSLIMIT_BUCK_IN_MASK          (0x7FU)
1448 #define DCDC_REG1_POSLIMIT_BUCK_IN_SHIFT         (0U)
1449 #define DCDC_REG1_POSLIMIT_BUCK_IN(x)            (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_POSLIMIT_BUCK_IN_SHIFT)) & DCDC_REG1_POSLIMIT_BUCK_IN_MASK)
1450 #define DCDC_REG1_POSLIMIT_BOOST_IN_MASK         (0x3F80U)
1451 #define DCDC_REG1_POSLIMIT_BOOST_IN_SHIFT        (7U)
1452 #define DCDC_REG1_POSLIMIT_BOOST_IN(x)           (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_POSLIMIT_BOOST_IN_SHIFT)) & DCDC_REG1_POSLIMIT_BOOST_IN_MASK)
1453 #define DCDC_REG1_DCDC_LOOPCTRL_CM_HST_THRESH_MASK (0x200000U)
1454 #define DCDC_REG1_DCDC_LOOPCTRL_CM_HST_THRESH_SHIFT (21U)
1455 #define DCDC_REG1_DCDC_LOOPCTRL_CM_HST_THRESH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_DCDC_LOOPCTRL_CM_HST_THRESH_SHIFT)) & DCDC_REG1_DCDC_LOOPCTRL_CM_HST_THRESH_MASK)
1456 #define DCDC_REG1_DCDC_LOOPCTRL_DF_HST_THRESH_MASK (0x400000U)
1457 #define DCDC_REG1_DCDC_LOOPCTRL_DF_HST_THRESH_SHIFT (22U)
1458 #define DCDC_REG1_DCDC_LOOPCTRL_DF_HST_THRESH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_DCDC_LOOPCTRL_DF_HST_THRESH_SHIFT)) & DCDC_REG1_DCDC_LOOPCTRL_DF_HST_THRESH_MASK)
1459 #define DCDC_REG1_DCDC_LOOPCTRL_EN_CM_HYST_MASK  (0x800000U)
1460 #define DCDC_REG1_DCDC_LOOPCTRL_EN_CM_HYST_SHIFT (23U)
1461 #define DCDC_REG1_DCDC_LOOPCTRL_EN_CM_HYST(x)    (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_DCDC_LOOPCTRL_EN_CM_HYST_SHIFT)) & DCDC_REG1_DCDC_LOOPCTRL_EN_CM_HYST_MASK)
1462 #define DCDC_REG1_DCDC_LOOPCTRL_EN_DF_HYST_MASK  (0x1000000U)
1463 #define DCDC_REG1_DCDC_LOOPCTRL_EN_DF_HYST_SHIFT (24U)
1464 #define DCDC_REG1_DCDC_LOOPCTRL_EN_DF_HYST(x)    (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_DCDC_LOOPCTRL_EN_DF_HYST_SHIFT)) & DCDC_REG1_DCDC_LOOPCTRL_EN_DF_HYST_MASK)
1465 
1466 /*! @name REG2 - DCDC REGISTER 2 */
1467 #define DCDC_REG2_DCDC_LOOPCTRL_HYST_SIGN_MASK   (0x2000U)
1468 #define DCDC_REG2_DCDC_LOOPCTRL_HYST_SIGN_SHIFT  (13U)
1469 #define DCDC_REG2_DCDC_LOOPCTRL_HYST_SIGN(x)     (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DCDC_LOOPCTRL_HYST_SIGN_SHIFT)) & DCDC_REG2_DCDC_LOOPCTRL_HYST_SIGN_MASK)
1470 #define DCDC_REG2_DCDC_BATTMONITOR_EN_BATADJ_MASK (0x8000U)
1471 #define DCDC_REG2_DCDC_BATTMONITOR_EN_BATADJ_SHIFT (15U)
1472 #define DCDC_REG2_DCDC_BATTMONITOR_EN_BATADJ(x)  (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DCDC_BATTMONITOR_EN_BATADJ_SHIFT)) & DCDC_REG2_DCDC_BATTMONITOR_EN_BATADJ_MASK)
1473 #define DCDC_REG2_DCDC_BATTMONITOR_BATT_VAL_MASK (0x3FF0000U)
1474 #define DCDC_REG2_DCDC_BATTMONITOR_BATT_VAL_SHIFT (16U)
1475 #define DCDC_REG2_DCDC_BATTMONITOR_BATT_VAL(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DCDC_BATTMONITOR_BATT_VAL_SHIFT)) & DCDC_REG2_DCDC_BATTMONITOR_BATT_VAL_MASK)
1476 
1477 /*! @name REG3 - DCDC REGISTER 3 */
1478 #define DCDC_REG3_DCDC_VDD1P8CTRL_TRG_MASK       (0x3FU)
1479 #define DCDC_REG3_DCDC_VDD1P8CTRL_TRG_SHIFT      (0U)
1480 #define DCDC_REG3_DCDC_VDD1P8CTRL_TRG(x)         (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DCDC_VDD1P8CTRL_TRG_SHIFT)) & DCDC_REG3_DCDC_VDD1P8CTRL_TRG_MASK)
1481 #define DCDC_REG3_DCDC_VDD1P5CTRL_TRG_BUCK_MASK  (0x7C0U)
1482 #define DCDC_REG3_DCDC_VDD1P5CTRL_TRG_BUCK_SHIFT (6U)
1483 #define DCDC_REG3_DCDC_VDD1P5CTRL_TRG_BUCK(x)    (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DCDC_VDD1P5CTRL_TRG_BUCK_SHIFT)) & DCDC_REG3_DCDC_VDD1P5CTRL_TRG_BUCK_MASK)
1484 #define DCDC_REG3_DCDC_VDD1P5CTRL_TRG_BOOST_MASK (0xF800U)
1485 #define DCDC_REG3_DCDC_VDD1P5CTRL_TRG_BOOST_SHIFT (11U)
1486 #define DCDC_REG3_DCDC_VDD1P5CTRL_TRG_BOOST(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DCDC_VDD1P5CTRL_TRG_BOOST_SHIFT)) & DCDC_REG3_DCDC_VDD1P5CTRL_TRG_BOOST_MASK)
1487 #define DCDC_REG3_DCDC_VDD1P5CTRL_ADJTN_MASK     (0x1E0000U)
1488 #define DCDC_REG3_DCDC_VDD1P5CTRL_ADJTN_SHIFT    (17U)
1489 #define DCDC_REG3_DCDC_VDD1P5CTRL_ADJTN(x)       (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DCDC_VDD1P5CTRL_ADJTN_SHIFT)) & DCDC_REG3_DCDC_VDD1P5CTRL_ADJTN_MASK)
1490 #define DCDC_REG3_DCDC_MINPWR_DC_HALFCLK_PULSED_MASK (0x200000U)
1491 #define DCDC_REG3_DCDC_MINPWR_DC_HALFCLK_PULSED_SHIFT (21U)
1492 #define DCDC_REG3_DCDC_MINPWR_DC_HALFCLK_PULSED(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DCDC_MINPWR_DC_HALFCLK_PULSED_SHIFT)) & DCDC_REG3_DCDC_MINPWR_DC_HALFCLK_PULSED_MASK)
1493 #define DCDC_REG3_DCDC_MINPWR_DOUBLE_FETS_PULSED_MASK (0x400000U)
1494 #define DCDC_REG3_DCDC_MINPWR_DOUBLE_FETS_PULSED_SHIFT (22U)
1495 #define DCDC_REG3_DCDC_MINPWR_DOUBLE_FETS_PULSED(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DCDC_MINPWR_DOUBLE_FETS_PULSED_SHIFT)) & DCDC_REG3_DCDC_MINPWR_DOUBLE_FETS_PULSED_MASK)
1496 #define DCDC_REG3_DCDC_MINPWR_HALF_FETS_PULSED_MASK (0x800000U)
1497 #define DCDC_REG3_DCDC_MINPWR_HALF_FETS_PULSED_SHIFT (23U)
1498 #define DCDC_REG3_DCDC_MINPWR_HALF_FETS_PULSED(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DCDC_MINPWR_HALF_FETS_PULSED_SHIFT)) & DCDC_REG3_DCDC_MINPWR_HALF_FETS_PULSED_MASK)
1499 #define DCDC_REG3_DCDC_MINPWR_DC_HALFCLK_MASK    (0x1000000U)
1500 #define DCDC_REG3_DCDC_MINPWR_DC_HALFCLK_SHIFT   (24U)
1501 #define DCDC_REG3_DCDC_MINPWR_DC_HALFCLK(x)      (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DCDC_MINPWR_DC_HALFCLK_SHIFT)) & DCDC_REG3_DCDC_MINPWR_DC_HALFCLK_MASK)
1502 #define DCDC_REG3_DCDC_MINPWR_DOUBLE_FETS_MASK   (0x2000000U)
1503 #define DCDC_REG3_DCDC_MINPWR_DOUBLE_FETS_SHIFT  (25U)
1504 #define DCDC_REG3_DCDC_MINPWR_DOUBLE_FETS(x)     (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DCDC_MINPWR_DOUBLE_FETS_SHIFT)) & DCDC_REG3_DCDC_MINPWR_DOUBLE_FETS_MASK)
1505 #define DCDC_REG3_DCDC_MINPWR_HALF_FETS_MASK     (0x4000000U)
1506 #define DCDC_REG3_DCDC_MINPWR_HALF_FETS_SHIFT    (26U)
1507 #define DCDC_REG3_DCDC_MINPWR_HALF_FETS(x)       (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DCDC_MINPWR_HALF_FETS_SHIFT)) & DCDC_REG3_DCDC_MINPWR_HALF_FETS_MASK)
1508 #define DCDC_REG3_DCDC_VDD1P5CTRL_DISABLE_STEP_MASK (0x20000000U)
1509 #define DCDC_REG3_DCDC_VDD1P5CTRL_DISABLE_STEP_SHIFT (29U)
1510 #define DCDC_REG3_DCDC_VDD1P5CTRL_DISABLE_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DCDC_VDD1P5CTRL_DISABLE_STEP_SHIFT)) & DCDC_REG3_DCDC_VDD1P5CTRL_DISABLE_STEP_MASK)
1511 #define DCDC_REG3_DCDC_VDD1P8CTRL_DISABLE_STEP_MASK (0x40000000U)
1512 #define DCDC_REG3_DCDC_VDD1P8CTRL_DISABLE_STEP_SHIFT (30U)
1513 #define DCDC_REG3_DCDC_VDD1P8CTRL_DISABLE_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DCDC_VDD1P8CTRL_DISABLE_STEP_SHIFT)) & DCDC_REG3_DCDC_VDD1P8CTRL_DISABLE_STEP_MASK)
1514 
1515 /*! @name REG4 - DCDC REGISTER 4 */
1516 #define DCDC_REG4_DCDC_SW_SHUTDOWN_MASK          (0x1U)
1517 #define DCDC_REG4_DCDC_SW_SHUTDOWN_SHIFT         (0U)
1518 #define DCDC_REG4_DCDC_SW_SHUTDOWN(x)            (((uint32_t)(((uint32_t)(x)) << DCDC_REG4_DCDC_SW_SHUTDOWN_SHIFT)) & DCDC_REG4_DCDC_SW_SHUTDOWN_MASK)
1519 #define DCDC_REG4_UNLOCK_MASK                    (0xFFFF0000U)
1520 #define DCDC_REG4_UNLOCK_SHIFT                   (16U)
1521 #define DCDC_REG4_UNLOCK(x)                      (((uint32_t)(((uint32_t)(x)) << DCDC_REG4_UNLOCK_SHIFT)) & DCDC_REG4_UNLOCK_MASK)
1522 
1523 /*! @name REG6 - DCDC REGISTER 6 */
1524 #define DCDC_REG6_PSWITCH_INT_RISE_EN_MASK       (0x1U)
1525 #define DCDC_REG6_PSWITCH_INT_RISE_EN_SHIFT      (0U)
1526 #define DCDC_REG6_PSWITCH_INT_RISE_EN(x)         (((uint32_t)(((uint32_t)(x)) << DCDC_REG6_PSWITCH_INT_RISE_EN_SHIFT)) & DCDC_REG6_PSWITCH_INT_RISE_EN_MASK)
1527 #define DCDC_REG6_PSWITCH_INT_FALL_EN_MASK       (0x2U)
1528 #define DCDC_REG6_PSWITCH_INT_FALL_EN_SHIFT      (1U)
1529 #define DCDC_REG6_PSWITCH_INT_FALL_EN(x)         (((uint32_t)(((uint32_t)(x)) << DCDC_REG6_PSWITCH_INT_FALL_EN_SHIFT)) & DCDC_REG6_PSWITCH_INT_FALL_EN_MASK)
1530 #define DCDC_REG6_PSWITCH_INT_CLEAR_MASK         (0x4U)
1531 #define DCDC_REG6_PSWITCH_INT_CLEAR_SHIFT        (2U)
1532 #define DCDC_REG6_PSWITCH_INT_CLEAR(x)           (((uint32_t)(((uint32_t)(x)) << DCDC_REG6_PSWITCH_INT_CLEAR_SHIFT)) & DCDC_REG6_PSWITCH_INT_CLEAR_MASK)
1533 #define DCDC_REG6_PSWITCH_INT_MUTE_MASK          (0x8U)
1534 #define DCDC_REG6_PSWITCH_INT_MUTE_SHIFT         (3U)
1535 #define DCDC_REG6_PSWITCH_INT_MUTE(x)            (((uint32_t)(((uint32_t)(x)) << DCDC_REG6_PSWITCH_INT_MUTE_SHIFT)) & DCDC_REG6_PSWITCH_INT_MUTE_MASK)
1536 #define DCDC_REG6_PSWITCH_INT_STS_MASK           (0x80000000U)
1537 #define DCDC_REG6_PSWITCH_INT_STS_SHIFT          (31U)
1538 #define DCDC_REG6_PSWITCH_INT_STS(x)             (((uint32_t)(((uint32_t)(x)) << DCDC_REG6_PSWITCH_INT_STS_SHIFT)) & DCDC_REG6_PSWITCH_INT_STS_MASK)
1539 
1540 /*! @name REG7 - DCDC REGISTER 7 */
1541 #define DCDC_REG7_INTEGRATOR_VALUE_MASK          (0x7FFFFU)
1542 #define DCDC_REG7_INTEGRATOR_VALUE_SHIFT         (0U)
1543 #define DCDC_REG7_INTEGRATOR_VALUE(x)            (((uint32_t)(((uint32_t)(x)) << DCDC_REG7_INTEGRATOR_VALUE_SHIFT)) & DCDC_REG7_INTEGRATOR_VALUE_MASK)
1544 #define DCDC_REG7_INTEGRATOR_VALUE_SEL_MASK      (0x80000U)
1545 #define DCDC_REG7_INTEGRATOR_VALUE_SEL_SHIFT     (19U)
1546 #define DCDC_REG7_INTEGRATOR_VALUE_SEL(x)        (((uint32_t)(((uint32_t)(x)) << DCDC_REG7_INTEGRATOR_VALUE_SEL_SHIFT)) & DCDC_REG7_INTEGRATOR_VALUE_SEL_MASK)
1547 #define DCDC_REG7_PULSE_RUN_SPEEDUP_MASK         (0x100000U)
1548 #define DCDC_REG7_PULSE_RUN_SPEEDUP_SHIFT        (20U)
1549 #define DCDC_REG7_PULSE_RUN_SPEEDUP(x)           (((uint32_t)(((uint32_t)(x)) << DCDC_REG7_PULSE_RUN_SPEEDUP_SHIFT)) & DCDC_REG7_PULSE_RUN_SPEEDUP_MASK)
1550 
1551 
1552 /*!
1553  * @}
1554  */ /* end of group DCDC_Register_Masks */
1555 
1556 
1557 /* DCDC - Peripheral instance base addresses */
1558 /** Peripheral DCDC base address */
1559 #define DCDC_BASE                                (0x4005A000u)
1560 /** Peripheral DCDC base pointer */
1561 #define DCDC                                     ((DCDC_Type *)DCDC_BASE)
1562 /** Array initializer of DCDC peripheral base addresses */
1563 #define DCDC_BASE_ADDRS                          { DCDC_BASE }
1564 /** Array initializer of DCDC peripheral base pointers */
1565 #define DCDC_BASE_PTRS                           { DCDC }
1566 
1567 /*!
1568  * @}
1569  */ /* end of group DCDC_Peripheral_Access_Layer */
1570 
1571 
1572 /* ----------------------------------------------------------------------------
1573    -- DMA Peripheral Access Layer
1574    ---------------------------------------------------------------------------- */
1575 
1576 /*!
1577  * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
1578  * @{
1579  */
1580 
1581 /** DMA - Register Layout Typedef */
1582 typedef struct {
1583   __IO uint32_t CR;                                /**< Control Register, offset: 0x0 */
1584   __I  uint32_t ES;                                /**< Error Status Register, offset: 0x4 */
1585        uint8_t RESERVED_0[4];
1586   __IO uint32_t ERQ;                               /**< Enable Request Register, offset: 0xC */
1587        uint8_t RESERVED_1[4];
1588   __IO uint32_t EEI;                               /**< Enable Error Interrupt Register, offset: 0x14 */
1589   __O  uint8_t CEEI;                               /**< Clear Enable Error Interrupt Register, offset: 0x18 */
1590   __O  uint8_t SEEI;                               /**< Set Enable Error Interrupt Register, offset: 0x19 */
1591   __O  uint8_t CERQ;                               /**< Clear Enable Request Register, offset: 0x1A */
1592   __O  uint8_t SERQ;                               /**< Set Enable Request Register, offset: 0x1B */
1593   __O  uint8_t CDNE;                               /**< Clear DONE Status Bit Register, offset: 0x1C */
1594   __O  uint8_t SSRT;                               /**< Set START Bit Register, offset: 0x1D */
1595   __O  uint8_t CERR;                               /**< Clear Error Register, offset: 0x1E */
1596   __O  uint8_t CINT;                               /**< Clear Interrupt Request Register, offset: 0x1F */
1597        uint8_t RESERVED_2[4];
1598   __IO uint32_t INT;                               /**< Interrupt Request Register, offset: 0x24 */
1599        uint8_t RESERVED_3[4];
1600   __IO uint32_t ERR;                               /**< Error Register, offset: 0x2C */
1601        uint8_t RESERVED_4[4];
1602   __I  uint32_t HRS;                               /**< Hardware Request Status Register, offset: 0x34 */
1603        uint8_t RESERVED_5[12];
1604   __IO uint32_t EARS;                              /**< Enable Asynchronous Request in Stop Register, offset: 0x44 */
1605        uint8_t RESERVED_6[184];
1606   __IO uint8_t DCHPRI3;                            /**< Channel n Priority Register, offset: 0x100 */
1607   __IO uint8_t DCHPRI2;                            /**< Channel n Priority Register, offset: 0x101 */
1608   __IO uint8_t DCHPRI1;                            /**< Channel n Priority Register, offset: 0x102 */
1609   __IO uint8_t DCHPRI0;                            /**< Channel n Priority Register, offset: 0x103 */
1610        uint8_t RESERVED_7[3836];
1611   struct {                                         /* offset: 0x1000, array step: 0x20 */
1612     __IO uint32_t SADDR;                             /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
1613     __IO uint16_t SOFF;                              /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
1614     __IO uint16_t ATTR;                              /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
1615     union {                                          /* offset: 0x1008, array step: 0x20 */
1616       __IO uint32_t NBYTES_MLNO;                       /**< TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008, array step: 0x20 */
1617       __IO uint32_t NBYTES_MLOFFNO;                    /**< TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
1618       __IO uint32_t NBYTES_MLOFFYES;                   /**< TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20 */
1619     };
1620     __IO uint32_t SLAST;                             /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
1621     __IO uint32_t DADDR;                             /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
1622     __IO uint16_t DOFF;                              /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
1623     union {                                          /* offset: 0x1016, array step: 0x20 */
1624       __IO uint16_t CITER_ELINKNO;                     /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
1625       __IO uint16_t CITER_ELINKYES;                    /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
1626     };
1627     __IO uint32_t DLAST_SGA;                         /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
1628     __IO uint16_t CSR;                               /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
1629     union {                                          /* offset: 0x101E, array step: 0x20 */
1630       __IO uint16_t BITER_ELINKNO;                     /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
1631       __IO uint16_t BITER_ELINKYES;                    /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
1632     };
1633   } TCD[4];
1634 } DMA_Type;
1635 
1636 /* ----------------------------------------------------------------------------
1637    -- DMA Register Masks
1638    ---------------------------------------------------------------------------- */
1639 
1640 /*!
1641  * @addtogroup DMA_Register_Masks DMA Register Masks
1642  * @{
1643  */
1644 
1645 /*! @name CR - Control Register */
1646 #define DMA_CR_EDBG_MASK                         (0x2U)
1647 #define DMA_CR_EDBG_SHIFT                        (1U)
1648 #define DMA_CR_EDBG(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)
1649 #define DMA_CR_ERCA_MASK                         (0x4U)
1650 #define DMA_CR_ERCA_SHIFT                        (2U)
1651 #define DMA_CR_ERCA(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)
1652 #define DMA_CR_HOE_MASK                          (0x10U)
1653 #define DMA_CR_HOE_SHIFT                         (4U)
1654 #define DMA_CR_HOE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)
1655 #define DMA_CR_HALT_MASK                         (0x20U)
1656 #define DMA_CR_HALT_SHIFT                        (5U)
1657 #define DMA_CR_HALT(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)
1658 #define DMA_CR_CLM_MASK                          (0x40U)
1659 #define DMA_CR_CLM_SHIFT                         (6U)
1660 #define DMA_CR_CLM(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)
1661 #define DMA_CR_EMLM_MASK                         (0x80U)
1662 #define DMA_CR_EMLM_SHIFT                        (7U)
1663 #define DMA_CR_EMLM(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)
1664 #define DMA_CR_ECX_MASK                          (0x10000U)
1665 #define DMA_CR_ECX_SHIFT                         (16U)
1666 #define DMA_CR_ECX(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)
1667 #define DMA_CR_CX_MASK                           (0x20000U)
1668 #define DMA_CR_CX_SHIFT                          (17U)
1669 #define DMA_CR_CX(x)                             (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)
1670 #define DMA_CR_ACTIVE_MASK                       (0x80000000U)
1671 #define DMA_CR_ACTIVE_SHIFT                      (31U)
1672 #define DMA_CR_ACTIVE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CR_ACTIVE_SHIFT)) & DMA_CR_ACTIVE_MASK)
1673 
1674 /*! @name ES - Error Status Register */
1675 #define DMA_ES_DBE_MASK                          (0x1U)
1676 #define DMA_ES_DBE_SHIFT                         (0U)
1677 #define DMA_ES_DBE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)
1678 #define DMA_ES_SBE_MASK                          (0x2U)
1679 #define DMA_ES_SBE_SHIFT                         (1U)
1680 #define DMA_ES_SBE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)
1681 #define DMA_ES_SGE_MASK                          (0x4U)
1682 #define DMA_ES_SGE_SHIFT                         (2U)
1683 #define DMA_ES_SGE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)
1684 #define DMA_ES_NCE_MASK                          (0x8U)
1685 #define DMA_ES_NCE_SHIFT                         (3U)
1686 #define DMA_ES_NCE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)
1687 #define DMA_ES_DOE_MASK                          (0x10U)
1688 #define DMA_ES_DOE_SHIFT                         (4U)
1689 #define DMA_ES_DOE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)
1690 #define DMA_ES_DAE_MASK                          (0x20U)
1691 #define DMA_ES_DAE_SHIFT                         (5U)
1692 #define DMA_ES_DAE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)
1693 #define DMA_ES_SOE_MASK                          (0x40U)
1694 #define DMA_ES_SOE_SHIFT                         (6U)
1695 #define DMA_ES_SOE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)
1696 #define DMA_ES_SAE_MASK                          (0x80U)
1697 #define DMA_ES_SAE_SHIFT                         (7U)
1698 #define DMA_ES_SAE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)
1699 #define DMA_ES_ERRCHN_MASK                       (0x300U)
1700 #define DMA_ES_ERRCHN_SHIFT                      (8U)
1701 #define DMA_ES_ERRCHN(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)
1702 #define DMA_ES_CPE_MASK                          (0x4000U)
1703 #define DMA_ES_CPE_SHIFT                         (14U)
1704 #define DMA_ES_CPE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)
1705 #define DMA_ES_ECX_MASK                          (0x10000U)
1706 #define DMA_ES_ECX_SHIFT                         (16U)
1707 #define DMA_ES_ECX(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)
1708 #define DMA_ES_VLD_MASK                          (0x80000000U)
1709 #define DMA_ES_VLD_SHIFT                         (31U)
1710 #define DMA_ES_VLD(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)
1711 
1712 /*! @name ERQ - Enable Request Register */
1713 #define DMA_ERQ_ERQ0_MASK                        (0x1U)
1714 #define DMA_ERQ_ERQ0_SHIFT                       (0U)
1715 #define DMA_ERQ_ERQ0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)
1716 #define DMA_ERQ_ERQ1_MASK                        (0x2U)
1717 #define DMA_ERQ_ERQ1_SHIFT                       (1U)
1718 #define DMA_ERQ_ERQ1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)
1719 #define DMA_ERQ_ERQ2_MASK                        (0x4U)
1720 #define DMA_ERQ_ERQ2_SHIFT                       (2U)
1721 #define DMA_ERQ_ERQ2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)
1722 #define DMA_ERQ_ERQ3_MASK                        (0x8U)
1723 #define DMA_ERQ_ERQ3_SHIFT                       (3U)
1724 #define DMA_ERQ_ERQ3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)
1725 
1726 /*! @name EEI - Enable Error Interrupt Register */
1727 #define DMA_EEI_EEI0_MASK                        (0x1U)
1728 #define DMA_EEI_EEI0_SHIFT                       (0U)
1729 #define DMA_EEI_EEI0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)
1730 #define DMA_EEI_EEI1_MASK                        (0x2U)
1731 #define DMA_EEI_EEI1_SHIFT                       (1U)
1732 #define DMA_EEI_EEI1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)
1733 #define DMA_EEI_EEI2_MASK                        (0x4U)
1734 #define DMA_EEI_EEI2_SHIFT                       (2U)
1735 #define DMA_EEI_EEI2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)
1736 #define DMA_EEI_EEI3_MASK                        (0x8U)
1737 #define DMA_EEI_EEI3_SHIFT                       (3U)
1738 #define DMA_EEI_EEI3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)
1739 
1740 /*! @name CEEI - Clear Enable Error Interrupt Register */
1741 #define DMA_CEEI_CEEI_MASK                       (0x3U)
1742 #define DMA_CEEI_CEEI_SHIFT                      (0U)
1743 #define DMA_CEEI_CEEI(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)
1744 #define DMA_CEEI_CAEE_MASK                       (0x40U)
1745 #define DMA_CEEI_CAEE_SHIFT                      (6U)
1746 #define DMA_CEEI_CAEE(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)
1747 #define DMA_CEEI_NOP_MASK                        (0x80U)
1748 #define DMA_CEEI_NOP_SHIFT                       (7U)
1749 #define DMA_CEEI_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)
1750 
1751 /*! @name SEEI - Set Enable Error Interrupt Register */
1752 #define DMA_SEEI_SEEI_MASK                       (0x3U)
1753 #define DMA_SEEI_SEEI_SHIFT                      (0U)
1754 #define DMA_SEEI_SEEI(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)
1755 #define DMA_SEEI_SAEE_MASK                       (0x40U)
1756 #define DMA_SEEI_SAEE_SHIFT                      (6U)
1757 #define DMA_SEEI_SAEE(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)
1758 #define DMA_SEEI_NOP_MASK                        (0x80U)
1759 #define DMA_SEEI_NOP_SHIFT                       (7U)
1760 #define DMA_SEEI_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)
1761 
1762 /*! @name CERQ - Clear Enable Request Register */
1763 #define DMA_CERQ_CERQ_MASK                       (0x3U)
1764 #define DMA_CERQ_CERQ_SHIFT                      (0U)
1765 #define DMA_CERQ_CERQ(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)
1766 #define DMA_CERQ_CAER_MASK                       (0x40U)
1767 #define DMA_CERQ_CAER_SHIFT                      (6U)
1768 #define DMA_CERQ_CAER(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)
1769 #define DMA_CERQ_NOP_MASK                        (0x80U)
1770 #define DMA_CERQ_NOP_SHIFT                       (7U)
1771 #define DMA_CERQ_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)
1772 
1773 /*! @name SERQ - Set Enable Request Register */
1774 #define DMA_SERQ_SERQ_MASK                       (0x3U)
1775 #define DMA_SERQ_SERQ_SHIFT                      (0U)
1776 #define DMA_SERQ_SERQ(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)
1777 #define DMA_SERQ_SAER_MASK                       (0x40U)
1778 #define DMA_SERQ_SAER_SHIFT                      (6U)
1779 #define DMA_SERQ_SAER(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)
1780 #define DMA_SERQ_NOP_MASK                        (0x80U)
1781 #define DMA_SERQ_NOP_SHIFT                       (7U)
1782 #define DMA_SERQ_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)
1783 
1784 /*! @name CDNE - Clear DONE Status Bit Register */
1785 #define DMA_CDNE_CDNE_MASK                       (0x3U)
1786 #define DMA_CDNE_CDNE_SHIFT                      (0U)
1787 #define DMA_CDNE_CDNE(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)
1788 #define DMA_CDNE_CADN_MASK                       (0x40U)
1789 #define DMA_CDNE_CADN_SHIFT                      (6U)
1790 #define DMA_CDNE_CADN(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)
1791 #define DMA_CDNE_NOP_MASK                        (0x80U)
1792 #define DMA_CDNE_NOP_SHIFT                       (7U)
1793 #define DMA_CDNE_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)
1794 
1795 /*! @name SSRT - Set START Bit Register */
1796 #define DMA_SSRT_SSRT_MASK                       (0x3U)
1797 #define DMA_SSRT_SSRT_SHIFT                      (0U)
1798 #define DMA_SSRT_SSRT(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)
1799 #define DMA_SSRT_SAST_MASK                       (0x40U)
1800 #define DMA_SSRT_SAST_SHIFT                      (6U)
1801 #define DMA_SSRT_SAST(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)
1802 #define DMA_SSRT_NOP_MASK                        (0x80U)
1803 #define DMA_SSRT_NOP_SHIFT                       (7U)
1804 #define DMA_SSRT_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)
1805 
1806 /*! @name CERR - Clear Error Register */
1807 #define DMA_CERR_CERR_MASK                       (0x3U)
1808 #define DMA_CERR_CERR_SHIFT                      (0U)
1809 #define DMA_CERR_CERR(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)
1810 #define DMA_CERR_CAEI_MASK                       (0x40U)
1811 #define DMA_CERR_CAEI_SHIFT                      (6U)
1812 #define DMA_CERR_CAEI(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)
1813 #define DMA_CERR_NOP_MASK                        (0x80U)
1814 #define DMA_CERR_NOP_SHIFT                       (7U)
1815 #define DMA_CERR_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)
1816 
1817 /*! @name CINT - Clear Interrupt Request Register */
1818 #define DMA_CINT_CINT_MASK                       (0x3U)
1819 #define DMA_CINT_CINT_SHIFT                      (0U)
1820 #define DMA_CINT_CINT(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)
1821 #define DMA_CINT_CAIR_MASK                       (0x40U)
1822 #define DMA_CINT_CAIR_SHIFT                      (6U)
1823 #define DMA_CINT_CAIR(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)
1824 #define DMA_CINT_NOP_MASK                        (0x80U)
1825 #define DMA_CINT_NOP_SHIFT                       (7U)
1826 #define DMA_CINT_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)
1827 
1828 /*! @name INT - Interrupt Request Register */
1829 #define DMA_INT_INT0_MASK                        (0x1U)
1830 #define DMA_INT_INT0_SHIFT                       (0U)
1831 #define DMA_INT_INT0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)
1832 #define DMA_INT_INT1_MASK                        (0x2U)
1833 #define DMA_INT_INT1_SHIFT                       (1U)
1834 #define DMA_INT_INT1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)
1835 #define DMA_INT_INT2_MASK                        (0x4U)
1836 #define DMA_INT_INT2_SHIFT                       (2U)
1837 #define DMA_INT_INT2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)
1838 #define DMA_INT_INT3_MASK                        (0x8U)
1839 #define DMA_INT_INT3_SHIFT                       (3U)
1840 #define DMA_INT_INT3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)
1841 
1842 /*! @name ERR - Error Register */
1843 #define DMA_ERR_ERR0_MASK                        (0x1U)
1844 #define DMA_ERR_ERR0_SHIFT                       (0U)
1845 #define DMA_ERR_ERR0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)
1846 #define DMA_ERR_ERR1_MASK                        (0x2U)
1847 #define DMA_ERR_ERR1_SHIFT                       (1U)
1848 #define DMA_ERR_ERR1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)
1849 #define DMA_ERR_ERR2_MASK                        (0x4U)
1850 #define DMA_ERR_ERR2_SHIFT                       (2U)
1851 #define DMA_ERR_ERR2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)
1852 #define DMA_ERR_ERR3_MASK                        (0x8U)
1853 #define DMA_ERR_ERR3_SHIFT                       (3U)
1854 #define DMA_ERR_ERR3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)
1855 
1856 /*! @name HRS - Hardware Request Status Register */
1857 #define DMA_HRS_HRS0_MASK                        (0x1U)
1858 #define DMA_HRS_HRS0_SHIFT                       (0U)
1859 #define DMA_HRS_HRS0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)
1860 #define DMA_HRS_HRS1_MASK                        (0x2U)
1861 #define DMA_HRS_HRS1_SHIFT                       (1U)
1862 #define DMA_HRS_HRS1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)
1863 #define DMA_HRS_HRS2_MASK                        (0x4U)
1864 #define DMA_HRS_HRS2_SHIFT                       (2U)
1865 #define DMA_HRS_HRS2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)
1866 #define DMA_HRS_HRS3_MASK                        (0x8U)
1867 #define DMA_HRS_HRS3_SHIFT                       (3U)
1868 #define DMA_HRS_HRS3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)
1869 
1870 /*! @name EARS - Enable Asynchronous Request in Stop Register */
1871 #define DMA_EARS_EDREQ_0_MASK                    (0x1U)
1872 #define DMA_EARS_EDREQ_0_SHIFT                   (0U)
1873 #define DMA_EARS_EDREQ_0(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK)
1874 #define DMA_EARS_EDREQ_1_MASK                    (0x2U)
1875 #define DMA_EARS_EDREQ_1_SHIFT                   (1U)
1876 #define DMA_EARS_EDREQ_1(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK)
1877 #define DMA_EARS_EDREQ_2_MASK                    (0x4U)
1878 #define DMA_EARS_EDREQ_2_SHIFT                   (2U)
1879 #define DMA_EARS_EDREQ_2(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK)
1880 #define DMA_EARS_EDREQ_3_MASK                    (0x8U)
1881 #define DMA_EARS_EDREQ_3_SHIFT                   (3U)
1882 #define DMA_EARS_EDREQ_3(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK)
1883 
1884 /*! @name DCHPRI3 - Channel n Priority Register */
1885 #define DMA_DCHPRI3_CHPRI_MASK                   (0x3U)
1886 #define DMA_DCHPRI3_CHPRI_SHIFT                  (0U)
1887 #define DMA_DCHPRI3_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)
1888 #define DMA_DCHPRI3_DPA_MASK                     (0x40U)
1889 #define DMA_DCHPRI3_DPA_SHIFT                    (6U)
1890 #define DMA_DCHPRI3_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)
1891 #define DMA_DCHPRI3_ECP_MASK                     (0x80U)
1892 #define DMA_DCHPRI3_ECP_SHIFT                    (7U)
1893 #define DMA_DCHPRI3_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)
1894 
1895 /*! @name DCHPRI2 - Channel n Priority Register */
1896 #define DMA_DCHPRI2_CHPRI_MASK                   (0x3U)
1897 #define DMA_DCHPRI2_CHPRI_SHIFT                  (0U)
1898 #define DMA_DCHPRI2_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)
1899 #define DMA_DCHPRI2_DPA_MASK                     (0x40U)
1900 #define DMA_DCHPRI2_DPA_SHIFT                    (6U)
1901 #define DMA_DCHPRI2_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)
1902 #define DMA_DCHPRI2_ECP_MASK                     (0x80U)
1903 #define DMA_DCHPRI2_ECP_SHIFT                    (7U)
1904 #define DMA_DCHPRI2_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)
1905 
1906 /*! @name DCHPRI1 - Channel n Priority Register */
1907 #define DMA_DCHPRI1_CHPRI_MASK                   (0x3U)
1908 #define DMA_DCHPRI1_CHPRI_SHIFT                  (0U)
1909 #define DMA_DCHPRI1_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)
1910 #define DMA_DCHPRI1_DPA_MASK                     (0x40U)
1911 #define DMA_DCHPRI1_DPA_SHIFT                    (6U)
1912 #define DMA_DCHPRI1_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)
1913 #define DMA_DCHPRI1_ECP_MASK                     (0x80U)
1914 #define DMA_DCHPRI1_ECP_SHIFT                    (7U)
1915 #define DMA_DCHPRI1_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)
1916 
1917 /*! @name DCHPRI0 - Channel n Priority Register */
1918 #define DMA_DCHPRI0_CHPRI_MASK                   (0x3U)
1919 #define DMA_DCHPRI0_CHPRI_SHIFT                  (0U)
1920 #define DMA_DCHPRI0_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)
1921 #define DMA_DCHPRI0_DPA_MASK                     (0x40U)
1922 #define DMA_DCHPRI0_DPA_SHIFT                    (6U)
1923 #define DMA_DCHPRI0_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)
1924 #define DMA_DCHPRI0_ECP_MASK                     (0x80U)
1925 #define DMA_DCHPRI0_ECP_SHIFT                    (7U)
1926 #define DMA_DCHPRI0_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)
1927 
1928 /*! @name SADDR - TCD Source Address */
1929 #define DMA_SADDR_SADDR_MASK                     (0xFFFFFFFFU)
1930 #define DMA_SADDR_SADDR_SHIFT                    (0U)
1931 #define DMA_SADDR_SADDR(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)
1932 
1933 /* The count of DMA_SADDR */
1934 #define DMA_SADDR_COUNT                          (4U)
1935 
1936 /*! @name SOFF - TCD Signed Source Address Offset */
1937 #define DMA_SOFF_SOFF_MASK                       (0xFFFFU)
1938 #define DMA_SOFF_SOFF_SHIFT                      (0U)
1939 #define DMA_SOFF_SOFF(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)
1940 
1941 /* The count of DMA_SOFF */
1942 #define DMA_SOFF_COUNT                           (4U)
1943 
1944 /*! @name ATTR - TCD Transfer Attributes */
1945 #define DMA_ATTR_DSIZE_MASK                      (0x7U)
1946 #define DMA_ATTR_DSIZE_SHIFT                     (0U)
1947 #define DMA_ATTR_DSIZE(x)                        (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)
1948 #define DMA_ATTR_DMOD_MASK                       (0xF8U)
1949 #define DMA_ATTR_DMOD_SHIFT                      (3U)
1950 #define DMA_ATTR_DMOD(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)
1951 #define DMA_ATTR_SSIZE_MASK                      (0x700U)
1952 #define DMA_ATTR_SSIZE_SHIFT                     (8U)
1953 #define DMA_ATTR_SSIZE(x)                        (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)
1954 #define DMA_ATTR_SMOD_MASK                       (0xF800U)
1955 #define DMA_ATTR_SMOD_SHIFT                      (11U)
1956 #define DMA_ATTR_SMOD(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)
1957 
1958 /* The count of DMA_ATTR */
1959 #define DMA_ATTR_COUNT                           (4U)
1960 
1961 /*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Mapping Disabled) */
1962 #define DMA_NBYTES_MLNO_NBYTES_MASK              (0xFFFFFFFFU)
1963 #define DMA_NBYTES_MLNO_NBYTES_SHIFT             (0U)
1964 #define DMA_NBYTES_MLNO_NBYTES(x)                (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)
1965 
1966 /* The count of DMA_NBYTES_MLNO */
1967 #define DMA_NBYTES_MLNO_COUNT                    (4U)
1968 
1969 /*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) */
1970 #define DMA_NBYTES_MLOFFNO_NBYTES_MASK           (0x3FFFFFFFU)
1971 #define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT          (0U)
1972 #define DMA_NBYTES_MLOFFNO_NBYTES(x)             (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)
1973 #define DMA_NBYTES_MLOFFNO_DMLOE_MASK            (0x40000000U)
1974 #define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT           (30U)
1975 #define DMA_NBYTES_MLOFFNO_DMLOE(x)              (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)
1976 #define DMA_NBYTES_MLOFFNO_SMLOE_MASK            (0x80000000U)
1977 #define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT           (31U)
1978 #define DMA_NBYTES_MLOFFNO_SMLOE(x)              (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)
1979 
1980 /* The count of DMA_NBYTES_MLOFFNO */
1981 #define DMA_NBYTES_MLOFFNO_COUNT                 (4U)
1982 
1983 /*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) */
1984 #define DMA_NBYTES_MLOFFYES_NBYTES_MASK          (0x3FFU)
1985 #define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT         (0U)
1986 #define DMA_NBYTES_MLOFFYES_NBYTES(x)            (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)
1987 #define DMA_NBYTES_MLOFFYES_MLOFF_MASK           (0x3FFFFC00U)
1988 #define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT          (10U)
1989 #define DMA_NBYTES_MLOFFYES_MLOFF(x)             (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)
1990 #define DMA_NBYTES_MLOFFYES_DMLOE_MASK           (0x40000000U)
1991 #define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT          (30U)
1992 #define DMA_NBYTES_MLOFFYES_DMLOE(x)             (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)
1993 #define DMA_NBYTES_MLOFFYES_SMLOE_MASK           (0x80000000U)
1994 #define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT          (31U)
1995 #define DMA_NBYTES_MLOFFYES_SMLOE(x)             (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)
1996 
1997 /* The count of DMA_NBYTES_MLOFFYES */
1998 #define DMA_NBYTES_MLOFFYES_COUNT                (4U)
1999 
2000 /*! @name SLAST - TCD Last Source Address Adjustment */
2001 #define DMA_SLAST_SLAST_MASK                     (0xFFFFFFFFU)
2002 #define DMA_SLAST_SLAST_SHIFT                    (0U)
2003 #define DMA_SLAST_SLAST(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)
2004 
2005 /* The count of DMA_SLAST */
2006 #define DMA_SLAST_COUNT                          (4U)
2007 
2008 /*! @name DADDR - TCD Destination Address */
2009 #define DMA_DADDR_DADDR_MASK                     (0xFFFFFFFFU)
2010 #define DMA_DADDR_DADDR_SHIFT                    (0U)
2011 #define DMA_DADDR_DADDR(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)
2012 
2013 /* The count of DMA_DADDR */
2014 #define DMA_DADDR_COUNT                          (4U)
2015 
2016 /*! @name DOFF - TCD Signed Destination Address Offset */
2017 #define DMA_DOFF_DOFF_MASK                       (0xFFFFU)
2018 #define DMA_DOFF_DOFF_SHIFT                      (0U)
2019 #define DMA_DOFF_DOFF(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)
2020 
2021 /* The count of DMA_DOFF */
2022 #define DMA_DOFF_COUNT                           (4U)
2023 
2024 /*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
2025 #define DMA_CITER_ELINKNO_CITER_MASK             (0x7FFFU)
2026 #define DMA_CITER_ELINKNO_CITER_SHIFT            (0U)
2027 #define DMA_CITER_ELINKNO_CITER(x)               (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)
2028 #define DMA_CITER_ELINKNO_ELINK_MASK             (0x8000U)
2029 #define DMA_CITER_ELINKNO_ELINK_SHIFT            (15U)
2030 #define DMA_CITER_ELINKNO_ELINK(x)               (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)
2031 
2032 /* The count of DMA_CITER_ELINKNO */
2033 #define DMA_CITER_ELINKNO_COUNT                  (4U)
2034 
2035 /*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
2036 #define DMA_CITER_ELINKYES_CITER_MASK            (0x1FFU)
2037 #define DMA_CITER_ELINKYES_CITER_SHIFT           (0U)
2038 #define DMA_CITER_ELINKYES_CITER(x)              (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)
2039 #define DMA_CITER_ELINKYES_LINKCH_MASK           (0x600U)
2040 #define DMA_CITER_ELINKYES_LINKCH_SHIFT          (9U)
2041 #define DMA_CITER_ELINKYES_LINKCH(x)             (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)
2042 #define DMA_CITER_ELINKYES_ELINK_MASK            (0x8000U)
2043 #define DMA_CITER_ELINKYES_ELINK_SHIFT           (15U)
2044 #define DMA_CITER_ELINKYES_ELINK(x)              (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)
2045 
2046 /* The count of DMA_CITER_ELINKYES */
2047 #define DMA_CITER_ELINKYES_COUNT                 (4U)
2048 
2049 /*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */
2050 #define DMA_DLAST_SGA_DLASTSGA_MASK              (0xFFFFFFFFU)
2051 #define DMA_DLAST_SGA_DLASTSGA_SHIFT             (0U)
2052 #define DMA_DLAST_SGA_DLASTSGA(x)                (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)
2053 
2054 /* The count of DMA_DLAST_SGA */
2055 #define DMA_DLAST_SGA_COUNT                      (4U)
2056 
2057 /*! @name CSR - TCD Control and Status */
2058 #define DMA_CSR_START_MASK                       (0x1U)
2059 #define DMA_CSR_START_SHIFT                      (0U)
2060 #define DMA_CSR_START(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)
2061 #define DMA_CSR_INTMAJOR_MASK                    (0x2U)
2062 #define DMA_CSR_INTMAJOR_SHIFT                   (1U)
2063 #define DMA_CSR_INTMAJOR(x)                      (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)
2064 #define DMA_CSR_INTHALF_MASK                     (0x4U)
2065 #define DMA_CSR_INTHALF_SHIFT                    (2U)
2066 #define DMA_CSR_INTHALF(x)                       (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
2067 #define DMA_CSR_DREQ_MASK                        (0x8U)
2068 #define DMA_CSR_DREQ_SHIFT                       (3U)
2069 #define DMA_CSR_DREQ(x)                          (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)
2070 #define DMA_CSR_ESG_MASK                         (0x10U)
2071 #define DMA_CSR_ESG_SHIFT                        (4U)
2072 #define DMA_CSR_ESG(x)                           (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)
2073 #define DMA_CSR_MAJORELINK_MASK                  (0x20U)
2074 #define DMA_CSR_MAJORELINK_SHIFT                 (5U)
2075 #define DMA_CSR_MAJORELINK(x)                    (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)
2076 #define DMA_CSR_ACTIVE_MASK                      (0x40U)
2077 #define DMA_CSR_ACTIVE_SHIFT                     (6U)
2078 #define DMA_CSR_ACTIVE(x)                        (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)
2079 #define DMA_CSR_DONE_MASK                        (0x80U)
2080 #define DMA_CSR_DONE_SHIFT                       (7U)
2081 #define DMA_CSR_DONE(x)                          (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)
2082 #define DMA_CSR_MAJORLINKCH_MASK                 (0x300U)
2083 #define DMA_CSR_MAJORLINKCH_SHIFT                (8U)
2084 #define DMA_CSR_MAJORLINKCH(x)                   (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)
2085 #define DMA_CSR_BWC_MASK                         (0xC000U)
2086 #define DMA_CSR_BWC_SHIFT                        (14U)
2087 #define DMA_CSR_BWC(x)                           (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)
2088 
2089 /* The count of DMA_CSR */
2090 #define DMA_CSR_COUNT                            (4U)
2091 
2092 /*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
2093 #define DMA_BITER_ELINKNO_BITER_MASK             (0x7FFFU)
2094 #define DMA_BITER_ELINKNO_BITER_SHIFT            (0U)
2095 #define DMA_BITER_ELINKNO_BITER(x)               (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)
2096 #define DMA_BITER_ELINKNO_ELINK_MASK             (0x8000U)
2097 #define DMA_BITER_ELINKNO_ELINK_SHIFT            (15U)
2098 #define DMA_BITER_ELINKNO_ELINK(x)               (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)
2099 
2100 /* The count of DMA_BITER_ELINKNO */
2101 #define DMA_BITER_ELINKNO_COUNT                  (4U)
2102 
2103 /*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
2104 #define DMA_BITER_ELINKYES_BITER_MASK            (0x1FFU)
2105 #define DMA_BITER_ELINKYES_BITER_SHIFT           (0U)
2106 #define DMA_BITER_ELINKYES_BITER(x)              (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)
2107 #define DMA_BITER_ELINKYES_LINKCH_MASK           (0x600U)
2108 #define DMA_BITER_ELINKYES_LINKCH_SHIFT          (9U)
2109 #define DMA_BITER_ELINKYES_LINKCH(x)             (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)
2110 #define DMA_BITER_ELINKYES_ELINK_MASK            (0x8000U)
2111 #define DMA_BITER_ELINKYES_ELINK_SHIFT           (15U)
2112 #define DMA_BITER_ELINKYES_ELINK(x)              (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)
2113 
2114 /* The count of DMA_BITER_ELINKYES */
2115 #define DMA_BITER_ELINKYES_COUNT                 (4U)
2116 
2117 
2118 /*!
2119  * @}
2120  */ /* end of group DMA_Register_Masks */
2121 
2122 
2123 /* DMA - Peripheral instance base addresses */
2124 /** Peripheral DMA base address */
2125 #define DMA_BASE                                 (0x40008000u)
2126 /** Peripheral DMA base pointer */
2127 #define DMA0                                     ((DMA_Type *)DMA_BASE)
2128 /** Array initializer of DMA peripheral base addresses */
2129 #define DMA_BASE_ADDRS                           { DMA_BASE }
2130 /** Array initializer of DMA peripheral base pointers */
2131 #define DMA_BASE_PTRS                            { DMA0 }
2132 /** Interrupt vectors for the DMA peripheral type */
2133 #define DMA_CHN_IRQS                             { { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn } }
2134 
2135 /*!
2136  * @}
2137  */ /* end of group DMA_Peripheral_Access_Layer */
2138 
2139 
2140 /* ----------------------------------------------------------------------------
2141    -- DMAMUX Peripheral Access Layer
2142    ---------------------------------------------------------------------------- */
2143 
2144 /*!
2145  * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
2146  * @{
2147  */
2148 
2149 /** DMAMUX - Register Layout Typedef */
2150 typedef struct {
2151   __IO uint8_t CHCFG[4];                           /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
2152 } DMAMUX_Type;
2153 
2154 /* ----------------------------------------------------------------------------
2155    -- DMAMUX Register Masks
2156    ---------------------------------------------------------------------------- */
2157 
2158 /*!
2159  * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
2160  * @{
2161  */
2162 
2163 /*! @name CHCFG - Channel Configuration register */
2164 #define DMAMUX_CHCFG_SOURCE_MASK                 (0x3FU)
2165 #define DMAMUX_CHCFG_SOURCE_SHIFT                (0U)
2166 #define DMAMUX_CHCFG_SOURCE(x)                   (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)
2167 #define DMAMUX_CHCFG_TRIG_MASK                   (0x40U)
2168 #define DMAMUX_CHCFG_TRIG_SHIFT                  (6U)
2169 #define DMAMUX_CHCFG_TRIG(x)                     (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK)
2170 #define DMAMUX_CHCFG_ENBL_MASK                   (0x80U)
2171 #define DMAMUX_CHCFG_ENBL_SHIFT                  (7U)
2172 #define DMAMUX_CHCFG_ENBL(x)                     (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
2173 
2174 /* The count of DMAMUX_CHCFG */
2175 #define DMAMUX_CHCFG_COUNT                       (4U)
2176 
2177 
2178 /*!
2179  * @}
2180  */ /* end of group DMAMUX_Register_Masks */
2181 
2182 
2183 /* DMAMUX - Peripheral instance base addresses */
2184 /** Peripheral DMAMUX0 base address */
2185 #define DMAMUX0_BASE                             (0x40021000u)
2186 /** Peripheral DMAMUX0 base pointer */
2187 #define DMAMUX0                                  ((DMAMUX_Type *)DMAMUX0_BASE)
2188 /** Array initializer of DMAMUX peripheral base addresses */
2189 #define DMAMUX_BASE_ADDRS                        { DMAMUX0_BASE }
2190 /** Array initializer of DMAMUX peripheral base pointers */
2191 #define DMAMUX_BASE_PTRS                         { DMAMUX0 }
2192 
2193 /*!
2194  * @}
2195  */ /* end of group DMAMUX_Peripheral_Access_Layer */
2196 
2197 
2198 /* ----------------------------------------------------------------------------
2199    -- FGPIO Peripheral Access Layer
2200    ---------------------------------------------------------------------------- */
2201 
2202 /*!
2203  * @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer
2204  * @{
2205  */
2206 
2207 /** FGPIO - Register Layout Typedef */
2208 typedef struct {
2209   __IO uint32_t PDOR;                              /**< Port Data Output Register, offset: 0x0 */
2210   __O  uint32_t PSOR;                              /**< Port Set Output Register, offset: 0x4 */
2211   __O  uint32_t PCOR;                              /**< Port Clear Output Register, offset: 0x8 */
2212   __O  uint32_t PTOR;                              /**< Port Toggle Output Register, offset: 0xC */
2213   __I  uint32_t PDIR;                              /**< Port Data Input Register, offset: 0x10 */
2214   __IO uint32_t PDDR;                              /**< Port Data Direction Register, offset: 0x14 */
2215 } FGPIO_Type;
2216 
2217 /* ----------------------------------------------------------------------------
2218    -- FGPIO Register Masks
2219    ---------------------------------------------------------------------------- */
2220 
2221 /*!
2222  * @addtogroup FGPIO_Register_Masks FGPIO Register Masks
2223  * @{
2224  */
2225 
2226 /*! @name PDOR - Port Data Output Register */
2227 #define FGPIO_PDOR_PDO_MASK                      (0xFFFFFFFFU)
2228 #define FGPIO_PDOR_PDO_SHIFT                     (0U)
2229 #define FGPIO_PDOR_PDO(x)                        (((uint32_t)(((uint32_t)(x)) << FGPIO_PDOR_PDO_SHIFT)) & FGPIO_PDOR_PDO_MASK)
2230 
2231 /*! @name PSOR - Port Set Output Register */
2232 #define FGPIO_PSOR_PTSO_MASK                     (0xFFFFFFFFU)
2233 #define FGPIO_PSOR_PTSO_SHIFT                    (0U)
2234 #define FGPIO_PSOR_PTSO(x)                       (((uint32_t)(((uint32_t)(x)) << FGPIO_PSOR_PTSO_SHIFT)) & FGPIO_PSOR_PTSO_MASK)
2235 
2236 /*! @name PCOR - Port Clear Output Register */
2237 #define FGPIO_PCOR_PTCO_MASK                     (0xFFFFFFFFU)
2238 #define FGPIO_PCOR_PTCO_SHIFT                    (0U)
2239 #define FGPIO_PCOR_PTCO(x)                       (((uint32_t)(((uint32_t)(x)) << FGPIO_PCOR_PTCO_SHIFT)) & FGPIO_PCOR_PTCO_MASK)
2240 
2241 /*! @name PTOR - Port Toggle Output Register */
2242 #define FGPIO_PTOR_PTTO_MASK                     (0xFFFFFFFFU)
2243 #define FGPIO_PTOR_PTTO_SHIFT                    (0U)
2244 #define FGPIO_PTOR_PTTO(x)                       (((uint32_t)(((uint32_t)(x)) << FGPIO_PTOR_PTTO_SHIFT)) & FGPIO_PTOR_PTTO_MASK)
2245 
2246 /*! @name PDIR - Port Data Input Register */
2247 #define FGPIO_PDIR_PDI_MASK                      (0xFFFFFFFFU)
2248 #define FGPIO_PDIR_PDI_SHIFT                     (0U)
2249 #define FGPIO_PDIR_PDI(x)                        (((uint32_t)(((uint32_t)(x)) << FGPIO_PDIR_PDI_SHIFT)) & FGPIO_PDIR_PDI_MASK)
2250 
2251 /*! @name PDDR - Port Data Direction Register */
2252 #define FGPIO_PDDR_PDD_MASK                      (0xFFFFFFFFU)
2253 #define FGPIO_PDDR_PDD_SHIFT                     (0U)
2254 #define FGPIO_PDDR_PDD(x)                        (((uint32_t)(((uint32_t)(x)) << FGPIO_PDDR_PDD_SHIFT)) & FGPIO_PDDR_PDD_MASK)
2255 
2256 
2257 /*!
2258  * @}
2259  */ /* end of group FGPIO_Register_Masks */
2260 
2261 
2262 /* FGPIO - Peripheral instance base addresses */
2263 /** Peripheral FGPIOA base address */
2264 #define FGPIOA_BASE                              (0xF8000000u)
2265 /** Peripheral FGPIOA base pointer */
2266 #define FGPIOA                                   ((FGPIO_Type *)FGPIOA_BASE)
2267 /** Peripheral FGPIOB base address */
2268 #define FGPIOB_BASE                              (0xF8000040u)
2269 /** Peripheral FGPIOB base pointer */
2270 #define FGPIOB                                   ((FGPIO_Type *)FGPIOB_BASE)
2271 /** Peripheral FGPIOC base address */
2272 #define FGPIOC_BASE                              (0xF8000080u)
2273 /** Peripheral FGPIOC base pointer */
2274 #define FGPIOC                                   ((FGPIO_Type *)FGPIOC_BASE)
2275 /** Array initializer of FGPIO peripheral base addresses */
2276 #define FGPIO_BASE_ADDRS                         { FGPIOA_BASE, FGPIOB_BASE, FGPIOC_BASE }
2277 /** Array initializer of FGPIO peripheral base pointers */
2278 #define FGPIO_BASE_PTRS                          { FGPIOA, FGPIOB, FGPIOC }
2279 
2280 /*!
2281  * @}
2282  */ /* end of group FGPIO_Peripheral_Access_Layer */
2283 
2284 
2285 /* ----------------------------------------------------------------------------
2286    -- FTFA Peripheral Access Layer
2287    ---------------------------------------------------------------------------- */
2288 
2289 /*!
2290  * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
2291  * @{
2292  */
2293 
2294 /** FTFA - Register Layout Typedef */
2295 typedef struct {
2296   __IO uint8_t FSTAT;                              /**< Flash Status Register, offset: 0x0 */
2297   __IO uint8_t FCNFG;                              /**< Flash Configuration Register, offset: 0x1 */
2298   __I  uint8_t FSEC;                               /**< Flash Security Register, offset: 0x2 */
2299   __I  uint8_t FOPT;                               /**< Flash Option Register, offset: 0x3 */
2300   __IO uint8_t FCCOB3;                             /**< Flash Common Command Object Registers, offset: 0x4 */
2301   __IO uint8_t FCCOB2;                             /**< Flash Common Command Object Registers, offset: 0x5 */
2302   __IO uint8_t FCCOB1;                             /**< Flash Common Command Object Registers, offset: 0x6 */
2303   __IO uint8_t FCCOB0;                             /**< Flash Common Command Object Registers, offset: 0x7 */
2304   __IO uint8_t FCCOB7;                             /**< Flash Common Command Object Registers, offset: 0x8 */
2305   __IO uint8_t FCCOB6;                             /**< Flash Common Command Object Registers, offset: 0x9 */
2306   __IO uint8_t FCCOB5;                             /**< Flash Common Command Object Registers, offset: 0xA */
2307   __IO uint8_t FCCOB4;                             /**< Flash Common Command Object Registers, offset: 0xB */
2308   __IO uint8_t FCCOBB;                             /**< Flash Common Command Object Registers, offset: 0xC */
2309   __IO uint8_t FCCOBA;                             /**< Flash Common Command Object Registers, offset: 0xD */
2310   __IO uint8_t FCCOB9;                             /**< Flash Common Command Object Registers, offset: 0xE */
2311   __IO uint8_t FCCOB8;                             /**< Flash Common Command Object Registers, offset: 0xF */
2312   __IO uint8_t FPROT3;                             /**< Program Flash Protection Registers, offset: 0x10 */
2313   __IO uint8_t FPROT2;                             /**< Program Flash Protection Registers, offset: 0x11 */
2314   __IO uint8_t FPROT1;                             /**< Program Flash Protection Registers, offset: 0x12 */
2315   __IO uint8_t FPROT0;                             /**< Program Flash Protection Registers, offset: 0x13 */
2316        uint8_t RESERVED_0[4];
2317   __I  uint8_t XACCH3;                             /**< Execute-only Access Registers, offset: 0x18 */
2318   __I  uint8_t XACCH2;                             /**< Execute-only Access Registers, offset: 0x19 */
2319   __I  uint8_t XACCH1;                             /**< Execute-only Access Registers, offset: 0x1A */
2320   __I  uint8_t XACCH0;                             /**< Execute-only Access Registers, offset: 0x1B */
2321   __I  uint8_t XACCL3;                             /**< Execute-only Access Registers, offset: 0x1C */
2322   __I  uint8_t XACCL2;                             /**< Execute-only Access Registers, offset: 0x1D */
2323   __I  uint8_t XACCL1;                             /**< Execute-only Access Registers, offset: 0x1E */
2324   __I  uint8_t XACCL0;                             /**< Execute-only Access Registers, offset: 0x1F */
2325   __I  uint8_t SACCH3;                             /**< Supervisor-only Access Registers, offset: 0x20 */
2326   __I  uint8_t SACCH2;                             /**< Supervisor-only Access Registers, offset: 0x21 */
2327   __I  uint8_t SACCH1;                             /**< Supervisor-only Access Registers, offset: 0x22 */
2328   __I  uint8_t SACCH0;                             /**< Supervisor-only Access Registers, offset: 0x23 */
2329   __I  uint8_t SACCL3;                             /**< Supervisor-only Access Registers, offset: 0x24 */
2330   __I  uint8_t SACCL2;                             /**< Supervisor-only Access Registers, offset: 0x25 */
2331   __I  uint8_t SACCL1;                             /**< Supervisor-only Access Registers, offset: 0x26 */
2332   __I  uint8_t SACCL0;                             /**< Supervisor-only Access Registers, offset: 0x27 */
2333   __I  uint8_t FACSS;                              /**< Flash Access Segment Size Register, offset: 0x28 */
2334        uint8_t RESERVED_1[2];
2335   __I  uint8_t FACSN;                              /**< Flash Access Segment Number Register, offset: 0x2B */
2336 } FTFA_Type;
2337 
2338 /* ----------------------------------------------------------------------------
2339    -- FTFA Register Masks
2340    ---------------------------------------------------------------------------- */
2341 
2342 /*!
2343  * @addtogroup FTFA_Register_Masks FTFA Register Masks
2344  * @{
2345  */
2346 
2347 /*! @name FSTAT - Flash Status Register */
2348 #define FTFA_FSTAT_MGSTAT0_MASK                  (0x1U)
2349 #define FTFA_FSTAT_MGSTAT0_SHIFT                 (0U)
2350 #define FTFA_FSTAT_MGSTAT0(x)                    (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_MGSTAT0_SHIFT)) & FTFA_FSTAT_MGSTAT0_MASK)
2351 #define FTFA_FSTAT_FPVIOL_MASK                   (0x10U)
2352 #define FTFA_FSTAT_FPVIOL_SHIFT                  (4U)
2353 #define FTFA_FSTAT_FPVIOL(x)                     (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_FPVIOL_SHIFT)) & FTFA_FSTAT_FPVIOL_MASK)
2354 #define FTFA_FSTAT_ACCERR_MASK                   (0x20U)
2355 #define FTFA_FSTAT_ACCERR_SHIFT                  (5U)
2356 #define FTFA_FSTAT_ACCERR(x)                     (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_ACCERR_SHIFT)) & FTFA_FSTAT_ACCERR_MASK)
2357 #define FTFA_FSTAT_RDCOLERR_MASK                 (0x40U)
2358 #define FTFA_FSTAT_RDCOLERR_SHIFT                (6U)
2359 #define FTFA_FSTAT_RDCOLERR(x)                   (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_RDCOLERR_SHIFT)) & FTFA_FSTAT_RDCOLERR_MASK)
2360 #define FTFA_FSTAT_CCIF_MASK                     (0x80U)
2361 #define FTFA_FSTAT_CCIF_SHIFT                    (7U)
2362 #define FTFA_FSTAT_CCIF(x)                       (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_CCIF_SHIFT)) & FTFA_FSTAT_CCIF_MASK)
2363 
2364 /*! @name FCNFG - Flash Configuration Register */
2365 #define FTFA_FCNFG_ERSSUSP_MASK                  (0x10U)
2366 #define FTFA_FCNFG_ERSSUSP_SHIFT                 (4U)
2367 #define FTFA_FCNFG_ERSSUSP(x)                    (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSSUSP_SHIFT)) & FTFA_FCNFG_ERSSUSP_MASK)
2368 #define FTFA_FCNFG_ERSAREQ_MASK                  (0x20U)
2369 #define FTFA_FCNFG_ERSAREQ_SHIFT                 (5U)
2370 #define FTFA_FCNFG_ERSAREQ(x)                    (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSAREQ_SHIFT)) & FTFA_FCNFG_ERSAREQ_MASK)
2371 #define FTFA_FCNFG_RDCOLLIE_MASK                 (0x40U)
2372 #define FTFA_FCNFG_RDCOLLIE_SHIFT                (6U)
2373 #define FTFA_FCNFG_RDCOLLIE(x)                   (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_RDCOLLIE_SHIFT)) & FTFA_FCNFG_RDCOLLIE_MASK)
2374 #define FTFA_FCNFG_CCIE_MASK                     (0x80U)
2375 #define FTFA_FCNFG_CCIE_SHIFT                    (7U)
2376 #define FTFA_FCNFG_CCIE(x)                       (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_CCIE_SHIFT)) & FTFA_FCNFG_CCIE_MASK)
2377 
2378 /*! @name FSEC - Flash Security Register */
2379 #define FTFA_FSEC_SEC_MASK                       (0x3U)
2380 #define FTFA_FSEC_SEC_SHIFT                      (0U)
2381 #define FTFA_FSEC_SEC(x)                         (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_SEC_SHIFT)) & FTFA_FSEC_SEC_MASK)
2382 #define FTFA_FSEC_FSLACC_MASK                    (0xCU)
2383 #define FTFA_FSEC_FSLACC_SHIFT                   (2U)
2384 #define FTFA_FSEC_FSLACC(x)                      (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_FSLACC_SHIFT)) & FTFA_FSEC_FSLACC_MASK)
2385 #define FTFA_FSEC_MEEN_MASK                      (0x30U)
2386 #define FTFA_FSEC_MEEN_SHIFT                     (4U)
2387 #define FTFA_FSEC_MEEN(x)                        (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_MEEN_SHIFT)) & FTFA_FSEC_MEEN_MASK)
2388 #define FTFA_FSEC_KEYEN_MASK                     (0xC0U)
2389 #define FTFA_FSEC_KEYEN_SHIFT                    (6U)
2390 #define FTFA_FSEC_KEYEN(x)                       (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_KEYEN_SHIFT)) & FTFA_FSEC_KEYEN_MASK)
2391 
2392 /*! @name FOPT - Flash Option Register */
2393 #define FTFA_FOPT_OPT_MASK                       (0xFFU)
2394 #define FTFA_FOPT_OPT_SHIFT                      (0U)
2395 #define FTFA_FOPT_OPT(x)                         (((uint8_t)(((uint8_t)(x)) << FTFA_FOPT_OPT_SHIFT)) & FTFA_FOPT_OPT_MASK)
2396 
2397 /*! @name FCCOB3 - Flash Common Command Object Registers */
2398 #define FTFA_FCCOB3_CCOBn_MASK                   (0xFFU)
2399 #define FTFA_FCCOB3_CCOBn_SHIFT                  (0U)
2400 #define FTFA_FCCOB3_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB3_CCOBn_SHIFT)) & FTFA_FCCOB3_CCOBn_MASK)
2401 
2402 /*! @name FCCOB2 - Flash Common Command Object Registers */
2403 #define FTFA_FCCOB2_CCOBn_MASK                   (0xFFU)
2404 #define FTFA_FCCOB2_CCOBn_SHIFT                  (0U)
2405 #define FTFA_FCCOB2_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB2_CCOBn_SHIFT)) & FTFA_FCCOB2_CCOBn_MASK)
2406 
2407 /*! @name FCCOB1 - Flash Common Command Object Registers */
2408 #define FTFA_FCCOB1_CCOBn_MASK                   (0xFFU)
2409 #define FTFA_FCCOB1_CCOBn_SHIFT                  (0U)
2410 #define FTFA_FCCOB1_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB1_CCOBn_SHIFT)) & FTFA_FCCOB1_CCOBn_MASK)
2411 
2412 /*! @name FCCOB0 - Flash Common Command Object Registers */
2413 #define FTFA_FCCOB0_CCOBn_MASK                   (0xFFU)
2414 #define FTFA_FCCOB0_CCOBn_SHIFT                  (0U)
2415 #define FTFA_FCCOB0_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB0_CCOBn_SHIFT)) & FTFA_FCCOB0_CCOBn_MASK)
2416 
2417 /*! @name FCCOB7 - Flash Common Command Object Registers */
2418 #define FTFA_FCCOB7_CCOBn_MASK                   (0xFFU)
2419 #define FTFA_FCCOB7_CCOBn_SHIFT                  (0U)
2420 #define FTFA_FCCOB7_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB7_CCOBn_SHIFT)) & FTFA_FCCOB7_CCOBn_MASK)
2421 
2422 /*! @name FCCOB6 - Flash Common Command Object Registers */
2423 #define FTFA_FCCOB6_CCOBn_MASK                   (0xFFU)
2424 #define FTFA_FCCOB6_CCOBn_SHIFT                  (0U)
2425 #define FTFA_FCCOB6_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB6_CCOBn_SHIFT)) & FTFA_FCCOB6_CCOBn_MASK)
2426 
2427 /*! @name FCCOB5 - Flash Common Command Object Registers */
2428 #define FTFA_FCCOB5_CCOBn_MASK                   (0xFFU)
2429 #define FTFA_FCCOB5_CCOBn_SHIFT                  (0U)
2430 #define FTFA_FCCOB5_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB5_CCOBn_SHIFT)) & FTFA_FCCOB5_CCOBn_MASK)
2431 
2432 /*! @name FCCOB4 - Flash Common Command Object Registers */
2433 #define FTFA_FCCOB4_CCOBn_MASK                   (0xFFU)
2434 #define FTFA_FCCOB4_CCOBn_SHIFT                  (0U)
2435 #define FTFA_FCCOB4_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB4_CCOBn_SHIFT)) & FTFA_FCCOB4_CCOBn_MASK)
2436 
2437 /*! @name FCCOBB - Flash Common Command Object Registers */
2438 #define FTFA_FCCOBB_CCOBn_MASK                   (0xFFU)
2439 #define FTFA_FCCOBB_CCOBn_SHIFT                  (0U)
2440 #define FTFA_FCCOBB_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBB_CCOBn_SHIFT)) & FTFA_FCCOBB_CCOBn_MASK)
2441 
2442 /*! @name FCCOBA - Flash Common Command Object Registers */
2443 #define FTFA_FCCOBA_CCOBn_MASK                   (0xFFU)
2444 #define FTFA_FCCOBA_CCOBn_SHIFT                  (0U)
2445 #define FTFA_FCCOBA_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBA_CCOBn_SHIFT)) & FTFA_FCCOBA_CCOBn_MASK)
2446 
2447 /*! @name FCCOB9 - Flash Common Command Object Registers */
2448 #define FTFA_FCCOB9_CCOBn_MASK                   (0xFFU)
2449 #define FTFA_FCCOB9_CCOBn_SHIFT                  (0U)
2450 #define FTFA_FCCOB9_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB9_CCOBn_SHIFT)) & FTFA_FCCOB9_CCOBn_MASK)
2451 
2452 /*! @name FCCOB8 - Flash Common Command Object Registers */
2453 #define FTFA_FCCOB8_CCOBn_MASK                   (0xFFU)
2454 #define FTFA_FCCOB8_CCOBn_SHIFT                  (0U)
2455 #define FTFA_FCCOB8_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB8_CCOBn_SHIFT)) & FTFA_FCCOB8_CCOBn_MASK)
2456 
2457 /*! @name FPROT3 - Program Flash Protection Registers */
2458 #define FTFA_FPROT3_PROT_MASK                    (0xFFU)
2459 #define FTFA_FPROT3_PROT_SHIFT                   (0U)
2460 #define FTFA_FPROT3_PROT(x)                      (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT3_PROT_SHIFT)) & FTFA_FPROT3_PROT_MASK)
2461 
2462 /*! @name FPROT2 - Program Flash Protection Registers */
2463 #define FTFA_FPROT2_PROT_MASK                    (0xFFU)
2464 #define FTFA_FPROT2_PROT_SHIFT                   (0U)
2465 #define FTFA_FPROT2_PROT(x)                      (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT2_PROT_SHIFT)) & FTFA_FPROT2_PROT_MASK)
2466 
2467 /*! @name FPROT1 - Program Flash Protection Registers */
2468 #define FTFA_FPROT1_PROT_MASK                    (0xFFU)
2469 #define FTFA_FPROT1_PROT_SHIFT                   (0U)
2470 #define FTFA_FPROT1_PROT(x)                      (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT1_PROT_SHIFT)) & FTFA_FPROT1_PROT_MASK)
2471 
2472 /*! @name FPROT0 - Program Flash Protection Registers */
2473 #define FTFA_FPROT0_PROT_MASK                    (0xFFU)
2474 #define FTFA_FPROT0_PROT_SHIFT                   (0U)
2475 #define FTFA_FPROT0_PROT(x)                      (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT0_PROT_SHIFT)) & FTFA_FPROT0_PROT_MASK)
2476 
2477 /*! @name XACCH3 - Execute-only Access Registers */
2478 #define FTFA_XACCH3_XA_MASK                      (0xFFU)
2479 #define FTFA_XACCH3_XA_SHIFT                     (0U)
2480 #define FTFA_XACCH3_XA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH3_XA_SHIFT)) & FTFA_XACCH3_XA_MASK)
2481 
2482 /*! @name XACCH2 - Execute-only Access Registers */
2483 #define FTFA_XACCH2_XA_MASK                      (0xFFU)
2484 #define FTFA_XACCH2_XA_SHIFT                     (0U)
2485 #define FTFA_XACCH2_XA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH2_XA_SHIFT)) & FTFA_XACCH2_XA_MASK)
2486 
2487 /*! @name XACCH1 - Execute-only Access Registers */
2488 #define FTFA_XACCH1_XA_MASK                      (0xFFU)
2489 #define FTFA_XACCH1_XA_SHIFT                     (0U)
2490 #define FTFA_XACCH1_XA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH1_XA_SHIFT)) & FTFA_XACCH1_XA_MASK)
2491 
2492 /*! @name XACCH0 - Execute-only Access Registers */
2493 #define FTFA_XACCH0_XA_MASK                      (0xFFU)
2494 #define FTFA_XACCH0_XA_SHIFT                     (0U)
2495 #define FTFA_XACCH0_XA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH0_XA_SHIFT)) & FTFA_XACCH0_XA_MASK)
2496 
2497 /*! @name XACCL3 - Execute-only Access Registers */
2498 #define FTFA_XACCL3_XA_MASK                      (0xFFU)
2499 #define FTFA_XACCL3_XA_SHIFT                     (0U)
2500 #define FTFA_XACCL3_XA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL3_XA_SHIFT)) & FTFA_XACCL3_XA_MASK)
2501 
2502 /*! @name XACCL2 - Execute-only Access Registers */
2503 #define FTFA_XACCL2_XA_MASK                      (0xFFU)
2504 #define FTFA_XACCL2_XA_SHIFT                     (0U)
2505 #define FTFA_XACCL2_XA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL2_XA_SHIFT)) & FTFA_XACCL2_XA_MASK)
2506 
2507 /*! @name XACCL1 - Execute-only Access Registers */
2508 #define FTFA_XACCL1_XA_MASK                      (0xFFU)
2509 #define FTFA_XACCL1_XA_SHIFT                     (0U)
2510 #define FTFA_XACCL1_XA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL1_XA_SHIFT)) & FTFA_XACCL1_XA_MASK)
2511 
2512 /*! @name XACCL0 - Execute-only Access Registers */
2513 #define FTFA_XACCL0_XA_MASK                      (0xFFU)
2514 #define FTFA_XACCL0_XA_SHIFT                     (0U)
2515 #define FTFA_XACCL0_XA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL0_XA_SHIFT)) & FTFA_XACCL0_XA_MASK)
2516 
2517 /*! @name SACCH3 - Supervisor-only Access Registers */
2518 #define FTFA_SACCH3_SA_MASK                      (0xFFU)
2519 #define FTFA_SACCH3_SA_SHIFT                     (0U)
2520 #define FTFA_SACCH3_SA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH3_SA_SHIFT)) & FTFA_SACCH3_SA_MASK)
2521 
2522 /*! @name SACCH2 - Supervisor-only Access Registers */
2523 #define FTFA_SACCH2_SA_MASK                      (0xFFU)
2524 #define FTFA_SACCH2_SA_SHIFT                     (0U)
2525 #define FTFA_SACCH2_SA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH2_SA_SHIFT)) & FTFA_SACCH2_SA_MASK)
2526 
2527 /*! @name SACCH1 - Supervisor-only Access Registers */
2528 #define FTFA_SACCH1_SA_MASK                      (0xFFU)
2529 #define FTFA_SACCH1_SA_SHIFT                     (0U)
2530 #define FTFA_SACCH1_SA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH1_SA_SHIFT)) & FTFA_SACCH1_SA_MASK)
2531 
2532 /*! @name SACCH0 - Supervisor-only Access Registers */
2533 #define FTFA_SACCH0_SA_MASK                      (0xFFU)
2534 #define FTFA_SACCH0_SA_SHIFT                     (0U)
2535 #define FTFA_SACCH0_SA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH0_SA_SHIFT)) & FTFA_SACCH0_SA_MASK)
2536 
2537 /*! @name SACCL3 - Supervisor-only Access Registers */
2538 #define FTFA_SACCL3_SA_MASK                      (0xFFU)
2539 #define FTFA_SACCL3_SA_SHIFT                     (0U)
2540 #define FTFA_SACCL3_SA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL3_SA_SHIFT)) & FTFA_SACCL3_SA_MASK)
2541 
2542 /*! @name SACCL2 - Supervisor-only Access Registers */
2543 #define FTFA_SACCL2_SA_MASK                      (0xFFU)
2544 #define FTFA_SACCL2_SA_SHIFT                     (0U)
2545 #define FTFA_SACCL2_SA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL2_SA_SHIFT)) & FTFA_SACCL2_SA_MASK)
2546 
2547 /*! @name SACCL1 - Supervisor-only Access Registers */
2548 #define FTFA_SACCL1_SA_MASK                      (0xFFU)
2549 #define FTFA_SACCL1_SA_SHIFT                     (0U)
2550 #define FTFA_SACCL1_SA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL1_SA_SHIFT)) & FTFA_SACCL1_SA_MASK)
2551 
2552 /*! @name SACCL0 - Supervisor-only Access Registers */
2553 #define FTFA_SACCL0_SA_MASK                      (0xFFU)
2554 #define FTFA_SACCL0_SA_SHIFT                     (0U)
2555 #define FTFA_SACCL0_SA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL0_SA_SHIFT)) & FTFA_SACCL0_SA_MASK)
2556 
2557 /*! @name FACSS - Flash Access Segment Size Register */
2558 #define FTFA_FACSS_SGSIZE_MASK                   (0xFFU)
2559 #define FTFA_FACSS_SGSIZE_SHIFT                  (0U)
2560 #define FTFA_FACSS_SGSIZE(x)                     (((uint8_t)(((uint8_t)(x)) << FTFA_FACSS_SGSIZE_SHIFT)) & FTFA_FACSS_SGSIZE_MASK)
2561 
2562 /*! @name FACSN - Flash Access Segment Number Register */
2563 #define FTFA_FACSN_NUMSG_MASK                    (0xFFU)
2564 #define FTFA_FACSN_NUMSG_SHIFT                   (0U)
2565 #define FTFA_FACSN_NUMSG(x)                      (((uint8_t)(((uint8_t)(x)) << FTFA_FACSN_NUMSG_SHIFT)) & FTFA_FACSN_NUMSG_MASK)
2566 
2567 
2568 /*!
2569  * @}
2570  */ /* end of group FTFA_Register_Masks */
2571 
2572 
2573 /* FTFA - Peripheral instance base addresses */
2574 /** Peripheral FTFA base address */
2575 #define FTFA_BASE                                (0x40020000u)
2576 /** Peripheral FTFA base pointer */
2577 #define FTFA                                     ((FTFA_Type *)FTFA_BASE)
2578 /** Array initializer of FTFA peripheral base addresses */
2579 #define FTFA_BASE_ADDRS                          { FTFA_BASE }
2580 /** Array initializer of FTFA peripheral base pointers */
2581 #define FTFA_BASE_PTRS                           { FTFA }
2582 /** Interrupt vectors for the FTFA peripheral type */
2583 #define FTFA_COMMAND_COMPLETE_IRQS               { FTFA_IRQn }
2584 
2585 /*!
2586  * @}
2587  */ /* end of group FTFA_Peripheral_Access_Layer */
2588 
2589 
2590 /* ----------------------------------------------------------------------------
2591    -- GENFSK Peripheral Access Layer
2592    ---------------------------------------------------------------------------- */
2593 
2594 /*!
2595  * @addtogroup GENFSK_Peripheral_Access_Layer GENFSK Peripheral Access Layer
2596  * @{
2597  */
2598 
2599 /** GENFSK - Register Layout Typedef */
2600 typedef struct {
2601   __IO uint32_t IRQ_CTRL;                          /**< IRQ CONTROL, offset: 0x0 */
2602   __IO uint32_t EVENT_TMR;                         /**< EVENT TIMER, offset: 0x4 */
2603   __IO uint32_t T1_CMP;                            /**< T1 COMPARE, offset: 0x8 */
2604   __IO uint32_t T2_CMP;                            /**< T2 COMPARE, offset: 0xC */
2605   __I  uint32_t TIMESTAMP;                         /**< TIMESTAMP, offset: 0x10 */
2606   __IO uint32_t XCVR_CTRL;                         /**< TRANSCEIVER CONTROL, offset: 0x14 */
2607   __I  uint32_t XCVR_STS;                          /**< TRANSCEIVER STATUS, offset: 0x18 */
2608   __IO uint32_t XCVR_CFG;                          /**< TRANSCEIVER CONFIGURATION, offset: 0x1C */
2609   __IO uint32_t CHANNEL_NUM;                       /**< CHANNEL NUMBER, offset: 0x20 */
2610   __IO uint32_t TX_POWER;                          /**< TRANSMIT POWER, offset: 0x24 */
2611   __IO uint32_t NTW_ADR_CTRL;                      /**< NETWORK ADDRESS CONTROL, offset: 0x28 */
2612   __IO uint32_t NTW_ADR_0;                         /**< NETWORK ADDRESS 0, offset: 0x2C */
2613   __IO uint32_t NTW_ADR_1;                         /**< NETWORK ADDRESS 1, offset: 0x30 */
2614   __IO uint32_t NTW_ADR_2;                         /**< NETWORK ADDRESS 2, offset: 0x34 */
2615   __IO uint32_t NTW_ADR_3;                         /**< NETWORK ADDRESS 3, offset: 0x38 */
2616   __IO uint32_t RX_WATERMARK;                      /**< RECEIVE WATERMARK, offset: 0x3C */
2617   __IO uint32_t DSM_CTRL;                          /**< DSM CONTROL, offset: 0x40 */
2618   __I  uint32_t PART_ID;                           /**< PART ID, offset: 0x44 */
2619        uint8_t RESERVED_0[24];
2620   __IO uint32_t PACKET_CFG;                        /**< PACKET CONFIGURATION, offset: 0x60 */
2621   __IO uint32_t H0_CFG;                            /**< H0 CONFIGURATION, offset: 0x64 */
2622   __IO uint32_t H1_CFG;                            /**< H1 CONFIGURATION, offset: 0x68 */
2623   __IO uint32_t CRC_CFG;                           /**< CRC CONFIGURATION, offset: 0x6C */
2624   __IO uint32_t CRC_INIT;                          /**< CRC INITIALIZATION, offset: 0x70 */
2625   __IO uint32_t CRC_POLY;                          /**< CRC POLYNOMIAL, offset: 0x74 */
2626   __IO uint32_t CRC_XOR_OUT;                       /**< CRC XOR OUT, offset: 0x78 */
2627   __IO uint32_t WHITEN_CFG;                        /**< WHITENER CONFIGURATION, offset: 0x7C */
2628   __IO uint32_t WHITEN_POLY;                       /**< WHITENER POLYNOMIAL, offset: 0x80 */
2629   __IO uint32_t WHITEN_SZ_THR;                     /**< WHITENER SIZE THRESHOLD, offset: 0x84 */
2630   __IO uint32_t BITRATE;                           /**< BIT RATE, offset: 0x88 */
2631   __IO uint32_t PB_PARTITION;                      /**< PACKET BUFFER PARTITION POINT, offset: 0x8C */
2632 } GENFSK_Type;
2633 
2634 /* ----------------------------------------------------------------------------
2635    -- GENFSK Register Masks
2636    ---------------------------------------------------------------------------- */
2637 
2638 /*!
2639  * @addtogroup GENFSK_Register_Masks GENFSK Register Masks
2640  * @{
2641  */
2642 
2643 /*! @name IRQ_CTRL - IRQ CONTROL */
2644 #define GENFSK_IRQ_CTRL_SEQ_END_IRQ_MASK         (0x1U)
2645 #define GENFSK_IRQ_CTRL_SEQ_END_IRQ_SHIFT        (0U)
2646 #define GENFSK_IRQ_CTRL_SEQ_END_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_SEQ_END_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_SEQ_END_IRQ_MASK)
2647 #define GENFSK_IRQ_CTRL_TX_IRQ_MASK              (0x2U)
2648 #define GENFSK_IRQ_CTRL_TX_IRQ_SHIFT             (1U)
2649 #define GENFSK_IRQ_CTRL_TX_IRQ(x)                (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_TX_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_TX_IRQ_MASK)
2650 #define GENFSK_IRQ_CTRL_RX_IRQ_MASK              (0x4U)
2651 #define GENFSK_IRQ_CTRL_RX_IRQ_SHIFT             (2U)
2652 #define GENFSK_IRQ_CTRL_RX_IRQ(x)                (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_RX_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_RX_IRQ_MASK)
2653 #define GENFSK_IRQ_CTRL_NTW_ADR_IRQ_MASK         (0x8U)
2654 #define GENFSK_IRQ_CTRL_NTW_ADR_IRQ_SHIFT        (3U)
2655 #define GENFSK_IRQ_CTRL_NTW_ADR_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_NTW_ADR_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_NTW_ADR_IRQ_MASK)
2656 #define GENFSK_IRQ_CTRL_T1_IRQ_MASK              (0x10U)
2657 #define GENFSK_IRQ_CTRL_T1_IRQ_SHIFT             (4U)
2658 #define GENFSK_IRQ_CTRL_T1_IRQ(x)                (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_T1_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_T1_IRQ_MASK)
2659 #define GENFSK_IRQ_CTRL_T2_IRQ_MASK              (0x20U)
2660 #define GENFSK_IRQ_CTRL_T2_IRQ_SHIFT             (5U)
2661 #define GENFSK_IRQ_CTRL_T2_IRQ(x)                (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_T2_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_T2_IRQ_MASK)
2662 #define GENFSK_IRQ_CTRL_PLL_UNLOCK_IRQ_MASK      (0x40U)
2663 #define GENFSK_IRQ_CTRL_PLL_UNLOCK_IRQ_SHIFT     (6U)
2664 #define GENFSK_IRQ_CTRL_PLL_UNLOCK_IRQ(x)        (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_PLL_UNLOCK_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_PLL_UNLOCK_IRQ_MASK)
2665 #define GENFSK_IRQ_CTRL_WAKE_IRQ_MASK            (0x80U)
2666 #define GENFSK_IRQ_CTRL_WAKE_IRQ_SHIFT           (7U)
2667 #define GENFSK_IRQ_CTRL_WAKE_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_WAKE_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_WAKE_IRQ_MASK)
2668 #define GENFSK_IRQ_CTRL_RX_WATERMARK_IRQ_MASK    (0x100U)
2669 #define GENFSK_IRQ_CTRL_RX_WATERMARK_IRQ_SHIFT   (8U)
2670 #define GENFSK_IRQ_CTRL_RX_WATERMARK_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_RX_WATERMARK_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_RX_WATERMARK_IRQ_MASK)
2671 #define GENFSK_IRQ_CTRL_TSM_IRQ_MASK             (0x200U)
2672 #define GENFSK_IRQ_CTRL_TSM_IRQ_SHIFT            (9U)
2673 #define GENFSK_IRQ_CTRL_TSM_IRQ(x)               (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_TSM_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_TSM_IRQ_MASK)
2674 #define GENFSK_IRQ_CTRL_SEQ_END_IRQ_EN_MASK      (0x10000U)
2675 #define GENFSK_IRQ_CTRL_SEQ_END_IRQ_EN_SHIFT     (16U)
2676 #define GENFSK_IRQ_CTRL_SEQ_END_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_SEQ_END_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_SEQ_END_IRQ_EN_MASK)
2677 #define GENFSK_IRQ_CTRL_TX_IRQ_EN_MASK           (0x20000U)
2678 #define GENFSK_IRQ_CTRL_TX_IRQ_EN_SHIFT          (17U)
2679 #define GENFSK_IRQ_CTRL_TX_IRQ_EN(x)             (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_TX_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_TX_IRQ_EN_MASK)
2680 #define GENFSK_IRQ_CTRL_RX_IRQ_EN_MASK           (0x40000U)
2681 #define GENFSK_IRQ_CTRL_RX_IRQ_EN_SHIFT          (18U)
2682 #define GENFSK_IRQ_CTRL_RX_IRQ_EN(x)             (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_RX_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_RX_IRQ_EN_MASK)
2683 #define GENFSK_IRQ_CTRL_NTW_ADR_IRQ_EN_MASK      (0x80000U)
2684 #define GENFSK_IRQ_CTRL_NTW_ADR_IRQ_EN_SHIFT     (19U)
2685 #define GENFSK_IRQ_CTRL_NTW_ADR_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_NTW_ADR_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_NTW_ADR_IRQ_EN_MASK)
2686 #define GENFSK_IRQ_CTRL_T1_IRQ_EN_MASK           (0x100000U)
2687 #define GENFSK_IRQ_CTRL_T1_IRQ_EN_SHIFT          (20U)
2688 #define GENFSK_IRQ_CTRL_T1_IRQ_EN(x)             (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_T1_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_T1_IRQ_EN_MASK)
2689 #define GENFSK_IRQ_CTRL_T2_IRQ_EN_MASK           (0x200000U)
2690 #define GENFSK_IRQ_CTRL_T2_IRQ_EN_SHIFT          (21U)
2691 #define GENFSK_IRQ_CTRL_T2_IRQ_EN(x)             (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_T2_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_T2_IRQ_EN_MASK)
2692 #define GENFSK_IRQ_CTRL_PLL_UNLOCK_IRQ_EN_MASK   (0x400000U)
2693 #define GENFSK_IRQ_CTRL_PLL_UNLOCK_IRQ_EN_SHIFT  (22U)
2694 #define GENFSK_IRQ_CTRL_PLL_UNLOCK_IRQ_EN(x)     (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_PLL_UNLOCK_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_PLL_UNLOCK_IRQ_EN_MASK)
2695 #define GENFSK_IRQ_CTRL_WAKE_IRQ_EN_MASK         (0x800000U)
2696 #define GENFSK_IRQ_CTRL_WAKE_IRQ_EN_SHIFT        (23U)
2697 #define GENFSK_IRQ_CTRL_WAKE_IRQ_EN(x)           (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_WAKE_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_WAKE_IRQ_EN_MASK)
2698 #define GENFSK_IRQ_CTRL_RX_WATERMARK_IRQ_EN_MASK (0x1000000U)
2699 #define GENFSK_IRQ_CTRL_RX_WATERMARK_IRQ_EN_SHIFT (24U)
2700 #define GENFSK_IRQ_CTRL_RX_WATERMARK_IRQ_EN(x)   (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_RX_WATERMARK_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_RX_WATERMARK_IRQ_EN_MASK)
2701 #define GENFSK_IRQ_CTRL_TSM_IRQ_EN_MASK          (0x2000000U)
2702 #define GENFSK_IRQ_CTRL_TSM_IRQ_EN_SHIFT         (25U)
2703 #define GENFSK_IRQ_CTRL_TSM_IRQ_EN(x)            (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_TSM_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_TSM_IRQ_EN_MASK)
2704 #define GENFSK_IRQ_CTRL_GENERIC_FSK_IRQ_EN_MASK  (0x4000000U)
2705 #define GENFSK_IRQ_CTRL_GENERIC_FSK_IRQ_EN_SHIFT (26U)
2706 #define GENFSK_IRQ_CTRL_GENERIC_FSK_IRQ_EN(x)    (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_GENERIC_FSK_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_GENERIC_FSK_IRQ_EN_MASK)
2707 #define GENFSK_IRQ_CTRL_CRC_IGNORE_MASK          (0x8000000U)
2708 #define GENFSK_IRQ_CTRL_CRC_IGNORE_SHIFT         (27U)
2709 #define GENFSK_IRQ_CTRL_CRC_IGNORE(x)            (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_CRC_IGNORE_SHIFT)) & GENFSK_IRQ_CTRL_CRC_IGNORE_MASK)
2710 #define GENFSK_IRQ_CTRL_CRC_VALID_MASK           (0x80000000U)
2711 #define GENFSK_IRQ_CTRL_CRC_VALID_SHIFT          (31U)
2712 #define GENFSK_IRQ_CTRL_CRC_VALID(x)             (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_CRC_VALID_SHIFT)) & GENFSK_IRQ_CTRL_CRC_VALID_MASK)
2713 
2714 /*! @name EVENT_TMR - EVENT TIMER */
2715 #define GENFSK_EVENT_TMR_EVENT_TMR_MASK          (0xFFFFFFU)
2716 #define GENFSK_EVENT_TMR_EVENT_TMR_SHIFT         (0U)
2717 #define GENFSK_EVENT_TMR_EVENT_TMR(x)            (((uint32_t)(((uint32_t)(x)) << GENFSK_EVENT_TMR_EVENT_TMR_SHIFT)) & GENFSK_EVENT_TMR_EVENT_TMR_MASK)
2718 #define GENFSK_EVENT_TMR_EVENT_TMR_LD_MASK       (0x1000000U)
2719 #define GENFSK_EVENT_TMR_EVENT_TMR_LD_SHIFT      (24U)
2720 #define GENFSK_EVENT_TMR_EVENT_TMR_LD(x)         (((uint32_t)(((uint32_t)(x)) << GENFSK_EVENT_TMR_EVENT_TMR_LD_SHIFT)) & GENFSK_EVENT_TMR_EVENT_TMR_LD_MASK)
2721 #define GENFSK_EVENT_TMR_EVENT_TMR_ADD_MASK      (0x2000000U)
2722 #define GENFSK_EVENT_TMR_EVENT_TMR_ADD_SHIFT     (25U)
2723 #define GENFSK_EVENT_TMR_EVENT_TMR_ADD(x)        (((uint32_t)(((uint32_t)(x)) << GENFSK_EVENT_TMR_EVENT_TMR_ADD_SHIFT)) & GENFSK_EVENT_TMR_EVENT_TMR_ADD_MASK)
2724 
2725 /*! @name T1_CMP - T1 COMPARE */
2726 #define GENFSK_T1_CMP_T1_CMP_MASK                (0xFFFFFFU)
2727 #define GENFSK_T1_CMP_T1_CMP_SHIFT               (0U)
2728 #define GENFSK_T1_CMP_T1_CMP(x)                  (((uint32_t)(((uint32_t)(x)) << GENFSK_T1_CMP_T1_CMP_SHIFT)) & GENFSK_T1_CMP_T1_CMP_MASK)
2729 #define GENFSK_T1_CMP_T1_CMP_EN_MASK             (0x1000000U)
2730 #define GENFSK_T1_CMP_T1_CMP_EN_SHIFT            (24U)
2731 #define GENFSK_T1_CMP_T1_CMP_EN(x)               (((uint32_t)(((uint32_t)(x)) << GENFSK_T1_CMP_T1_CMP_EN_SHIFT)) & GENFSK_T1_CMP_T1_CMP_EN_MASK)
2732 
2733 /*! @name T2_CMP - T2 COMPARE */
2734 #define GENFSK_T2_CMP_T2_CMP_MASK                (0xFFFFFFU)
2735 #define GENFSK_T2_CMP_T2_CMP_SHIFT               (0U)
2736 #define GENFSK_T2_CMP_T2_CMP(x)                  (((uint32_t)(((uint32_t)(x)) << GENFSK_T2_CMP_T2_CMP_SHIFT)) & GENFSK_T2_CMP_T2_CMP_MASK)
2737 #define GENFSK_T2_CMP_T2_CMP_EN_MASK             (0x1000000U)
2738 #define GENFSK_T2_CMP_T2_CMP_EN_SHIFT            (24U)
2739 #define GENFSK_T2_CMP_T2_CMP_EN(x)               (((uint32_t)(((uint32_t)(x)) << GENFSK_T2_CMP_T2_CMP_EN_SHIFT)) & GENFSK_T2_CMP_T2_CMP_EN_MASK)
2740 
2741 /*! @name TIMESTAMP - TIMESTAMP */
2742 #define GENFSK_TIMESTAMP_TIMESTAMP_MASK          (0xFFFFFFU)
2743 #define GENFSK_TIMESTAMP_TIMESTAMP_SHIFT         (0U)
2744 #define GENFSK_TIMESTAMP_TIMESTAMP(x)            (((uint32_t)(((uint32_t)(x)) << GENFSK_TIMESTAMP_TIMESTAMP_SHIFT)) & GENFSK_TIMESTAMP_TIMESTAMP_MASK)
2745 
2746 /*! @name XCVR_CTRL - TRANSCEIVER CONTROL */
2747 #define GENFSK_XCVR_CTRL_SEQCMD_MASK             (0xFU)
2748 #define GENFSK_XCVR_CTRL_SEQCMD_SHIFT            (0U)
2749 #define GENFSK_XCVR_CTRL_SEQCMD(x)               (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CTRL_SEQCMD_SHIFT)) & GENFSK_XCVR_CTRL_SEQCMD_MASK)
2750 #define GENFSK_XCVR_CTRL_CMDDEC_CS_MASK          (0x7000000U)
2751 #define GENFSK_XCVR_CTRL_CMDDEC_CS_SHIFT         (24U)
2752 #define GENFSK_XCVR_CTRL_CMDDEC_CS(x)            (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CTRL_CMDDEC_CS_SHIFT)) & GENFSK_XCVR_CTRL_CMDDEC_CS_MASK)
2753 #define GENFSK_XCVR_CTRL_XCVR_BUSY_MASK          (0x80000000U)
2754 #define GENFSK_XCVR_CTRL_XCVR_BUSY_SHIFT         (31U)
2755 #define GENFSK_XCVR_CTRL_XCVR_BUSY(x)            (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CTRL_XCVR_BUSY_SHIFT)) & GENFSK_XCVR_CTRL_XCVR_BUSY_MASK)
2756 
2757 /*! @name XCVR_STS - TRANSCEIVER STATUS */
2758 #define GENFSK_XCVR_STS_TX_START_T1_PEND_MASK    (0x1U)
2759 #define GENFSK_XCVR_STS_TX_START_T1_PEND_SHIFT   (0U)
2760 #define GENFSK_XCVR_STS_TX_START_T1_PEND(x)      (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_TX_START_T1_PEND_SHIFT)) & GENFSK_XCVR_STS_TX_START_T1_PEND_MASK)
2761 #define GENFSK_XCVR_STS_TX_START_T2_PEND_MASK    (0x2U)
2762 #define GENFSK_XCVR_STS_TX_START_T2_PEND_SHIFT   (1U)
2763 #define GENFSK_XCVR_STS_TX_START_T2_PEND(x)      (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_TX_START_T2_PEND_SHIFT)) & GENFSK_XCVR_STS_TX_START_T2_PEND_MASK)
2764 #define GENFSK_XCVR_STS_TX_IN_WARMUP_MASK        (0x4U)
2765 #define GENFSK_XCVR_STS_TX_IN_WARMUP_SHIFT       (2U)
2766 #define GENFSK_XCVR_STS_TX_IN_WARMUP(x)          (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_TX_IN_WARMUP_SHIFT)) & GENFSK_XCVR_STS_TX_IN_WARMUP_MASK)
2767 #define GENFSK_XCVR_STS_TX_IN_PROGRESS_MASK      (0x8U)
2768 #define GENFSK_XCVR_STS_TX_IN_PROGRESS_SHIFT     (3U)
2769 #define GENFSK_XCVR_STS_TX_IN_PROGRESS(x)        (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_TX_IN_PROGRESS_SHIFT)) & GENFSK_XCVR_STS_TX_IN_PROGRESS_MASK)
2770 #define GENFSK_XCVR_STS_TX_IN_WARMDN_MASK        (0x10U)
2771 #define GENFSK_XCVR_STS_TX_IN_WARMDN_SHIFT       (4U)
2772 #define GENFSK_XCVR_STS_TX_IN_WARMDN(x)          (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_TX_IN_WARMDN_SHIFT)) & GENFSK_XCVR_STS_TX_IN_WARMDN_MASK)
2773 #define GENFSK_XCVR_STS_RX_START_T1_PEND_MASK    (0x20U)
2774 #define GENFSK_XCVR_STS_RX_START_T1_PEND_SHIFT   (5U)
2775 #define GENFSK_XCVR_STS_RX_START_T1_PEND(x)      (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_RX_START_T1_PEND_SHIFT)) & GENFSK_XCVR_STS_RX_START_T1_PEND_MASK)
2776 #define GENFSK_XCVR_STS_RX_START_T2_PEND_MASK    (0x40U)
2777 #define GENFSK_XCVR_STS_RX_START_T2_PEND_SHIFT   (6U)
2778 #define GENFSK_XCVR_STS_RX_START_T2_PEND(x)      (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_RX_START_T2_PEND_SHIFT)) & GENFSK_XCVR_STS_RX_START_T2_PEND_MASK)
2779 #define GENFSK_XCVR_STS_RX_STOP_T1_PEND_MASK     (0x80U)
2780 #define GENFSK_XCVR_STS_RX_STOP_T1_PEND_SHIFT    (7U)
2781 #define GENFSK_XCVR_STS_RX_STOP_T1_PEND(x)       (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_RX_STOP_T1_PEND_SHIFT)) & GENFSK_XCVR_STS_RX_STOP_T1_PEND_MASK)
2782 #define GENFSK_XCVR_STS_RX_STOP_T2_PEND_MASK     (0x100U)
2783 #define GENFSK_XCVR_STS_RX_STOP_T2_PEND_SHIFT    (8U)
2784 #define GENFSK_XCVR_STS_RX_STOP_T2_PEND(x)       (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_RX_STOP_T2_PEND_SHIFT)) & GENFSK_XCVR_STS_RX_STOP_T2_PEND_MASK)
2785 #define GENFSK_XCVR_STS_RX_IN_WARMUP_MASK        (0x200U)
2786 #define GENFSK_XCVR_STS_RX_IN_WARMUP_SHIFT       (9U)
2787 #define GENFSK_XCVR_STS_RX_IN_WARMUP(x)          (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_RX_IN_WARMUP_SHIFT)) & GENFSK_XCVR_STS_RX_IN_WARMUP_MASK)
2788 #define GENFSK_XCVR_STS_RX_IN_SEARCH_MASK        (0x400U)
2789 #define GENFSK_XCVR_STS_RX_IN_SEARCH_SHIFT       (10U)
2790 #define GENFSK_XCVR_STS_RX_IN_SEARCH(x)          (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_RX_IN_SEARCH_SHIFT)) & GENFSK_XCVR_STS_RX_IN_SEARCH_MASK)
2791 #define GENFSK_XCVR_STS_RX_IN_PROGRESS_MASK      (0x800U)
2792 #define GENFSK_XCVR_STS_RX_IN_PROGRESS_SHIFT     (11U)
2793 #define GENFSK_XCVR_STS_RX_IN_PROGRESS(x)        (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_RX_IN_PROGRESS_SHIFT)) & GENFSK_XCVR_STS_RX_IN_PROGRESS_MASK)
2794 #define GENFSK_XCVR_STS_RX_IN_WARMDN_MASK        (0x1000U)
2795 #define GENFSK_XCVR_STS_RX_IN_WARMDN_SHIFT       (12U)
2796 #define GENFSK_XCVR_STS_RX_IN_WARMDN(x)          (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_RX_IN_WARMDN_SHIFT)) & GENFSK_XCVR_STS_RX_IN_WARMDN_MASK)
2797 #define GENFSK_XCVR_STS_LQI_VALID_MASK           (0x4000U)
2798 #define GENFSK_XCVR_STS_LQI_VALID_SHIFT          (14U)
2799 #define GENFSK_XCVR_STS_LQI_VALID(x)             (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_LQI_VALID_SHIFT)) & GENFSK_XCVR_STS_LQI_VALID_MASK)
2800 #define GENFSK_XCVR_STS_CRC_VALID_MASK           (0x8000U)
2801 #define GENFSK_XCVR_STS_CRC_VALID_SHIFT          (15U)
2802 #define GENFSK_XCVR_STS_CRC_VALID(x)             (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_CRC_VALID_SHIFT)) & GENFSK_XCVR_STS_CRC_VALID_MASK)
2803 #define GENFSK_XCVR_STS_RSSI_MASK                (0xFF0000U)
2804 #define GENFSK_XCVR_STS_RSSI_SHIFT               (16U)
2805 #define GENFSK_XCVR_STS_RSSI(x)                  (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_RSSI_SHIFT)) & GENFSK_XCVR_STS_RSSI_MASK)
2806 #define GENFSK_XCVR_STS_LQI_MASK                 (0xFF000000U)
2807 #define GENFSK_XCVR_STS_LQI_SHIFT                (24U)
2808 #define GENFSK_XCVR_STS_LQI(x)                   (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_LQI_SHIFT)) & GENFSK_XCVR_STS_LQI_MASK)
2809 
2810 /*! @name XCVR_CFG - TRANSCEIVER CONFIGURATION */
2811 #define GENFSK_XCVR_CFG_TX_WHITEN_DIS_MASK       (0x1U)
2812 #define GENFSK_XCVR_CFG_TX_WHITEN_DIS_SHIFT      (0U)
2813 #define GENFSK_XCVR_CFG_TX_WHITEN_DIS(x)         (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CFG_TX_WHITEN_DIS_SHIFT)) & GENFSK_XCVR_CFG_TX_WHITEN_DIS_MASK)
2814 #define GENFSK_XCVR_CFG_RX_DEWHITEN_DIS_MASK     (0x2U)
2815 #define GENFSK_XCVR_CFG_RX_DEWHITEN_DIS_SHIFT    (1U)
2816 #define GENFSK_XCVR_CFG_RX_DEWHITEN_DIS(x)       (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CFG_RX_DEWHITEN_DIS_SHIFT)) & GENFSK_XCVR_CFG_RX_DEWHITEN_DIS_MASK)
2817 #define GENFSK_XCVR_CFG_SW_CRC_EN_MASK           (0x4U)
2818 #define GENFSK_XCVR_CFG_SW_CRC_EN_SHIFT          (2U)
2819 #define GENFSK_XCVR_CFG_SW_CRC_EN(x)             (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CFG_SW_CRC_EN_SHIFT)) & GENFSK_XCVR_CFG_SW_CRC_EN_MASK)
2820 #define GENFSK_XCVR_CFG_PREAMBLE_SZ_MASK         (0x70U)
2821 #define GENFSK_XCVR_CFG_PREAMBLE_SZ_SHIFT        (4U)
2822 #define GENFSK_XCVR_CFG_PREAMBLE_SZ(x)           (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CFG_PREAMBLE_SZ_SHIFT)) & GENFSK_XCVR_CFG_PREAMBLE_SZ_MASK)
2823 #define GENFSK_XCVR_CFG_TX_WARMUP_MASK           (0xFF00U)
2824 #define GENFSK_XCVR_CFG_TX_WARMUP_SHIFT          (8U)
2825 #define GENFSK_XCVR_CFG_TX_WARMUP(x)             (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CFG_TX_WARMUP_SHIFT)) & GENFSK_XCVR_CFG_TX_WARMUP_MASK)
2826 #define GENFSK_XCVR_CFG_RX_WARMUP_MASK           (0xFF0000U)
2827 #define GENFSK_XCVR_CFG_RX_WARMUP_SHIFT          (16U)
2828 #define GENFSK_XCVR_CFG_RX_WARMUP(x)             (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CFG_RX_WARMUP_SHIFT)) & GENFSK_XCVR_CFG_RX_WARMUP_MASK)
2829 
2830 /*! @name CHANNEL_NUM - CHANNEL NUMBER */
2831 #define GENFSK_CHANNEL_NUM_CHANNEL_NUM_MASK      (0x7FU)
2832 #define GENFSK_CHANNEL_NUM_CHANNEL_NUM_SHIFT     (0U)
2833 #define GENFSK_CHANNEL_NUM_CHANNEL_NUM(x)        (((uint32_t)(((uint32_t)(x)) << GENFSK_CHANNEL_NUM_CHANNEL_NUM_SHIFT)) & GENFSK_CHANNEL_NUM_CHANNEL_NUM_MASK)
2834 
2835 /*! @name TX_POWER - TRANSMIT POWER */
2836 #define GENFSK_TX_POWER_TX_POWER_MASK            (0x3FU)
2837 #define GENFSK_TX_POWER_TX_POWER_SHIFT           (0U)
2838 #define GENFSK_TX_POWER_TX_POWER(x)              (((uint32_t)(((uint32_t)(x)) << GENFSK_TX_POWER_TX_POWER_SHIFT)) & GENFSK_TX_POWER_TX_POWER_MASK)
2839 
2840 /*! @name NTW_ADR_CTRL - NETWORK ADDRESS CONTROL */
2841 #define GENFSK_NTW_ADR_CTRL_NTW_ADR_EN_MASK      (0xFU)
2842 #define GENFSK_NTW_ADR_CTRL_NTW_ADR_EN_SHIFT     (0U)
2843 #define GENFSK_NTW_ADR_CTRL_NTW_ADR_EN(x)        (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_CTRL_NTW_ADR_EN_SHIFT)) & GENFSK_NTW_ADR_CTRL_NTW_ADR_EN_MASK)
2844 #define GENFSK_NTW_ADR_CTRL_NTW_ADR_MCH_MASK     (0xF0U)
2845 #define GENFSK_NTW_ADR_CTRL_NTW_ADR_MCH_SHIFT    (4U)
2846 #define GENFSK_NTW_ADR_CTRL_NTW_ADR_MCH(x)       (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_CTRL_NTW_ADR_MCH_SHIFT)) & GENFSK_NTW_ADR_CTRL_NTW_ADR_MCH_MASK)
2847 #define GENFSK_NTW_ADR_CTRL_NTW_ADR0_SZ_MASK     (0x300U)
2848 #define GENFSK_NTW_ADR_CTRL_NTW_ADR0_SZ_SHIFT    (8U)
2849 #define GENFSK_NTW_ADR_CTRL_NTW_ADR0_SZ(x)       (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_CTRL_NTW_ADR0_SZ_SHIFT)) & GENFSK_NTW_ADR_CTRL_NTW_ADR0_SZ_MASK)
2850 #define GENFSK_NTW_ADR_CTRL_NTW_ADR1_SZ_MASK     (0xC00U)
2851 #define GENFSK_NTW_ADR_CTRL_NTW_ADR1_SZ_SHIFT    (10U)
2852 #define GENFSK_NTW_ADR_CTRL_NTW_ADR1_SZ(x)       (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_CTRL_NTW_ADR1_SZ_SHIFT)) & GENFSK_NTW_ADR_CTRL_NTW_ADR1_SZ_MASK)
2853 #define GENFSK_NTW_ADR_CTRL_NTW_ADR2_SZ_MASK     (0x3000U)
2854 #define GENFSK_NTW_ADR_CTRL_NTW_ADR2_SZ_SHIFT    (12U)
2855 #define GENFSK_NTW_ADR_CTRL_NTW_ADR2_SZ(x)       (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_CTRL_NTW_ADR2_SZ_SHIFT)) & GENFSK_NTW_ADR_CTRL_NTW_ADR2_SZ_MASK)
2856 #define GENFSK_NTW_ADR_CTRL_NTW_ADR3_SZ_MASK     (0xC000U)
2857 #define GENFSK_NTW_ADR_CTRL_NTW_ADR3_SZ_SHIFT    (14U)
2858 #define GENFSK_NTW_ADR_CTRL_NTW_ADR3_SZ(x)       (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_CTRL_NTW_ADR3_SZ_SHIFT)) & GENFSK_NTW_ADR_CTRL_NTW_ADR3_SZ_MASK)
2859 #define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR0_MASK    (0x70000U)
2860 #define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR0_SHIFT   (16U)
2861 #define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR0(x)      (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_CTRL_NTW_ADR_THR0_SHIFT)) & GENFSK_NTW_ADR_CTRL_NTW_ADR_THR0_MASK)
2862 #define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR1_MASK    (0x700000U)
2863 #define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR1_SHIFT   (20U)
2864 #define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR1(x)      (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_CTRL_NTW_ADR_THR1_SHIFT)) & GENFSK_NTW_ADR_CTRL_NTW_ADR_THR1_MASK)
2865 #define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR2_MASK    (0x7000000U)
2866 #define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR2_SHIFT   (24U)
2867 #define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR2(x)      (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_CTRL_NTW_ADR_THR2_SHIFT)) & GENFSK_NTW_ADR_CTRL_NTW_ADR_THR2_MASK)
2868 #define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR3_MASK    (0x70000000U)
2869 #define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR3_SHIFT   (28U)
2870 #define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR3(x)      (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_CTRL_NTW_ADR_THR3_SHIFT)) & GENFSK_NTW_ADR_CTRL_NTW_ADR_THR3_MASK)
2871 
2872 /*! @name NTW_ADR_0 - NETWORK ADDRESS 0 */
2873 #define GENFSK_NTW_ADR_0_NTW_ADR_0_MASK          (0xFFFFFFFFU)
2874 #define GENFSK_NTW_ADR_0_NTW_ADR_0_SHIFT         (0U)
2875 #define GENFSK_NTW_ADR_0_NTW_ADR_0(x)            (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_0_NTW_ADR_0_SHIFT)) & GENFSK_NTW_ADR_0_NTW_ADR_0_MASK)
2876 
2877 /*! @name NTW_ADR_1 - NETWORK ADDRESS 1 */
2878 #define GENFSK_NTW_ADR_1_NTW_ADR_1_MASK          (0xFFFFFFFFU)
2879 #define GENFSK_NTW_ADR_1_NTW_ADR_1_SHIFT         (0U)
2880 #define GENFSK_NTW_ADR_1_NTW_ADR_1(x)            (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_1_NTW_ADR_1_SHIFT)) & GENFSK_NTW_ADR_1_NTW_ADR_1_MASK)
2881 
2882 /*! @name NTW_ADR_2 - NETWORK ADDRESS 2 */
2883 #define GENFSK_NTW_ADR_2_NTW_ADR_2_MASK          (0xFFFFFFFFU)
2884 #define GENFSK_NTW_ADR_2_NTW_ADR_2_SHIFT         (0U)
2885 #define GENFSK_NTW_ADR_2_NTW_ADR_2(x)            (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_2_NTW_ADR_2_SHIFT)) & GENFSK_NTW_ADR_2_NTW_ADR_2_MASK)
2886 
2887 /*! @name NTW_ADR_3 - NETWORK ADDRESS 3 */
2888 #define GENFSK_NTW_ADR_3_NTW_ADR_3_MASK          (0xFFFFFFFFU)
2889 #define GENFSK_NTW_ADR_3_NTW_ADR_3_SHIFT         (0U)
2890 #define GENFSK_NTW_ADR_3_NTW_ADR_3(x)            (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_3_NTW_ADR_3_SHIFT)) & GENFSK_NTW_ADR_3_NTW_ADR_3_MASK)
2891 
2892 /*! @name RX_WATERMARK - RECEIVE WATERMARK */
2893 #define GENFSK_RX_WATERMARK_RX_WATERMARK_MASK    (0x1FFFU)
2894 #define GENFSK_RX_WATERMARK_RX_WATERMARK_SHIFT   (0U)
2895 #define GENFSK_RX_WATERMARK_RX_WATERMARK(x)      (((uint32_t)(((uint32_t)(x)) << GENFSK_RX_WATERMARK_RX_WATERMARK_SHIFT)) & GENFSK_RX_WATERMARK_RX_WATERMARK_MASK)
2896 #define GENFSK_RX_WATERMARK_BYTE_COUNTER_MASK    (0x1FFF0000U)
2897 #define GENFSK_RX_WATERMARK_BYTE_COUNTER_SHIFT   (16U)
2898 #define GENFSK_RX_WATERMARK_BYTE_COUNTER(x)      (((uint32_t)(((uint32_t)(x)) << GENFSK_RX_WATERMARK_BYTE_COUNTER_SHIFT)) & GENFSK_RX_WATERMARK_BYTE_COUNTER_MASK)
2899 
2900 /*! @name DSM_CTRL - DSM CONTROL */
2901 #define GENFSK_DSM_CTRL_GENERIC_FSK_SLEEP_EN_MASK (0x1U)
2902 #define GENFSK_DSM_CTRL_GENERIC_FSK_SLEEP_EN_SHIFT (0U)
2903 #define GENFSK_DSM_CTRL_GENERIC_FSK_SLEEP_EN(x)  (((uint32_t)(((uint32_t)(x)) << GENFSK_DSM_CTRL_GENERIC_FSK_SLEEP_EN_SHIFT)) & GENFSK_DSM_CTRL_GENERIC_FSK_SLEEP_EN_MASK)
2904 
2905 /*! @name PART_ID - PART ID */
2906 #define GENFSK_PART_ID_PART_ID_MASK              (0xFFU)
2907 #define GENFSK_PART_ID_PART_ID_SHIFT             (0U)
2908 #define GENFSK_PART_ID_PART_ID(x)                (((uint32_t)(((uint32_t)(x)) << GENFSK_PART_ID_PART_ID_SHIFT)) & GENFSK_PART_ID_PART_ID_MASK)
2909 
2910 /*! @name PACKET_CFG - PACKET CONFIGURATION */
2911 #define GENFSK_PACKET_CFG_LENGTH_SZ_MASK         (0x1FU)
2912 #define GENFSK_PACKET_CFG_LENGTH_SZ_SHIFT        (0U)
2913 #define GENFSK_PACKET_CFG_LENGTH_SZ(x)           (((uint32_t)(((uint32_t)(x)) << GENFSK_PACKET_CFG_LENGTH_SZ_SHIFT)) & GENFSK_PACKET_CFG_LENGTH_SZ_MASK)
2914 #define GENFSK_PACKET_CFG_LENGTH_BIT_ORD_MASK    (0x20U)
2915 #define GENFSK_PACKET_CFG_LENGTH_BIT_ORD_SHIFT   (5U)
2916 #define GENFSK_PACKET_CFG_LENGTH_BIT_ORD(x)      (((uint32_t)(((uint32_t)(x)) << GENFSK_PACKET_CFG_LENGTH_BIT_ORD_SHIFT)) & GENFSK_PACKET_CFG_LENGTH_BIT_ORD_MASK)
2917 #define GENFSK_PACKET_CFG_SYNC_ADDR_SZ_MASK      (0xC0U)
2918 #define GENFSK_PACKET_CFG_SYNC_ADDR_SZ_SHIFT     (6U)
2919 #define GENFSK_PACKET_CFG_SYNC_ADDR_SZ(x)        (((uint32_t)(((uint32_t)(x)) << GENFSK_PACKET_CFG_SYNC_ADDR_SZ_SHIFT)) & GENFSK_PACKET_CFG_SYNC_ADDR_SZ_MASK)
2920 #define GENFSK_PACKET_CFG_LENGTH_ADJ_MASK        (0x3F00U)
2921 #define GENFSK_PACKET_CFG_LENGTH_ADJ_SHIFT       (8U)
2922 #define GENFSK_PACKET_CFG_LENGTH_ADJ(x)          (((uint32_t)(((uint32_t)(x)) << GENFSK_PACKET_CFG_LENGTH_ADJ_SHIFT)) & GENFSK_PACKET_CFG_LENGTH_ADJ_MASK)
2923 #define GENFSK_PACKET_CFG_LENGTH_FAIL_MASK       (0x8000U)
2924 #define GENFSK_PACKET_CFG_LENGTH_FAIL_SHIFT      (15U)
2925 #define GENFSK_PACKET_CFG_LENGTH_FAIL(x)         (((uint32_t)(((uint32_t)(x)) << GENFSK_PACKET_CFG_LENGTH_FAIL_SHIFT)) & GENFSK_PACKET_CFG_LENGTH_FAIL_MASK)
2926 #define GENFSK_PACKET_CFG_H0_SZ_MASK             (0x1F0000U)
2927 #define GENFSK_PACKET_CFG_H0_SZ_SHIFT            (16U)
2928 #define GENFSK_PACKET_CFG_H0_SZ(x)               (((uint32_t)(((uint32_t)(x)) << GENFSK_PACKET_CFG_H0_SZ_SHIFT)) & GENFSK_PACKET_CFG_H0_SZ_MASK)
2929 #define GENFSK_PACKET_CFG_H0_FAIL_MASK           (0x800000U)
2930 #define GENFSK_PACKET_CFG_H0_FAIL_SHIFT          (23U)
2931 #define GENFSK_PACKET_CFG_H0_FAIL(x)             (((uint32_t)(((uint32_t)(x)) << GENFSK_PACKET_CFG_H0_FAIL_SHIFT)) & GENFSK_PACKET_CFG_H0_FAIL_MASK)
2932 #define GENFSK_PACKET_CFG_H1_SZ_MASK             (0x1F000000U)
2933 #define GENFSK_PACKET_CFG_H1_SZ_SHIFT            (24U)
2934 #define GENFSK_PACKET_CFG_H1_SZ(x)               (((uint32_t)(((uint32_t)(x)) << GENFSK_PACKET_CFG_H1_SZ_SHIFT)) & GENFSK_PACKET_CFG_H1_SZ_MASK)
2935 #define GENFSK_PACKET_CFG_H1_FAIL_MASK           (0x80000000U)
2936 #define GENFSK_PACKET_CFG_H1_FAIL_SHIFT          (31U)
2937 #define GENFSK_PACKET_CFG_H1_FAIL(x)             (((uint32_t)(((uint32_t)(x)) << GENFSK_PACKET_CFG_H1_FAIL_SHIFT)) & GENFSK_PACKET_CFG_H1_FAIL_MASK)
2938 
2939 /*! @name H0_CFG - H0 CONFIGURATION */
2940 #define GENFSK_H0_CFG_H0_MATCH_MASK              (0xFFFFU)
2941 #define GENFSK_H0_CFG_H0_MATCH_SHIFT             (0U)
2942 #define GENFSK_H0_CFG_H0_MATCH(x)                (((uint32_t)(((uint32_t)(x)) << GENFSK_H0_CFG_H0_MATCH_SHIFT)) & GENFSK_H0_CFG_H0_MATCH_MASK)
2943 #define GENFSK_H0_CFG_H0_MASK_MASK               (0xFFFF0000U)
2944 #define GENFSK_H0_CFG_H0_MASK_SHIFT              (16U)
2945 #define GENFSK_H0_CFG_H0_MASK(x)                 (((uint32_t)(((uint32_t)(x)) << GENFSK_H0_CFG_H0_MASK_SHIFT)) & GENFSK_H0_CFG_H0_MASK_MASK)
2946 
2947 /*! @name H1_CFG - H1 CONFIGURATION */
2948 #define GENFSK_H1_CFG_H1_MATCH_MASK              (0xFFFFU)
2949 #define GENFSK_H1_CFG_H1_MATCH_SHIFT             (0U)
2950 #define GENFSK_H1_CFG_H1_MATCH(x)                (((uint32_t)(((uint32_t)(x)) << GENFSK_H1_CFG_H1_MATCH_SHIFT)) & GENFSK_H1_CFG_H1_MATCH_MASK)
2951 #define GENFSK_H1_CFG_H1_MASK_MASK               (0xFFFF0000U)
2952 #define GENFSK_H1_CFG_H1_MASK_SHIFT              (16U)
2953 #define GENFSK_H1_CFG_H1_MASK(x)                 (((uint32_t)(((uint32_t)(x)) << GENFSK_H1_CFG_H1_MASK_SHIFT)) & GENFSK_H1_CFG_H1_MASK_MASK)
2954 
2955 /*! @name CRC_CFG - CRC CONFIGURATION */
2956 #define GENFSK_CRC_CFG_CRC_SZ_MASK               (0x7U)
2957 #define GENFSK_CRC_CFG_CRC_SZ_SHIFT              (0U)
2958 #define GENFSK_CRC_CFG_CRC_SZ(x)                 (((uint32_t)(((uint32_t)(x)) << GENFSK_CRC_CFG_CRC_SZ_SHIFT)) & GENFSK_CRC_CFG_CRC_SZ_MASK)
2959 #define GENFSK_CRC_CFG_CRC_START_BYTE_MASK       (0xF00U)
2960 #define GENFSK_CRC_CFG_CRC_START_BYTE_SHIFT      (8U)
2961 #define GENFSK_CRC_CFG_CRC_START_BYTE(x)         (((uint32_t)(((uint32_t)(x)) << GENFSK_CRC_CFG_CRC_START_BYTE_SHIFT)) & GENFSK_CRC_CFG_CRC_START_BYTE_MASK)
2962 #define GENFSK_CRC_CFG_CRC_REF_IN_MASK           (0x10000U)
2963 #define GENFSK_CRC_CFG_CRC_REF_IN_SHIFT          (16U)
2964 #define GENFSK_CRC_CFG_CRC_REF_IN(x)             (((uint32_t)(((uint32_t)(x)) << GENFSK_CRC_CFG_CRC_REF_IN_SHIFT)) & GENFSK_CRC_CFG_CRC_REF_IN_MASK)
2965 #define GENFSK_CRC_CFG_CRC_REF_OUT_MASK          (0x20000U)
2966 #define GENFSK_CRC_CFG_CRC_REF_OUT_SHIFT         (17U)
2967 #define GENFSK_CRC_CFG_CRC_REF_OUT(x)            (((uint32_t)(((uint32_t)(x)) << GENFSK_CRC_CFG_CRC_REF_OUT_SHIFT)) & GENFSK_CRC_CFG_CRC_REF_OUT_MASK)
2968 #define GENFSK_CRC_CFG_CRC_BYTE_ORD_MASK         (0x40000U)
2969 #define GENFSK_CRC_CFG_CRC_BYTE_ORD_SHIFT        (18U)
2970 #define GENFSK_CRC_CFG_CRC_BYTE_ORD(x)           (((uint32_t)(((uint32_t)(x)) << GENFSK_CRC_CFG_CRC_BYTE_ORD_SHIFT)) & GENFSK_CRC_CFG_CRC_BYTE_ORD_MASK)
2971 
2972 /*! @name CRC_INIT - CRC INITIALIZATION */
2973 #define GENFSK_CRC_INIT_CRC_SEED_MASK            (0xFFFFFFFFU)
2974 #define GENFSK_CRC_INIT_CRC_SEED_SHIFT           (0U)
2975 #define GENFSK_CRC_INIT_CRC_SEED(x)              (((uint32_t)(((uint32_t)(x)) << GENFSK_CRC_INIT_CRC_SEED_SHIFT)) & GENFSK_CRC_INIT_CRC_SEED_MASK)
2976 
2977 /*! @name CRC_POLY - CRC POLYNOMIAL */
2978 #define GENFSK_CRC_POLY_CRC_POLY_MASK            (0xFFFFFFFFU)
2979 #define GENFSK_CRC_POLY_CRC_POLY_SHIFT           (0U)
2980 #define GENFSK_CRC_POLY_CRC_POLY(x)              (((uint32_t)(((uint32_t)(x)) << GENFSK_CRC_POLY_CRC_POLY_SHIFT)) & GENFSK_CRC_POLY_CRC_POLY_MASK)
2981 
2982 /*! @name CRC_XOR_OUT - CRC XOR OUT */
2983 #define GENFSK_CRC_XOR_OUT_CRC_XOR_OUT_MASK      (0xFFFFFFFFU)
2984 #define GENFSK_CRC_XOR_OUT_CRC_XOR_OUT_SHIFT     (0U)
2985 #define GENFSK_CRC_XOR_OUT_CRC_XOR_OUT(x)        (((uint32_t)(((uint32_t)(x)) << GENFSK_CRC_XOR_OUT_CRC_XOR_OUT_SHIFT)) & GENFSK_CRC_XOR_OUT_CRC_XOR_OUT_MASK)
2986 
2987 /*! @name WHITEN_CFG - WHITENER CONFIGURATION */
2988 #define GENFSK_WHITEN_CFG_WHITEN_START_MASK      (0x3U)
2989 #define GENFSK_WHITEN_CFG_WHITEN_START_SHIFT     (0U)
2990 #define GENFSK_WHITEN_CFG_WHITEN_START(x)        (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_CFG_WHITEN_START_SHIFT)) & GENFSK_WHITEN_CFG_WHITEN_START_MASK)
2991 #define GENFSK_WHITEN_CFG_WHITEN_END_MASK        (0x4U)
2992 #define GENFSK_WHITEN_CFG_WHITEN_END_SHIFT       (2U)
2993 #define GENFSK_WHITEN_CFG_WHITEN_END(x)          (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_CFG_WHITEN_END_SHIFT)) & GENFSK_WHITEN_CFG_WHITEN_END_MASK)
2994 #define GENFSK_WHITEN_CFG_WHITEN_B4_CRC_MASK     (0x8U)
2995 #define GENFSK_WHITEN_CFG_WHITEN_B4_CRC_SHIFT    (3U)
2996 #define GENFSK_WHITEN_CFG_WHITEN_B4_CRC(x)       (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_CFG_WHITEN_B4_CRC_SHIFT)) & GENFSK_WHITEN_CFG_WHITEN_B4_CRC_MASK)
2997 #define GENFSK_WHITEN_CFG_WHITEN_POLY_TYPE_MASK  (0x10U)
2998 #define GENFSK_WHITEN_CFG_WHITEN_POLY_TYPE_SHIFT (4U)
2999 #define GENFSK_WHITEN_CFG_WHITEN_POLY_TYPE(x)    (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_CFG_WHITEN_POLY_TYPE_SHIFT)) & GENFSK_WHITEN_CFG_WHITEN_POLY_TYPE_MASK)
3000 #define GENFSK_WHITEN_CFG_WHITEN_REF_IN_MASK     (0x20U)
3001 #define GENFSK_WHITEN_CFG_WHITEN_REF_IN_SHIFT    (5U)
3002 #define GENFSK_WHITEN_CFG_WHITEN_REF_IN(x)       (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_CFG_WHITEN_REF_IN_SHIFT)) & GENFSK_WHITEN_CFG_WHITEN_REF_IN_MASK)
3003 #define GENFSK_WHITEN_CFG_WHITEN_PAYLOAD_REINIT_MASK (0x40U)
3004 #define GENFSK_WHITEN_CFG_WHITEN_PAYLOAD_REINIT_SHIFT (6U)
3005 #define GENFSK_WHITEN_CFG_WHITEN_PAYLOAD_REINIT(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_CFG_WHITEN_PAYLOAD_REINIT_SHIFT)) & GENFSK_WHITEN_CFG_WHITEN_PAYLOAD_REINIT_MASK)
3006 #define GENFSK_WHITEN_CFG_WHITEN_SIZE_MASK       (0xF00U)
3007 #define GENFSK_WHITEN_CFG_WHITEN_SIZE_SHIFT      (8U)
3008 #define GENFSK_WHITEN_CFG_WHITEN_SIZE(x)         (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_CFG_WHITEN_SIZE_SHIFT)) & GENFSK_WHITEN_CFG_WHITEN_SIZE_MASK)
3009 #define GENFSK_WHITEN_CFG_MANCHESTER_EN_MASK     (0x1000U)
3010 #define GENFSK_WHITEN_CFG_MANCHESTER_EN_SHIFT    (12U)
3011 #define GENFSK_WHITEN_CFG_MANCHESTER_EN(x)       (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_CFG_MANCHESTER_EN_SHIFT)) & GENFSK_WHITEN_CFG_MANCHESTER_EN_MASK)
3012 #define GENFSK_WHITEN_CFG_MANCHESTER_INV_MASK    (0x2000U)
3013 #define GENFSK_WHITEN_CFG_MANCHESTER_INV_SHIFT   (13U)
3014 #define GENFSK_WHITEN_CFG_MANCHESTER_INV(x)      (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_CFG_MANCHESTER_INV_SHIFT)) & GENFSK_WHITEN_CFG_MANCHESTER_INV_MASK)
3015 #define GENFSK_WHITEN_CFG_MANCHESTER_START_MASK  (0x4000U)
3016 #define GENFSK_WHITEN_CFG_MANCHESTER_START_SHIFT (14U)
3017 #define GENFSK_WHITEN_CFG_MANCHESTER_START(x)    (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_CFG_MANCHESTER_START_SHIFT)) & GENFSK_WHITEN_CFG_MANCHESTER_START_MASK)
3018 #define GENFSK_WHITEN_CFG_WHITEN_INIT_MASK       (0x1FF0000U)
3019 #define GENFSK_WHITEN_CFG_WHITEN_INIT_SHIFT      (16U)
3020 #define GENFSK_WHITEN_CFG_WHITEN_INIT(x)         (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_CFG_WHITEN_INIT_SHIFT)) & GENFSK_WHITEN_CFG_WHITEN_INIT_MASK)
3021 
3022 /*! @name WHITEN_POLY - WHITENER POLYNOMIAL */
3023 #define GENFSK_WHITEN_POLY_WHITEN_POLY_MASK      (0x1FFU)
3024 #define GENFSK_WHITEN_POLY_WHITEN_POLY_SHIFT     (0U)
3025 #define GENFSK_WHITEN_POLY_WHITEN_POLY(x)        (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_POLY_WHITEN_POLY_SHIFT)) & GENFSK_WHITEN_POLY_WHITEN_POLY_MASK)
3026 
3027 /*! @name WHITEN_SZ_THR - WHITENER SIZE THRESHOLD */
3028 #define GENFSK_WHITEN_SZ_THR_WHITEN_SZ_THR_MASK  (0xFFFU)
3029 #define GENFSK_WHITEN_SZ_THR_WHITEN_SZ_THR_SHIFT (0U)
3030 #define GENFSK_WHITEN_SZ_THR_WHITEN_SZ_THR(x)    (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_SZ_THR_WHITEN_SZ_THR_SHIFT)) & GENFSK_WHITEN_SZ_THR_WHITEN_SZ_THR_MASK)
3031 #define GENFSK_WHITEN_SZ_THR_LENGTH_MAX_MASK     (0x7F0000U)
3032 #define GENFSK_WHITEN_SZ_THR_LENGTH_MAX_SHIFT    (16U)
3033 #define GENFSK_WHITEN_SZ_THR_LENGTH_MAX(x)       (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_SZ_THR_LENGTH_MAX_SHIFT)) & GENFSK_WHITEN_SZ_THR_LENGTH_MAX_MASK)
3034 #define GENFSK_WHITEN_SZ_THR_REC_BAD_PKT_MASK    (0x800000U)
3035 #define GENFSK_WHITEN_SZ_THR_REC_BAD_PKT_SHIFT   (23U)
3036 #define GENFSK_WHITEN_SZ_THR_REC_BAD_PKT(x)      (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_SZ_THR_REC_BAD_PKT_SHIFT)) & GENFSK_WHITEN_SZ_THR_REC_BAD_PKT_MASK)
3037 
3038 /*! @name BITRATE - BIT RATE */
3039 #define GENFSK_BITRATE_BITRATE_MASK              (0x3U)
3040 #define GENFSK_BITRATE_BITRATE_SHIFT             (0U)
3041 #define GENFSK_BITRATE_BITRATE(x)                (((uint32_t)(((uint32_t)(x)) << GENFSK_BITRATE_BITRATE_SHIFT)) & GENFSK_BITRATE_BITRATE_MASK)
3042 
3043 /*! @name PB_PARTITION - PACKET BUFFER PARTITION POINT */
3044 #define GENFSK_PB_PARTITION_PB_PARTITION_MASK    (0x7FFU)
3045 #define GENFSK_PB_PARTITION_PB_PARTITION_SHIFT   (0U)
3046 #define GENFSK_PB_PARTITION_PB_PARTITION(x)      (((uint32_t)(((uint32_t)(x)) << GENFSK_PB_PARTITION_PB_PARTITION_SHIFT)) & GENFSK_PB_PARTITION_PB_PARTITION_MASK)
3047 
3048 
3049 /*!
3050  * @}
3051  */ /* end of group GENFSK_Register_Masks */
3052 
3053 
3054 /* GENFSK - Peripheral instance base addresses */
3055 /** Peripheral GENFSK base address */
3056 #define GENFSK_BASE                              (0x4005F000u)
3057 /** Peripheral GENFSK base pointer */
3058 #define GENFSK                                   ((GENFSK_Type *)GENFSK_BASE)
3059 /** Array initializer of GENFSK peripheral base addresses */
3060 #define GENFSK_BASE_ADDRS                        { GENFSK_BASE }
3061 /** Array initializer of GENFSK peripheral base pointers */
3062 #define GENFSK_BASE_PTRS                         { GENFSK }
3063 
3064 /*!
3065  * @}
3066  */ /* end of group GENFSK_Peripheral_Access_Layer */
3067 
3068 
3069 /* ----------------------------------------------------------------------------
3070    -- GPIO Peripheral Access Layer
3071    ---------------------------------------------------------------------------- */
3072 
3073 /*!
3074  * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
3075  * @{
3076  */
3077 
3078 /** GPIO - Register Layout Typedef */
3079 typedef struct {
3080   __IO uint32_t PDOR;                              /**< Port Data Output Register, offset: 0x0 */
3081   __O  uint32_t PSOR;                              /**< Port Set Output Register, offset: 0x4 */
3082   __O  uint32_t PCOR;                              /**< Port Clear Output Register, offset: 0x8 */
3083   __O  uint32_t PTOR;                              /**< Port Toggle Output Register, offset: 0xC */
3084   __I  uint32_t PDIR;                              /**< Port Data Input Register, offset: 0x10 */
3085   __IO uint32_t PDDR;                              /**< Port Data Direction Register, offset: 0x14 */
3086 } GPIO_Type;
3087 
3088 /* ----------------------------------------------------------------------------
3089    -- GPIO Register Masks
3090    ---------------------------------------------------------------------------- */
3091 
3092 /*!
3093  * @addtogroup GPIO_Register_Masks GPIO Register Masks
3094  * @{
3095  */
3096 
3097 /*! @name PDOR - Port Data Output Register */
3098 #define GPIO_PDOR_PDO_MASK                       (0xFFFFFFFFU)
3099 #define GPIO_PDOR_PDO_SHIFT                      (0U)
3100 #define GPIO_PDOR_PDO(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK)
3101 
3102 /*! @name PSOR - Port Set Output Register */
3103 #define GPIO_PSOR_PTSO_MASK                      (0xFFFFFFFFU)
3104 #define GPIO_PSOR_PTSO_SHIFT                     (0U)
3105 #define GPIO_PSOR_PTSO(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK)
3106 
3107 /*! @name PCOR - Port Clear Output Register */
3108 #define GPIO_PCOR_PTCO_MASK                      (0xFFFFFFFFU)
3109 #define GPIO_PCOR_PTCO_SHIFT                     (0U)
3110 #define GPIO_PCOR_PTCO(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK)
3111 
3112 /*! @name PTOR - Port Toggle Output Register */
3113 #define GPIO_PTOR_PTTO_MASK                      (0xFFFFFFFFU)
3114 #define GPIO_PTOR_PTTO_SHIFT                     (0U)
3115 #define GPIO_PTOR_PTTO(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK)
3116 
3117 /*! @name PDIR - Port Data Input Register */
3118 #define GPIO_PDIR_PDI_MASK                       (0xFFFFFFFFU)
3119 #define GPIO_PDIR_PDI_SHIFT                      (0U)
3120 #define GPIO_PDIR_PDI(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK)
3121 
3122 /*! @name PDDR - Port Data Direction Register */
3123 #define GPIO_PDDR_PDD_MASK                       (0xFFFFFFFFU)
3124 #define GPIO_PDDR_PDD_SHIFT                      (0U)
3125 #define GPIO_PDDR_PDD(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK)
3126 
3127 
3128 /*!
3129  * @}
3130  */ /* end of group GPIO_Register_Masks */
3131 
3132 
3133 /* GPIO - Peripheral instance base addresses */
3134 /** Peripheral GPIOA base address */
3135 #define GPIOA_BASE                               (0x400FF000u)
3136 /** Peripheral GPIOA base pointer */
3137 #define GPIOA                                    ((GPIO_Type *)GPIOA_BASE)
3138 /** Peripheral GPIOB base address */
3139 #define GPIOB_BASE                               (0x400FF040u)
3140 /** Peripheral GPIOB base pointer */
3141 #define GPIOB                                    ((GPIO_Type *)GPIOB_BASE)
3142 /** Peripheral GPIOC base address */
3143 #define GPIOC_BASE                               (0x400FF080u)
3144 /** Peripheral GPIOC base pointer */
3145 #define GPIOC                                    ((GPIO_Type *)GPIOC_BASE)
3146 /** Array initializer of GPIO peripheral base addresses */
3147 #define GPIO_BASE_ADDRS                          { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE }
3148 /** Array initializer of GPIO peripheral base pointers */
3149 #define GPIO_BASE_PTRS                           { GPIOA, GPIOB, GPIOC }
3150 
3151 /*!
3152  * @}
3153  */ /* end of group GPIO_Peripheral_Access_Layer */
3154 
3155 
3156 /* ----------------------------------------------------------------------------
3157    -- I2C Peripheral Access Layer
3158    ---------------------------------------------------------------------------- */
3159 
3160 /*!
3161  * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
3162  * @{
3163  */
3164 
3165 /** I2C - Register Layout Typedef */
3166 typedef struct {
3167   __IO uint8_t A1;                                 /**< I2C Address Register 1, offset: 0x0 */
3168   __IO uint8_t F;                                  /**< I2C Frequency Divider register, offset: 0x1 */
3169   __IO uint8_t C1;                                 /**< I2C Control Register 1, offset: 0x2 */
3170   __IO uint8_t S;                                  /**< I2C Status register, offset: 0x3 */
3171   __IO uint8_t D;                                  /**< I2C Data I/O register, offset: 0x4 */
3172   __IO uint8_t C2;                                 /**< I2C Control Register 2, offset: 0x5 */
3173   __IO uint8_t FLT;                                /**< I2C Programmable Input Glitch Filter Register, offset: 0x6 */
3174   __IO uint8_t RA;                                 /**< I2C Range Address register, offset: 0x7 */
3175   __IO uint8_t SMB;                                /**< I2C SMBus Control and Status register, offset: 0x8 */
3176   __IO uint8_t A2;                                 /**< I2C Address Register 2, offset: 0x9 */
3177   __IO uint8_t SLTH;                               /**< I2C SCL Low Timeout Register High, offset: 0xA */
3178   __IO uint8_t SLTL;                               /**< I2C SCL Low Timeout Register Low, offset: 0xB */
3179   __IO uint8_t S2;                                 /**< I2C Status register 2, offset: 0xC */
3180 } I2C_Type;
3181 
3182 /* ----------------------------------------------------------------------------
3183    -- I2C Register Masks
3184    ---------------------------------------------------------------------------- */
3185 
3186 /*!
3187  * @addtogroup I2C_Register_Masks I2C Register Masks
3188  * @{
3189  */
3190 
3191 /*! @name A1 - I2C Address Register 1 */
3192 #define I2C_A1_AD_MASK                           (0xFEU)
3193 #define I2C_A1_AD_SHIFT                          (1U)
3194 #define I2C_A1_AD(x)                             (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK)
3195 
3196 /*! @name F - I2C Frequency Divider register */
3197 #define I2C_F_ICR_MASK                           (0x3FU)
3198 #define I2C_F_ICR_SHIFT                          (0U)
3199 #define I2C_F_ICR(x)                             (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK)
3200 #define I2C_F_MULT_MASK                          (0xC0U)
3201 #define I2C_F_MULT_SHIFT                         (6U)
3202 #define I2C_F_MULT(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK)
3203 
3204 /*! @name C1 - I2C Control Register 1 */
3205 #define I2C_C1_DMAEN_MASK                        (0x1U)
3206 #define I2C_C1_DMAEN_SHIFT                       (0U)
3207 #define I2C_C1_DMAEN(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK)
3208 #define I2C_C1_WUEN_MASK                         (0x2U)
3209 #define I2C_C1_WUEN_SHIFT                        (1U)
3210 #define I2C_C1_WUEN(x)                           (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK)
3211 #define I2C_C1_RSTA_MASK                         (0x4U)
3212 #define I2C_C1_RSTA_SHIFT                        (2U)
3213 #define I2C_C1_RSTA(x)                           (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK)
3214 #define I2C_C1_TXAK_MASK                         (0x8U)
3215 #define I2C_C1_TXAK_SHIFT                        (3U)
3216 #define I2C_C1_TXAK(x)                           (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK)
3217 #define I2C_C1_TX_MASK                           (0x10U)
3218 #define I2C_C1_TX_SHIFT                          (4U)
3219 #define I2C_C1_TX(x)                             (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK)
3220 #define I2C_C1_MST_MASK                          (0x20U)
3221 #define I2C_C1_MST_SHIFT                         (5U)
3222 #define I2C_C1_MST(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK)
3223 #define I2C_C1_IICIE_MASK                        (0x40U)
3224 #define I2C_C1_IICIE_SHIFT                       (6U)
3225 #define I2C_C1_IICIE(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK)
3226 #define I2C_C1_IICEN_MASK                        (0x80U)
3227 #define I2C_C1_IICEN_SHIFT                       (7U)
3228 #define I2C_C1_IICEN(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK)
3229 
3230 /*! @name S - I2C Status register */
3231 #define I2C_S_RXAK_MASK                          (0x1U)
3232 #define I2C_S_RXAK_SHIFT                         (0U)
3233 #define I2C_S_RXAK(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK)
3234 #define I2C_S_IICIF_MASK                         (0x2U)
3235 #define I2C_S_IICIF_SHIFT                        (1U)
3236 #define I2C_S_IICIF(x)                           (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK)
3237 #define I2C_S_SRW_MASK                           (0x4U)
3238 #define I2C_S_SRW_SHIFT                          (2U)
3239 #define I2C_S_SRW(x)                             (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK)
3240 #define I2C_S_RAM_MASK                           (0x8U)
3241 #define I2C_S_RAM_SHIFT                          (3U)
3242 #define I2C_S_RAM(x)                             (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK)
3243 #define I2C_S_ARBL_MASK                          (0x10U)
3244 #define I2C_S_ARBL_SHIFT                         (4U)
3245 #define I2C_S_ARBL(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK)
3246 #define I2C_S_BUSY_MASK                          (0x20U)
3247 #define I2C_S_BUSY_SHIFT                         (5U)
3248 #define I2C_S_BUSY(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK)
3249 #define I2C_S_IAAS_MASK                          (0x40U)
3250 #define I2C_S_IAAS_SHIFT                         (6U)
3251 #define I2C_S_IAAS(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK)
3252 #define I2C_S_TCF_MASK                           (0x80U)
3253 #define I2C_S_TCF_SHIFT                          (7U)
3254 #define I2C_S_TCF(x)                             (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK)
3255 
3256 /*! @name D - I2C Data I/O register */
3257 #define I2C_D_DATA_MASK                          (0xFFU)
3258 #define I2C_D_DATA_SHIFT                         (0U)
3259 #define I2C_D_DATA(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK)
3260 
3261 /*! @name C2 - I2C Control Register 2 */
3262 #define I2C_C2_AD_MASK                           (0x7U)
3263 #define I2C_C2_AD_SHIFT                          (0U)
3264 #define I2C_C2_AD(x)                             (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK)
3265 #define I2C_C2_RMEN_MASK                         (0x8U)
3266 #define I2C_C2_RMEN_SHIFT                        (3U)
3267 #define I2C_C2_RMEN(x)                           (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK)
3268 #define I2C_C2_SBRC_MASK                         (0x10U)
3269 #define I2C_C2_SBRC_SHIFT                        (4U)
3270 #define I2C_C2_SBRC(x)                           (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK)
3271 #define I2C_C2_HDRS_MASK                         (0x20U)
3272 #define I2C_C2_HDRS_SHIFT                        (5U)
3273 #define I2C_C2_HDRS(x)                           (((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK)
3274 #define I2C_C2_ADEXT_MASK                        (0x40U)
3275 #define I2C_C2_ADEXT_SHIFT                       (6U)
3276 #define I2C_C2_ADEXT(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK)
3277 #define I2C_C2_GCAEN_MASK                        (0x80U)
3278 #define I2C_C2_GCAEN_SHIFT                       (7U)
3279 #define I2C_C2_GCAEN(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK)
3280 
3281 /*! @name FLT - I2C Programmable Input Glitch Filter Register */
3282 #define I2C_FLT_FLT_MASK                         (0xFU)
3283 #define I2C_FLT_FLT_SHIFT                        (0U)
3284 #define I2C_FLT_FLT(x)                           (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK)
3285 #define I2C_FLT_STARTF_MASK                      (0x10U)
3286 #define I2C_FLT_STARTF_SHIFT                     (4U)
3287 #define I2C_FLT_STARTF(x)                        (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STARTF_SHIFT)) & I2C_FLT_STARTF_MASK)
3288 #define I2C_FLT_SSIE_MASK                        (0x20U)
3289 #define I2C_FLT_SSIE_SHIFT                       (5U)
3290 #define I2C_FLT_SSIE(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SSIE_SHIFT)) & I2C_FLT_SSIE_MASK)
3291 #define I2C_FLT_STOPF_MASK                       (0x40U)
3292 #define I2C_FLT_STOPF_SHIFT                      (6U)
3293 #define I2C_FLT_STOPF(x)                         (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STOPF_SHIFT)) & I2C_FLT_STOPF_MASK)
3294 #define I2C_FLT_SHEN_MASK                        (0x80U)
3295 #define I2C_FLT_SHEN_SHIFT                       (7U)
3296 #define I2C_FLT_SHEN(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SHEN_SHIFT)) & I2C_FLT_SHEN_MASK)
3297 
3298 /*! @name RA - I2C Range Address register */
3299 #define I2C_RA_RAD_MASK                          (0xFEU)
3300 #define I2C_RA_RAD_SHIFT                         (1U)
3301 #define I2C_RA_RAD(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK)
3302 
3303 /*! @name SMB - I2C SMBus Control and Status register */
3304 #define I2C_SMB_SHTF2IE_MASK                     (0x1U)
3305 #define I2C_SMB_SHTF2IE_SHIFT                    (0U)
3306 #define I2C_SMB_SHTF2IE(x)                       (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK)
3307 #define I2C_SMB_SHTF2_MASK                       (0x2U)
3308 #define I2C_SMB_SHTF2_SHIFT                      (1U)
3309 #define I2C_SMB_SHTF2(x)                         (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK)
3310 #define I2C_SMB_SHTF1_MASK                       (0x4U)
3311 #define I2C_SMB_SHTF1_SHIFT                      (2U)
3312 #define I2C_SMB_SHTF1(x)                         (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK)
3313 #define I2C_SMB_SLTF_MASK                        (0x8U)
3314 #define I2C_SMB_SLTF_SHIFT                       (3U)
3315 #define I2C_SMB_SLTF(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK)
3316 #define I2C_SMB_TCKSEL_MASK                      (0x10U)
3317 #define I2C_SMB_TCKSEL_SHIFT                     (4U)
3318 #define I2C_SMB_TCKSEL(x)                        (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK)
3319 #define I2C_SMB_SIICAEN_MASK                     (0x20U)
3320 #define I2C_SMB_SIICAEN_SHIFT                    (5U)
3321 #define I2C_SMB_SIICAEN(x)                       (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK)
3322 #define I2C_SMB_ALERTEN_MASK                     (0x40U)
3323 #define I2C_SMB_ALERTEN_SHIFT                    (6U)
3324 #define I2C_SMB_ALERTEN(x)                       (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK)
3325 #define I2C_SMB_FACK_MASK                        (0x80U)
3326 #define I2C_SMB_FACK_SHIFT                       (7U)
3327 #define I2C_SMB_FACK(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK)
3328 
3329 /*! @name A2 - I2C Address Register 2 */
3330 #define I2C_A2_SAD_MASK                          (0xFEU)
3331 #define I2C_A2_SAD_SHIFT                         (1U)
3332 #define I2C_A2_SAD(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK)
3333 
3334 /*! @name SLTH - I2C SCL Low Timeout Register High */
3335 #define I2C_SLTH_SSLT_MASK                       (0xFFU)
3336 #define I2C_SLTH_SSLT_SHIFT                      (0U)
3337 #define I2C_SLTH_SSLT(x)                         (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK)
3338 
3339 /*! @name SLTL - I2C SCL Low Timeout Register Low */
3340 #define I2C_SLTL_SSLT_MASK                       (0xFFU)
3341 #define I2C_SLTL_SSLT_SHIFT                      (0U)
3342 #define I2C_SLTL_SSLT(x)                         (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK)
3343 
3344 /*! @name S2 - I2C Status register 2 */
3345 #define I2C_S2_EMPTY_MASK                        (0x1U)
3346 #define I2C_S2_EMPTY_SHIFT                       (0U)
3347 #define I2C_S2_EMPTY(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_S2_EMPTY_SHIFT)) & I2C_S2_EMPTY_MASK)
3348 #define I2C_S2_ERROR_MASK                        (0x2U)
3349 #define I2C_S2_ERROR_SHIFT                       (1U)
3350 #define I2C_S2_ERROR(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_S2_ERROR_SHIFT)) & I2C_S2_ERROR_MASK)
3351 #define I2C_S2_DFEN_MASK                         (0x4U)
3352 #define I2C_S2_DFEN_SHIFT                        (2U)
3353 #define I2C_S2_DFEN(x)                           (((uint8_t)(((uint8_t)(x)) << I2C_S2_DFEN_SHIFT)) & I2C_S2_DFEN_MASK)
3354 
3355 
3356 /*!
3357  * @}
3358  */ /* end of group I2C_Register_Masks */
3359 
3360 
3361 /* I2C - Peripheral instance base addresses */
3362 /** Peripheral I2C0 base address */
3363 #define I2C0_BASE                                (0x40066000u)
3364 /** Peripheral I2C0 base pointer */
3365 #define I2C0                                     ((I2C_Type *)I2C0_BASE)
3366 /** Peripheral I2C1 base address */
3367 #define I2C1_BASE                                (0x40067000u)
3368 /** Peripheral I2C1 base pointer */
3369 #define I2C1                                     ((I2C_Type *)I2C1_BASE)
3370 /** Array initializer of I2C peripheral base addresses */
3371 #define I2C_BASE_ADDRS                           { I2C0_BASE, I2C1_BASE }
3372 /** Array initializer of I2C peripheral base pointers */
3373 #define I2C_BASE_PTRS                            { I2C0, I2C1 }
3374 /** Interrupt vectors for the I2C peripheral type */
3375 #define I2C_IRQS                                 { I2C0_IRQn, I2C1_IRQn }
3376 
3377 /*!
3378  * @}
3379  */ /* end of group I2C_Peripheral_Access_Layer */
3380 
3381 
3382 /* ----------------------------------------------------------------------------
3383    -- LLWU Peripheral Access Layer
3384    ---------------------------------------------------------------------------- */
3385 
3386 /*!
3387  * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
3388  * @{
3389  */
3390 
3391 /** LLWU - Register Layout Typedef */
3392 typedef struct {
3393   __IO uint8_t PE1;                                /**< LLWU Pin Enable 1 register, offset: 0x0 */
3394   __IO uint8_t PE2;                                /**< LLWU Pin Enable 2 register, offset: 0x1 */
3395   __IO uint8_t PE3;                                /**< LLWU Pin Enable 3 register, offset: 0x2 */
3396   __IO uint8_t PE4;                                /**< LLWU Pin Enable 4 register, offset: 0x3 */
3397   __IO uint8_t ME;                                 /**< LLWU Module Enable register, offset: 0x4 */
3398   __IO uint8_t F1;                                 /**< LLWU Flag 1 register, offset: 0x5 */
3399   __IO uint8_t F2;                                 /**< LLWU Flag 2 register, offset: 0x6 */
3400   __I  uint8_t F3;                                 /**< LLWU Flag 3 register, offset: 0x7 */
3401   __IO uint8_t FILT1;                              /**< LLWU Pin Filter 1 register, offset: 0x8 */
3402   __IO uint8_t FILT2;                              /**< LLWU Pin Filter 2 register, offset: 0x9 */
3403 } LLWU_Type;
3404 
3405 /* ----------------------------------------------------------------------------
3406    -- LLWU Register Masks
3407    ---------------------------------------------------------------------------- */
3408 
3409 /*!
3410  * @addtogroup LLWU_Register_Masks LLWU Register Masks
3411  * @{
3412  */
3413 
3414 /*! @name PE1 - LLWU Pin Enable 1 register */
3415 #define LLWU_PE1_WUPE0_MASK                      (0x3U)
3416 #define LLWU_PE1_WUPE0_SHIFT                     (0U)
3417 #define LLWU_PE1_WUPE0(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK)
3418 #define LLWU_PE1_WUPE1_MASK                      (0xCU)
3419 #define LLWU_PE1_WUPE1_SHIFT                     (2U)
3420 #define LLWU_PE1_WUPE1(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK)
3421 #define LLWU_PE1_WUPE2_MASK                      (0x30U)
3422 #define LLWU_PE1_WUPE2_SHIFT                     (4U)
3423 #define LLWU_PE1_WUPE2(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK)
3424 #define LLWU_PE1_WUPE3_MASK                      (0xC0U)
3425 #define LLWU_PE1_WUPE3_SHIFT                     (6U)
3426 #define LLWU_PE1_WUPE3(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK)
3427 
3428 /*! @name PE2 - LLWU Pin Enable 2 register */
3429 #define LLWU_PE2_WUPE4_MASK                      (0x3U)
3430 #define LLWU_PE2_WUPE4_SHIFT                     (0U)
3431 #define LLWU_PE2_WUPE4(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE4_SHIFT)) & LLWU_PE2_WUPE4_MASK)
3432 #define LLWU_PE2_WUPE5_MASK                      (0xCU)
3433 #define LLWU_PE2_WUPE5_SHIFT                     (2U)
3434 #define LLWU_PE2_WUPE5(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE5_SHIFT)) & LLWU_PE2_WUPE5_MASK)
3435 #define LLWU_PE2_WUPE6_MASK                      (0x30U)
3436 #define LLWU_PE2_WUPE6_SHIFT                     (4U)
3437 #define LLWU_PE2_WUPE6(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE6_SHIFT)) & LLWU_PE2_WUPE6_MASK)
3438 #define LLWU_PE2_WUPE7_MASK                      (0xC0U)
3439 #define LLWU_PE2_WUPE7_SHIFT                     (6U)
3440 #define LLWU_PE2_WUPE7(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE7_SHIFT)) & LLWU_PE2_WUPE7_MASK)
3441 
3442 /*! @name PE3 - LLWU Pin Enable 3 register */
3443 #define LLWU_PE3_WUPE8_MASK                      (0x3U)
3444 #define LLWU_PE3_WUPE8_SHIFT                     (0U)
3445 #define LLWU_PE3_WUPE8(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE8_SHIFT)) & LLWU_PE3_WUPE8_MASK)
3446 #define LLWU_PE3_WUPE9_MASK                      (0xCU)
3447 #define LLWU_PE3_WUPE9_SHIFT                     (2U)
3448 #define LLWU_PE3_WUPE9(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE9_SHIFT)) & LLWU_PE3_WUPE9_MASK)
3449 #define LLWU_PE3_WUPE10_MASK                     (0x30U)
3450 #define LLWU_PE3_WUPE10_SHIFT                    (4U)
3451 #define LLWU_PE3_WUPE10(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE10_SHIFT)) & LLWU_PE3_WUPE10_MASK)
3452 #define LLWU_PE3_WUPE11_MASK                     (0xC0U)
3453 #define LLWU_PE3_WUPE11_SHIFT                    (6U)
3454 #define LLWU_PE3_WUPE11(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE11_SHIFT)) & LLWU_PE3_WUPE11_MASK)
3455 
3456 /*! @name PE4 - LLWU Pin Enable 4 register */
3457 #define LLWU_PE4_WUPE12_MASK                     (0x3U)
3458 #define LLWU_PE4_WUPE12_SHIFT                    (0U)
3459 #define LLWU_PE4_WUPE12(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE12_SHIFT)) & LLWU_PE4_WUPE12_MASK)
3460 #define LLWU_PE4_WUPE13_MASK                     (0xCU)
3461 #define LLWU_PE4_WUPE13_SHIFT                    (2U)
3462 #define LLWU_PE4_WUPE13(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE13_SHIFT)) & LLWU_PE4_WUPE13_MASK)
3463 #define LLWU_PE4_WUPE14_MASK                     (0x30U)
3464 #define LLWU_PE4_WUPE14_SHIFT                    (4U)
3465 #define LLWU_PE4_WUPE14(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE14_SHIFT)) & LLWU_PE4_WUPE14_MASK)
3466 #define LLWU_PE4_WUPE15_MASK                     (0xC0U)
3467 #define LLWU_PE4_WUPE15_SHIFT                    (6U)
3468 #define LLWU_PE4_WUPE15(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE15_SHIFT)) & LLWU_PE4_WUPE15_MASK)
3469 
3470 /*! @name ME - LLWU Module Enable register */
3471 #define LLWU_ME_WUME0_MASK                       (0x1U)
3472 #define LLWU_ME_WUME0_SHIFT                      (0U)
3473 #define LLWU_ME_WUME0(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME0_SHIFT)) & LLWU_ME_WUME0_MASK)
3474 #define LLWU_ME_WUME1_MASK                       (0x2U)
3475 #define LLWU_ME_WUME1_SHIFT                      (1U)
3476 #define LLWU_ME_WUME1(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME1_SHIFT)) & LLWU_ME_WUME1_MASK)
3477 #define LLWU_ME_WUME2_MASK                       (0x4U)
3478 #define LLWU_ME_WUME2_SHIFT                      (2U)
3479 #define LLWU_ME_WUME2(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME2_SHIFT)) & LLWU_ME_WUME2_MASK)
3480 #define LLWU_ME_WUME3_MASK                       (0x8U)
3481 #define LLWU_ME_WUME3_SHIFT                      (3U)
3482 #define LLWU_ME_WUME3(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME3_SHIFT)) & LLWU_ME_WUME3_MASK)
3483 #define LLWU_ME_WUME4_MASK                       (0x10U)
3484 #define LLWU_ME_WUME4_SHIFT                      (4U)
3485 #define LLWU_ME_WUME4(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME4_SHIFT)) & LLWU_ME_WUME4_MASK)
3486 #define LLWU_ME_WUME5_MASK                       (0x20U)
3487 #define LLWU_ME_WUME5_SHIFT                      (5U)
3488 #define LLWU_ME_WUME5(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME5_SHIFT)) & LLWU_ME_WUME5_MASK)
3489 #define LLWU_ME_WUME6_MASK                       (0x40U)
3490 #define LLWU_ME_WUME6_SHIFT                      (6U)
3491 #define LLWU_ME_WUME6(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME6_SHIFT)) & LLWU_ME_WUME6_MASK)
3492 #define LLWU_ME_WUME7_MASK                       (0x80U)
3493 #define LLWU_ME_WUME7_SHIFT                      (7U)
3494 #define LLWU_ME_WUME7(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME7_SHIFT)) & LLWU_ME_WUME7_MASK)
3495 
3496 /*! @name F1 - LLWU Flag 1 register */
3497 #define LLWU_F1_WUF0_MASK                        (0x1U)
3498 #define LLWU_F1_WUF0_SHIFT                       (0U)
3499 #define LLWU_F1_WUF0(x)                          (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF0_SHIFT)) & LLWU_F1_WUF0_MASK)
3500 #define LLWU_F1_WUF1_MASK                        (0x2U)
3501 #define LLWU_F1_WUF1_SHIFT                       (1U)
3502 #define LLWU_F1_WUF1(x)                          (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF1_SHIFT)) & LLWU_F1_WUF1_MASK)
3503 #define LLWU_F1_WUF2_MASK                        (0x4U)
3504 #define LLWU_F1_WUF2_SHIFT                       (2U)
3505 #define LLWU_F1_WUF2(x)                          (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF2_SHIFT)) & LLWU_F1_WUF2_MASK)
3506 #define LLWU_F1_WUF3_MASK                        (0x8U)
3507 #define LLWU_F1_WUF3_SHIFT                       (3U)
3508 #define LLWU_F1_WUF3(x)                          (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF3_SHIFT)) & LLWU_F1_WUF3_MASK)
3509 #define LLWU_F1_WUF4_MASK                        (0x10U)
3510 #define LLWU_F1_WUF4_SHIFT                       (4U)
3511 #define LLWU_F1_WUF4(x)                          (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF4_SHIFT)) & LLWU_F1_WUF4_MASK)
3512 #define LLWU_F1_WUF5_MASK                        (0x20U)
3513 #define LLWU_F1_WUF5_SHIFT                       (5U)
3514 #define LLWU_F1_WUF5(x)                          (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF5_SHIFT)) & LLWU_F1_WUF5_MASK)
3515 #define LLWU_F1_WUF6_MASK                        (0x40U)
3516 #define LLWU_F1_WUF6_SHIFT                       (6U)
3517 #define LLWU_F1_WUF6(x)                          (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF6_SHIFT)) & LLWU_F1_WUF6_MASK)
3518 #define LLWU_F1_WUF7_MASK                        (0x80U)
3519 #define LLWU_F1_WUF7_SHIFT                       (7U)
3520 #define LLWU_F1_WUF7(x)                          (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF7_SHIFT)) & LLWU_F1_WUF7_MASK)
3521 
3522 /*! @name F2 - LLWU Flag 2 register */
3523 #define LLWU_F2_WUF8_MASK                        (0x1U)
3524 #define LLWU_F2_WUF8_SHIFT                       (0U)
3525 #define LLWU_F2_WUF8(x)                          (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF8_SHIFT)) & LLWU_F2_WUF8_MASK)
3526 #define LLWU_F2_WUF9_MASK                        (0x2U)
3527 #define LLWU_F2_WUF9_SHIFT                       (1U)
3528 #define LLWU_F2_WUF9(x)                          (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF9_SHIFT)) & LLWU_F2_WUF9_MASK)
3529 #define LLWU_F2_WUF10_MASK                       (0x4U)
3530 #define LLWU_F2_WUF10_SHIFT                      (2U)
3531 #define LLWU_F2_WUF10(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF10_SHIFT)) & LLWU_F2_WUF10_MASK)
3532 #define LLWU_F2_WUF11_MASK                       (0x8U)
3533 #define LLWU_F2_WUF11_SHIFT                      (3U)
3534 #define LLWU_F2_WUF11(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF11_SHIFT)) & LLWU_F2_WUF11_MASK)
3535 #define LLWU_F2_WUF12_MASK                       (0x10U)
3536 #define LLWU_F2_WUF12_SHIFT                      (4U)
3537 #define LLWU_F2_WUF12(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF12_SHIFT)) & LLWU_F2_WUF12_MASK)
3538 #define LLWU_F2_WUF13_MASK                       (0x20U)
3539 #define LLWU_F2_WUF13_SHIFT                      (5U)
3540 #define LLWU_F2_WUF13(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF13_SHIFT)) & LLWU_F2_WUF13_MASK)
3541 #define LLWU_F2_WUF14_MASK                       (0x40U)
3542 #define LLWU_F2_WUF14_SHIFT                      (6U)
3543 #define LLWU_F2_WUF14(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF14_SHIFT)) & LLWU_F2_WUF14_MASK)
3544 #define LLWU_F2_WUF15_MASK                       (0x80U)
3545 #define LLWU_F2_WUF15_SHIFT                      (7U)
3546 #define LLWU_F2_WUF15(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF15_SHIFT)) & LLWU_F2_WUF15_MASK)
3547 
3548 /*! @name F3 - LLWU Flag 3 register */
3549 #define LLWU_F3_MWUF0_MASK                       (0x1U)
3550 #define LLWU_F3_MWUF0_SHIFT                      (0U)
3551 #define LLWU_F3_MWUF0(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF0_SHIFT)) & LLWU_F3_MWUF0_MASK)
3552 #define LLWU_F3_MWUF1_MASK                       (0x2U)
3553 #define LLWU_F3_MWUF1_SHIFT                      (1U)
3554 #define LLWU_F3_MWUF1(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF1_SHIFT)) & LLWU_F3_MWUF1_MASK)
3555 #define LLWU_F3_MWUF2_MASK                       (0x4U)
3556 #define LLWU_F3_MWUF2_SHIFT                      (2U)
3557 #define LLWU_F3_MWUF2(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF2_SHIFT)) & LLWU_F3_MWUF2_MASK)
3558 #define LLWU_F3_MWUF3_MASK                       (0x8U)
3559 #define LLWU_F3_MWUF3_SHIFT                      (3U)
3560 #define LLWU_F3_MWUF3(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF3_SHIFT)) & LLWU_F3_MWUF3_MASK)
3561 #define LLWU_F3_MWUF4_MASK                       (0x10U)
3562 #define LLWU_F3_MWUF4_SHIFT                      (4U)
3563 #define LLWU_F3_MWUF4(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF4_SHIFT)) & LLWU_F3_MWUF4_MASK)
3564 #define LLWU_F3_MWUF5_MASK                       (0x20U)
3565 #define LLWU_F3_MWUF5_SHIFT                      (5U)
3566 #define LLWU_F3_MWUF5(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF5_SHIFT)) & LLWU_F3_MWUF5_MASK)
3567 #define LLWU_F3_MWUF6_MASK                       (0x40U)
3568 #define LLWU_F3_MWUF6_SHIFT                      (6U)
3569 #define LLWU_F3_MWUF6(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF6_SHIFT)) & LLWU_F3_MWUF6_MASK)
3570 #define LLWU_F3_MWUF7_MASK                       (0x80U)
3571 #define LLWU_F3_MWUF7_SHIFT                      (7U)
3572 #define LLWU_F3_MWUF7(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF7_SHIFT)) & LLWU_F3_MWUF7_MASK)
3573 
3574 /*! @name FILT1 - LLWU Pin Filter 1 register */
3575 #define LLWU_FILT1_FILTSEL_MASK                  (0xFU)
3576 #define LLWU_FILT1_FILTSEL_SHIFT                 (0U)
3577 #define LLWU_FILT1_FILTSEL(x)                    (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTSEL_SHIFT)) & LLWU_FILT1_FILTSEL_MASK)
3578 #define LLWU_FILT1_FILTE_MASK                    (0x60U)
3579 #define LLWU_FILT1_FILTE_SHIFT                   (5U)
3580 #define LLWU_FILT1_FILTE(x)                      (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTE_SHIFT)) & LLWU_FILT1_FILTE_MASK)
3581 #define LLWU_FILT1_FILTF_MASK                    (0x80U)
3582 #define LLWU_FILT1_FILTF_SHIFT                   (7U)
3583 #define LLWU_FILT1_FILTF(x)                      (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTF_SHIFT)) & LLWU_FILT1_FILTF_MASK)
3584 
3585 /*! @name FILT2 - LLWU Pin Filter 2 register */
3586 #define LLWU_FILT2_FILTSEL_MASK                  (0xFU)
3587 #define LLWU_FILT2_FILTSEL_SHIFT                 (0U)
3588 #define LLWU_FILT2_FILTSEL(x)                    (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTSEL_SHIFT)) & LLWU_FILT2_FILTSEL_MASK)
3589 #define LLWU_FILT2_FILTE_MASK                    (0x60U)
3590 #define LLWU_FILT2_FILTE_SHIFT                   (5U)
3591 #define LLWU_FILT2_FILTE(x)                      (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTE_SHIFT)) & LLWU_FILT2_FILTE_MASK)
3592 #define LLWU_FILT2_FILTF_MASK                    (0x80U)
3593 #define LLWU_FILT2_FILTF_SHIFT                   (7U)
3594 #define LLWU_FILT2_FILTF(x)                      (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTF_SHIFT)) & LLWU_FILT2_FILTF_MASK)
3595 
3596 
3597 /*!
3598  * @}
3599  */ /* end of group LLWU_Register_Masks */
3600 
3601 
3602 /* LLWU - Peripheral instance base addresses */
3603 /** Peripheral LLWU base address */
3604 #define LLWU_BASE                                (0x4007C000u)
3605 /** Peripheral LLWU base pointer */
3606 #define LLWU                                     ((LLWU_Type *)LLWU_BASE)
3607 /** Array initializer of LLWU peripheral base addresses */
3608 #define LLWU_BASE_ADDRS                          { LLWU_BASE }
3609 /** Array initializer of LLWU peripheral base pointers */
3610 #define LLWU_BASE_PTRS                           { LLWU }
3611 /** Interrupt vectors for the LLWU peripheral type */
3612 #define LLWU_IRQS                                { LLWU_IRQn }
3613 
3614 /*!
3615  * @}
3616  */ /* end of group LLWU_Peripheral_Access_Layer */
3617 
3618 
3619 /* ----------------------------------------------------------------------------
3620    -- LPTMR Peripheral Access Layer
3621    ---------------------------------------------------------------------------- */
3622 
3623 /*!
3624  * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
3625  * @{
3626  */
3627 
3628 /** LPTMR - Register Layout Typedef */
3629 typedef struct {
3630   __IO uint32_t CSR;                               /**< Low Power Timer Control Status Register, offset: 0x0 */
3631   __IO uint32_t PSR;                               /**< Low Power Timer Prescale Register, offset: 0x4 */
3632   __IO uint32_t CMR;                               /**< Low Power Timer Compare Register, offset: 0x8 */
3633   __IO uint32_t CNR;                               /**< Low Power Timer Counter Register, offset: 0xC */
3634 } LPTMR_Type;
3635 
3636 /* ----------------------------------------------------------------------------
3637    -- LPTMR Register Masks
3638    ---------------------------------------------------------------------------- */
3639 
3640 /*!
3641  * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
3642  * @{
3643  */
3644 
3645 /*! @name CSR - Low Power Timer Control Status Register */
3646 #define LPTMR_CSR_TEN_MASK                       (0x1U)
3647 #define LPTMR_CSR_TEN_SHIFT                      (0U)
3648 #define LPTMR_CSR_TEN(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
3649 #define LPTMR_CSR_TMS_MASK                       (0x2U)
3650 #define LPTMR_CSR_TMS_SHIFT                      (1U)
3651 #define LPTMR_CSR_TMS(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
3652 #define LPTMR_CSR_TFC_MASK                       (0x4U)
3653 #define LPTMR_CSR_TFC_SHIFT                      (2U)
3654 #define LPTMR_CSR_TFC(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK)
3655 #define LPTMR_CSR_TPP_MASK                       (0x8U)
3656 #define LPTMR_CSR_TPP_SHIFT                      (3U)
3657 #define LPTMR_CSR_TPP(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
3658 #define LPTMR_CSR_TPS_MASK                       (0x30U)
3659 #define LPTMR_CSR_TPS_SHIFT                      (4U)
3660 #define LPTMR_CSR_TPS(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
3661 #define LPTMR_CSR_TIE_MASK                       (0x40U)
3662 #define LPTMR_CSR_TIE_SHIFT                      (6U)
3663 #define LPTMR_CSR_TIE(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK)
3664 #define LPTMR_CSR_TCF_MASK                       (0x80U)
3665 #define LPTMR_CSR_TCF_SHIFT                      (7U)
3666 #define LPTMR_CSR_TCF(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK)
3667 
3668 /*! @name PSR - Low Power Timer Prescale Register */
3669 #define LPTMR_PSR_PCS_MASK                       (0x3U)
3670 #define LPTMR_PSR_PCS_SHIFT                      (0U)
3671 #define LPTMR_PSR_PCS(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK)
3672 #define LPTMR_PSR_PBYP_MASK                      (0x4U)
3673 #define LPTMR_PSR_PBYP_SHIFT                     (2U)
3674 #define LPTMR_PSR_PBYP(x)                        (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK)
3675 #define LPTMR_PSR_PRESCALE_MASK                  (0x78U)
3676 #define LPTMR_PSR_PRESCALE_SHIFT                 (3U)
3677 #define LPTMR_PSR_PRESCALE(x)                    (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK)
3678 
3679 /*! @name CMR - Low Power Timer Compare Register */
3680 #define LPTMR_CMR_COMPARE_MASK                   (0xFFFFU)
3681 #define LPTMR_CMR_COMPARE_SHIFT                  (0U)
3682 #define LPTMR_CMR_COMPARE(x)                     (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK)
3683 
3684 /*! @name CNR - Low Power Timer Counter Register */
3685 #define LPTMR_CNR_COUNTER_MASK                   (0xFFFFU)
3686 #define LPTMR_CNR_COUNTER_SHIFT                  (0U)
3687 #define LPTMR_CNR_COUNTER(x)                     (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK)
3688 
3689 
3690 /*!
3691  * @}
3692  */ /* end of group LPTMR_Register_Masks */
3693 
3694 
3695 /* LPTMR - Peripheral instance base addresses */
3696 /** Peripheral LPTMR0 base address */
3697 #define LPTMR0_BASE                              (0x40040000u)
3698 /** Peripheral LPTMR0 base pointer */
3699 #define LPTMR0                                   ((LPTMR_Type *)LPTMR0_BASE)
3700 /** Array initializer of LPTMR peripheral base addresses */
3701 #define LPTMR_BASE_ADDRS                         { LPTMR0_BASE }
3702 /** Array initializer of LPTMR peripheral base pointers */
3703 #define LPTMR_BASE_PTRS                          { LPTMR0 }
3704 /** Interrupt vectors for the LPTMR peripheral type */
3705 #define LPTMR_IRQS                               { LPTMR0_IRQn }
3706 
3707 /*!
3708  * @}
3709  */ /* end of group LPTMR_Peripheral_Access_Layer */
3710 
3711 
3712 /* ----------------------------------------------------------------------------
3713    -- LPUART Peripheral Access Layer
3714    ---------------------------------------------------------------------------- */
3715 
3716 /*!
3717  * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer
3718  * @{
3719  */
3720 
3721 /** LPUART - Register Layout Typedef */
3722 typedef struct {
3723   __IO uint32_t BAUD;                              /**< LPUART Baud Rate Register, offset: 0x0 */
3724   __IO uint32_t STAT;                              /**< LPUART Status Register, offset: 0x4 */
3725   __IO uint32_t CTRL;                              /**< LPUART Control Register, offset: 0x8 */
3726   __IO uint32_t DATA;                              /**< LPUART Data Register, offset: 0xC */
3727   __IO uint32_t MATCH;                             /**< LPUART Match Address Register, offset: 0x10 */
3728   __IO uint32_t MODIR;                             /**< LPUART Modem IrDA Register, offset: 0x14 */
3729 } LPUART_Type;
3730 
3731 /* ----------------------------------------------------------------------------
3732    -- LPUART Register Masks
3733    ---------------------------------------------------------------------------- */
3734 
3735 /*!
3736  * @addtogroup LPUART_Register_Masks LPUART Register Masks
3737  * @{
3738  */
3739 
3740 /*! @name BAUD - LPUART Baud Rate Register */
3741 #define LPUART_BAUD_SBR_MASK                     (0x1FFFU)
3742 #define LPUART_BAUD_SBR_SHIFT                    (0U)
3743 #define LPUART_BAUD_SBR(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK)
3744 #define LPUART_BAUD_SBNS_MASK                    (0x2000U)
3745 #define LPUART_BAUD_SBNS_SHIFT                   (13U)
3746 #define LPUART_BAUD_SBNS(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK)
3747 #define LPUART_BAUD_RXEDGIE_MASK                 (0x4000U)
3748 #define LPUART_BAUD_RXEDGIE_SHIFT                (14U)
3749 #define LPUART_BAUD_RXEDGIE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK)
3750 #define LPUART_BAUD_LBKDIE_MASK                  (0x8000U)
3751 #define LPUART_BAUD_LBKDIE_SHIFT                 (15U)
3752 #define LPUART_BAUD_LBKDIE(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK)
3753 #define LPUART_BAUD_RESYNCDIS_MASK               (0x10000U)
3754 #define LPUART_BAUD_RESYNCDIS_SHIFT              (16U)
3755 #define LPUART_BAUD_RESYNCDIS(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK)
3756 #define LPUART_BAUD_BOTHEDGE_MASK                (0x20000U)
3757 #define LPUART_BAUD_BOTHEDGE_SHIFT               (17U)
3758 #define LPUART_BAUD_BOTHEDGE(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK)
3759 #define LPUART_BAUD_MATCFG_MASK                  (0xC0000U)
3760 #define LPUART_BAUD_MATCFG_SHIFT                 (18U)
3761 #define LPUART_BAUD_MATCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK)
3762 #define LPUART_BAUD_RDMAE_MASK                   (0x200000U)
3763 #define LPUART_BAUD_RDMAE_SHIFT                  (21U)
3764 #define LPUART_BAUD_RDMAE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK)
3765 #define LPUART_BAUD_TDMAE_MASK                   (0x800000U)
3766 #define LPUART_BAUD_TDMAE_SHIFT                  (23U)
3767 #define LPUART_BAUD_TDMAE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK)
3768 #define LPUART_BAUD_OSR_MASK                     (0x1F000000U)
3769 #define LPUART_BAUD_OSR_SHIFT                    (24U)
3770 #define LPUART_BAUD_OSR(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK)
3771 #define LPUART_BAUD_M10_MASK                     (0x20000000U)
3772 #define LPUART_BAUD_M10_SHIFT                    (29U)
3773 #define LPUART_BAUD_M10(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK)
3774 #define LPUART_BAUD_MAEN2_MASK                   (0x40000000U)
3775 #define LPUART_BAUD_MAEN2_SHIFT                  (30U)
3776 #define LPUART_BAUD_MAEN2(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK)
3777 #define LPUART_BAUD_MAEN1_MASK                   (0x80000000U)
3778 #define LPUART_BAUD_MAEN1_SHIFT                  (31U)
3779 #define LPUART_BAUD_MAEN1(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK)
3780 
3781 /*! @name STAT - LPUART Status Register */
3782 #define LPUART_STAT_MA2F_MASK                    (0x4000U)
3783 #define LPUART_STAT_MA2F_SHIFT                   (14U)
3784 #define LPUART_STAT_MA2F(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK)
3785 #define LPUART_STAT_MA1F_MASK                    (0x8000U)
3786 #define LPUART_STAT_MA1F_SHIFT                   (15U)
3787 #define LPUART_STAT_MA1F(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK)
3788 #define LPUART_STAT_PF_MASK                      (0x10000U)
3789 #define LPUART_STAT_PF_SHIFT                     (16U)
3790 #define LPUART_STAT_PF(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK)
3791 #define LPUART_STAT_FE_MASK                      (0x20000U)
3792 #define LPUART_STAT_FE_SHIFT                     (17U)
3793 #define LPUART_STAT_FE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK)
3794 #define LPUART_STAT_NF_MASK                      (0x40000U)
3795 #define LPUART_STAT_NF_SHIFT                     (18U)
3796 #define LPUART_STAT_NF(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK)
3797 #define LPUART_STAT_OR_MASK                      (0x80000U)
3798 #define LPUART_STAT_OR_SHIFT                     (19U)
3799 #define LPUART_STAT_OR(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK)
3800 #define LPUART_STAT_IDLE_MASK                    (0x100000U)
3801 #define LPUART_STAT_IDLE_SHIFT                   (20U)
3802 #define LPUART_STAT_IDLE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK)
3803 #define LPUART_STAT_RDRF_MASK                    (0x200000U)
3804 #define LPUART_STAT_RDRF_SHIFT                   (21U)
3805 #define LPUART_STAT_RDRF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK)
3806 #define LPUART_STAT_TC_MASK                      (0x400000U)
3807 #define LPUART_STAT_TC_SHIFT                     (22U)
3808 #define LPUART_STAT_TC(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK)
3809 #define LPUART_STAT_TDRE_MASK                    (0x800000U)
3810 #define LPUART_STAT_TDRE_SHIFT                   (23U)
3811 #define LPUART_STAT_TDRE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK)
3812 #define LPUART_STAT_RAF_MASK                     (0x1000000U)
3813 #define LPUART_STAT_RAF_SHIFT                    (24U)
3814 #define LPUART_STAT_RAF(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK)
3815 #define LPUART_STAT_LBKDE_MASK                   (0x2000000U)
3816 #define LPUART_STAT_LBKDE_SHIFT                  (25U)
3817 #define LPUART_STAT_LBKDE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK)
3818 #define LPUART_STAT_BRK13_MASK                   (0x4000000U)
3819 #define LPUART_STAT_BRK13_SHIFT                  (26U)
3820 #define LPUART_STAT_BRK13(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK)
3821 #define LPUART_STAT_RWUID_MASK                   (0x8000000U)
3822 #define LPUART_STAT_RWUID_SHIFT                  (27U)
3823 #define LPUART_STAT_RWUID(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK)
3824 #define LPUART_STAT_RXINV_MASK                   (0x10000000U)
3825 #define LPUART_STAT_RXINV_SHIFT                  (28U)
3826 #define LPUART_STAT_RXINV(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK)
3827 #define LPUART_STAT_MSBF_MASK                    (0x20000000U)
3828 #define LPUART_STAT_MSBF_SHIFT                   (29U)
3829 #define LPUART_STAT_MSBF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK)
3830 #define LPUART_STAT_RXEDGIF_MASK                 (0x40000000U)
3831 #define LPUART_STAT_RXEDGIF_SHIFT                (30U)
3832 #define LPUART_STAT_RXEDGIF(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK)
3833 #define LPUART_STAT_LBKDIF_MASK                  (0x80000000U)
3834 #define LPUART_STAT_LBKDIF_SHIFT                 (31U)
3835 #define LPUART_STAT_LBKDIF(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK)
3836 
3837 /*! @name CTRL - LPUART Control Register */
3838 #define LPUART_CTRL_PT_MASK                      (0x1U)
3839 #define LPUART_CTRL_PT_SHIFT                     (0U)
3840 #define LPUART_CTRL_PT(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK)
3841 #define LPUART_CTRL_PE_MASK                      (0x2U)
3842 #define LPUART_CTRL_PE_SHIFT                     (1U)
3843 #define LPUART_CTRL_PE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK)
3844 #define LPUART_CTRL_ILT_MASK                     (0x4U)
3845 #define LPUART_CTRL_ILT_SHIFT                    (2U)
3846 #define LPUART_CTRL_ILT(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK)
3847 #define LPUART_CTRL_WAKE_MASK                    (0x8U)
3848 #define LPUART_CTRL_WAKE_SHIFT                   (3U)
3849 #define LPUART_CTRL_WAKE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK)
3850 #define LPUART_CTRL_M_MASK                       (0x10U)
3851 #define LPUART_CTRL_M_SHIFT                      (4U)
3852 #define LPUART_CTRL_M(x)                         (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK)
3853 #define LPUART_CTRL_RSRC_MASK                    (0x20U)
3854 #define LPUART_CTRL_RSRC_SHIFT                   (5U)
3855 #define LPUART_CTRL_RSRC(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK)
3856 #define LPUART_CTRL_DOZEEN_MASK                  (0x40U)
3857 #define LPUART_CTRL_DOZEEN_SHIFT                 (6U)
3858 #define LPUART_CTRL_DOZEEN(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK)
3859 #define LPUART_CTRL_LOOPS_MASK                   (0x80U)
3860 #define LPUART_CTRL_LOOPS_SHIFT                  (7U)
3861 #define LPUART_CTRL_LOOPS(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK)
3862 #define LPUART_CTRL_IDLECFG_MASK                 (0x700U)
3863 #define LPUART_CTRL_IDLECFG_SHIFT                (8U)
3864 #define LPUART_CTRL_IDLECFG(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK)
3865 #define LPUART_CTRL_MA2IE_MASK                   (0x4000U)
3866 #define LPUART_CTRL_MA2IE_SHIFT                  (14U)
3867 #define LPUART_CTRL_MA2IE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK)
3868 #define LPUART_CTRL_MA1IE_MASK                   (0x8000U)
3869 #define LPUART_CTRL_MA1IE_SHIFT                  (15U)
3870 #define LPUART_CTRL_MA1IE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK)
3871 #define LPUART_CTRL_SBK_MASK                     (0x10000U)
3872 #define LPUART_CTRL_SBK_SHIFT                    (16U)
3873 #define LPUART_CTRL_SBK(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK)
3874 #define LPUART_CTRL_RWU_MASK                     (0x20000U)
3875 #define LPUART_CTRL_RWU_SHIFT                    (17U)
3876 #define LPUART_CTRL_RWU(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK)
3877 #define LPUART_CTRL_RE_MASK                      (0x40000U)
3878 #define LPUART_CTRL_RE_SHIFT                     (18U)
3879 #define LPUART_CTRL_RE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK)
3880 #define LPUART_CTRL_TE_MASK                      (0x80000U)
3881 #define LPUART_CTRL_TE_SHIFT                     (19U)
3882 #define LPUART_CTRL_TE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK)
3883 #define LPUART_CTRL_ILIE_MASK                    (0x100000U)
3884 #define LPUART_CTRL_ILIE_SHIFT                   (20U)
3885 #define LPUART_CTRL_ILIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK)
3886 #define LPUART_CTRL_RIE_MASK                     (0x200000U)
3887 #define LPUART_CTRL_RIE_SHIFT                    (21U)
3888 #define LPUART_CTRL_RIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK)
3889 #define LPUART_CTRL_TCIE_MASK                    (0x400000U)
3890 #define LPUART_CTRL_TCIE_SHIFT                   (22U)
3891 #define LPUART_CTRL_TCIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK)
3892 #define LPUART_CTRL_TIE_MASK                     (0x800000U)
3893 #define LPUART_CTRL_TIE_SHIFT                    (23U)
3894 #define LPUART_CTRL_TIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK)
3895 #define LPUART_CTRL_PEIE_MASK                    (0x1000000U)
3896 #define LPUART_CTRL_PEIE_SHIFT                   (24U)
3897 #define LPUART_CTRL_PEIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK)
3898 #define LPUART_CTRL_FEIE_MASK                    (0x2000000U)
3899 #define LPUART_CTRL_FEIE_SHIFT                   (25U)
3900 #define LPUART_CTRL_FEIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK)
3901 #define LPUART_CTRL_NEIE_MASK                    (0x4000000U)
3902 #define LPUART_CTRL_NEIE_SHIFT                   (26U)
3903 #define LPUART_CTRL_NEIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK)
3904 #define LPUART_CTRL_ORIE_MASK                    (0x8000000U)
3905 #define LPUART_CTRL_ORIE_SHIFT                   (27U)
3906 #define LPUART_CTRL_ORIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK)
3907 #define LPUART_CTRL_TXINV_MASK                   (0x10000000U)
3908 #define LPUART_CTRL_TXINV_SHIFT                  (28U)
3909 #define LPUART_CTRL_TXINV(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK)
3910 #define LPUART_CTRL_TXDIR_MASK                   (0x20000000U)
3911 #define LPUART_CTRL_TXDIR_SHIFT                  (29U)
3912 #define LPUART_CTRL_TXDIR(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK)
3913 #define LPUART_CTRL_R9T8_MASK                    (0x40000000U)
3914 #define LPUART_CTRL_R9T8_SHIFT                   (30U)
3915 #define LPUART_CTRL_R9T8(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK)
3916 #define LPUART_CTRL_R8T9_MASK                    (0x80000000U)
3917 #define LPUART_CTRL_R8T9_SHIFT                   (31U)
3918 #define LPUART_CTRL_R8T9(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK)
3919 
3920 /*! @name DATA - LPUART Data Register */
3921 #define LPUART_DATA_R0T0_MASK                    (0x1U)
3922 #define LPUART_DATA_R0T0_SHIFT                   (0U)
3923 #define LPUART_DATA_R0T0(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK)
3924 #define LPUART_DATA_R1T1_MASK                    (0x2U)
3925 #define LPUART_DATA_R1T1_SHIFT                   (1U)
3926 #define LPUART_DATA_R1T1(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK)
3927 #define LPUART_DATA_R2T2_MASK                    (0x4U)
3928 #define LPUART_DATA_R2T2_SHIFT                   (2U)
3929 #define LPUART_DATA_R2T2(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK)
3930 #define LPUART_DATA_R3T3_MASK                    (0x8U)
3931 #define LPUART_DATA_R3T3_SHIFT                   (3U)
3932 #define LPUART_DATA_R3T3(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK)
3933 #define LPUART_DATA_R4T4_MASK                    (0x10U)
3934 #define LPUART_DATA_R4T4_SHIFT                   (4U)
3935 #define LPUART_DATA_R4T4(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK)
3936 #define LPUART_DATA_R5T5_MASK                    (0x20U)
3937 #define LPUART_DATA_R5T5_SHIFT                   (5U)
3938 #define LPUART_DATA_R5T5(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK)
3939 #define LPUART_DATA_R6T6_MASK                    (0x40U)
3940 #define LPUART_DATA_R6T6_SHIFT                   (6U)
3941 #define LPUART_DATA_R6T6(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK)
3942 #define LPUART_DATA_R7T7_MASK                    (0x80U)
3943 #define LPUART_DATA_R7T7_SHIFT                   (7U)
3944 #define LPUART_DATA_R7T7(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK)
3945 #define LPUART_DATA_R8T8_MASK                    (0x100U)
3946 #define LPUART_DATA_R8T8_SHIFT                   (8U)
3947 #define LPUART_DATA_R8T8(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK)
3948 #define LPUART_DATA_R9T9_MASK                    (0x200U)
3949 #define LPUART_DATA_R9T9_SHIFT                   (9U)
3950 #define LPUART_DATA_R9T9(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK)
3951 #define LPUART_DATA_IDLINE_MASK                  (0x800U)
3952 #define LPUART_DATA_IDLINE_SHIFT                 (11U)
3953 #define LPUART_DATA_IDLINE(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK)
3954 #define LPUART_DATA_RXEMPT_MASK                  (0x1000U)
3955 #define LPUART_DATA_RXEMPT_SHIFT                 (12U)
3956 #define LPUART_DATA_RXEMPT(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK)
3957 #define LPUART_DATA_FRETSC_MASK                  (0x2000U)
3958 #define LPUART_DATA_FRETSC_SHIFT                 (13U)
3959 #define LPUART_DATA_FRETSC(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK)
3960 #define LPUART_DATA_PARITYE_MASK                 (0x4000U)
3961 #define LPUART_DATA_PARITYE_SHIFT                (14U)
3962 #define LPUART_DATA_PARITYE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK)
3963 #define LPUART_DATA_NOISY_MASK                   (0x8000U)
3964 #define LPUART_DATA_NOISY_SHIFT                  (15U)
3965 #define LPUART_DATA_NOISY(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK)
3966 
3967 /*! @name MATCH - LPUART Match Address Register */
3968 #define LPUART_MATCH_MA1_MASK                    (0x3FFU)
3969 #define LPUART_MATCH_MA1_SHIFT                   (0U)
3970 #define LPUART_MATCH_MA1(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK)
3971 #define LPUART_MATCH_MA2_MASK                    (0x3FF0000U)
3972 #define LPUART_MATCH_MA2_SHIFT                   (16U)
3973 #define LPUART_MATCH_MA2(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK)
3974 
3975 /*! @name MODIR - LPUART Modem IrDA Register */
3976 #define LPUART_MODIR_TXCTSE_MASK                 (0x1U)
3977 #define LPUART_MODIR_TXCTSE_SHIFT                (0U)
3978 #define LPUART_MODIR_TXCTSE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK)
3979 #define LPUART_MODIR_TXRTSE_MASK                 (0x2U)
3980 #define LPUART_MODIR_TXRTSE_SHIFT                (1U)
3981 #define LPUART_MODIR_TXRTSE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK)
3982 #define LPUART_MODIR_TXRTSPOL_MASK               (0x4U)
3983 #define LPUART_MODIR_TXRTSPOL_SHIFT              (2U)
3984 #define LPUART_MODIR_TXRTSPOL(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK)
3985 #define LPUART_MODIR_RXRTSE_MASK                 (0x8U)
3986 #define LPUART_MODIR_RXRTSE_SHIFT                (3U)
3987 #define LPUART_MODIR_RXRTSE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK)
3988 #define LPUART_MODIR_TXCTSC_MASK                 (0x10U)
3989 #define LPUART_MODIR_TXCTSC_SHIFT                (4U)
3990 #define LPUART_MODIR_TXCTSC(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK)
3991 #define LPUART_MODIR_TXCTSSRC_MASK               (0x20U)
3992 #define LPUART_MODIR_TXCTSSRC_SHIFT              (5U)
3993 #define LPUART_MODIR_TXCTSSRC(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK)
3994 #define LPUART_MODIR_TNP_MASK                    (0x30000U)
3995 #define LPUART_MODIR_TNP_SHIFT                   (16U)
3996 #define LPUART_MODIR_TNP(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK)
3997 #define LPUART_MODIR_IREN_MASK                   (0x40000U)
3998 #define LPUART_MODIR_IREN_SHIFT                  (18U)
3999 #define LPUART_MODIR_IREN(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK)
4000 
4001 
4002 /*!
4003  * @}
4004  */ /* end of group LPUART_Register_Masks */
4005 
4006 
4007 /* LPUART - Peripheral instance base addresses */
4008 /** Peripheral LPUART0 base address */
4009 #define LPUART0_BASE                             (0x40054000u)
4010 /** Peripheral LPUART0 base pointer */
4011 #define LPUART0                                  ((LPUART_Type *)LPUART0_BASE)
4012 /** Array initializer of LPUART peripheral base addresses */
4013 #define LPUART_BASE_ADDRS                        { LPUART0_BASE }
4014 /** Array initializer of LPUART peripheral base pointers */
4015 #define LPUART_BASE_PTRS                         { LPUART0 }
4016 /** Interrupt vectors for the LPUART peripheral type */
4017 #define LPUART_RX_TX_IRQS                        { LPUART0_IRQn }
4018 #define LPUART_ERR_IRQS                          { LPUART0_IRQn }
4019 
4020 /*!
4021  * @}
4022  */ /* end of group LPUART_Peripheral_Access_Layer */
4023 
4024 
4025 /* ----------------------------------------------------------------------------
4026    -- LTC Peripheral Access Layer
4027    ---------------------------------------------------------------------------- */
4028 
4029 /*!
4030  * @addtogroup LTC_Peripheral_Access_Layer LTC Peripheral Access Layer
4031  * @{
4032  */
4033 
4034 /** LTC - Register Layout Typedef */
4035 typedef struct {
4036   __IO uint32_t MD;                                /**< Mode Register, offset: 0x0 */
4037        uint8_t RESERVED_0[4];
4038   __IO uint32_t KS;                                /**< Key Size Register, offset: 0x8 */
4039        uint8_t RESERVED_1[4];
4040   __IO uint32_t DS;                                /**< Data Size Register, offset: 0x10 */
4041        uint8_t RESERVED_2[4];
4042   __IO uint32_t ICVS;                              /**< ICV Size Register, offset: 0x18 */
4043        uint8_t RESERVED_3[20];
4044   __IO uint32_t COM;                               /**< Command Register, offset: 0x30 */
4045   __IO uint32_t CTL;                               /**< Control Register, offset: 0x34 */
4046        uint8_t RESERVED_4[8];
4047   __IO uint32_t CW;                                /**< Clear Written Register, offset: 0x40 */
4048        uint8_t RESERVED_5[4];
4049   __IO uint32_t STA;                               /**< Status Register, offset: 0x48 */
4050   __I  uint32_t ESTA;                              /**< Error Status Register, offset: 0x4C */
4051        uint8_t RESERVED_6[8];
4052   __IO uint32_t AADSZ;                             /**< AAD Size Register, offset: 0x58 */
4053        uint8_t RESERVED_7[164];
4054   __IO uint32_t CTX[14];                           /**< Context Register, array offset: 0x100, array step: 0x4 */
4055        uint8_t RESERVED_8[200];
4056   __IO uint32_t KEY[4];                            /**< Key Registers, array offset: 0x200, array step: 0x4 */
4057        uint8_t RESERVED_9[736];
4058   __I  uint32_t VID1;                              /**< Version ID Register, offset: 0x4F0 */
4059   __I  uint32_t VID2;                              /**< Version ID 2 Register, offset: 0x4F4 */
4060   __I  uint32_t CHAVID;                            /**< CHA Version ID Register, offset: 0x4F8 */
4061        uint8_t RESERVED_10[708];
4062   __I  uint32_t FIFOSTA;                           /**< FIFO Status Register, offset: 0x7C0 */
4063        uint8_t RESERVED_11[28];
4064   __O  uint32_t IFIFO;                             /**< Input Data FIFO, offset: 0x7E0 */
4065        uint8_t RESERVED_12[12];
4066   __I  uint32_t OFIFO;                             /**< Output Data FIFO, offset: 0x7F0 */
4067 } LTC_Type;
4068 
4069 /* ----------------------------------------------------------------------------
4070    -- LTC Register Masks
4071    ---------------------------------------------------------------------------- */
4072 
4073 /*!
4074  * @addtogroup LTC_Register_Masks LTC Register Masks
4075  * @{
4076  */
4077 
4078 /*! @name MD - Mode Register */
4079 #define LTC_MD_ENC_MASK                          (0x1U)
4080 #define LTC_MD_ENC_SHIFT                         (0U)
4081 #define LTC_MD_ENC(x)                            (((uint32_t)(((uint32_t)(x)) << LTC_MD_ENC_SHIFT)) & LTC_MD_ENC_MASK)
4082 #define LTC_MD_ICV_TEST_MASK                     (0x2U)
4083 #define LTC_MD_ICV_TEST_SHIFT                    (1U)
4084 #define LTC_MD_ICV_TEST(x)                       (((uint32_t)(((uint32_t)(x)) << LTC_MD_ICV_TEST_SHIFT)) & LTC_MD_ICV_TEST_MASK)
4085 #define LTC_MD_AS_MASK                           (0xCU)
4086 #define LTC_MD_AS_SHIFT                          (2U)
4087 #define LTC_MD_AS(x)                             (((uint32_t)(((uint32_t)(x)) << LTC_MD_AS_SHIFT)) & LTC_MD_AS_MASK)
4088 #define LTC_MD_AAI_MASK                          (0x1FF0U)
4089 #define LTC_MD_AAI_SHIFT                         (4U)
4090 #define LTC_MD_AAI(x)                            (((uint32_t)(((uint32_t)(x)) << LTC_MD_AAI_SHIFT)) & LTC_MD_AAI_MASK)
4091 #define LTC_MD_ALG_MASK                          (0xFF0000U)
4092 #define LTC_MD_ALG_SHIFT                         (16U)
4093 #define LTC_MD_ALG(x)                            (((uint32_t)(((uint32_t)(x)) << LTC_MD_ALG_SHIFT)) & LTC_MD_ALG_MASK)
4094 
4095 /*! @name KS - Key Size Register */
4096 #define LTC_KS_KS_MASK                           (0x1FU)
4097 #define LTC_KS_KS_SHIFT                          (0U)
4098 #define LTC_KS_KS(x)                             (((uint32_t)(((uint32_t)(x)) << LTC_KS_KS_SHIFT)) & LTC_KS_KS_MASK)
4099 
4100 /*! @name DS - Data Size Register */
4101 #define LTC_DS_DS_MASK                           (0xFFFU)
4102 #define LTC_DS_DS_SHIFT                          (0U)
4103 #define LTC_DS_DS(x)                             (((uint32_t)(((uint32_t)(x)) << LTC_DS_DS_SHIFT)) & LTC_DS_DS_MASK)
4104 
4105 /*! @name ICVS - ICV Size Register */
4106 #define LTC_ICVS_ICVS_MASK                       (0x1FU)
4107 #define LTC_ICVS_ICVS_SHIFT                      (0U)
4108 #define LTC_ICVS_ICVS(x)                         (((uint32_t)(((uint32_t)(x)) << LTC_ICVS_ICVS_SHIFT)) & LTC_ICVS_ICVS_MASK)
4109 
4110 /*! @name COM - Command Register */
4111 #define LTC_COM_ALL_MASK                         (0x1U)
4112 #define LTC_COM_ALL_SHIFT                        (0U)
4113 #define LTC_COM_ALL(x)                           (((uint32_t)(((uint32_t)(x)) << LTC_COM_ALL_SHIFT)) & LTC_COM_ALL_MASK)
4114 #define LTC_COM_AES_MASK                         (0x2U)
4115 #define LTC_COM_AES_SHIFT                        (1U)
4116 #define LTC_COM_AES(x)                           (((uint32_t)(((uint32_t)(x)) << LTC_COM_AES_SHIFT)) & LTC_COM_AES_MASK)
4117 
4118 /*! @name CTL - Control Register */
4119 #define LTC_CTL_IM_MASK                          (0x1U)
4120 #define LTC_CTL_IM_SHIFT                         (0U)
4121 #define LTC_CTL_IM(x)                            (((uint32_t)(((uint32_t)(x)) << LTC_CTL_IM_SHIFT)) & LTC_CTL_IM_MASK)
4122 #define LTC_CTL_IFE_MASK                         (0x100U)
4123 #define LTC_CTL_IFE_SHIFT                        (8U)
4124 #define LTC_CTL_IFE(x)                           (((uint32_t)(((uint32_t)(x)) << LTC_CTL_IFE_SHIFT)) & LTC_CTL_IFE_MASK)
4125 #define LTC_CTL_IFR_MASK                         (0x200U)
4126 #define LTC_CTL_IFR_SHIFT                        (9U)
4127 #define LTC_CTL_IFR(x)                           (((uint32_t)(((uint32_t)(x)) << LTC_CTL_IFR_SHIFT)) & LTC_CTL_IFR_MASK)
4128 #define LTC_CTL_OFE_MASK                         (0x1000U)
4129 #define LTC_CTL_OFE_SHIFT                        (12U)
4130 #define LTC_CTL_OFE(x)                           (((uint32_t)(((uint32_t)(x)) << LTC_CTL_OFE_SHIFT)) & LTC_CTL_OFE_MASK)
4131 #define LTC_CTL_OFR_MASK                         (0x2000U)
4132 #define LTC_CTL_OFR_SHIFT                        (13U)
4133 #define LTC_CTL_OFR(x)                           (((uint32_t)(((uint32_t)(x)) << LTC_CTL_OFR_SHIFT)) & LTC_CTL_OFR_MASK)
4134 #define LTC_CTL_IFS_MASK                         (0x10000U)
4135 #define LTC_CTL_IFS_SHIFT                        (16U)
4136 #define LTC_CTL_IFS(x)                           (((uint32_t)(((uint32_t)(x)) << LTC_CTL_IFS_SHIFT)) & LTC_CTL_IFS_MASK)
4137 #define LTC_CTL_OFS_MASK                         (0x20000U)
4138 #define LTC_CTL_OFS_SHIFT                        (17U)
4139 #define LTC_CTL_OFS(x)                           (((uint32_t)(((uint32_t)(x)) << LTC_CTL_OFS_SHIFT)) & LTC_CTL_OFS_MASK)
4140 #define LTC_CTL_KIS_MASK                         (0x100000U)
4141 #define LTC_CTL_KIS_SHIFT                        (20U)
4142 #define LTC_CTL_KIS(x)                           (((uint32_t)(((uint32_t)(x)) << LTC_CTL_KIS_SHIFT)) & LTC_CTL_KIS_MASK)
4143 #define LTC_CTL_KOS_MASK                         (0x200000U)
4144 #define LTC_CTL_KOS_SHIFT                        (21U)
4145 #define LTC_CTL_KOS(x)                           (((uint32_t)(((uint32_t)(x)) << LTC_CTL_KOS_SHIFT)) & LTC_CTL_KOS_MASK)
4146 #define LTC_CTL_CIS_MASK                         (0x400000U)
4147 #define LTC_CTL_CIS_SHIFT                        (22U)
4148 #define LTC_CTL_CIS(x)                           (((uint32_t)(((uint32_t)(x)) << LTC_CTL_CIS_SHIFT)) & LTC_CTL_CIS_MASK)
4149 #define LTC_CTL_COS_MASK                         (0x800000U)
4150 #define LTC_CTL_COS_SHIFT                        (23U)
4151 #define LTC_CTL_COS(x)                           (((uint32_t)(((uint32_t)(x)) << LTC_CTL_COS_SHIFT)) & LTC_CTL_COS_MASK)
4152 #define LTC_CTL_KAL_MASK                         (0x80000000U)
4153 #define LTC_CTL_KAL_SHIFT                        (31U)
4154 #define LTC_CTL_KAL(x)                           (((uint32_t)(((uint32_t)(x)) << LTC_CTL_KAL_SHIFT)) & LTC_CTL_KAL_MASK)
4155 
4156 /*! @name CW - Clear Written Register */
4157 #define LTC_CW_CM_MASK                           (0x1U)
4158 #define LTC_CW_CM_SHIFT                          (0U)
4159 #define LTC_CW_CM(x)                             (((uint32_t)(((uint32_t)(x)) << LTC_CW_CM_SHIFT)) & LTC_CW_CM_MASK)
4160 #define LTC_CW_CDS_MASK                          (0x4U)
4161 #define LTC_CW_CDS_SHIFT                         (2U)
4162 #define LTC_CW_CDS(x)                            (((uint32_t)(((uint32_t)(x)) << LTC_CW_CDS_SHIFT)) & LTC_CW_CDS_MASK)
4163 #define LTC_CW_CICV_MASK                         (0x8U)
4164 #define LTC_CW_CICV_SHIFT                        (3U)
4165 #define LTC_CW_CICV(x)                           (((uint32_t)(((uint32_t)(x)) << LTC_CW_CICV_SHIFT)) & LTC_CW_CICV_MASK)
4166 #define LTC_CW_CCR_MASK                          (0x20U)
4167 #define LTC_CW_CCR_SHIFT                         (5U)
4168 #define LTC_CW_CCR(x)                            (((uint32_t)(((uint32_t)(x)) << LTC_CW_CCR_SHIFT)) & LTC_CW_CCR_MASK)
4169 #define LTC_CW_CKR_MASK                          (0x40U)
4170 #define LTC_CW_CKR_SHIFT                         (6U)
4171 #define LTC_CW_CKR(x)                            (((uint32_t)(((uint32_t)(x)) << LTC_CW_CKR_SHIFT)) & LTC_CW_CKR_MASK)
4172 #define LTC_CW_COF_MASK                          (0x40000000U)
4173 #define LTC_CW_COF_SHIFT                         (30U)
4174 #define LTC_CW_COF(x)                            (((uint32_t)(((uint32_t)(x)) << LTC_CW_COF_SHIFT)) & LTC_CW_COF_MASK)
4175 #define LTC_CW_CIF_MASK                          (0x80000000U)
4176 #define LTC_CW_CIF_SHIFT                         (31U)
4177 #define LTC_CW_CIF(x)                            (((uint32_t)(((uint32_t)(x)) << LTC_CW_CIF_SHIFT)) & LTC_CW_CIF_MASK)
4178 
4179 /*! @name STA - Status Register */
4180 #define LTC_STA_AB_MASK                          (0x2U)
4181 #define LTC_STA_AB_SHIFT                         (1U)
4182 #define LTC_STA_AB(x)                            (((uint32_t)(((uint32_t)(x)) << LTC_STA_AB_SHIFT)) & LTC_STA_AB_MASK)
4183 #define LTC_STA_DI_MASK                          (0x10000U)
4184 #define LTC_STA_DI_SHIFT                         (16U)
4185 #define LTC_STA_DI(x)                            (((uint32_t)(((uint32_t)(x)) << LTC_STA_DI_SHIFT)) & LTC_STA_DI_MASK)
4186 #define LTC_STA_EI_MASK                          (0x100000U)
4187 #define LTC_STA_EI_SHIFT                         (20U)
4188 #define LTC_STA_EI(x)                            (((uint32_t)(((uint32_t)(x)) << LTC_STA_EI_SHIFT)) & LTC_STA_EI_MASK)
4189 
4190 /*! @name ESTA - Error Status Register */
4191 #define LTC_ESTA_ERRID1_MASK                     (0xFU)
4192 #define LTC_ESTA_ERRID1_SHIFT                    (0U)
4193 #define LTC_ESTA_ERRID1(x)                       (((uint32_t)(((uint32_t)(x)) << LTC_ESTA_ERRID1_SHIFT)) & LTC_ESTA_ERRID1_MASK)
4194 #define LTC_ESTA_CL1_MASK                        (0xF00U)
4195 #define LTC_ESTA_CL1_SHIFT                       (8U)
4196 #define LTC_ESTA_CL1(x)                          (((uint32_t)(((uint32_t)(x)) << LTC_ESTA_CL1_SHIFT)) & LTC_ESTA_CL1_MASK)
4197 
4198 /*! @name AADSZ - AAD Size Register */
4199 #define LTC_AADSZ_AADSZ_MASK                     (0xFU)
4200 #define LTC_AADSZ_AADSZ_SHIFT                    (0U)
4201 #define LTC_AADSZ_AADSZ(x)                       (((uint32_t)(((uint32_t)(x)) << LTC_AADSZ_AADSZ_SHIFT)) & LTC_AADSZ_AADSZ_MASK)
4202 #define LTC_AADSZ_AL_MASK                        (0x80000000U)
4203 #define LTC_AADSZ_AL_SHIFT                       (31U)
4204 #define LTC_AADSZ_AL(x)                          (((uint32_t)(((uint32_t)(x)) << LTC_AADSZ_AL_SHIFT)) & LTC_AADSZ_AL_MASK)
4205 
4206 /*! @name CTX - Context Register */
4207 #define LTC_CTX_CTX_MASK                         (0xFFFFFFFFU)
4208 #define LTC_CTX_CTX_SHIFT                        (0U)
4209 #define LTC_CTX_CTX(x)                           (((uint32_t)(((uint32_t)(x)) << LTC_CTX_CTX_SHIFT)) & LTC_CTX_CTX_MASK)
4210 
4211 /* The count of LTC_CTX */
4212 #define LTC_CTX_COUNT                            (14U)
4213 
4214 /*! @name KEY - Key Registers */
4215 #define LTC_KEY_KEY_MASK                         (0xFFFFFFFFU)
4216 #define LTC_KEY_KEY_SHIFT                        (0U)
4217 #define LTC_KEY_KEY(x)                           (((uint32_t)(((uint32_t)(x)) << LTC_KEY_KEY_SHIFT)) & LTC_KEY_KEY_MASK)
4218 
4219 /* The count of LTC_KEY */
4220 #define LTC_KEY_COUNT                            (4U)
4221 
4222 /*! @name VID1 - Version ID Register */
4223 #define LTC_VID1_MIN_REV_MASK                    (0xFFU)
4224 #define LTC_VID1_MIN_REV_SHIFT                   (0U)
4225 #define LTC_VID1_MIN_REV(x)                      (((uint32_t)(((uint32_t)(x)) << LTC_VID1_MIN_REV_SHIFT)) & LTC_VID1_MIN_REV_MASK)
4226 #define LTC_VID1_MAJ_REV_MASK                    (0xFF00U)
4227 #define LTC_VID1_MAJ_REV_SHIFT                   (8U)
4228 #define LTC_VID1_MAJ_REV(x)                      (((uint32_t)(((uint32_t)(x)) << LTC_VID1_MAJ_REV_SHIFT)) & LTC_VID1_MAJ_REV_MASK)
4229 #define LTC_VID1_IP_ID_MASK                      (0xFFFF0000U)
4230 #define LTC_VID1_IP_ID_SHIFT                     (16U)
4231 #define LTC_VID1_IP_ID(x)                        (((uint32_t)(((uint32_t)(x)) << LTC_VID1_IP_ID_SHIFT)) & LTC_VID1_IP_ID_MASK)
4232 
4233 /*! @name VID2 - Version ID 2 Register */
4234 #define LTC_VID2_ECO_REV_MASK                    (0xFFU)
4235 #define LTC_VID2_ECO_REV_SHIFT                   (0U)
4236 #define LTC_VID2_ECO_REV(x)                      (((uint32_t)(((uint32_t)(x)) << LTC_VID2_ECO_REV_SHIFT)) & LTC_VID2_ECO_REV_MASK)
4237 #define LTC_VID2_ARCH_ERA_MASK                   (0xFF00U)
4238 #define LTC_VID2_ARCH_ERA_SHIFT                  (8U)
4239 #define LTC_VID2_ARCH_ERA(x)                     (((uint32_t)(((uint32_t)(x)) << LTC_VID2_ARCH_ERA_SHIFT)) & LTC_VID2_ARCH_ERA_MASK)
4240 
4241 /*! @name CHAVID - CHA Version ID Register */
4242 #define LTC_CHAVID_AESREV_MASK                   (0xFU)
4243 #define LTC_CHAVID_AESREV_SHIFT                  (0U)
4244 #define LTC_CHAVID_AESREV(x)                     (((uint32_t)(((uint32_t)(x)) << LTC_CHAVID_AESREV_SHIFT)) & LTC_CHAVID_AESREV_MASK)
4245 #define LTC_CHAVID_AESVID_MASK                   (0xF0U)
4246 #define LTC_CHAVID_AESVID_SHIFT                  (4U)
4247 #define LTC_CHAVID_AESVID(x)                     (((uint32_t)(((uint32_t)(x)) << LTC_CHAVID_AESVID_SHIFT)) & LTC_CHAVID_AESVID_MASK)
4248 
4249 /*! @name FIFOSTA - FIFO Status Register */
4250 #define LTC_FIFOSTA_IFL_MASK                     (0x7FU)
4251 #define LTC_FIFOSTA_IFL_SHIFT                    (0U)
4252 #define LTC_FIFOSTA_IFL(x)                       (((uint32_t)(((uint32_t)(x)) << LTC_FIFOSTA_IFL_SHIFT)) & LTC_FIFOSTA_IFL_MASK)
4253 #define LTC_FIFOSTA_IFF_MASK                     (0x8000U)
4254 #define LTC_FIFOSTA_IFF_SHIFT                    (15U)
4255 #define LTC_FIFOSTA_IFF(x)                       (((uint32_t)(((uint32_t)(x)) << LTC_FIFOSTA_IFF_SHIFT)) & LTC_FIFOSTA_IFF_MASK)
4256 #define LTC_FIFOSTA_OFL_MASK                     (0x7F0000U)
4257 #define LTC_FIFOSTA_OFL_SHIFT                    (16U)
4258 #define LTC_FIFOSTA_OFL(x)                       (((uint32_t)(((uint32_t)(x)) << LTC_FIFOSTA_OFL_SHIFT)) & LTC_FIFOSTA_OFL_MASK)
4259 #define LTC_FIFOSTA_OFF_MASK                     (0x80000000U)
4260 #define LTC_FIFOSTA_OFF_SHIFT                    (31U)
4261 #define LTC_FIFOSTA_OFF(x)                       (((uint32_t)(((uint32_t)(x)) << LTC_FIFOSTA_OFF_SHIFT)) & LTC_FIFOSTA_OFF_MASK)
4262 
4263 /*! @name IFIFO - Input Data FIFO */
4264 #define LTC_IFIFO_IFIFO_MASK                     (0xFFFFFFFFU)
4265 #define LTC_IFIFO_IFIFO_SHIFT                    (0U)
4266 #define LTC_IFIFO_IFIFO(x)                       (((uint32_t)(((uint32_t)(x)) << LTC_IFIFO_IFIFO_SHIFT)) & LTC_IFIFO_IFIFO_MASK)
4267 
4268 /*! @name OFIFO - Output Data FIFO */
4269 #define LTC_OFIFO_OFIFO_MASK                     (0xFFFFFFFFU)
4270 #define LTC_OFIFO_OFIFO_SHIFT                    (0U)
4271 #define LTC_OFIFO_OFIFO(x)                       (((uint32_t)(((uint32_t)(x)) << LTC_OFIFO_OFIFO_SHIFT)) & LTC_OFIFO_OFIFO_MASK)
4272 
4273 
4274 /*!
4275  * @}
4276  */ /* end of group LTC_Register_Masks */
4277 
4278 
4279 /* LTC - Peripheral instance base addresses */
4280 /** Peripheral LTC0 base address */
4281 #define LTC0_BASE                                (0x40058000u)
4282 /** Peripheral LTC0 base pointer */
4283 #define LTC0                                     ((LTC_Type *)LTC0_BASE)
4284 /** Array initializer of LTC peripheral base addresses */
4285 #define LTC_BASE_ADDRS                           { LTC0_BASE }
4286 /** Array initializer of LTC peripheral base pointers */
4287 #define LTC_BASE_PTRS                            { LTC0 }
4288 /** Interrupt vectors for the LTC peripheral type */
4289 #define LTC_IRQS                                 { LTC0_IRQn }
4290 
4291 /*!
4292  * @}
4293  */ /* end of group LTC_Peripheral_Access_Layer */
4294 
4295 
4296 /* ----------------------------------------------------------------------------
4297    -- MCG Peripheral Access Layer
4298    ---------------------------------------------------------------------------- */
4299 
4300 /*!
4301  * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
4302  * @{
4303  */
4304 
4305 /** MCG - Register Layout Typedef */
4306 typedef struct {
4307   __IO uint8_t C1;                                 /**< MCG Control 1 Register, offset: 0x0 */
4308   __IO uint8_t C2;                                 /**< MCG Control 2 Register, offset: 0x1 */
4309   __IO uint8_t C3;                                 /**< MCG Control 3 Register, offset: 0x2 */
4310   __IO uint8_t C4;                                 /**< MCG Control 4 Register, offset: 0x3 */
4311   __I  uint8_t C5;                                 /**< MCG Control 5 Register, offset: 0x4 */
4312   __IO uint8_t C6;                                 /**< MCG Control 6 Register, offset: 0x5 */
4313   __I  uint8_t S;                                  /**< MCG Status Register, offset: 0x6 */
4314        uint8_t RESERVED_0[1];
4315   __IO uint8_t SC;                                 /**< MCG Status and Control Register, offset: 0x8 */
4316        uint8_t RESERVED_1[1];
4317   __IO uint8_t ATCVH;                              /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
4318   __IO uint8_t ATCVL;                              /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
4319   __IO uint8_t C7;                                 /**< MCG Control 7 Register, offset: 0xC */
4320   __IO uint8_t C8;                                 /**< MCG Control 8 Register, offset: 0xD */
4321 } MCG_Type;
4322 
4323 /* ----------------------------------------------------------------------------
4324    -- MCG Register Masks
4325    ---------------------------------------------------------------------------- */
4326 
4327 /*!
4328  * @addtogroup MCG_Register_Masks MCG Register Masks
4329  * @{
4330  */
4331 
4332 /*! @name C1 - MCG Control 1 Register */
4333 #define MCG_C1_IREFSTEN_MASK                     (0x1U)
4334 #define MCG_C1_IREFSTEN_SHIFT                    (0U)
4335 #define MCG_C1_IREFSTEN(x)                       (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK)
4336 #define MCG_C1_IRCLKEN_MASK                      (0x2U)
4337 #define MCG_C1_IRCLKEN_SHIFT                     (1U)
4338 #define MCG_C1_IRCLKEN(x)                        (((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK)
4339 #define MCG_C1_IREFS_MASK                        (0x4U)
4340 #define MCG_C1_IREFS_SHIFT                       (2U)
4341 #define MCG_C1_IREFS(x)                          (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFS_SHIFT)) & MCG_C1_IREFS_MASK)
4342 #define MCG_C1_FRDIV_MASK                        (0x38U)
4343 #define MCG_C1_FRDIV_SHIFT                       (3U)
4344 #define MCG_C1_FRDIV(x)                          (((uint8_t)(((uint8_t)(x)) << MCG_C1_FRDIV_SHIFT)) & MCG_C1_FRDIV_MASK)
4345 #define MCG_C1_CLKS_MASK                         (0xC0U)
4346 #define MCG_C1_CLKS_SHIFT                        (6U)
4347 #define MCG_C1_CLKS(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK)
4348 
4349 /*! @name C2 - MCG Control 2 Register */
4350 #define MCG_C2_IRCS_MASK                         (0x1U)
4351 #define MCG_C2_IRCS_SHIFT                        (0U)
4352 #define MCG_C2_IRCS(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK)
4353 #define MCG_C2_LP_MASK                           (0x2U)
4354 #define MCG_C2_LP_SHIFT                          (1U)
4355 #define MCG_C2_LP(x)                             (((uint8_t)(((uint8_t)(x)) << MCG_C2_LP_SHIFT)) & MCG_C2_LP_MASK)
4356 #define MCG_C2_EREFS_MASK                        (0x4U)
4357 #define MCG_C2_EREFS_SHIFT                       (2U)
4358 #define MCG_C2_EREFS(x)                          (((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS_SHIFT)) & MCG_C2_EREFS_MASK)
4359 #define MCG_C2_HGO_MASK                          (0x8U)
4360 #define MCG_C2_HGO_SHIFT                         (3U)
4361 #define MCG_C2_HGO(x)                            (((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO_SHIFT)) & MCG_C2_HGO_MASK)
4362 #define MCG_C2_RANGE_MASK                        (0x30U)
4363 #define MCG_C2_RANGE_SHIFT                       (4U)
4364 #define MCG_C2_RANGE(x)                          (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE_SHIFT)) & MCG_C2_RANGE_MASK)
4365 #define MCG_C2_FCFTRIM_MASK                      (0x40U)
4366 #define MCG_C2_FCFTRIM_SHIFT                     (6U)
4367 #define MCG_C2_FCFTRIM(x)                        (((uint8_t)(((uint8_t)(x)) << MCG_C2_FCFTRIM_SHIFT)) & MCG_C2_FCFTRIM_MASK)
4368 #define MCG_C2_LOCRE0_MASK                       (0x80U)
4369 #define MCG_C2_LOCRE0_SHIFT                      (7U)
4370 #define MCG_C2_LOCRE0(x)                         (((uint8_t)(((uint8_t)(x)) << MCG_C2_LOCRE0_SHIFT)) & MCG_C2_LOCRE0_MASK)
4371 
4372 /*! @name C3 - MCG Control 3 Register */
4373 #define MCG_C3_SCTRIM_MASK                       (0xFFU)
4374 #define MCG_C3_SCTRIM_SHIFT                      (0U)
4375 #define MCG_C3_SCTRIM(x)                         (((uint8_t)(((uint8_t)(x)) << MCG_C3_SCTRIM_SHIFT)) & MCG_C3_SCTRIM_MASK)
4376 
4377 /*! @name C4 - MCG Control 4 Register */
4378 #define MCG_C4_SCFTRIM_MASK                      (0x1U)
4379 #define MCG_C4_SCFTRIM_SHIFT                     (0U)
4380 #define MCG_C4_SCFTRIM(x)                        (((uint8_t)(((uint8_t)(x)) << MCG_C4_SCFTRIM_SHIFT)) & MCG_C4_SCFTRIM_MASK)
4381 #define MCG_C4_FCTRIM_MASK                       (0x1EU)
4382 #define MCG_C4_FCTRIM_SHIFT                      (1U)
4383 #define MCG_C4_FCTRIM(x)                         (((uint8_t)(((uint8_t)(x)) << MCG_C4_FCTRIM_SHIFT)) & MCG_C4_FCTRIM_MASK)
4384 #define MCG_C4_DRST_DRS_MASK                     (0x60U)
4385 #define MCG_C4_DRST_DRS_SHIFT                    (5U)
4386 #define MCG_C4_DRST_DRS(x)                       (((uint8_t)(((uint8_t)(x)) << MCG_C4_DRST_DRS_SHIFT)) & MCG_C4_DRST_DRS_MASK)
4387 #define MCG_C4_DMX32_MASK                        (0x80U)
4388 #define MCG_C4_DMX32_SHIFT                       (7U)
4389 #define MCG_C4_DMX32(x)                          (((uint8_t)(((uint8_t)(x)) << MCG_C4_DMX32_SHIFT)) & MCG_C4_DMX32_MASK)
4390 
4391 /*! @name C6 - MCG Control 6 Register */
4392 #define MCG_C6_CME0_MASK                         (0x20U)
4393 #define MCG_C6_CME0_SHIFT                        (5U)
4394 #define MCG_C6_CME0(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_C6_CME0_SHIFT)) & MCG_C6_CME0_MASK)
4395 
4396 /*! @name S - MCG Status Register */
4397 #define MCG_S_IRCST_MASK                         (0x1U)
4398 #define MCG_S_IRCST_SHIFT                        (0U)
4399 #define MCG_S_IRCST(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_S_IRCST_SHIFT)) & MCG_S_IRCST_MASK)
4400 #define MCG_S_OSCINIT0_MASK                      (0x2U)
4401 #define MCG_S_OSCINIT0_SHIFT                     (1U)
4402 #define MCG_S_OSCINIT0(x)                        (((uint8_t)(((uint8_t)(x)) << MCG_S_OSCINIT0_SHIFT)) & MCG_S_OSCINIT0_MASK)
4403 #define MCG_S_CLKST_MASK                         (0xCU)
4404 #define MCG_S_CLKST_SHIFT                        (2U)
4405 #define MCG_S_CLKST(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK)
4406 #define MCG_S_IREFST_MASK                        (0x10U)
4407 #define MCG_S_IREFST_SHIFT                       (4U)
4408 #define MCG_S_IREFST(x)                          (((uint8_t)(((uint8_t)(x)) << MCG_S_IREFST_SHIFT)) & MCG_S_IREFST_MASK)
4409 
4410 /*! @name SC - MCG Status and Control Register */
4411 #define MCG_SC_LOCS0_MASK                        (0x1U)
4412 #define MCG_SC_LOCS0_SHIFT                       (0U)
4413 #define MCG_SC_LOCS0(x)                          (((uint8_t)(((uint8_t)(x)) << MCG_SC_LOCS0_SHIFT)) & MCG_SC_LOCS0_MASK)
4414 #define MCG_SC_FCRDIV_MASK                       (0xEU)
4415 #define MCG_SC_FCRDIV_SHIFT                      (1U)
4416 #define MCG_SC_FCRDIV(x)                         (((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK)
4417 #define MCG_SC_FLTPRSRV_MASK                     (0x10U)
4418 #define MCG_SC_FLTPRSRV_SHIFT                    (4U)
4419 #define MCG_SC_FLTPRSRV(x)                       (((uint8_t)(((uint8_t)(x)) << MCG_SC_FLTPRSRV_SHIFT)) & MCG_SC_FLTPRSRV_MASK)
4420 #define MCG_SC_ATMF_MASK                         (0x20U)
4421 #define MCG_SC_ATMF_SHIFT                        (5U)
4422 #define MCG_SC_ATMF(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMF_SHIFT)) & MCG_SC_ATMF_MASK)
4423 #define MCG_SC_ATMS_MASK                         (0x40U)
4424 #define MCG_SC_ATMS_SHIFT                        (6U)
4425 #define MCG_SC_ATMS(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMS_SHIFT)) & MCG_SC_ATMS_MASK)
4426 #define MCG_SC_ATME_MASK                         (0x80U)
4427 #define MCG_SC_ATME_SHIFT                        (7U)
4428 #define MCG_SC_ATME(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATME_SHIFT)) & MCG_SC_ATME_MASK)
4429 
4430 /*! @name ATCVH - MCG Auto Trim Compare Value High Register */
4431 #define MCG_ATCVH_ATCVH_MASK                     (0xFFU)
4432 #define MCG_ATCVH_ATCVH_SHIFT                    (0U)
4433 #define MCG_ATCVH_ATCVH(x)                       (((uint8_t)(((uint8_t)(x)) << MCG_ATCVH_ATCVH_SHIFT)) & MCG_ATCVH_ATCVH_MASK)
4434 
4435 /*! @name ATCVL - MCG Auto Trim Compare Value Low Register */
4436 #define MCG_ATCVL_ATCVL_MASK                     (0xFFU)
4437 #define MCG_ATCVL_ATCVL_SHIFT                    (0U)
4438 #define MCG_ATCVL_ATCVL(x)                       (((uint8_t)(((uint8_t)(x)) << MCG_ATCVL_ATCVL_SHIFT)) & MCG_ATCVL_ATCVL_MASK)
4439 
4440 /*! @name C7 - MCG Control 7 Register */
4441 #define MCG_C7_OSCSEL_MASK                       (0x1U)
4442 #define MCG_C7_OSCSEL_SHIFT                      (0U)
4443 #define MCG_C7_OSCSEL(x)                         (((uint8_t)(((uint8_t)(x)) << MCG_C7_OSCSEL_SHIFT)) & MCG_C7_OSCSEL_MASK)
4444 
4445 /*! @name C8 - MCG Control 8 Register */
4446 #define MCG_C8_LOCS1_MASK                        (0x1U)
4447 #define MCG_C8_LOCS1_SHIFT                       (0U)
4448 #define MCG_C8_LOCS1(x)                          (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCS1_SHIFT)) & MCG_C8_LOCS1_MASK)
4449 #define MCG_C8_CME1_MASK                         (0x20U)
4450 #define MCG_C8_CME1_SHIFT                        (5U)
4451 #define MCG_C8_CME1(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_C8_CME1_SHIFT)) & MCG_C8_CME1_MASK)
4452 #define MCG_C8_LOCRE1_MASK                       (0x80U)
4453 #define MCG_C8_LOCRE1_SHIFT                      (7U)
4454 #define MCG_C8_LOCRE1(x)                         (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCRE1_SHIFT)) & MCG_C8_LOCRE1_MASK)
4455 
4456 
4457 /*!
4458  * @}
4459  */ /* end of group MCG_Register_Masks */
4460 
4461 
4462 /* MCG - Peripheral instance base addresses */
4463 /** Peripheral MCG base address */
4464 #define MCG_BASE                                 (0x40064000u)
4465 /** Peripheral MCG base pointer */
4466 #define MCG                                      ((MCG_Type *)MCG_BASE)
4467 /** Array initializer of MCG peripheral base addresses */
4468 #define MCG_BASE_ADDRS                           { MCG_BASE }
4469 /** Array initializer of MCG peripheral base pointers */
4470 #define MCG_BASE_PTRS                            { MCG }
4471 /** Interrupt vectors for the MCG peripheral type */
4472 #define MCG_IRQS                                 { MCG_IRQn }
4473 
4474 /*!
4475  * @}
4476  */ /* end of group MCG_Peripheral_Access_Layer */
4477 
4478 
4479 /* ----------------------------------------------------------------------------
4480    -- MCM Peripheral Access Layer
4481    ---------------------------------------------------------------------------- */
4482 
4483 /*!
4484  * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
4485  * @{
4486  */
4487 
4488 /** MCM - Register Layout Typedef */
4489 typedef struct {
4490        uint8_t RESERVED_0[8];
4491   __I  uint16_t PLASC;                             /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
4492   __I  uint16_t PLAMC;                             /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
4493   __IO uint32_t PLACR;                             /**< Platform Control Register, offset: 0xC */
4494        uint8_t RESERVED_1[48];
4495   __IO uint32_t CPO;                               /**< Compute Operation Control Register, offset: 0x40 */
4496 } MCM_Type;
4497 
4498 /* ----------------------------------------------------------------------------
4499    -- MCM Register Masks
4500    ---------------------------------------------------------------------------- */
4501 
4502 /*!
4503  * @addtogroup MCM_Register_Masks MCM Register Masks
4504  * @{
4505  */
4506 
4507 /*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */
4508 #define MCM_PLASC_ASC_MASK                       (0xFFU)
4509 #define MCM_PLASC_ASC_SHIFT                      (0U)
4510 #define MCM_PLASC_ASC(x)                         (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK)
4511 
4512 /*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */
4513 #define MCM_PLAMC_AMC_MASK                       (0xFFU)
4514 #define MCM_PLAMC_AMC_SHIFT                      (0U)
4515 #define MCM_PLAMC_AMC(x)                         (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK)
4516 
4517 /*! @name PLACR - Platform Control Register */
4518 #define MCM_PLACR_ARB_MASK                       (0x200U)
4519 #define MCM_PLACR_ARB_SHIFT                      (9U)
4520 #define MCM_PLACR_ARB(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_ARB_SHIFT)) & MCM_PLACR_ARB_MASK)
4521 #define MCM_PLACR_CFCC_MASK                      (0x400U)
4522 #define MCM_PLACR_CFCC_SHIFT                     (10U)
4523 #define MCM_PLACR_CFCC(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_CFCC_SHIFT)) & MCM_PLACR_CFCC_MASK)
4524 #define MCM_PLACR_DFCDA_MASK                     (0x800U)
4525 #define MCM_PLACR_DFCDA_SHIFT                    (11U)
4526 #define MCM_PLACR_DFCDA(x)                       (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCDA_SHIFT)) & MCM_PLACR_DFCDA_MASK)
4527 #define MCM_PLACR_DFCIC_MASK                     (0x1000U)
4528 #define MCM_PLACR_DFCIC_SHIFT                    (12U)
4529 #define MCM_PLACR_DFCIC(x)                       (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCIC_SHIFT)) & MCM_PLACR_DFCIC_MASK)
4530 #define MCM_PLACR_DFCC_MASK                      (0x2000U)
4531 #define MCM_PLACR_DFCC_SHIFT                     (13U)
4532 #define MCM_PLACR_DFCC(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCC_SHIFT)) & MCM_PLACR_DFCC_MASK)
4533 #define MCM_PLACR_EFDS_MASK                      (0x4000U)
4534 #define MCM_PLACR_EFDS_SHIFT                     (14U)
4535 #define MCM_PLACR_EFDS(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_EFDS_SHIFT)) & MCM_PLACR_EFDS_MASK)
4536 #define MCM_PLACR_DFCS_MASK                      (0x8000U)
4537 #define MCM_PLACR_DFCS_SHIFT                     (15U)
4538 #define MCM_PLACR_DFCS(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCS_SHIFT)) & MCM_PLACR_DFCS_MASK)
4539 #define MCM_PLACR_ESFC_MASK                      (0x10000U)
4540 #define MCM_PLACR_ESFC_SHIFT                     (16U)
4541 #define MCM_PLACR_ESFC(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_ESFC_SHIFT)) & MCM_PLACR_ESFC_MASK)
4542 
4543 /*! @name CPO - Compute Operation Control Register */
4544 #define MCM_CPO_CPOREQ_MASK                      (0x1U)
4545 #define MCM_CPO_CPOREQ_SHIFT                     (0U)
4546 #define MCM_CPO_CPOREQ(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOREQ_SHIFT)) & MCM_CPO_CPOREQ_MASK)
4547 #define MCM_CPO_CPOACK_MASK                      (0x2U)
4548 #define MCM_CPO_CPOACK_SHIFT                     (1U)
4549 #define MCM_CPO_CPOACK(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOACK_SHIFT)) & MCM_CPO_CPOACK_MASK)
4550 #define MCM_CPO_CPOWOI_MASK                      (0x4U)
4551 #define MCM_CPO_CPOWOI_SHIFT                     (2U)
4552 #define MCM_CPO_CPOWOI(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOWOI_SHIFT)) & MCM_CPO_CPOWOI_MASK)
4553 
4554 
4555 /*!
4556  * @}
4557  */ /* end of group MCM_Register_Masks */
4558 
4559 
4560 /* MCM - Peripheral instance base addresses */
4561 /** Peripheral MCM base address */
4562 #define MCM_BASE                                 (0xF0003000u)
4563 /** Peripheral MCM base pointer */
4564 #define MCM                                      ((MCM_Type *)MCM_BASE)
4565 /** Array initializer of MCM peripheral base addresses */
4566 #define MCM_BASE_ADDRS                           { MCM_BASE }
4567 /** Array initializer of MCM peripheral base pointers */
4568 #define MCM_BASE_PTRS                            { MCM }
4569 
4570 /*!
4571  * @}
4572  */ /* end of group MCM_Peripheral_Access_Layer */
4573 
4574 
4575 /* ----------------------------------------------------------------------------
4576    -- MTB Peripheral Access Layer
4577    ---------------------------------------------------------------------------- */
4578 
4579 /*!
4580  * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer
4581  * @{
4582  */
4583 
4584 /** MTB - Register Layout Typedef */
4585 typedef struct {
4586   __IO uint32_t POSITION;                          /**< MTB Position Register, offset: 0x0 */
4587   __IO uint32_t MASTER;                            /**< MTB Master Register, offset: 0x4 */
4588   __IO uint32_t FLOW;                              /**< MTB Flow Register, offset: 0x8 */
4589   __I  uint32_t _BASE;                              /**< MTB Base Register, offset: 0xC */
4590        uint8_t RESERVED_0[3824];
4591   __I  uint32_t MODECTRL;                          /**< Integration Mode Control Register, offset: 0xF00 */
4592        uint8_t RESERVED_1[156];
4593   __I  uint32_t TAGSET;                            /**< Claim TAG Set Register, offset: 0xFA0 */
4594   __I  uint32_t TAGCLEAR;                          /**< Claim TAG Clear Register, offset: 0xFA4 */
4595        uint8_t RESERVED_2[8];
4596   __I  uint32_t LOCKACCESS;                        /**< Lock Access Register, offset: 0xFB0 */
4597   __I  uint32_t LOCKSTAT;                          /**< Lock Status Register, offset: 0xFB4 */
4598   __I  uint32_t AUTHSTAT;                          /**< Authentication Status Register, offset: 0xFB8 */
4599   __I  uint32_t DEVICEARCH;                        /**< Device Architecture Register, offset: 0xFBC */
4600        uint8_t RESERVED_3[8];
4601   __I  uint32_t DEVICECFG;                         /**< Device Configuration Register, offset: 0xFC8 */
4602   __I  uint32_t DEVICETYPID;                       /**< Device Type Identifier Register, offset: 0xFCC */
4603   __I  uint32_t PERIPHID4;                         /**< Peripheral ID Register, offset: 0xFD0 */
4604   __I  uint32_t PERIPHID5;                         /**< Peripheral ID Register, offset: 0xFD4 */
4605   __I  uint32_t PERIPHID6;                         /**< Peripheral ID Register, offset: 0xFD8 */
4606   __I  uint32_t PERIPHID7;                         /**< Peripheral ID Register, offset: 0xFDC */
4607   __I  uint32_t PERIPHID0;                         /**< Peripheral ID Register, offset: 0xFE0 */
4608   __I  uint32_t PERIPHID1;                         /**< Peripheral ID Register, offset: 0xFE4 */
4609   __I  uint32_t PERIPHID2;                         /**< Peripheral ID Register, offset: 0xFE8 */
4610   __I  uint32_t PERIPHID3;                         /**< Peripheral ID Register, offset: 0xFEC */
4611   __I  uint32_t COMPID[4];                         /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
4612 } MTB_Type;
4613 
4614 /* ----------------------------------------------------------------------------
4615    -- MTB Register Masks
4616    ---------------------------------------------------------------------------- */
4617 
4618 /*!
4619  * @addtogroup MTB_Register_Masks MTB Register Masks
4620  * @{
4621  */
4622 
4623 /*! @name POSITION - MTB Position Register */
4624 #define MTB_POSITION_WRAP_MASK                   (0x4U)
4625 #define MTB_POSITION_WRAP_SHIFT                  (2U)
4626 #define MTB_POSITION_WRAP(x)                     (((uint32_t)(((uint32_t)(x)) << MTB_POSITION_WRAP_SHIFT)) & MTB_POSITION_WRAP_MASK)
4627 #define MTB_POSITION_POINTER_MASK                (0xFFFFFFF8U)
4628 #define MTB_POSITION_POINTER_SHIFT               (3U)
4629 #define MTB_POSITION_POINTER(x)                  (((uint32_t)(((uint32_t)(x)) << MTB_POSITION_POINTER_SHIFT)) & MTB_POSITION_POINTER_MASK)
4630 
4631 /*! @name MASTER - MTB Master Register */
4632 #define MTB_MASTER_MASK_MASK                     (0x1FU)
4633 #define MTB_MASTER_MASK_SHIFT                    (0U)
4634 #define MTB_MASTER_MASK(x)                       (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_MASK_SHIFT)) & MTB_MASTER_MASK_MASK)
4635 #define MTB_MASTER_TSTARTEN_MASK                 (0x20U)
4636 #define MTB_MASTER_TSTARTEN_SHIFT                (5U)
4637 #define MTB_MASTER_TSTARTEN(x)                   (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTARTEN_SHIFT)) & MTB_MASTER_TSTARTEN_MASK)
4638 #define MTB_MASTER_TSTOPEN_MASK                  (0x40U)
4639 #define MTB_MASTER_TSTOPEN_SHIFT                 (6U)
4640 #define MTB_MASTER_TSTOPEN(x)                    (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTOPEN_SHIFT)) & MTB_MASTER_TSTOPEN_MASK)
4641 #define MTB_MASTER_SFRWPRIV_MASK                 (0x80U)
4642 #define MTB_MASTER_SFRWPRIV_SHIFT                (7U)
4643 #define MTB_MASTER_SFRWPRIV(x)                   (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_SFRWPRIV_SHIFT)) & MTB_MASTER_SFRWPRIV_MASK)
4644 #define MTB_MASTER_RAMPRIV_MASK                  (0x100U)
4645 #define MTB_MASTER_RAMPRIV_SHIFT                 (8U)
4646 #define MTB_MASTER_RAMPRIV(x)                    (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_RAMPRIV_SHIFT)) & MTB_MASTER_RAMPRIV_MASK)
4647 #define MTB_MASTER_HALTREQ_MASK                  (0x200U)
4648 #define MTB_MASTER_HALTREQ_SHIFT                 (9U)
4649 #define MTB_MASTER_HALTREQ(x)                    (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_HALTREQ_SHIFT)) & MTB_MASTER_HALTREQ_MASK)
4650 #define MTB_MASTER_EN_MASK                       (0x80000000U)
4651 #define MTB_MASTER_EN_SHIFT                      (31U)
4652 #define MTB_MASTER_EN(x)                         (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_EN_SHIFT)) & MTB_MASTER_EN_MASK)
4653 
4654 /*! @name FLOW - MTB Flow Register */
4655 #define MTB_FLOW_AUTOSTOP_MASK                   (0x1U)
4656 #define MTB_FLOW_AUTOSTOP_SHIFT                  (0U)
4657 #define MTB_FLOW_AUTOSTOP(x)                     (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOSTOP_SHIFT)) & MTB_FLOW_AUTOSTOP_MASK)
4658 #define MTB_FLOW_AUTOHALT_MASK                   (0x2U)
4659 #define MTB_FLOW_AUTOHALT_SHIFT                  (1U)
4660 #define MTB_FLOW_AUTOHALT(x)                     (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOHALT_SHIFT)) & MTB_FLOW_AUTOHALT_MASK)
4661 #define MTB_FLOW_WATERMARK_MASK                  (0xFFFFFFF8U)
4662 #define MTB_FLOW_WATERMARK_SHIFT                 (3U)
4663 #define MTB_FLOW_WATERMARK(x)                    (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_WATERMARK_SHIFT)) & MTB_FLOW_WATERMARK_MASK)
4664 
4665 /*! @name BASE - MTB Base Register */
4666 #define MTB_BASE_BASEADDR_MASK                   (0xFFFFFFFFU)
4667 #define MTB_BASE_BASEADDR_SHIFT                  (0U)
4668 #define MTB_BASE_BASEADDR(x)                     (((uint32_t)(((uint32_t)(x)) << MTB_BASE_BASEADDR_SHIFT)) & MTB_BASE_BASEADDR_MASK)
4669 
4670 /*! @name MODECTRL - Integration Mode Control Register */
4671 #define MTB_MODECTRL_MODECTRL_MASK               (0xFFFFFFFFU)
4672 #define MTB_MODECTRL_MODECTRL_SHIFT              (0U)
4673 #define MTB_MODECTRL_MODECTRL(x)                 (((uint32_t)(((uint32_t)(x)) << MTB_MODECTRL_MODECTRL_SHIFT)) & MTB_MODECTRL_MODECTRL_MASK)
4674 
4675 /*! @name TAGSET - Claim TAG Set Register */
4676 #define MTB_TAGSET_TAGSET_MASK                   (0xFFFFFFFFU)
4677 #define MTB_TAGSET_TAGSET_SHIFT                  (0U)
4678 #define MTB_TAGSET_TAGSET(x)                     (((uint32_t)(((uint32_t)(x)) << MTB_TAGSET_TAGSET_SHIFT)) & MTB_TAGSET_TAGSET_MASK)
4679 
4680 /*! @name TAGCLEAR - Claim TAG Clear Register */
4681 #define MTB_TAGCLEAR_TAGCLEAR_MASK               (0xFFFFFFFFU)
4682 #define MTB_TAGCLEAR_TAGCLEAR_SHIFT              (0U)
4683 #define MTB_TAGCLEAR_TAGCLEAR(x)                 (((uint32_t)(((uint32_t)(x)) << MTB_TAGCLEAR_TAGCLEAR_SHIFT)) & MTB_TAGCLEAR_TAGCLEAR_MASK)
4684 
4685 /*! @name LOCKACCESS - Lock Access Register */
4686 #define MTB_LOCKACCESS_LOCKACCESS_MASK           (0xFFFFFFFFU)
4687 #define MTB_LOCKACCESS_LOCKACCESS_SHIFT          (0U)
4688 #define MTB_LOCKACCESS_LOCKACCESS(x)             (((uint32_t)(((uint32_t)(x)) << MTB_LOCKACCESS_LOCKACCESS_SHIFT)) & MTB_LOCKACCESS_LOCKACCESS_MASK)
4689 
4690 /*! @name LOCKSTAT - Lock Status Register */
4691 #define MTB_LOCKSTAT_LOCKSTAT_MASK               (0xFFFFFFFFU)
4692 #define MTB_LOCKSTAT_LOCKSTAT_SHIFT              (0U)
4693 #define MTB_LOCKSTAT_LOCKSTAT(x)                 (((uint32_t)(((uint32_t)(x)) << MTB_LOCKSTAT_LOCKSTAT_SHIFT)) & MTB_LOCKSTAT_LOCKSTAT_MASK)
4694 
4695 /*! @name AUTHSTAT - Authentication Status Register */
4696 #define MTB_AUTHSTAT_BIT0_MASK                   (0x1U)
4697 #define MTB_AUTHSTAT_BIT0_SHIFT                  (0U)
4698 #define MTB_AUTHSTAT_BIT0(x)                     (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT0_SHIFT)) & MTB_AUTHSTAT_BIT0_MASK)
4699 #define MTB_AUTHSTAT_BIT1_MASK                   (0x2U)
4700 #define MTB_AUTHSTAT_BIT1_SHIFT                  (1U)
4701 #define MTB_AUTHSTAT_BIT1(x)                     (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT1_SHIFT)) & MTB_AUTHSTAT_BIT1_MASK)
4702 #define MTB_AUTHSTAT_BIT2_MASK                   (0x4U)
4703 #define MTB_AUTHSTAT_BIT2_SHIFT                  (2U)
4704 #define MTB_AUTHSTAT_BIT2(x)                     (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT2_SHIFT)) & MTB_AUTHSTAT_BIT2_MASK)
4705 #define MTB_AUTHSTAT_BIT3_MASK                   (0x8U)
4706 #define MTB_AUTHSTAT_BIT3_SHIFT                  (3U)
4707 #define MTB_AUTHSTAT_BIT3(x)                     (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT3_SHIFT)) & MTB_AUTHSTAT_BIT3_MASK)
4708 
4709 /*! @name DEVICEARCH - Device Architecture Register */
4710 #define MTB_DEVICEARCH_DEVICEARCH_MASK           (0xFFFFFFFFU)
4711 #define MTB_DEVICEARCH_DEVICEARCH_SHIFT          (0U)
4712 #define MTB_DEVICEARCH_DEVICEARCH(x)             (((uint32_t)(((uint32_t)(x)) << MTB_DEVICEARCH_DEVICEARCH_SHIFT)) & MTB_DEVICEARCH_DEVICEARCH_MASK)
4713 
4714 /*! @name DEVICECFG - Device Configuration Register */
4715 #define MTB_DEVICECFG_DEVICECFG_MASK             (0xFFFFFFFFU)
4716 #define MTB_DEVICECFG_DEVICECFG_SHIFT            (0U)
4717 #define MTB_DEVICECFG_DEVICECFG(x)               (((uint32_t)(((uint32_t)(x)) << MTB_DEVICECFG_DEVICECFG_SHIFT)) & MTB_DEVICECFG_DEVICECFG_MASK)
4718 
4719 /*! @name DEVICETYPID - Device Type Identifier Register */
4720 #define MTB_DEVICETYPID_DEVICETYPID_MASK         (0xFFFFFFFFU)
4721 #define MTB_DEVICETYPID_DEVICETYPID_SHIFT        (0U)
4722 #define MTB_DEVICETYPID_DEVICETYPID(x)           (((uint32_t)(((uint32_t)(x)) << MTB_DEVICETYPID_DEVICETYPID_SHIFT)) & MTB_DEVICETYPID_DEVICETYPID_MASK)
4723 
4724 /*! @name PERIPHID4 - Peripheral ID Register */
4725 #define MTB_PERIPHID4_PERIPHID_MASK              (0xFFFFFFFFU)
4726 #define MTB_PERIPHID4_PERIPHID_SHIFT             (0U)
4727 #define MTB_PERIPHID4_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID4_PERIPHID_SHIFT)) & MTB_PERIPHID4_PERIPHID_MASK)
4728 
4729 /*! @name PERIPHID5 - Peripheral ID Register */
4730 #define MTB_PERIPHID5_PERIPHID_MASK              (0xFFFFFFFFU)
4731 #define MTB_PERIPHID5_PERIPHID_SHIFT             (0U)
4732 #define MTB_PERIPHID5_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID5_PERIPHID_SHIFT)) & MTB_PERIPHID5_PERIPHID_MASK)
4733 
4734 /*! @name PERIPHID6 - Peripheral ID Register */
4735 #define MTB_PERIPHID6_PERIPHID_MASK              (0xFFFFFFFFU)
4736 #define MTB_PERIPHID6_PERIPHID_SHIFT             (0U)
4737 #define MTB_PERIPHID6_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID6_PERIPHID_SHIFT)) & MTB_PERIPHID6_PERIPHID_MASK)
4738 
4739 /*! @name PERIPHID7 - Peripheral ID Register */
4740 #define MTB_PERIPHID7_PERIPHID_MASK              (0xFFFFFFFFU)
4741 #define MTB_PERIPHID7_PERIPHID_SHIFT             (0U)
4742 #define MTB_PERIPHID7_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID7_PERIPHID_SHIFT)) & MTB_PERIPHID7_PERIPHID_MASK)
4743 
4744 /*! @name PERIPHID0 - Peripheral ID Register */
4745 #define MTB_PERIPHID0_PERIPHID_MASK              (0xFFFFFFFFU)
4746 #define MTB_PERIPHID0_PERIPHID_SHIFT             (0U)
4747 #define MTB_PERIPHID0_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID0_PERIPHID_SHIFT)) & MTB_PERIPHID0_PERIPHID_MASK)
4748 
4749 /*! @name PERIPHID1 - Peripheral ID Register */
4750 #define MTB_PERIPHID1_PERIPHID_MASK              (0xFFFFFFFFU)
4751 #define MTB_PERIPHID1_PERIPHID_SHIFT             (0U)
4752 #define MTB_PERIPHID1_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID1_PERIPHID_SHIFT)) & MTB_PERIPHID1_PERIPHID_MASK)
4753 
4754 /*! @name PERIPHID2 - Peripheral ID Register */
4755 #define MTB_PERIPHID2_PERIPHID_MASK              (0xFFFFFFFFU)
4756 #define MTB_PERIPHID2_PERIPHID_SHIFT             (0U)
4757 #define MTB_PERIPHID2_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID2_PERIPHID_SHIFT)) & MTB_PERIPHID2_PERIPHID_MASK)
4758 
4759 /*! @name PERIPHID3 - Peripheral ID Register */
4760 #define MTB_PERIPHID3_PERIPHID_MASK              (0xFFFFFFFFU)
4761 #define MTB_PERIPHID3_PERIPHID_SHIFT             (0U)
4762 #define MTB_PERIPHID3_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID3_PERIPHID_SHIFT)) & MTB_PERIPHID3_PERIPHID_MASK)
4763 
4764 /*! @name COMPID - Component ID Register */
4765 #define MTB_COMPID_COMPID_MASK                   (0xFFFFFFFFU)
4766 #define MTB_COMPID_COMPID_SHIFT                  (0U)
4767 #define MTB_COMPID_COMPID(x)                     (((uint32_t)(((uint32_t)(x)) << MTB_COMPID_COMPID_SHIFT)) & MTB_COMPID_COMPID_MASK)
4768 
4769 /* The count of MTB_COMPID */
4770 #define MTB_COMPID_COUNT                         (4U)
4771 
4772 
4773 /*!
4774  * @}
4775  */ /* end of group MTB_Register_Masks */
4776 
4777 
4778 /* MTB - Peripheral instance base addresses */
4779 /** Peripheral MTB base address */
4780 #define MTB_BASE                                 (0xF0000000u)
4781 /** Peripheral MTB base pointer */
4782 #define MTB                                      ((MTB_Type *)MTB_BASE)
4783 /** Array initializer of MTB peripheral base addresses */
4784 #define MTB_BASE_ADDRS                           { MTB_BASE }
4785 /** Array initializer of MTB peripheral base pointers */
4786 #define MTB_BASE_PTRS                            { MTB }
4787 
4788 /*!
4789  * @}
4790  */ /* end of group MTB_Peripheral_Access_Layer */
4791 
4792 
4793 /* ----------------------------------------------------------------------------
4794    -- MTBDWT Peripheral Access Layer
4795    ---------------------------------------------------------------------------- */
4796 
4797 /*!
4798  * @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer
4799  * @{
4800  */
4801 
4802 /** MTBDWT - Register Layout Typedef */
4803 typedef struct {
4804   __I  uint32_t CTRL;                              /**< MTB DWT Control Register, offset: 0x0 */
4805        uint8_t RESERVED_0[28];
4806   struct {                                         /* offset: 0x20, array step: 0x10 */
4807     __IO uint32_t COMP;                              /**< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 */
4808     __IO uint32_t MASK;                              /**< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */
4809     __IO uint32_t FCT;                               /**< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 */
4810          uint8_t RESERVED_0[4];
4811   } COMPARATOR[2];
4812        uint8_t RESERVED_1[448];
4813   __IO uint32_t TBCTRL;                            /**< MTB_DWT Trace Buffer Control Register, offset: 0x200 */
4814        uint8_t RESERVED_2[3524];
4815   __I  uint32_t DEVICECFG;                         /**< Device Configuration Register, offset: 0xFC8 */
4816   __I  uint32_t DEVICETYPID;                       /**< Device Type Identifier Register, offset: 0xFCC */
4817   __I  uint32_t PERIPHID4;                         /**< Peripheral ID Register, offset: 0xFD0 */
4818   __I  uint32_t PERIPHID5;                         /**< Peripheral ID Register, offset: 0xFD4 */
4819   __I  uint32_t PERIPHID6;                         /**< Peripheral ID Register, offset: 0xFD8 */
4820   __I  uint32_t PERIPHID7;                         /**< Peripheral ID Register, offset: 0xFDC */
4821   __I  uint32_t PERIPHID0;                         /**< Peripheral ID Register, offset: 0xFE0 */
4822   __I  uint32_t PERIPHID1;                         /**< Peripheral ID Register, offset: 0xFE4 */
4823   __I  uint32_t PERIPHID2;                         /**< Peripheral ID Register, offset: 0xFE8 */
4824   __I  uint32_t PERIPHID3;                         /**< Peripheral ID Register, offset: 0xFEC */
4825   __I  uint32_t COMPID[4];                         /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
4826 } MTBDWT_Type;
4827 
4828 /* ----------------------------------------------------------------------------
4829    -- MTBDWT Register Masks
4830    ---------------------------------------------------------------------------- */
4831 
4832 /*!
4833  * @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks
4834  * @{
4835  */
4836 
4837 /*! @name CTRL - MTB DWT Control Register */
4838 #define MTBDWT_CTRL_DWTCFGCTRL_MASK              (0xFFFFFFFU)
4839 #define MTBDWT_CTRL_DWTCFGCTRL_SHIFT             (0U)
4840 #define MTBDWT_CTRL_DWTCFGCTRL(x)                (((uint32_t)(((uint32_t)(x)) << MTBDWT_CTRL_DWTCFGCTRL_SHIFT)) & MTBDWT_CTRL_DWTCFGCTRL_MASK)
4841 #define MTBDWT_CTRL_NUMCMP_MASK                  (0xF0000000U)
4842 #define MTBDWT_CTRL_NUMCMP_SHIFT                 (28U)
4843 #define MTBDWT_CTRL_NUMCMP(x)                    (((uint32_t)(((uint32_t)(x)) << MTBDWT_CTRL_NUMCMP_SHIFT)) & MTBDWT_CTRL_NUMCMP_MASK)
4844 
4845 /*! @name COMP - MTB_DWT Comparator Register */
4846 #define MTBDWT_COMP_COMP_MASK                    (0xFFFFFFFFU)
4847 #define MTBDWT_COMP_COMP_SHIFT                   (0U)
4848 #define MTBDWT_COMP_COMP(x)                      (((uint32_t)(((uint32_t)(x)) << MTBDWT_COMP_COMP_SHIFT)) & MTBDWT_COMP_COMP_MASK)
4849 
4850 /* The count of MTBDWT_COMP */
4851 #define MTBDWT_COMP_COUNT                        (2U)
4852 
4853 /*! @name MASK - MTB_DWT Comparator Mask Register */
4854 #define MTBDWT_MASK_MASK_MASK                    (0x1FU)
4855 #define MTBDWT_MASK_MASK_SHIFT                   (0U)
4856 #define MTBDWT_MASK_MASK(x)                      (((uint32_t)(((uint32_t)(x)) << MTBDWT_MASK_MASK_SHIFT)) & MTBDWT_MASK_MASK_MASK)
4857 
4858 /* The count of MTBDWT_MASK */
4859 #define MTBDWT_MASK_COUNT                        (2U)
4860 
4861 /*! @name FCT - MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1 */
4862 #define MTBDWT_FCT_FUNCTION_MASK                 (0xFU)
4863 #define MTBDWT_FCT_FUNCTION_SHIFT                (0U)
4864 #define MTBDWT_FCT_FUNCTION(x)                   (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_FUNCTION_SHIFT)) & MTBDWT_FCT_FUNCTION_MASK)
4865 #define MTBDWT_FCT_DATAVMATCH_MASK               (0x100U)
4866 #define MTBDWT_FCT_DATAVMATCH_SHIFT              (8U)
4867 #define MTBDWT_FCT_DATAVMATCH(x)                 (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVMATCH_SHIFT)) & MTBDWT_FCT_DATAVMATCH_MASK)
4868 #define MTBDWT_FCT_DATAVSIZE_MASK                (0xC00U)
4869 #define MTBDWT_FCT_DATAVSIZE_SHIFT               (10U)
4870 #define MTBDWT_FCT_DATAVSIZE(x)                  (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVSIZE_SHIFT)) & MTBDWT_FCT_DATAVSIZE_MASK)
4871 #define MTBDWT_FCT_DATAVADDR0_MASK               (0xF000U)
4872 #define MTBDWT_FCT_DATAVADDR0_SHIFT              (12U)
4873 #define MTBDWT_FCT_DATAVADDR0(x)                 (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVADDR0_SHIFT)) & MTBDWT_FCT_DATAVADDR0_MASK)
4874 #define MTBDWT_FCT_MATCHED_MASK                  (0x1000000U)
4875 #define MTBDWT_FCT_MATCHED_SHIFT                 (24U)
4876 #define MTBDWT_FCT_MATCHED(x)                    (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_MATCHED_SHIFT)) & MTBDWT_FCT_MATCHED_MASK)
4877 
4878 /* The count of MTBDWT_FCT */
4879 #define MTBDWT_FCT_COUNT                         (2U)
4880 
4881 /*! @name TBCTRL - MTB_DWT Trace Buffer Control Register */
4882 #define MTBDWT_TBCTRL_ACOMP0_MASK                (0x1U)
4883 #define MTBDWT_TBCTRL_ACOMP0_SHIFT               (0U)
4884 #define MTBDWT_TBCTRL_ACOMP0(x)                  (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_ACOMP0_SHIFT)) & MTBDWT_TBCTRL_ACOMP0_MASK)
4885 #define MTBDWT_TBCTRL_ACOMP1_MASK                (0x2U)
4886 #define MTBDWT_TBCTRL_ACOMP1_SHIFT               (1U)
4887 #define MTBDWT_TBCTRL_ACOMP1(x)                  (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_ACOMP1_SHIFT)) & MTBDWT_TBCTRL_ACOMP1_MASK)
4888 #define MTBDWT_TBCTRL_NUMCOMP_MASK               (0xF0000000U)
4889 #define MTBDWT_TBCTRL_NUMCOMP_SHIFT              (28U)
4890 #define MTBDWT_TBCTRL_NUMCOMP(x)                 (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_NUMCOMP_SHIFT)) & MTBDWT_TBCTRL_NUMCOMP_MASK)
4891 
4892 /*! @name DEVICECFG - Device Configuration Register */
4893 #define MTBDWT_DEVICECFG_DEVICECFG_MASK          (0xFFFFFFFFU)
4894 #define MTBDWT_DEVICECFG_DEVICECFG_SHIFT         (0U)
4895 #define MTBDWT_DEVICECFG_DEVICECFG(x)            (((uint32_t)(((uint32_t)(x)) << MTBDWT_DEVICECFG_DEVICECFG_SHIFT)) & MTBDWT_DEVICECFG_DEVICECFG_MASK)
4896 
4897 /*! @name DEVICETYPID - Device Type Identifier Register */
4898 #define MTBDWT_DEVICETYPID_DEVICETYPID_MASK      (0xFFFFFFFFU)
4899 #define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT     (0U)
4900 #define MTBDWT_DEVICETYPID_DEVICETYPID(x)        (((uint32_t)(((uint32_t)(x)) << MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT)) & MTBDWT_DEVICETYPID_DEVICETYPID_MASK)
4901 
4902 /*! @name PERIPHID4 - Peripheral ID Register */
4903 #define MTBDWT_PERIPHID4_PERIPHID_MASK           (0xFFFFFFFFU)
4904 #define MTBDWT_PERIPHID4_PERIPHID_SHIFT          (0U)
4905 #define MTBDWT_PERIPHID4_PERIPHID(x)             (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID4_PERIPHID_SHIFT)) & MTBDWT_PERIPHID4_PERIPHID_MASK)
4906 
4907 /*! @name PERIPHID5 - Peripheral ID Register */
4908 #define MTBDWT_PERIPHID5_PERIPHID_MASK           (0xFFFFFFFFU)
4909 #define MTBDWT_PERIPHID5_PERIPHID_SHIFT          (0U)
4910 #define MTBDWT_PERIPHID5_PERIPHID(x)             (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID5_PERIPHID_SHIFT)) & MTBDWT_PERIPHID5_PERIPHID_MASK)
4911 
4912 /*! @name PERIPHID6 - Peripheral ID Register */
4913 #define MTBDWT_PERIPHID6_PERIPHID_MASK           (0xFFFFFFFFU)
4914 #define MTBDWT_PERIPHID6_PERIPHID_SHIFT          (0U)
4915 #define MTBDWT_PERIPHID6_PERIPHID(x)             (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID6_PERIPHID_SHIFT)) & MTBDWT_PERIPHID6_PERIPHID_MASK)
4916 
4917 /*! @name PERIPHID7 - Peripheral ID Register */
4918 #define MTBDWT_PERIPHID7_PERIPHID_MASK           (0xFFFFFFFFU)
4919 #define MTBDWT_PERIPHID7_PERIPHID_SHIFT          (0U)
4920 #define MTBDWT_PERIPHID7_PERIPHID(x)             (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID7_PERIPHID_SHIFT)) & MTBDWT_PERIPHID7_PERIPHID_MASK)
4921 
4922 /*! @name PERIPHID0 - Peripheral ID Register */
4923 #define MTBDWT_PERIPHID0_PERIPHID_MASK           (0xFFFFFFFFU)
4924 #define MTBDWT_PERIPHID0_PERIPHID_SHIFT          (0U)
4925 #define MTBDWT_PERIPHID0_PERIPHID(x)             (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID0_PERIPHID_SHIFT)) & MTBDWT_PERIPHID0_PERIPHID_MASK)
4926 
4927 /*! @name PERIPHID1 - Peripheral ID Register */
4928 #define MTBDWT_PERIPHID1_PERIPHID_MASK           (0xFFFFFFFFU)
4929 #define MTBDWT_PERIPHID1_PERIPHID_SHIFT          (0U)
4930 #define MTBDWT_PERIPHID1_PERIPHID(x)             (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID1_PERIPHID_SHIFT)) & MTBDWT_PERIPHID1_PERIPHID_MASK)
4931 
4932 /*! @name PERIPHID2 - Peripheral ID Register */
4933 #define MTBDWT_PERIPHID2_PERIPHID_MASK           (0xFFFFFFFFU)
4934 #define MTBDWT_PERIPHID2_PERIPHID_SHIFT          (0U)
4935 #define MTBDWT_PERIPHID2_PERIPHID(x)             (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID2_PERIPHID_SHIFT)) & MTBDWT_PERIPHID2_PERIPHID_MASK)
4936 
4937 /*! @name PERIPHID3 - Peripheral ID Register */
4938 #define MTBDWT_PERIPHID3_PERIPHID_MASK           (0xFFFFFFFFU)
4939 #define MTBDWT_PERIPHID3_PERIPHID_SHIFT          (0U)
4940 #define MTBDWT_PERIPHID3_PERIPHID(x)             (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID3_PERIPHID_SHIFT)) & MTBDWT_PERIPHID3_PERIPHID_MASK)
4941 
4942 /*! @name COMPID - Component ID Register */
4943 #define MTBDWT_COMPID_COMPID_MASK                (0xFFFFFFFFU)
4944 #define MTBDWT_COMPID_COMPID_SHIFT               (0U)
4945 #define MTBDWT_COMPID_COMPID(x)                  (((uint32_t)(((uint32_t)(x)) << MTBDWT_COMPID_COMPID_SHIFT)) & MTBDWT_COMPID_COMPID_MASK)
4946 
4947 /* The count of MTBDWT_COMPID */
4948 #define MTBDWT_COMPID_COUNT                      (4U)
4949 
4950 
4951 /*!
4952  * @}
4953  */ /* end of group MTBDWT_Register_Masks */
4954 
4955 
4956 /* MTBDWT - Peripheral instance base addresses */
4957 /** Peripheral MTBDWT base address */
4958 #define MTBDWT_BASE                              (0xF0001000u)
4959 /** Peripheral MTBDWT base pointer */
4960 #define MTBDWT                                   ((MTBDWT_Type *)MTBDWT_BASE)
4961 /** Array initializer of MTBDWT peripheral base addresses */
4962 #define MTBDWT_BASE_ADDRS                        { MTBDWT_BASE }
4963 /** Array initializer of MTBDWT peripheral base pointers */
4964 #define MTBDWT_BASE_PTRS                         { MTBDWT }
4965 
4966 /*!
4967  * @}
4968  */ /* end of group MTBDWT_Peripheral_Access_Layer */
4969 
4970 
4971 /* ----------------------------------------------------------------------------
4972    -- NV Peripheral Access Layer
4973    ---------------------------------------------------------------------------- */
4974 
4975 /*!
4976  * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
4977  * @{
4978  */
4979 
4980 /** NV - Register Layout Typedef */
4981 typedef struct {
4982   __I  uint8_t BACKKEY3;                           /**< Backdoor Comparison Key 3., offset: 0x0 */
4983   __I  uint8_t BACKKEY2;                           /**< Backdoor Comparison Key 2., offset: 0x1 */
4984   __I  uint8_t BACKKEY1;                           /**< Backdoor Comparison Key 1., offset: 0x2 */
4985   __I  uint8_t BACKKEY0;                           /**< Backdoor Comparison Key 0., offset: 0x3 */
4986   __I  uint8_t BACKKEY7;                           /**< Backdoor Comparison Key 7., offset: 0x4 */
4987   __I  uint8_t BACKKEY6;                           /**< Backdoor Comparison Key 6., offset: 0x5 */
4988   __I  uint8_t BACKKEY5;                           /**< Backdoor Comparison Key 5., offset: 0x6 */
4989   __I  uint8_t BACKKEY4;                           /**< Backdoor Comparison Key 4., offset: 0x7 */
4990   __I  uint8_t FPROT3;                             /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
4991   __I  uint8_t FPROT2;                             /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
4992   __I  uint8_t FPROT1;                             /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
4993   __I  uint8_t FPROT0;                             /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
4994   __I  uint8_t FSEC;                               /**< Non-volatile Flash Security Register, offset: 0xC */
4995   __I  uint8_t FOPT;                               /**< Non-volatile Flash Option Register, offset: 0xD */
4996 } NV_Type;
4997 
4998 /* ----------------------------------------------------------------------------
4999    -- NV Register Masks
5000    ---------------------------------------------------------------------------- */
5001 
5002 /*!
5003  * @addtogroup NV_Register_Masks NV Register Masks
5004  * @{
5005  */
5006 
5007 /*! @name BACKKEY3 - Backdoor Comparison Key 3. */
5008 #define NV_BACKKEY3_KEY_MASK                     (0xFFU)
5009 #define NV_BACKKEY3_KEY_SHIFT                    (0U)
5010 #define NV_BACKKEY3_KEY(x)                       (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY3_KEY_SHIFT)) & NV_BACKKEY3_KEY_MASK)
5011 
5012 /*! @name BACKKEY2 - Backdoor Comparison Key 2. */
5013 #define NV_BACKKEY2_KEY_MASK                     (0xFFU)
5014 #define NV_BACKKEY2_KEY_SHIFT                    (0U)
5015 #define NV_BACKKEY2_KEY(x)                       (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY2_KEY_SHIFT)) & NV_BACKKEY2_KEY_MASK)
5016 
5017 /*! @name BACKKEY1 - Backdoor Comparison Key 1. */
5018 #define NV_BACKKEY1_KEY_MASK                     (0xFFU)
5019 #define NV_BACKKEY1_KEY_SHIFT                    (0U)
5020 #define NV_BACKKEY1_KEY(x)                       (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY1_KEY_SHIFT)) & NV_BACKKEY1_KEY_MASK)
5021 
5022 /*! @name BACKKEY0 - Backdoor Comparison Key 0. */
5023 #define NV_BACKKEY0_KEY_MASK                     (0xFFU)
5024 #define NV_BACKKEY0_KEY_SHIFT                    (0U)
5025 #define NV_BACKKEY0_KEY(x)                       (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY0_KEY_SHIFT)) & NV_BACKKEY0_KEY_MASK)
5026 
5027 /*! @name BACKKEY7 - Backdoor Comparison Key 7. */
5028 #define NV_BACKKEY7_KEY_MASK                     (0xFFU)
5029 #define NV_BACKKEY7_KEY_SHIFT                    (0U)
5030 #define NV_BACKKEY7_KEY(x)                       (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY7_KEY_SHIFT)) & NV_BACKKEY7_KEY_MASK)
5031 
5032 /*! @name BACKKEY6 - Backdoor Comparison Key 6. */
5033 #define NV_BACKKEY6_KEY_MASK                     (0xFFU)
5034 #define NV_BACKKEY6_KEY_SHIFT                    (0U)
5035 #define NV_BACKKEY6_KEY(x)                       (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY6_KEY_SHIFT)) & NV_BACKKEY6_KEY_MASK)
5036 
5037 /*! @name BACKKEY5 - Backdoor Comparison Key 5. */
5038 #define NV_BACKKEY5_KEY_MASK                     (0xFFU)
5039 #define NV_BACKKEY5_KEY_SHIFT                    (0U)
5040 #define NV_BACKKEY5_KEY(x)                       (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY5_KEY_SHIFT)) & NV_BACKKEY5_KEY_MASK)
5041 
5042 /*! @name BACKKEY4 - Backdoor Comparison Key 4. */
5043 #define NV_BACKKEY4_KEY_MASK                     (0xFFU)
5044 #define NV_BACKKEY4_KEY_SHIFT                    (0U)
5045 #define NV_BACKKEY4_KEY(x)                       (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY4_KEY_SHIFT)) & NV_BACKKEY4_KEY_MASK)
5046 
5047 /*! @name FPROT3 - Non-volatile P-Flash Protection 1 - Low Register */
5048 #define NV_FPROT3_PROT_MASK                      (0xFFU)
5049 #define NV_FPROT3_PROT_SHIFT                     (0U)
5050 #define NV_FPROT3_PROT(x)                        (((uint8_t)(((uint8_t)(x)) << NV_FPROT3_PROT_SHIFT)) & NV_FPROT3_PROT_MASK)
5051 
5052 /*! @name FPROT2 - Non-volatile P-Flash Protection 1 - High Register */
5053 #define NV_FPROT2_PROT_MASK                      (0xFFU)
5054 #define NV_FPROT2_PROT_SHIFT                     (0U)
5055 #define NV_FPROT2_PROT(x)                        (((uint8_t)(((uint8_t)(x)) << NV_FPROT2_PROT_SHIFT)) & NV_FPROT2_PROT_MASK)
5056 
5057 /*! @name FPROT1 - Non-volatile P-Flash Protection 0 - Low Register */
5058 #define NV_FPROT1_PROT_MASK                      (0xFFU)
5059 #define NV_FPROT1_PROT_SHIFT                     (0U)
5060 #define NV_FPROT1_PROT(x)                        (((uint8_t)(((uint8_t)(x)) << NV_FPROT1_PROT_SHIFT)) & NV_FPROT1_PROT_MASK)
5061 
5062 /*! @name FPROT0 - Non-volatile P-Flash Protection 0 - High Register */
5063 #define NV_FPROT0_PROT_MASK                      (0xFFU)
5064 #define NV_FPROT0_PROT_SHIFT                     (0U)
5065 #define NV_FPROT0_PROT(x)                        (((uint8_t)(((uint8_t)(x)) << NV_FPROT0_PROT_SHIFT)) & NV_FPROT0_PROT_MASK)
5066 
5067 /*! @name FSEC - Non-volatile Flash Security Register */
5068 #define NV_FSEC_SEC_MASK                         (0x3U)
5069 #define NV_FSEC_SEC_SHIFT                        (0U)
5070 #define NV_FSEC_SEC(x)                           (((uint8_t)(((uint8_t)(x)) << NV_FSEC_SEC_SHIFT)) & NV_FSEC_SEC_MASK)
5071 #define NV_FSEC_FSLACC_MASK                      (0xCU)
5072 #define NV_FSEC_FSLACC_SHIFT                     (2U)
5073 #define NV_FSEC_FSLACC(x)                        (((uint8_t)(((uint8_t)(x)) << NV_FSEC_FSLACC_SHIFT)) & NV_FSEC_FSLACC_MASK)
5074 #define NV_FSEC_MEEN_MASK                        (0x30U)
5075 #define NV_FSEC_MEEN_SHIFT                       (4U)
5076 #define NV_FSEC_MEEN(x)                          (((uint8_t)(((uint8_t)(x)) << NV_FSEC_MEEN_SHIFT)) & NV_FSEC_MEEN_MASK)
5077 #define NV_FSEC_KEYEN_MASK                       (0xC0U)
5078 #define NV_FSEC_KEYEN_SHIFT                      (6U)
5079 #define NV_FSEC_KEYEN(x)                         (((uint8_t)(((uint8_t)(x)) << NV_FSEC_KEYEN_SHIFT)) & NV_FSEC_KEYEN_MASK)
5080 
5081 /*! @name FOPT - Non-volatile Flash Option Register */
5082 #define NV_FOPT_LPBOOT0_MASK                     (0x1U)
5083 #define NV_FOPT_LPBOOT0_SHIFT                    (0U)
5084 #define NV_FOPT_LPBOOT0(x)                       (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT0_SHIFT)) & NV_FOPT_LPBOOT0_MASK)
5085 #define NV_FOPT_NMI_DIS_MASK                     (0x4U)
5086 #define NV_FOPT_NMI_DIS_SHIFT                    (2U)
5087 #define NV_FOPT_NMI_DIS(x)                       (((uint8_t)(((uint8_t)(x)) << NV_FOPT_NMI_DIS_SHIFT)) & NV_FOPT_NMI_DIS_MASK)
5088 #define NV_FOPT_RESET_PIN_CFG_MASK               (0x8U)
5089 #define NV_FOPT_RESET_PIN_CFG_SHIFT              (3U)
5090 #define NV_FOPT_RESET_PIN_CFG(x)                 (((uint8_t)(((uint8_t)(x)) << NV_FOPT_RESET_PIN_CFG_SHIFT)) & NV_FOPT_RESET_PIN_CFG_MASK)
5091 #define NV_FOPT_LPBOOT1_MASK                     (0x10U)
5092 #define NV_FOPT_LPBOOT1_SHIFT                    (4U)
5093 #define NV_FOPT_LPBOOT1(x)                       (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT1_SHIFT)) & NV_FOPT_LPBOOT1_MASK)
5094 #define NV_FOPT_FAST_INIT_MASK                   (0x20U)
5095 #define NV_FOPT_FAST_INIT_SHIFT                  (5U)
5096 #define NV_FOPT_FAST_INIT(x)                     (((uint8_t)(((uint8_t)(x)) << NV_FOPT_FAST_INIT_SHIFT)) & NV_FOPT_FAST_INIT_MASK)
5097 
5098 
5099 /*!
5100  * @}
5101  */ /* end of group NV_Register_Masks */
5102 
5103 
5104 /* NV - Peripheral instance base addresses */
5105 /** Peripheral FTFA_FlashConfig base address */
5106 #define FTFA_FlashConfig_BASE                    (0x400u)
5107 /** Peripheral FTFA_FlashConfig base pointer */
5108 #define FTFA_FlashConfig                         ((NV_Type *)FTFA_FlashConfig_BASE)
5109 /** Array initializer of NV peripheral base addresses */
5110 #define NV_BASE_ADDRS                            { FTFA_FlashConfig_BASE }
5111 /** Array initializer of NV peripheral base pointers */
5112 #define NV_BASE_PTRS                             { FTFA_FlashConfig }
5113 
5114 /*!
5115  * @}
5116  */ /* end of group NV_Peripheral_Access_Layer */
5117 
5118 
5119 /* ----------------------------------------------------------------------------
5120    -- PIT Peripheral Access Layer
5121    ---------------------------------------------------------------------------- */
5122 
5123 /*!
5124  * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
5125  * @{
5126  */
5127 
5128 /** PIT - Register Layout Typedef */
5129 typedef struct {
5130   __IO uint32_t MCR;                               /**< PIT Module Control Register, offset: 0x0 */
5131        uint8_t RESERVED_0[220];
5132   __I  uint32_t LTMR64H;                           /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */
5133   __I  uint32_t LTMR64L;                           /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */
5134        uint8_t RESERVED_1[24];
5135   struct {                                         /* offset: 0x100, array step: 0x10 */
5136     __IO uint32_t LDVAL;                             /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
5137     __I  uint32_t CVAL;                              /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
5138     __IO uint32_t TCTRL;                             /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
5139     __IO uint32_t TFLG;                              /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
5140   } CHANNEL[2];
5141 } PIT_Type;
5142 
5143 /* ----------------------------------------------------------------------------
5144    -- PIT Register Masks
5145    ---------------------------------------------------------------------------- */
5146 
5147 /*!
5148  * @addtogroup PIT_Register_Masks PIT Register Masks
5149  * @{
5150  */
5151 
5152 /*! @name MCR - PIT Module Control Register */
5153 #define PIT_MCR_FRZ_MASK                         (0x1U)
5154 #define PIT_MCR_FRZ_SHIFT                        (0U)
5155 #define PIT_MCR_FRZ(x)                           (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)
5156 #define PIT_MCR_MDIS_MASK                        (0x2U)
5157 #define PIT_MCR_MDIS_SHIFT                       (1U)
5158 #define PIT_MCR_MDIS(x)                          (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)
5159 
5160 /*! @name LTMR64H - PIT Upper Lifetime Timer Register */
5161 #define PIT_LTMR64H_LTH_MASK                     (0xFFFFFFFFU)
5162 #define PIT_LTMR64H_LTH_SHIFT                    (0U)
5163 #define PIT_LTMR64H_LTH(x)                       (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK)
5164 
5165 /*! @name LTMR64L - PIT Lower Lifetime Timer Register */
5166 #define PIT_LTMR64L_LTL_MASK                     (0xFFFFFFFFU)
5167 #define PIT_LTMR64L_LTL_SHIFT                    (0U)
5168 #define PIT_LTMR64L_LTL(x)                       (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK)
5169 
5170 /*! @name LDVAL - Timer Load Value Register */
5171 #define PIT_LDVAL_TSV_MASK                       (0xFFFFFFFFU)
5172 #define PIT_LDVAL_TSV_SHIFT                      (0U)
5173 #define PIT_LDVAL_TSV(x)                         (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)
5174 
5175 /* The count of PIT_LDVAL */
5176 #define PIT_LDVAL_COUNT                          (2U)
5177 
5178 /*! @name CVAL - Current Timer Value Register */
5179 #define PIT_CVAL_TVL_MASK                        (0xFFFFFFFFU)
5180 #define PIT_CVAL_TVL_SHIFT                       (0U)
5181 #define PIT_CVAL_TVL(x)                          (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
5182 
5183 /* The count of PIT_CVAL */
5184 #define PIT_CVAL_COUNT                           (2U)
5185 
5186 /*! @name TCTRL - Timer Control Register */
5187 #define PIT_TCTRL_TEN_MASK                       (0x1U)
5188 #define PIT_TCTRL_TEN_SHIFT                      (0U)
5189 #define PIT_TCTRL_TEN(x)                         (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
5190 #define PIT_TCTRL_TIE_MASK                       (0x2U)
5191 #define PIT_TCTRL_TIE_SHIFT                      (1U)
5192 #define PIT_TCTRL_TIE(x)                         (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)
5193 #define PIT_TCTRL_CHN_MASK                       (0x4U)
5194 #define PIT_TCTRL_CHN_SHIFT                      (2U)
5195 #define PIT_TCTRL_CHN(x)                         (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
5196 
5197 /* The count of PIT_TCTRL */
5198 #define PIT_TCTRL_COUNT                          (2U)
5199 
5200 /*! @name TFLG - Timer Flag Register */
5201 #define PIT_TFLG_TIF_MASK                        (0x1U)
5202 #define PIT_TFLG_TIF_SHIFT                       (0U)
5203 #define PIT_TFLG_TIF(x)                          (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)
5204 
5205 /* The count of PIT_TFLG */
5206 #define PIT_TFLG_COUNT                           (2U)
5207 
5208 
5209 /*!
5210  * @}
5211  */ /* end of group PIT_Register_Masks */
5212 
5213 
5214 /* PIT - Peripheral instance base addresses */
5215 /** Peripheral PIT base address */
5216 #define PIT_BASE                                 (0x40037000u)
5217 /** Peripheral PIT base pointer */
5218 #define PIT                                      ((PIT_Type *)PIT_BASE)
5219 /** Array initializer of PIT peripheral base addresses */
5220 #define PIT_BASE_ADDRS                           { PIT_BASE }
5221 /** Array initializer of PIT peripheral base pointers */
5222 #define PIT_BASE_PTRS                            { PIT }
5223 /** Interrupt vectors for the PIT peripheral type */
5224 #define PIT_IRQS                                 { { PIT_IRQn, PIT_IRQn } }
5225 
5226 /*!
5227  * @}
5228  */ /* end of group PIT_Peripheral_Access_Layer */
5229 
5230 
5231 /* ----------------------------------------------------------------------------
5232    -- PMC Peripheral Access Layer
5233    ---------------------------------------------------------------------------- */
5234 
5235 /*!
5236  * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
5237  * @{
5238  */
5239 
5240 /** PMC - Register Layout Typedef */
5241 typedef struct {
5242   __IO uint8_t LVDSC1;                             /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
5243   __IO uint8_t LVDSC2;                             /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
5244   __IO uint8_t REGSC;                              /**< Regulator Status And Control register, offset: 0x2 */
5245 } PMC_Type;
5246 
5247 /* ----------------------------------------------------------------------------
5248    -- PMC Register Masks
5249    ---------------------------------------------------------------------------- */
5250 
5251 /*!
5252  * @addtogroup PMC_Register_Masks PMC Register Masks
5253  * @{
5254  */
5255 
5256 /*! @name LVDSC1 - Low Voltage Detect Status And Control 1 register */
5257 #define PMC_LVDSC1_LVDV_MASK                     (0x3U)
5258 #define PMC_LVDSC1_LVDV_SHIFT                    (0U)
5259 #define PMC_LVDSC1_LVDV(x)                       (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDV_SHIFT)) & PMC_LVDSC1_LVDV_MASK)
5260 #define PMC_LVDSC1_LVDRE_MASK                    (0x10U)
5261 #define PMC_LVDSC1_LVDRE_SHIFT                   (4U)
5262 #define PMC_LVDSC1_LVDRE(x)                      (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDRE_SHIFT)) & PMC_LVDSC1_LVDRE_MASK)
5263 #define PMC_LVDSC1_LVDIE_MASK                    (0x20U)
5264 #define PMC_LVDSC1_LVDIE_SHIFT                   (5U)
5265 #define PMC_LVDSC1_LVDIE(x)                      (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDIE_SHIFT)) & PMC_LVDSC1_LVDIE_MASK)
5266 #define PMC_LVDSC1_LVDACK_MASK                   (0x40U)
5267 #define PMC_LVDSC1_LVDACK_SHIFT                  (6U)
5268 #define PMC_LVDSC1_LVDACK(x)                     (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDACK_SHIFT)) & PMC_LVDSC1_LVDACK_MASK)
5269 #define PMC_LVDSC1_LVDF_MASK                     (0x80U)
5270 #define PMC_LVDSC1_LVDF_SHIFT                    (7U)
5271 #define PMC_LVDSC1_LVDF(x)                       (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDF_SHIFT)) & PMC_LVDSC1_LVDF_MASK)
5272 
5273 /*! @name LVDSC2 - Low Voltage Detect Status And Control 2 register */
5274 #define PMC_LVDSC2_LVWV_MASK                     (0x3U)
5275 #define PMC_LVDSC2_LVWV_SHIFT                    (0U)
5276 #define PMC_LVDSC2_LVWV(x)                       (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWV_SHIFT)) & PMC_LVDSC2_LVWV_MASK)
5277 #define PMC_LVDSC2_LVWIE_MASK                    (0x20U)
5278 #define PMC_LVDSC2_LVWIE_SHIFT                   (5U)
5279 #define PMC_LVDSC2_LVWIE(x)                      (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWIE_SHIFT)) & PMC_LVDSC2_LVWIE_MASK)
5280 #define PMC_LVDSC2_LVWACK_MASK                   (0x40U)
5281 #define PMC_LVDSC2_LVWACK_SHIFT                  (6U)
5282 #define PMC_LVDSC2_LVWACK(x)                     (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWACK_SHIFT)) & PMC_LVDSC2_LVWACK_MASK)
5283 #define PMC_LVDSC2_LVWF_MASK                     (0x80U)
5284 #define PMC_LVDSC2_LVWF_SHIFT                    (7U)
5285 #define PMC_LVDSC2_LVWF(x)                       (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWF_SHIFT)) & PMC_LVDSC2_LVWF_MASK)
5286 
5287 /*! @name REGSC - Regulator Status And Control register */
5288 #define PMC_REGSC_BGBE_MASK                      (0x1U)
5289 #define PMC_REGSC_BGBE_SHIFT                     (0U)
5290 #define PMC_REGSC_BGBE(x)                        (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGBE_SHIFT)) & PMC_REGSC_BGBE_MASK)
5291 #define PMC_REGSC_REGONS_MASK                    (0x4U)
5292 #define PMC_REGSC_REGONS_SHIFT                   (2U)
5293 #define PMC_REGSC_REGONS(x)                      (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_REGONS_SHIFT)) & PMC_REGSC_REGONS_MASK)
5294 #define PMC_REGSC_ACKISO_MASK                    (0x8U)
5295 #define PMC_REGSC_ACKISO_SHIFT                   (3U)
5296 #define PMC_REGSC_ACKISO(x)                      (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_ACKISO_SHIFT)) & PMC_REGSC_ACKISO_MASK)
5297 #define PMC_REGSC_VLPO_MASK                      (0x40U)
5298 #define PMC_REGSC_VLPO_SHIFT                     (6U)
5299 #define PMC_REGSC_VLPO(x)                        (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_VLPO_SHIFT)) & PMC_REGSC_VLPO_MASK)
5300 
5301 
5302 /*!
5303  * @}
5304  */ /* end of group PMC_Register_Masks */
5305 
5306 
5307 /* PMC - Peripheral instance base addresses */
5308 /** Peripheral PMC base address */
5309 #define PMC_BASE                                 (0x4007D000u)
5310 /** Peripheral PMC base pointer */
5311 #define PMC                                      ((PMC_Type *)PMC_BASE)
5312 /** Array initializer of PMC peripheral base addresses */
5313 #define PMC_BASE_ADDRS                           { PMC_BASE }
5314 /** Array initializer of PMC peripheral base pointers */
5315 #define PMC_BASE_PTRS                            { PMC }
5316 /** Interrupt vectors for the PMC peripheral type */
5317 #define PMC_IRQS                                 { LVD_LVW_DCDC_IRQn }
5318 
5319 /*!
5320  * @}
5321  */ /* end of group PMC_Peripheral_Access_Layer */
5322 
5323 
5324 /* ----------------------------------------------------------------------------
5325    -- PORT Peripheral Access Layer
5326    ---------------------------------------------------------------------------- */
5327 
5328 /*!
5329  * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
5330  * @{
5331  */
5332 
5333 /** PORT - Register Layout Typedef */
5334 typedef struct {
5335   __IO uint32_t PCR[32];                           /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
5336   __O  uint32_t GPCLR;                             /**< Global Pin Control Low Register, offset: 0x80 */
5337   __O  uint32_t GPCHR;                             /**< Global Pin Control High Register, offset: 0x84 */
5338        uint8_t RESERVED_0[24];
5339   __IO uint32_t ISFR;                              /**< Interrupt Status Flag Register, offset: 0xA0 */
5340 } PORT_Type;
5341 
5342 /* ----------------------------------------------------------------------------
5343    -- PORT Register Masks
5344    ---------------------------------------------------------------------------- */
5345 
5346 /*!
5347  * @addtogroup PORT_Register_Masks PORT Register Masks
5348  * @{
5349  */
5350 
5351 /*! @name PCR - Pin Control Register n */
5352 #define PORT_PCR_PS_MASK                         (0x1U)
5353 #define PORT_PCR_PS_SHIFT                        (0U)
5354 #define PORT_PCR_PS(x)                           (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK)
5355 #define PORT_PCR_PE_MASK                         (0x2U)
5356 #define PORT_PCR_PE_SHIFT                        (1U)
5357 #define PORT_PCR_PE(x)                           (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK)
5358 #define PORT_PCR_SRE_MASK                        (0x4U)
5359 #define PORT_PCR_SRE_SHIFT                       (2U)
5360 #define PORT_PCR_SRE(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK)
5361 #define PORT_PCR_PFE_MASK                        (0x10U)
5362 #define PORT_PCR_PFE_SHIFT                       (4U)
5363 #define PORT_PCR_PFE(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK)
5364 #define PORT_PCR_DSE_MASK                        (0x40U)
5365 #define PORT_PCR_DSE_SHIFT                       (6U)
5366 #define PORT_PCR_DSE(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK)
5367 #define PORT_PCR_MUX_MASK                        (0x700U)
5368 #define PORT_PCR_MUX_SHIFT                       (8U)
5369 #define PORT_PCR_MUX(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK)
5370 #define PORT_PCR_IRQC_MASK                       (0xF0000U)
5371 #define PORT_PCR_IRQC_SHIFT                      (16U)
5372 #define PORT_PCR_IRQC(x)                         (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK)
5373 #define PORT_PCR_ISF_MASK                        (0x1000000U)
5374 #define PORT_PCR_ISF_SHIFT                       (24U)
5375 #define PORT_PCR_ISF(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK)
5376 
5377 /* The count of PORT_PCR */
5378 #define PORT_PCR_COUNT                           (32U)
5379 
5380 /*! @name GPCLR - Global Pin Control Low Register */
5381 #define PORT_GPCLR_GPWD_MASK                     (0xFFFFU)
5382 #define PORT_GPCLR_GPWD_SHIFT                    (0U)
5383 #define PORT_GPCLR_GPWD(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK)
5384 #define PORT_GPCLR_GPWE_MASK                     (0xFFFF0000U)
5385 #define PORT_GPCLR_GPWE_SHIFT                    (16U)
5386 #define PORT_GPCLR_GPWE(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK)
5387 
5388 /*! @name GPCHR - Global Pin Control High Register */
5389 #define PORT_GPCHR_GPWD_MASK                     (0xFFFFU)
5390 #define PORT_GPCHR_GPWD_SHIFT                    (0U)
5391 #define PORT_GPCHR_GPWD(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK)
5392 #define PORT_GPCHR_GPWE_MASK                     (0xFFFF0000U)
5393 #define PORT_GPCHR_GPWE_SHIFT                    (16U)
5394 #define PORT_GPCHR_GPWE(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK)
5395 
5396 /*! @name ISFR - Interrupt Status Flag Register */
5397 #define PORT_ISFR_ISF_MASK                       (0xFFFFFFFFU)
5398 #define PORT_ISFR_ISF_SHIFT                      (0U)
5399 #define PORT_ISFR_ISF(x)                         (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK)
5400 
5401 
5402 /*!
5403  * @}
5404  */ /* end of group PORT_Register_Masks */
5405 
5406 
5407 /* PORT - Peripheral instance base addresses */
5408 /** Peripheral PORTA base address */
5409 #define PORTA_BASE                               (0x40049000u)
5410 /** Peripheral PORTA base pointer */
5411 #define PORTA                                    ((PORT_Type *)PORTA_BASE)
5412 /** Peripheral PORTB base address */
5413 #define PORTB_BASE                               (0x4004A000u)
5414 /** Peripheral PORTB base pointer */
5415 #define PORTB                                    ((PORT_Type *)PORTB_BASE)
5416 /** Peripheral PORTC base address */
5417 #define PORTC_BASE                               (0x4004B000u)
5418 /** Peripheral PORTC base pointer */
5419 #define PORTC                                    ((PORT_Type *)PORTC_BASE)
5420 /** Array initializer of PORT peripheral base addresses */
5421 #define PORT_BASE_ADDRS                          { PORTA_BASE, PORTB_BASE, PORTC_BASE }
5422 /** Array initializer of PORT peripheral base pointers */
5423 #define PORT_BASE_PTRS                           { PORTA, PORTB, PORTC }
5424 /** Interrupt vectors for the PORT peripheral type */
5425 #define PORT_IRQS                                { PORTA_IRQn, PORTB_PORTC_IRQn, PORTB_PORTC_IRQn }
5426 
5427 /*!
5428  * @}
5429  */ /* end of group PORT_Peripheral_Access_Layer */
5430 
5431 
5432 /* ----------------------------------------------------------------------------
5433    -- RCM Peripheral Access Layer
5434    ---------------------------------------------------------------------------- */
5435 
5436 /*!
5437  * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
5438  * @{
5439  */
5440 
5441 /** RCM - Register Layout Typedef */
5442 typedef struct {
5443   __I  uint8_t SRS0;                               /**< System Reset Status Register 0, offset: 0x0 */
5444   __I  uint8_t SRS1;                               /**< System Reset Status Register 1, offset: 0x1 */
5445        uint8_t RESERVED_0[2];
5446   __IO uint8_t RPFC;                               /**< Reset Pin Filter Control register, offset: 0x4 */
5447   __IO uint8_t RPFW;                               /**< Reset Pin Filter Width register, offset: 0x5 */
5448 } RCM_Type;
5449 
5450 /* ----------------------------------------------------------------------------
5451    -- RCM Register Masks
5452    ---------------------------------------------------------------------------- */
5453 
5454 /*!
5455  * @addtogroup RCM_Register_Masks RCM Register Masks
5456  * @{
5457  */
5458 
5459 /*! @name SRS0 - System Reset Status Register 0 */
5460 #define RCM_SRS0_WAKEUP_MASK                     (0x1U)
5461 #define RCM_SRS0_WAKEUP_SHIFT                    (0U)
5462 #define RCM_SRS0_WAKEUP(x)                       (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WAKEUP_SHIFT)) & RCM_SRS0_WAKEUP_MASK)
5463 #define RCM_SRS0_LVD_MASK                        (0x2U)
5464 #define RCM_SRS0_LVD_SHIFT                       (1U)
5465 #define RCM_SRS0_LVD(x)                          (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LVD_SHIFT)) & RCM_SRS0_LVD_MASK)
5466 #define RCM_SRS0_LOC_MASK                        (0x4U)
5467 #define RCM_SRS0_LOC_SHIFT                       (2U)
5468 #define RCM_SRS0_LOC(x)                          (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOC_SHIFT)) & RCM_SRS0_LOC_MASK)
5469 #define RCM_SRS0_WDOG_MASK                       (0x20U)
5470 #define RCM_SRS0_WDOG_SHIFT                      (5U)
5471 #define RCM_SRS0_WDOG(x)                         (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WDOG_SHIFT)) & RCM_SRS0_WDOG_MASK)
5472 #define RCM_SRS0_PIN_MASK                        (0x40U)
5473 #define RCM_SRS0_PIN_SHIFT                       (6U)
5474 #define RCM_SRS0_PIN(x)                          (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_PIN_SHIFT)) & RCM_SRS0_PIN_MASK)
5475 #define RCM_SRS0_POR_MASK                        (0x80U)
5476 #define RCM_SRS0_POR_SHIFT                       (7U)
5477 #define RCM_SRS0_POR(x)                          (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_POR_SHIFT)) & RCM_SRS0_POR_MASK)
5478 
5479 /*! @name SRS1 - System Reset Status Register 1 */
5480 #define RCM_SRS1_LOCKUP_MASK                     (0x2U)
5481 #define RCM_SRS1_LOCKUP_SHIFT                    (1U)
5482 #define RCM_SRS1_LOCKUP(x)                       (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_LOCKUP_SHIFT)) & RCM_SRS1_LOCKUP_MASK)
5483 #define RCM_SRS1_SW_MASK                         (0x4U)
5484 #define RCM_SRS1_SW_SHIFT                        (2U)
5485 #define RCM_SRS1_SW(x)                           (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SW_SHIFT)) & RCM_SRS1_SW_MASK)
5486 #define RCM_SRS1_MDM_AP_MASK                     (0x8U)
5487 #define RCM_SRS1_MDM_AP_SHIFT                    (3U)
5488 #define RCM_SRS1_MDM_AP(x)                       (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_MDM_AP_SHIFT)) & RCM_SRS1_MDM_AP_MASK)
5489 #define RCM_SRS1_SACKERR_MASK                    (0x20U)
5490 #define RCM_SRS1_SACKERR_SHIFT                   (5U)
5491 #define RCM_SRS1_SACKERR(x)                      (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SACKERR_SHIFT)) & RCM_SRS1_SACKERR_MASK)
5492 
5493 /*! @name RPFC - Reset Pin Filter Control register */
5494 #define RCM_RPFC_RSTFLTSRW_MASK                  (0x3U)
5495 #define RCM_RPFC_RSTFLTSRW_SHIFT                 (0U)
5496 #define RCM_RPFC_RSTFLTSRW(x)                    (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSRW_SHIFT)) & RCM_RPFC_RSTFLTSRW_MASK)
5497 #define RCM_RPFC_RSTFLTSS_MASK                   (0x4U)
5498 #define RCM_RPFC_RSTFLTSS_SHIFT                  (2U)
5499 #define RCM_RPFC_RSTFLTSS(x)                     (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSS_SHIFT)) & RCM_RPFC_RSTFLTSS_MASK)
5500 
5501 /*! @name RPFW - Reset Pin Filter Width register */
5502 #define RCM_RPFW_RSTFLTSEL_MASK                  (0x1FU)
5503 #define RCM_RPFW_RSTFLTSEL_SHIFT                 (0U)
5504 #define RCM_RPFW_RSTFLTSEL(x)                    (((uint8_t)(((uint8_t)(x)) << RCM_RPFW_RSTFLTSEL_SHIFT)) & RCM_RPFW_RSTFLTSEL_MASK)
5505 
5506 
5507 /*!
5508  * @}
5509  */ /* end of group RCM_Register_Masks */
5510 
5511 
5512 /* RCM - Peripheral instance base addresses */
5513 /** Peripheral RCM base address */
5514 #define RCM_BASE                                 (0x4007F000u)
5515 /** Peripheral RCM base pointer */
5516 #define RCM                                      ((RCM_Type *)RCM_BASE)
5517 /** Array initializer of RCM peripheral base addresses */
5518 #define RCM_BASE_ADDRS                           { RCM_BASE }
5519 /** Array initializer of RCM peripheral base pointers */
5520 #define RCM_BASE_PTRS                            { RCM }
5521 
5522 /*!
5523  * @}
5524  */ /* end of group RCM_Peripheral_Access_Layer */
5525 
5526 
5527 /* ----------------------------------------------------------------------------
5528    -- RFSYS Peripheral Access Layer
5529    ---------------------------------------------------------------------------- */
5530 
5531 /*!
5532  * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
5533  * @{
5534  */
5535 
5536 /** RFSYS - Register Layout Typedef */
5537 typedef struct {
5538   __IO uint32_t REG[8];                            /**< Register file register, array offset: 0x0, array step: 0x4 */
5539 } RFSYS_Type;
5540 
5541 /* ----------------------------------------------------------------------------
5542    -- RFSYS Register Masks
5543    ---------------------------------------------------------------------------- */
5544 
5545 /*!
5546  * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
5547  * @{
5548  */
5549 
5550 /*! @name REG - Register file register */
5551 #define RFSYS_REG_LL_MASK                        (0xFFU)
5552 #define RFSYS_REG_LL_SHIFT                       (0U)
5553 #define RFSYS_REG_LL(x)                          (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LL_SHIFT)) & RFSYS_REG_LL_MASK)
5554 #define RFSYS_REG_LH_MASK                        (0xFF00U)
5555 #define RFSYS_REG_LH_SHIFT                       (8U)
5556 #define RFSYS_REG_LH(x)                          (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LH_SHIFT)) & RFSYS_REG_LH_MASK)
5557 #define RFSYS_REG_HL_MASK                        (0xFF0000U)
5558 #define RFSYS_REG_HL_SHIFT                       (16U)
5559 #define RFSYS_REG_HL(x)                          (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HL_SHIFT)) & RFSYS_REG_HL_MASK)
5560 #define RFSYS_REG_HH_MASK                        (0xFF000000U)
5561 #define RFSYS_REG_HH_SHIFT                       (24U)
5562 #define RFSYS_REG_HH(x)                          (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HH_SHIFT)) & RFSYS_REG_HH_MASK)
5563 
5564 /* The count of RFSYS_REG */
5565 #define RFSYS_REG_COUNT                          (8U)
5566 
5567 
5568 /*!
5569  * @}
5570  */ /* end of group RFSYS_Register_Masks */
5571 
5572 
5573 /* RFSYS - Peripheral instance base addresses */
5574 /** Peripheral RFSYS base address */
5575 #define RFSYS_BASE                               (0x40041000u)
5576 /** Peripheral RFSYS base pointer */
5577 #define RFSYS                                    ((RFSYS_Type *)RFSYS_BASE)
5578 /** Array initializer of RFSYS peripheral base addresses */
5579 #define RFSYS_BASE_ADDRS                         { RFSYS_BASE }
5580 /** Array initializer of RFSYS peripheral base pointers */
5581 #define RFSYS_BASE_PTRS                          { RFSYS }
5582 
5583 /*!
5584  * @}
5585  */ /* end of group RFSYS_Peripheral_Access_Layer */
5586 
5587 
5588 /* ----------------------------------------------------------------------------
5589    -- ROM Peripheral Access Layer
5590    ---------------------------------------------------------------------------- */
5591 
5592 /*!
5593  * @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer
5594  * @{
5595  */
5596 
5597 /** ROM - Register Layout Typedef */
5598 typedef struct {
5599   __I  uint32_t ENTRY[3];                          /**< Entry, array offset: 0x0, array step: 0x4 */
5600   __I  uint32_t TABLEMARK;                         /**< End of Table Marker Register, offset: 0xC */
5601        uint8_t RESERVED_0[4028];
5602   __I  uint32_t SYSACCESS;                         /**< System Access Register, offset: 0xFCC */
5603   __I  uint32_t PERIPHID4;                         /**< Peripheral ID Register, offset: 0xFD0 */
5604   __I  uint32_t PERIPHID5;                         /**< Peripheral ID Register, offset: 0xFD4 */
5605   __I  uint32_t PERIPHID6;                         /**< Peripheral ID Register, offset: 0xFD8 */
5606   __I  uint32_t PERIPHID7;                         /**< Peripheral ID Register, offset: 0xFDC */
5607   __I  uint32_t PERIPHID0;                         /**< Peripheral ID Register, offset: 0xFE0 */
5608   __I  uint32_t PERIPHID1;                         /**< Peripheral ID Register, offset: 0xFE4 */
5609   __I  uint32_t PERIPHID2;                         /**< Peripheral ID Register, offset: 0xFE8 */
5610   __I  uint32_t PERIPHID3;                         /**< Peripheral ID Register, offset: 0xFEC */
5611   __I  uint32_t COMPID[4];                         /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
5612 } ROM_Type;
5613 
5614 /* ----------------------------------------------------------------------------
5615    -- ROM Register Masks
5616    ---------------------------------------------------------------------------- */
5617 
5618 /*!
5619  * @addtogroup ROM_Register_Masks ROM Register Masks
5620  * @{
5621  */
5622 
5623 /*! @name ENTRY - Entry */
5624 #define ROM_ENTRY_ENTRY_MASK                     (0xFFFFFFFFU)
5625 #define ROM_ENTRY_ENTRY_SHIFT                    (0U)
5626 #define ROM_ENTRY_ENTRY(x)                       (((uint32_t)(((uint32_t)(x)) << ROM_ENTRY_ENTRY_SHIFT)) & ROM_ENTRY_ENTRY_MASK)
5627 
5628 /* The count of ROM_ENTRY */
5629 #define ROM_ENTRY_COUNT                          (3U)
5630 
5631 /*! @name TABLEMARK - End of Table Marker Register */
5632 #define ROM_TABLEMARK_MARK_MASK                  (0xFFFFFFFFU)
5633 #define ROM_TABLEMARK_MARK_SHIFT                 (0U)
5634 #define ROM_TABLEMARK_MARK(x)                    (((uint32_t)(((uint32_t)(x)) << ROM_TABLEMARK_MARK_SHIFT)) & ROM_TABLEMARK_MARK_MASK)
5635 
5636 /*! @name SYSACCESS - System Access Register */
5637 #define ROM_SYSACCESS_SYSACCESS_MASK             (0xFFFFFFFFU)
5638 #define ROM_SYSACCESS_SYSACCESS_SHIFT            (0U)
5639 #define ROM_SYSACCESS_SYSACCESS(x)               (((uint32_t)(((uint32_t)(x)) << ROM_SYSACCESS_SYSACCESS_SHIFT)) & ROM_SYSACCESS_SYSACCESS_MASK)
5640 
5641 /*! @name PERIPHID4 - Peripheral ID Register */
5642 #define ROM_PERIPHID4_PERIPHID_MASK              (0xFFFFFFFFU)
5643 #define ROM_PERIPHID4_PERIPHID_SHIFT             (0U)
5644 #define ROM_PERIPHID4_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID4_PERIPHID_SHIFT)) & ROM_PERIPHID4_PERIPHID_MASK)
5645 
5646 /*! @name PERIPHID5 - Peripheral ID Register */
5647 #define ROM_PERIPHID5_PERIPHID_MASK              (0xFFFFFFFFU)
5648 #define ROM_PERIPHID5_PERIPHID_SHIFT             (0U)
5649 #define ROM_PERIPHID5_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID5_PERIPHID_SHIFT)) & ROM_PERIPHID5_PERIPHID_MASK)
5650 
5651 /*! @name PERIPHID6 - Peripheral ID Register */
5652 #define ROM_PERIPHID6_PERIPHID_MASK              (0xFFFFFFFFU)
5653 #define ROM_PERIPHID6_PERIPHID_SHIFT             (0U)
5654 #define ROM_PERIPHID6_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID6_PERIPHID_SHIFT)) & ROM_PERIPHID6_PERIPHID_MASK)
5655 
5656 /*! @name PERIPHID7 - Peripheral ID Register */
5657 #define ROM_PERIPHID7_PERIPHID_MASK              (0xFFFFFFFFU)
5658 #define ROM_PERIPHID7_PERIPHID_SHIFT             (0U)
5659 #define ROM_PERIPHID7_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID7_PERIPHID_SHIFT)) & ROM_PERIPHID7_PERIPHID_MASK)
5660 
5661 /*! @name PERIPHID0 - Peripheral ID Register */
5662 #define ROM_PERIPHID0_PERIPHID_MASK              (0xFFFFFFFFU)
5663 #define ROM_PERIPHID0_PERIPHID_SHIFT             (0U)
5664 #define ROM_PERIPHID0_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID0_PERIPHID_SHIFT)) & ROM_PERIPHID0_PERIPHID_MASK)
5665 
5666 /*! @name PERIPHID1 - Peripheral ID Register */
5667 #define ROM_PERIPHID1_PERIPHID_MASK              (0xFFFFFFFFU)
5668 #define ROM_PERIPHID1_PERIPHID_SHIFT             (0U)
5669 #define ROM_PERIPHID1_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID1_PERIPHID_SHIFT)) & ROM_PERIPHID1_PERIPHID_MASK)
5670 
5671 /*! @name PERIPHID2 - Peripheral ID Register */
5672 #define ROM_PERIPHID2_PERIPHID_MASK              (0xFFFFFFFFU)
5673 #define ROM_PERIPHID2_PERIPHID_SHIFT             (0U)
5674 #define ROM_PERIPHID2_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID2_PERIPHID_SHIFT)) & ROM_PERIPHID2_PERIPHID_MASK)
5675 
5676 /*! @name PERIPHID3 - Peripheral ID Register */
5677 #define ROM_PERIPHID3_PERIPHID_MASK              (0xFFFFFFFFU)
5678 #define ROM_PERIPHID3_PERIPHID_SHIFT             (0U)
5679 #define ROM_PERIPHID3_PERIPHID(x)                (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID3_PERIPHID_SHIFT)) & ROM_PERIPHID3_PERIPHID_MASK)
5680 
5681 /*! @name COMPID - Component ID Register */
5682 #define ROM_COMPID_COMPID_MASK                   (0xFFFFFFFFU)
5683 #define ROM_COMPID_COMPID_SHIFT                  (0U)
5684 #define ROM_COMPID_COMPID(x)                     (((uint32_t)(((uint32_t)(x)) << ROM_COMPID_COMPID_SHIFT)) & ROM_COMPID_COMPID_MASK)
5685 
5686 /* The count of ROM_COMPID */
5687 #define ROM_COMPID_COUNT                         (4U)
5688 
5689 
5690 /*!
5691  * @}
5692  */ /* end of group ROM_Register_Masks */
5693 
5694 
5695 /* ROM - Peripheral instance base addresses */
5696 /** Peripheral ROM base address */
5697 #define ROM_BASE                                 (0xF0002000u)
5698 /** Peripheral ROM base pointer */
5699 #define ROM                                      ((ROM_Type *)ROM_BASE)
5700 /** Array initializer of ROM peripheral base addresses */
5701 #define ROM_BASE_ADDRS                           { ROM_BASE }
5702 /** Array initializer of ROM peripheral base pointers */
5703 #define ROM_BASE_PTRS                            { ROM }
5704 
5705 /*!
5706  * @}
5707  */ /* end of group ROM_Peripheral_Access_Layer */
5708 
5709 
5710 /* ----------------------------------------------------------------------------
5711    -- RSIM Peripheral Access Layer
5712    ---------------------------------------------------------------------------- */
5713 
5714 /*!
5715  * @addtogroup RSIM_Peripheral_Access_Layer RSIM Peripheral Access Layer
5716  * @{
5717  */
5718 
5719 /** RSIM - Register Layout Typedef */
5720 typedef struct {
5721   __IO uint32_t CONTROL;                           /**< Radio System Control, offset: 0x0 */
5722   __IO uint32_t ACTIVE_DELAY;                      /**< Radio Active Early Warning, offset: 0x4 */
5723   __I  uint32_t MAC_MSB;                           /**< Radio MAC Address, offset: 0x8 */
5724   __I  uint32_t MAC_LSB;                           /**< Radio MAC Address, offset: 0xC */
5725   __IO uint32_t MISC;                              /**< Radio Miscellaneous, offset: 0x10 */
5726        uint8_t RESERVED_0[236];
5727   __I  uint32_t DSM_TIMER;                         /**< Deep Sleep Timer, offset: 0x100 */
5728   __IO uint32_t DSM_CONTROL;                       /**< Deep Sleep Timer Control, offset: 0x104 */
5729   __IO uint32_t DSM_OSC_OFFSET;                    /**< Deep Sleep Wakeup Time Offset, offset: 0x108 */
5730   __IO uint32_t ANT_SLEEP;                         /**< ANT Link Layer Sleep Time, offset: 0x10C */
5731   __IO uint32_t ANT_WAKE;                          /**< ANT Link Layer Wake Time, offset: 0x110 */
5732   __IO uint32_t ZIG_SLEEP;                         /**< 802.15.4 Link Layer Sleep Time, offset: 0x114 */
5733   __IO uint32_t ZIG_WAKE;                          /**< 802.15.4 Link Layer Wake Time, offset: 0x118 */
5734   __IO uint32_t GEN_SLEEP;                         /**< Generic FSK Link Layer Sleep Time, offset: 0x11C */
5735   __IO uint32_t GEN_WAKE;                          /**< Generic FSK Link Layer Wake Time, offset: 0x120 */
5736   __IO uint32_t RF_OSC_CTRL;                       /**< Radio Oscillator Control, offset: 0x124 */
5737   __IO uint32_t ANA_TEST;                          /**< Radio Analog Test Registers, offset: 0x128 */
5738   __IO uint32_t ANA_TRIM;                          /**< Radio Analog Trim Registers, offset: 0x12C */
5739 } RSIM_Type;
5740 
5741 /* ----------------------------------------------------------------------------
5742    -- RSIM Register Masks
5743    ---------------------------------------------------------------------------- */
5744 
5745 /*!
5746  * @addtogroup RSIM_Register_Masks RSIM Register Masks
5747  * @{
5748  */
5749 
5750 /*! @name CONTROL - Radio System Control */
5751 #define RSIM_CONTROL_BLE_RF_OSC_REQ_EN_MASK      (0x1U)
5752 #define RSIM_CONTROL_BLE_RF_OSC_REQ_EN_SHIFT     (0U)
5753 #define RSIM_CONTROL_BLE_RF_OSC_REQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_BLE_RF_OSC_REQ_EN_SHIFT)) & RSIM_CONTROL_BLE_RF_OSC_REQ_EN_MASK)
5754 #define RSIM_CONTROL_BLE_RF_OSC_REQ_STAT_MASK    (0x2U)
5755 #define RSIM_CONTROL_BLE_RF_OSC_REQ_STAT_SHIFT   (1U)
5756 #define RSIM_CONTROL_BLE_RF_OSC_REQ_STAT(x)      (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_BLE_RF_OSC_REQ_STAT_SHIFT)) & RSIM_CONTROL_BLE_RF_OSC_REQ_STAT_MASK)
5757 #define RSIM_CONTROL_BLE_RF_OSC_REQ_INT_EN_MASK  (0x10U)
5758 #define RSIM_CONTROL_BLE_RF_OSC_REQ_INT_EN_SHIFT (4U)
5759 #define RSIM_CONTROL_BLE_RF_OSC_REQ_INT_EN(x)    (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_BLE_RF_OSC_REQ_INT_EN_SHIFT)) & RSIM_CONTROL_BLE_RF_OSC_REQ_INT_EN_MASK)
5760 #define RSIM_CONTROL_BLE_RF_OSC_REQ_INT_MASK     (0x20U)
5761 #define RSIM_CONTROL_BLE_RF_OSC_REQ_INT_SHIFT    (5U)
5762 #define RSIM_CONTROL_BLE_RF_OSC_REQ_INT(x)       (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_BLE_RF_OSC_REQ_INT_SHIFT)) & RSIM_CONTROL_BLE_RF_OSC_REQ_INT_MASK)
5763 #define RSIM_CONTROL_RF_OSC_EN_MASK              (0xF00U)
5764 #define RSIM_CONTROL_RF_OSC_EN_SHIFT             (8U)
5765 #define RSIM_CONTROL_RF_OSC_EN(x)                (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RF_OSC_EN_SHIFT)) & RSIM_CONTROL_RF_OSC_EN_MASK)
5766 #define RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_EN_MASK (0x1000U)
5767 #define RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_EN_SHIFT (12U)
5768 #define RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_EN_SHIFT)) & RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_EN_MASK)
5769 #define RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_MASK (0x2000U)
5770 #define RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_SHIFT (13U)
5771 #define RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_SHIFT)) & RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_MASK)
5772 #define RSIM_CONTROL_IPP_OBE_3V_BLE_ACTIVE_1_MASK (0x10000U)
5773 #define RSIM_CONTROL_IPP_OBE_3V_BLE_ACTIVE_1_SHIFT (16U)
5774 #define RSIM_CONTROL_IPP_OBE_3V_BLE_ACTIVE_1(x)  (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_IPP_OBE_3V_BLE_ACTIVE_1_SHIFT)) & RSIM_CONTROL_IPP_OBE_3V_BLE_ACTIVE_1_MASK)
5775 #define RSIM_CONTROL_IPP_OBE_3V_BLE_ACTIVE_2_MASK (0x20000U)
5776 #define RSIM_CONTROL_IPP_OBE_3V_BLE_ACTIVE_2_SHIFT (17U)
5777 #define RSIM_CONTROL_IPP_OBE_3V_BLE_ACTIVE_2(x)  (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_IPP_OBE_3V_BLE_ACTIVE_2_SHIFT)) & RSIM_CONTROL_IPP_OBE_3V_BLE_ACTIVE_2_MASK)
5778 #define RSIM_CONTROL_RADIO_RAM_ACCESS_OVRD_EN_MASK (0x40000U)
5779 #define RSIM_CONTROL_RADIO_RAM_ACCESS_OVRD_EN_SHIFT (18U)
5780 #define RSIM_CONTROL_RADIO_RAM_ACCESS_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RADIO_RAM_ACCESS_OVRD_EN_SHIFT)) & RSIM_CONTROL_RADIO_RAM_ACCESS_OVRD_EN_MASK)
5781 #define RSIM_CONTROL_RADIO_RAM_ACCESS_OVRD_MASK  (0x80000U)
5782 #define RSIM_CONTROL_RADIO_RAM_ACCESS_OVRD_SHIFT (19U)
5783 #define RSIM_CONTROL_RADIO_RAM_ACCESS_OVRD(x)    (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RADIO_RAM_ACCESS_OVRD_SHIFT)) & RSIM_CONTROL_RADIO_RAM_ACCESS_OVRD_MASK)
5784 #define RSIM_CONTROL_RSIM_DSM_EXIT_MASK          (0x100000U)
5785 #define RSIM_CONTROL_RSIM_DSM_EXIT_SHIFT         (20U)
5786 #define RSIM_CONTROL_RSIM_DSM_EXIT(x)            (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RSIM_DSM_EXIT_SHIFT)) & RSIM_CONTROL_RSIM_DSM_EXIT_MASK)
5787 #define RSIM_CONTROL_RSIM_STOP_ACK_OVRD_EN_MASK  (0x400000U)
5788 #define RSIM_CONTROL_RSIM_STOP_ACK_OVRD_EN_SHIFT (22U)
5789 #define RSIM_CONTROL_RSIM_STOP_ACK_OVRD_EN(x)    (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RSIM_STOP_ACK_OVRD_EN_SHIFT)) & RSIM_CONTROL_RSIM_STOP_ACK_OVRD_EN_MASK)
5790 #define RSIM_CONTROL_RSIM_STOP_ACK_OVRD_MASK     (0x800000U)
5791 #define RSIM_CONTROL_RSIM_STOP_ACK_OVRD_SHIFT    (23U)
5792 #define RSIM_CONTROL_RSIM_STOP_ACK_OVRD(x)       (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RSIM_STOP_ACK_OVRD_SHIFT)) & RSIM_CONTROL_RSIM_STOP_ACK_OVRD_MASK)
5793 #define RSIM_CONTROL_RF_OSC_READY_MASK           (0x1000000U)
5794 #define RSIM_CONTROL_RF_OSC_READY_SHIFT          (24U)
5795 #define RSIM_CONTROL_RF_OSC_READY(x)             (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RF_OSC_READY_SHIFT)) & RSIM_CONTROL_RF_OSC_READY_MASK)
5796 #define RSIM_CONTROL_RF_OSC_READY_OVRD_EN_MASK   (0x2000000U)
5797 #define RSIM_CONTROL_RF_OSC_READY_OVRD_EN_SHIFT  (25U)
5798 #define RSIM_CONTROL_RF_OSC_READY_OVRD_EN(x)     (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RF_OSC_READY_OVRD_EN_SHIFT)) & RSIM_CONTROL_RF_OSC_READY_OVRD_EN_MASK)
5799 #define RSIM_CONTROL_RF_OSC_READY_OVRD_MASK      (0x4000000U)
5800 #define RSIM_CONTROL_RF_OSC_READY_OVRD_SHIFT     (26U)
5801 #define RSIM_CONTROL_RF_OSC_READY_OVRD(x)        (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RF_OSC_READY_OVRD_SHIFT)) & RSIM_CONTROL_RF_OSC_READY_OVRD_MASK)
5802 #define RSIM_CONTROL_BLOCK_SOC_RESETS_MASK       (0x10000000U)
5803 #define RSIM_CONTROL_BLOCK_SOC_RESETS_SHIFT      (28U)
5804 #define RSIM_CONTROL_BLOCK_SOC_RESETS(x)         (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_BLOCK_SOC_RESETS_SHIFT)) & RSIM_CONTROL_BLOCK_SOC_RESETS_MASK)
5805 #define RSIM_CONTROL_BLOCK_RADIO_OUTPUTS_MASK    (0x20000000U)
5806 #define RSIM_CONTROL_BLOCK_RADIO_OUTPUTS_SHIFT   (29U)
5807 #define RSIM_CONTROL_BLOCK_RADIO_OUTPUTS(x)      (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_BLOCK_RADIO_OUTPUTS_SHIFT)) & RSIM_CONTROL_BLOCK_RADIO_OUTPUTS_MASK)
5808 #define RSIM_CONTROL_ALLOW_DFT_RESETS_MASK       (0x40000000U)
5809 #define RSIM_CONTROL_ALLOW_DFT_RESETS_SHIFT      (30U)
5810 #define RSIM_CONTROL_ALLOW_DFT_RESETS(x)         (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_ALLOW_DFT_RESETS_SHIFT)) & RSIM_CONTROL_ALLOW_DFT_RESETS_MASK)
5811 #define RSIM_CONTROL_RADIO_RESET_BIT_MASK        (0x80000000U)
5812 #define RSIM_CONTROL_RADIO_RESET_BIT_SHIFT       (31U)
5813 #define RSIM_CONTROL_RADIO_RESET_BIT(x)          (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RADIO_RESET_BIT_SHIFT)) & RSIM_CONTROL_RADIO_RESET_BIT_MASK)
5814 
5815 /*! @name ACTIVE_DELAY - Radio Active Early Warning */
5816 #define RSIM_ACTIVE_DELAY_BLE_FINE_DELAY_MASK    (0x3FU)
5817 #define RSIM_ACTIVE_DELAY_BLE_FINE_DELAY_SHIFT   (0U)
5818 #define RSIM_ACTIVE_DELAY_BLE_FINE_DELAY(x)      (((uint32_t)(((uint32_t)(x)) << RSIM_ACTIVE_DELAY_BLE_FINE_DELAY_SHIFT)) & RSIM_ACTIVE_DELAY_BLE_FINE_DELAY_MASK)
5819 #define RSIM_ACTIVE_DELAY_BLE_COARSE_DELAY_MASK  (0xF0000U)
5820 #define RSIM_ACTIVE_DELAY_BLE_COARSE_DELAY_SHIFT (16U)
5821 #define RSIM_ACTIVE_DELAY_BLE_COARSE_DELAY(x)    (((uint32_t)(((uint32_t)(x)) << RSIM_ACTIVE_DELAY_BLE_COARSE_DELAY_SHIFT)) & RSIM_ACTIVE_DELAY_BLE_COARSE_DELAY_MASK)
5822 
5823 /*! @name MAC_MSB - Radio MAC Address */
5824 #define RSIM_MAC_MSB_MAC_ADDR_MSB_MASK           (0xFFU)
5825 #define RSIM_MAC_MSB_MAC_ADDR_MSB_SHIFT          (0U)
5826 #define RSIM_MAC_MSB_MAC_ADDR_MSB(x)             (((uint32_t)(((uint32_t)(x)) << RSIM_MAC_MSB_MAC_ADDR_MSB_SHIFT)) & RSIM_MAC_MSB_MAC_ADDR_MSB_MASK)
5827 
5828 /*! @name MAC_LSB - Radio MAC Address */
5829 #define RSIM_MAC_LSB_MAC_ADDR_LSB_MASK           (0xFFFFFFFFU)
5830 #define RSIM_MAC_LSB_MAC_ADDR_LSB_SHIFT          (0U)
5831 #define RSIM_MAC_LSB_MAC_ADDR_LSB(x)             (((uint32_t)(((uint32_t)(x)) << RSIM_MAC_LSB_MAC_ADDR_LSB_SHIFT)) & RSIM_MAC_LSB_MAC_ADDR_LSB_MASK)
5832 
5833 /*! @name MISC - Radio Miscellaneous */
5834 #define RSIM_MISC_ANALOG_TEST_EN_MASK            (0x1FU)
5835 #define RSIM_MISC_ANALOG_TEST_EN_SHIFT           (0U)
5836 #define RSIM_MISC_ANALOG_TEST_EN(x)              (((uint32_t)(((uint32_t)(x)) << RSIM_MISC_ANALOG_TEST_EN_SHIFT)) & RSIM_MISC_ANALOG_TEST_EN_MASK)
5837 #define RSIM_MISC_RADIO_VERSION_MASK             (0xFF000000U)
5838 #define RSIM_MISC_RADIO_VERSION_SHIFT            (24U)
5839 #define RSIM_MISC_RADIO_VERSION(x)               (((uint32_t)(((uint32_t)(x)) << RSIM_MISC_RADIO_VERSION_SHIFT)) & RSIM_MISC_RADIO_VERSION_MASK)
5840 
5841 /*! @name DSM_TIMER - Deep Sleep Timer */
5842 #define RSIM_DSM_TIMER_DSM_TIMER_MASK            (0xFFFFFFU)
5843 #define RSIM_DSM_TIMER_DSM_TIMER_SHIFT           (0U)
5844 #define RSIM_DSM_TIMER_DSM_TIMER(x)              (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_TIMER_DSM_TIMER_SHIFT)) & RSIM_DSM_TIMER_DSM_TIMER_MASK)
5845 
5846 /*! @name DSM_CONTROL - Deep Sleep Timer Control */
5847 #define RSIM_DSM_CONTROL_DSM_ANT_READY_MASK      (0x1U)
5848 #define RSIM_DSM_CONTROL_DSM_ANT_READY_SHIFT     (0U)
5849 #define RSIM_DSM_CONTROL_DSM_ANT_READY(x)        (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_DSM_ANT_READY_SHIFT)) & RSIM_DSM_CONTROL_DSM_ANT_READY_MASK)
5850 #define RSIM_DSM_CONTROL_ANT_DEEP_SLEEP_STATUS_MASK (0x2U)
5851 #define RSIM_DSM_CONTROL_ANT_DEEP_SLEEP_STATUS_SHIFT (1U)
5852 #define RSIM_DSM_CONTROL_ANT_DEEP_SLEEP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_ANT_DEEP_SLEEP_STATUS_SHIFT)) & RSIM_DSM_CONTROL_ANT_DEEP_SLEEP_STATUS_MASK)
5853 #define RSIM_DSM_CONTROL_DSM_ANT_FINISHED_MASK   (0x4U)
5854 #define RSIM_DSM_CONTROL_DSM_ANT_FINISHED_SHIFT  (2U)
5855 #define RSIM_DSM_CONTROL_DSM_ANT_FINISHED(x)     (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_DSM_ANT_FINISHED_SHIFT)) & RSIM_DSM_CONTROL_DSM_ANT_FINISHED_MASK)
5856 #define RSIM_DSM_CONTROL_ANT_SYSCLK_REQUEST_EN_MASK (0x8U)
5857 #define RSIM_DSM_CONTROL_ANT_SYSCLK_REQUEST_EN_SHIFT (3U)
5858 #define RSIM_DSM_CONTROL_ANT_SYSCLK_REQUEST_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_ANT_SYSCLK_REQUEST_EN_SHIFT)) & RSIM_DSM_CONTROL_ANT_SYSCLK_REQUEST_EN_MASK)
5859 #define RSIM_DSM_CONTROL_ANT_SLEEP_REQUEST_MASK  (0x10U)
5860 #define RSIM_DSM_CONTROL_ANT_SLEEP_REQUEST_SHIFT (4U)
5861 #define RSIM_DSM_CONTROL_ANT_SLEEP_REQUEST(x)    (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_ANT_SLEEP_REQUEST_SHIFT)) & RSIM_DSM_CONTROL_ANT_SLEEP_REQUEST_MASK)
5862 #define RSIM_DSM_CONTROL_ANT_SYSCLK_REQ_MASK     (0x20U)
5863 #define RSIM_DSM_CONTROL_ANT_SYSCLK_REQ_SHIFT    (5U)
5864 #define RSIM_DSM_CONTROL_ANT_SYSCLK_REQ(x)       (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_ANT_SYSCLK_REQ_SHIFT)) & RSIM_DSM_CONTROL_ANT_SYSCLK_REQ_MASK)
5865 #define RSIM_DSM_CONTROL_ANT_SYSCLK_INTERRUPT_EN_MASK (0x40U)
5866 #define RSIM_DSM_CONTROL_ANT_SYSCLK_INTERRUPT_EN_SHIFT (6U)
5867 #define RSIM_DSM_CONTROL_ANT_SYSCLK_INTERRUPT_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_ANT_SYSCLK_INTERRUPT_EN_SHIFT)) & RSIM_DSM_CONTROL_ANT_SYSCLK_INTERRUPT_EN_MASK)
5868 #define RSIM_DSM_CONTROL_ANT_SYSCLK_REQ_INT_MASK (0x80U)
5869 #define RSIM_DSM_CONTROL_ANT_SYSCLK_REQ_INT_SHIFT (7U)
5870 #define RSIM_DSM_CONTROL_ANT_SYSCLK_REQ_INT(x)   (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_ANT_SYSCLK_REQ_INT_SHIFT)) & RSIM_DSM_CONTROL_ANT_SYSCLK_REQ_INT_MASK)
5871 #define RSIM_DSM_CONTROL_DSM_GEN_READY_MASK      (0x100U)
5872 #define RSIM_DSM_CONTROL_DSM_GEN_READY_SHIFT     (8U)
5873 #define RSIM_DSM_CONTROL_DSM_GEN_READY(x)        (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_DSM_GEN_READY_SHIFT)) & RSIM_DSM_CONTROL_DSM_GEN_READY_MASK)
5874 #define RSIM_DSM_CONTROL_GEN_DEEP_SLEEP_STATUS_MASK (0x200U)
5875 #define RSIM_DSM_CONTROL_GEN_DEEP_SLEEP_STATUS_SHIFT (9U)
5876 #define RSIM_DSM_CONTROL_GEN_DEEP_SLEEP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_GEN_DEEP_SLEEP_STATUS_SHIFT)) & RSIM_DSM_CONTROL_GEN_DEEP_SLEEP_STATUS_MASK)
5877 #define RSIM_DSM_CONTROL_DSM_GEN_FINISHED_MASK   (0x400U)
5878 #define RSIM_DSM_CONTROL_DSM_GEN_FINISHED_SHIFT  (10U)
5879 #define RSIM_DSM_CONTROL_DSM_GEN_FINISHED(x)     (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_DSM_GEN_FINISHED_SHIFT)) & RSIM_DSM_CONTROL_DSM_GEN_FINISHED_MASK)
5880 #define RSIM_DSM_CONTROL_GEN_SYSCLK_REQUEST_EN_MASK (0x800U)
5881 #define RSIM_DSM_CONTROL_GEN_SYSCLK_REQUEST_EN_SHIFT (11U)
5882 #define RSIM_DSM_CONTROL_GEN_SYSCLK_REQUEST_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_GEN_SYSCLK_REQUEST_EN_SHIFT)) & RSIM_DSM_CONTROL_GEN_SYSCLK_REQUEST_EN_MASK)
5883 #define RSIM_DSM_CONTROL_GEN_SLEEP_REQUEST_MASK  (0x1000U)
5884 #define RSIM_DSM_CONTROL_GEN_SLEEP_REQUEST_SHIFT (12U)
5885 #define RSIM_DSM_CONTROL_GEN_SLEEP_REQUEST(x)    (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_GEN_SLEEP_REQUEST_SHIFT)) & RSIM_DSM_CONTROL_GEN_SLEEP_REQUEST_MASK)
5886 #define RSIM_DSM_CONTROL_GEN_SYSCLK_REQ_MASK     (0x2000U)
5887 #define RSIM_DSM_CONTROL_GEN_SYSCLK_REQ_SHIFT    (13U)
5888 #define RSIM_DSM_CONTROL_GEN_SYSCLK_REQ(x)       (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_GEN_SYSCLK_REQ_SHIFT)) & RSIM_DSM_CONTROL_GEN_SYSCLK_REQ_MASK)
5889 #define RSIM_DSM_CONTROL_GEN_SYSCLK_INTERRUPT_EN_MASK (0x4000U)
5890 #define RSIM_DSM_CONTROL_GEN_SYSCLK_INTERRUPT_EN_SHIFT (14U)
5891 #define RSIM_DSM_CONTROL_GEN_SYSCLK_INTERRUPT_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_GEN_SYSCLK_INTERRUPT_EN_SHIFT)) & RSIM_DSM_CONTROL_GEN_SYSCLK_INTERRUPT_EN_MASK)
5892 #define RSIM_DSM_CONTROL_GEN_SYSCLK_REQ_INT_MASK (0x8000U)
5893 #define RSIM_DSM_CONTROL_GEN_SYSCLK_REQ_INT_SHIFT (15U)
5894 #define RSIM_DSM_CONTROL_GEN_SYSCLK_REQ_INT(x)   (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_GEN_SYSCLK_REQ_INT_SHIFT)) & RSIM_DSM_CONTROL_GEN_SYSCLK_REQ_INT_MASK)
5895 #define RSIM_DSM_CONTROL_DSM_ZIG_READY_MASK      (0x10000U)
5896 #define RSIM_DSM_CONTROL_DSM_ZIG_READY_SHIFT     (16U)
5897 #define RSIM_DSM_CONTROL_DSM_ZIG_READY(x)        (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_DSM_ZIG_READY_SHIFT)) & RSIM_DSM_CONTROL_DSM_ZIG_READY_MASK)
5898 #define RSIM_DSM_CONTROL_ZIG_DEEP_SLEEP_STATUS_MASK (0x20000U)
5899 #define RSIM_DSM_CONTROL_ZIG_DEEP_SLEEP_STATUS_SHIFT (17U)
5900 #define RSIM_DSM_CONTROL_ZIG_DEEP_SLEEP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_ZIG_DEEP_SLEEP_STATUS_SHIFT)) & RSIM_DSM_CONTROL_ZIG_DEEP_SLEEP_STATUS_MASK)
5901 #define RSIM_DSM_CONTROL_DSM_ZIG_FINISHED_MASK   (0x40000U)
5902 #define RSIM_DSM_CONTROL_DSM_ZIG_FINISHED_SHIFT  (18U)
5903 #define RSIM_DSM_CONTROL_DSM_ZIG_FINISHED(x)     (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_DSM_ZIG_FINISHED_SHIFT)) & RSIM_DSM_CONTROL_DSM_ZIG_FINISHED_MASK)
5904 #define RSIM_DSM_CONTROL_ZIG_SYSCLK_REQUEST_EN_MASK (0x80000U)
5905 #define RSIM_DSM_CONTROL_ZIG_SYSCLK_REQUEST_EN_SHIFT (19U)
5906 #define RSIM_DSM_CONTROL_ZIG_SYSCLK_REQUEST_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_ZIG_SYSCLK_REQUEST_EN_SHIFT)) & RSIM_DSM_CONTROL_ZIG_SYSCLK_REQUEST_EN_MASK)
5907 #define RSIM_DSM_CONTROL_ZIG_SLEEP_REQUEST_MASK  (0x100000U)
5908 #define RSIM_DSM_CONTROL_ZIG_SLEEP_REQUEST_SHIFT (20U)
5909 #define RSIM_DSM_CONTROL_ZIG_SLEEP_REQUEST(x)    (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_ZIG_SLEEP_REQUEST_SHIFT)) & RSIM_DSM_CONTROL_ZIG_SLEEP_REQUEST_MASK)
5910 #define RSIM_DSM_CONTROL_ZIG_SYSCLK_REQ_MASK     (0x200000U)
5911 #define RSIM_DSM_CONTROL_ZIG_SYSCLK_REQ_SHIFT    (21U)
5912 #define RSIM_DSM_CONTROL_ZIG_SYSCLK_REQ(x)       (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_ZIG_SYSCLK_REQ_SHIFT)) & RSIM_DSM_CONTROL_ZIG_SYSCLK_REQ_MASK)
5913 #define RSIM_DSM_CONTROL_ZIG_SYSCLK_INTERRUPT_EN_MASK (0x400000U)
5914 #define RSIM_DSM_CONTROL_ZIG_SYSCLK_INTERRUPT_EN_SHIFT (22U)
5915 #define RSIM_DSM_CONTROL_ZIG_SYSCLK_INTERRUPT_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_ZIG_SYSCLK_INTERRUPT_EN_SHIFT)) & RSIM_DSM_CONTROL_ZIG_SYSCLK_INTERRUPT_EN_MASK)
5916 #define RSIM_DSM_CONTROL_ZIG_SYSCLK_REQ_INT_MASK (0x800000U)
5917 #define RSIM_DSM_CONTROL_ZIG_SYSCLK_REQ_INT_SHIFT (23U)
5918 #define RSIM_DSM_CONTROL_ZIG_SYSCLK_REQ_INT(x)   (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_ZIG_SYSCLK_REQ_INT_SHIFT)) & RSIM_DSM_CONTROL_ZIG_SYSCLK_REQ_INT_MASK)
5919 #define RSIM_DSM_CONTROL_DSM_TIMER_CLR_MASK      (0x8000000U)
5920 #define RSIM_DSM_CONTROL_DSM_TIMER_CLR_SHIFT     (27U)
5921 #define RSIM_DSM_CONTROL_DSM_TIMER_CLR(x)        (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_DSM_TIMER_CLR_SHIFT)) & RSIM_DSM_CONTROL_DSM_TIMER_CLR_MASK)
5922 #define RSIM_DSM_CONTROL_DSM_TIMER_EN_MASK       (0x80000000U)
5923 #define RSIM_DSM_CONTROL_DSM_TIMER_EN_SHIFT      (31U)
5924 #define RSIM_DSM_CONTROL_DSM_TIMER_EN(x)         (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_DSM_TIMER_EN_SHIFT)) & RSIM_DSM_CONTROL_DSM_TIMER_EN_MASK)
5925 
5926 /*! @name DSM_OSC_OFFSET - Deep Sleep Wakeup Time Offset */
5927 #define RSIM_DSM_OSC_OFFSET_DSM_OSC_STABILIZE_TIME_MASK (0x3FFU)
5928 #define RSIM_DSM_OSC_OFFSET_DSM_OSC_STABILIZE_TIME_SHIFT (0U)
5929 #define RSIM_DSM_OSC_OFFSET_DSM_OSC_STABILIZE_TIME(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_OSC_OFFSET_DSM_OSC_STABILIZE_TIME_SHIFT)) & RSIM_DSM_OSC_OFFSET_DSM_OSC_STABILIZE_TIME_MASK)
5930 
5931 /*! @name ANT_SLEEP - ANT Link Layer Sleep Time */
5932 #define RSIM_ANT_SLEEP_ANT_SLEEP_TIME_MASK       (0xFFFFFFU)
5933 #define RSIM_ANT_SLEEP_ANT_SLEEP_TIME_SHIFT      (0U)
5934 #define RSIM_ANT_SLEEP_ANT_SLEEP_TIME(x)         (((uint32_t)(((uint32_t)(x)) << RSIM_ANT_SLEEP_ANT_SLEEP_TIME_SHIFT)) & RSIM_ANT_SLEEP_ANT_SLEEP_TIME_MASK)
5935 
5936 /*! @name ANT_WAKE - ANT Link Layer Wake Time */
5937 #define RSIM_ANT_WAKE_ANT_WAKE_TIME_MASK         (0xFFFFFFU)
5938 #define RSIM_ANT_WAKE_ANT_WAKE_TIME_SHIFT        (0U)
5939 #define RSIM_ANT_WAKE_ANT_WAKE_TIME(x)           (((uint32_t)(((uint32_t)(x)) << RSIM_ANT_WAKE_ANT_WAKE_TIME_SHIFT)) & RSIM_ANT_WAKE_ANT_WAKE_TIME_MASK)
5940 
5941 /*! @name ZIG_SLEEP - 802.15.4 Link Layer Sleep Time */
5942 #define RSIM_ZIG_SLEEP_ZIG_SLEEP_TIME_MASK       (0xFFFFFFU)
5943 #define RSIM_ZIG_SLEEP_ZIG_SLEEP_TIME_SHIFT      (0U)
5944 #define RSIM_ZIG_SLEEP_ZIG_SLEEP_TIME(x)         (((uint32_t)(((uint32_t)(x)) << RSIM_ZIG_SLEEP_ZIG_SLEEP_TIME_SHIFT)) & RSIM_ZIG_SLEEP_ZIG_SLEEP_TIME_MASK)
5945 
5946 /*! @name ZIG_WAKE - 802.15.4 Link Layer Wake Time */
5947 #define RSIM_ZIG_WAKE_ZIG_WAKE_TIME_MASK         (0xFFFFFFU)
5948 #define RSIM_ZIG_WAKE_ZIG_WAKE_TIME_SHIFT        (0U)
5949 #define RSIM_ZIG_WAKE_ZIG_WAKE_TIME(x)           (((uint32_t)(((uint32_t)(x)) << RSIM_ZIG_WAKE_ZIG_WAKE_TIME_SHIFT)) & RSIM_ZIG_WAKE_ZIG_WAKE_TIME_MASK)
5950 
5951 /*! @name GEN_SLEEP - Generic FSK Link Layer Sleep Time */
5952 #define RSIM_GEN_SLEEP_GEN_SLEEP_TIME_MASK       (0xFFFFFFU)
5953 #define RSIM_GEN_SLEEP_GEN_SLEEP_TIME_SHIFT      (0U)
5954 #define RSIM_GEN_SLEEP_GEN_SLEEP_TIME(x)         (((uint32_t)(((uint32_t)(x)) << RSIM_GEN_SLEEP_GEN_SLEEP_TIME_SHIFT)) & RSIM_GEN_SLEEP_GEN_SLEEP_TIME_MASK)
5955 
5956 /*! @name GEN_WAKE - Generic FSK Link Layer Wake Time */
5957 #define RSIM_GEN_WAKE_GEN_WAKE_TIME_MASK         (0xFFFFFFU)
5958 #define RSIM_GEN_WAKE_GEN_WAKE_TIME_SHIFT        (0U)
5959 #define RSIM_GEN_WAKE_GEN_WAKE_TIME(x)           (((uint32_t)(((uint32_t)(x)) << RSIM_GEN_WAKE_GEN_WAKE_TIME_SHIFT)) & RSIM_GEN_WAKE_GEN_WAKE_TIME_MASK)
5960 
5961 /*! @name RF_OSC_CTRL - Radio Oscillator Control */
5962 #define RSIM_RF_OSC_CTRL_BB_XTAL_ALC_COUNT_SEL_MASK (0x3U)
5963 #define RSIM_RF_OSC_CTRL_BB_XTAL_ALC_COUNT_SEL_SHIFT (0U)
5964 #define RSIM_RF_OSC_CTRL_BB_XTAL_ALC_COUNT_SEL(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_ALC_COUNT_SEL_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_ALC_COUNT_SEL_MASK)
5965 #define RSIM_RF_OSC_CTRL_BB_XTAL_ALC_ON_MASK     (0x4U)
5966 #define RSIM_RF_OSC_CTRL_BB_XTAL_ALC_ON_SHIFT    (2U)
5967 #define RSIM_RF_OSC_CTRL_BB_XTAL_ALC_ON(x)       (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_ALC_ON_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_ALC_ON_MASK)
5968 #define RSIM_RF_OSC_CTRL_RF_OSC_BYPASS_EN_MASK   (0x8U)
5969 #define RSIM_RF_OSC_CTRL_RF_OSC_BYPASS_EN_SHIFT  (3U)
5970 #define RSIM_RF_OSC_CTRL_RF_OSC_BYPASS_EN(x)     (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_RF_OSC_BYPASS_EN_SHIFT)) & RSIM_RF_OSC_CTRL_RF_OSC_BYPASS_EN_MASK)
5971 #define RSIM_RF_OSC_CTRL_BB_XTAL_COMP_BIAS_MASK  (0x1F0U)
5972 #define RSIM_RF_OSC_CTRL_BB_XTAL_COMP_BIAS_SHIFT (4U)
5973 #define RSIM_RF_OSC_CTRL_BB_XTAL_COMP_BIAS(x)    (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_COMP_BIAS_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_COMP_BIAS_MASK)
5974 #define RSIM_RF_OSC_CTRL_BB_XTAL_DC_COUP_MODE_EN_MASK (0x200U)
5975 #define RSIM_RF_OSC_CTRL_BB_XTAL_DC_COUP_MODE_EN_SHIFT (9U)
5976 #define RSIM_RF_OSC_CTRL_BB_XTAL_DC_COUP_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_DC_COUP_MODE_EN_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_DC_COUP_MODE_EN_MASK)
5977 #define RSIM_RF_OSC_CTRL_BB_XTAL_DIAGSEL_MASK    (0x400U)
5978 #define RSIM_RF_OSC_CTRL_BB_XTAL_DIAGSEL_SHIFT   (10U)
5979 #define RSIM_RF_OSC_CTRL_BB_XTAL_DIAGSEL(x)      (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_DIAGSEL_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_DIAGSEL_MASK)
5980 #define RSIM_RF_OSC_CTRL_BB_XTAL_DIG_CLK_ON_MASK (0x800U)
5981 #define RSIM_RF_OSC_CTRL_BB_XTAL_DIG_CLK_ON_SHIFT (11U)
5982 #define RSIM_RF_OSC_CTRL_BB_XTAL_DIG_CLK_ON(x)   (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_DIG_CLK_ON_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_DIG_CLK_ON_MASK)
5983 #define RSIM_RF_OSC_CTRL_BB_XTAL_GM_MASK         (0x1F000U)
5984 #define RSIM_RF_OSC_CTRL_BB_XTAL_GM_SHIFT        (12U)
5985 #define RSIM_RF_OSC_CTRL_BB_XTAL_GM(x)           (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_GM_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_GM_MASK)
5986 #define RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD_MASK    (0x20000U)
5987 #define RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD_SHIFT   (17U)
5988 #define RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD(x)      (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD_MASK)
5989 #define RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD_ON_MASK (0x40000U)
5990 #define RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD_ON_SHIFT (18U)
5991 #define RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD_ON(x)   (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD_ON_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD_ON_MASK)
5992 #define RSIM_RF_OSC_CTRL_BB_XTAL_READY_COUNT_SEL_MASK (0x300000U)
5993 #define RSIM_RF_OSC_CTRL_BB_XTAL_READY_COUNT_SEL_SHIFT (20U)
5994 #define RSIM_RF_OSC_CTRL_BB_XTAL_READY_COUNT_SEL(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_READY_COUNT_SEL_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_READY_COUNT_SEL_MASK)
5995 #define RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_RF_EN_SEL_MASK (0x8000000U)
5996 #define RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_RF_EN_SEL_SHIFT (27U)
5997 #define RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_RF_EN_SEL(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_RF_EN_SEL_SHIFT)) & RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_RF_EN_SEL_MASK)
5998 #define RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_MASK (0x10000000U)
5999 #define RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_SHIFT (28U)
6000 #define RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD(x)   (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_SHIFT)) & RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_MASK)
6001 #define RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_EN_MASK (0x20000000U)
6002 #define RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_EN_SHIFT (29U)
6003 #define RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_EN_SHIFT)) & RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_EN_MASK)
6004 #define RSIM_RF_OSC_CTRL_RADIO_RF_ABORT_OVRD_MASK (0x40000000U)
6005 #define RSIM_RF_OSC_CTRL_RADIO_RF_ABORT_OVRD_SHIFT (30U)
6006 #define RSIM_RF_OSC_CTRL_RADIO_RF_ABORT_OVRD(x)  (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_RADIO_RF_ABORT_OVRD_SHIFT)) & RSIM_RF_OSC_CTRL_RADIO_RF_ABORT_OVRD_MASK)
6007 #define RSIM_RF_OSC_CTRL_RADIO_RF_ABORT_OVRD_EN_MASK (0x80000000U)
6008 #define RSIM_RF_OSC_CTRL_RADIO_RF_ABORT_OVRD_EN_SHIFT (31U)
6009 #define RSIM_RF_OSC_CTRL_RADIO_RF_ABORT_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_RADIO_RF_ABORT_OVRD_EN_SHIFT)) & RSIM_RF_OSC_CTRL_RADIO_RF_ABORT_OVRD_EN_MASK)
6010 
6011 /*! @name ANA_TEST - Radio Analog Test Registers */
6012 #define RSIM_ANA_TEST_BB_LDO_LS_BYP_MASK         (0x1U)
6013 #define RSIM_ANA_TEST_BB_LDO_LS_BYP_SHIFT        (0U)
6014 #define RSIM_ANA_TEST_BB_LDO_LS_BYP(x)           (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TEST_BB_LDO_LS_BYP_SHIFT)) & RSIM_ANA_TEST_BB_LDO_LS_BYP_MASK)
6015 #define RSIM_ANA_TEST_BB_LDO_LS_DIAGSEL_MASK     (0x2U)
6016 #define RSIM_ANA_TEST_BB_LDO_LS_DIAGSEL_SHIFT    (1U)
6017 #define RSIM_ANA_TEST_BB_LDO_LS_DIAGSEL(x)       (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TEST_BB_LDO_LS_DIAGSEL_SHIFT)) & RSIM_ANA_TEST_BB_LDO_LS_DIAGSEL_MASK)
6018 #define RSIM_ANA_TEST_BB_LDO_XO_BYP_ON_MASK      (0x4U)
6019 #define RSIM_ANA_TEST_BB_LDO_XO_BYP_ON_SHIFT     (2U)
6020 #define RSIM_ANA_TEST_BB_LDO_XO_BYP_ON(x)        (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TEST_BB_LDO_XO_BYP_ON_SHIFT)) & RSIM_ANA_TEST_BB_LDO_XO_BYP_ON_MASK)
6021 #define RSIM_ANA_TEST_BB_LDO_XO_DIAGSEL_MASK     (0x8U)
6022 #define RSIM_ANA_TEST_BB_LDO_XO_DIAGSEL_SHIFT    (3U)
6023 #define RSIM_ANA_TEST_BB_LDO_XO_DIAGSEL(x)       (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TEST_BB_LDO_XO_DIAGSEL_SHIFT)) & RSIM_ANA_TEST_BB_LDO_XO_DIAGSEL_MASK)
6024 #define RSIM_ANA_TEST_BB_XTAL_TEST_MASK          (0x10U)
6025 #define RSIM_ANA_TEST_BB_XTAL_TEST_SHIFT         (4U)
6026 #define RSIM_ANA_TEST_BB_XTAL_TEST(x)            (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TEST_BB_XTAL_TEST_SHIFT)) & RSIM_ANA_TEST_BB_XTAL_TEST_MASK)
6027 #define RSIM_ANA_TEST_BG_DIAGBUF_MASK            (0x20U)
6028 #define RSIM_ANA_TEST_BG_DIAGBUF_SHIFT           (5U)
6029 #define RSIM_ANA_TEST_BG_DIAGBUF(x)              (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TEST_BG_DIAGBUF_SHIFT)) & RSIM_ANA_TEST_BG_DIAGBUF_MASK)
6030 #define RSIM_ANA_TEST_BG_DIAGSEL_MASK            (0x40U)
6031 #define RSIM_ANA_TEST_BG_DIAGSEL_SHIFT           (6U)
6032 #define RSIM_ANA_TEST_BG_DIAGSEL(x)              (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TEST_BG_DIAGSEL_SHIFT)) & RSIM_ANA_TEST_BG_DIAGSEL_MASK)
6033 #define RSIM_ANA_TEST_BG_STARTUPFORCE_MASK       (0x80U)
6034 #define RSIM_ANA_TEST_BG_STARTUPFORCE_SHIFT      (7U)
6035 #define RSIM_ANA_TEST_BG_STARTUPFORCE(x)         (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TEST_BG_STARTUPFORCE_SHIFT)) & RSIM_ANA_TEST_BG_STARTUPFORCE_MASK)
6036 #define RSIM_ANA_TEST_DIAG_1234_ON_MASK          (0x100U)
6037 #define RSIM_ANA_TEST_DIAG_1234_ON_SHIFT         (8U)
6038 #define RSIM_ANA_TEST_DIAG_1234_ON(x)            (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TEST_DIAG_1234_ON_SHIFT)) & RSIM_ANA_TEST_DIAG_1234_ON_MASK)
6039 #define RSIM_ANA_TEST_DIAG2SOCADC_DEC_MASK       (0x600U)
6040 #define RSIM_ANA_TEST_DIAG2SOCADC_DEC_SHIFT      (9U)
6041 #define RSIM_ANA_TEST_DIAG2SOCADC_DEC(x)         (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TEST_DIAG2SOCADC_DEC_SHIFT)) & RSIM_ANA_TEST_DIAG2SOCADC_DEC_MASK)
6042 #define RSIM_ANA_TEST_DIAG2SOCADC_DEC_ON_MASK    (0x800U)
6043 #define RSIM_ANA_TEST_DIAG2SOCADC_DEC_ON_SHIFT   (11U)
6044 #define RSIM_ANA_TEST_DIAG2SOCADC_DEC_ON(x)      (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TEST_DIAG2SOCADC_DEC_ON_SHIFT)) & RSIM_ANA_TEST_DIAG2SOCADC_DEC_ON_MASK)
6045 #define RSIM_ANA_TEST_DIAGCODE_MASK              (0x7000U)
6046 #define RSIM_ANA_TEST_DIAGCODE_SHIFT             (12U)
6047 #define RSIM_ANA_TEST_DIAGCODE(x)                (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TEST_DIAGCODE_SHIFT)) & RSIM_ANA_TEST_DIAGCODE_MASK)
6048 
6049 /*! @name ANA_TRIM - Radio Analog Trim Registers */
6050 #define RSIM_ANA_TRIM_BB_LDO_LS_SPARE_MASK       (0x3U)
6051 #define RSIM_ANA_TRIM_BB_LDO_LS_SPARE_SHIFT      (0U)
6052 #define RSIM_ANA_TRIM_BB_LDO_LS_SPARE(x)         (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TRIM_BB_LDO_LS_SPARE_SHIFT)) & RSIM_ANA_TRIM_BB_LDO_LS_SPARE_MASK)
6053 #define RSIM_ANA_TRIM_BB_LDO_LS_TRIM_MASK        (0x38U)
6054 #define RSIM_ANA_TRIM_BB_LDO_LS_TRIM_SHIFT       (3U)
6055 #define RSIM_ANA_TRIM_BB_LDO_LS_TRIM(x)          (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TRIM_BB_LDO_LS_TRIM_SHIFT)) & RSIM_ANA_TRIM_BB_LDO_LS_TRIM_MASK)
6056 #define RSIM_ANA_TRIM_BB_LDO_XO_SPARE_MASK       (0xC0U)
6057 #define RSIM_ANA_TRIM_BB_LDO_XO_SPARE_SHIFT      (6U)
6058 #define RSIM_ANA_TRIM_BB_LDO_XO_SPARE(x)         (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TRIM_BB_LDO_XO_SPARE_SHIFT)) & RSIM_ANA_TRIM_BB_LDO_XO_SPARE_MASK)
6059 #define RSIM_ANA_TRIM_BB_LDO_XO_TRIM_MASK        (0x700U)
6060 #define RSIM_ANA_TRIM_BB_LDO_XO_TRIM_SHIFT       (8U)
6061 #define RSIM_ANA_TRIM_BB_LDO_XO_TRIM(x)          (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TRIM_BB_LDO_XO_TRIM_SHIFT)) & RSIM_ANA_TRIM_BB_LDO_XO_TRIM_MASK)
6062 #define RSIM_ANA_TRIM_BB_XTAL_SPARE_MASK         (0xF800U)
6063 #define RSIM_ANA_TRIM_BB_XTAL_SPARE_SHIFT        (11U)
6064 #define RSIM_ANA_TRIM_BB_XTAL_SPARE(x)           (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TRIM_BB_XTAL_SPARE_SHIFT)) & RSIM_ANA_TRIM_BB_XTAL_SPARE_MASK)
6065 #define RSIM_ANA_TRIM_BB_XTAL_TRIM_MASK          (0xFF0000U)
6066 #define RSIM_ANA_TRIM_BB_XTAL_TRIM_SHIFT         (16U)
6067 #define RSIM_ANA_TRIM_BB_XTAL_TRIM(x)            (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TRIM_BB_XTAL_TRIM_SHIFT)) & RSIM_ANA_TRIM_BB_XTAL_TRIM_MASK)
6068 #define RSIM_ANA_TRIM_BG_1V_TRIM_MASK            (0xF000000U)
6069 #define RSIM_ANA_TRIM_BG_1V_TRIM_SHIFT           (24U)
6070 #define RSIM_ANA_TRIM_BG_1V_TRIM(x)              (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TRIM_BG_1V_TRIM_SHIFT)) & RSIM_ANA_TRIM_BG_1V_TRIM_MASK)
6071 #define RSIM_ANA_TRIM_BG_IBIAS_5U_TRIM_MASK      (0xF0000000U)
6072 #define RSIM_ANA_TRIM_BG_IBIAS_5U_TRIM_SHIFT     (28U)
6073 #define RSIM_ANA_TRIM_BG_IBIAS_5U_TRIM(x)        (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TRIM_BG_IBIAS_5U_TRIM_SHIFT)) & RSIM_ANA_TRIM_BG_IBIAS_5U_TRIM_MASK)
6074 
6075 
6076 /*!
6077  * @}
6078  */ /* end of group RSIM_Register_Masks */
6079 
6080 
6081 /* RSIM - Peripheral instance base addresses */
6082 /** Peripheral RSIM base address */
6083 #define RSIM_BASE                                (0x40059000u)
6084 /** Peripheral RSIM base pointer */
6085 #define RSIM                                     ((RSIM_Type *)RSIM_BASE)
6086 /** Array initializer of RSIM peripheral base addresses */
6087 #define RSIM_BASE_ADDRS                          { RSIM_BASE }
6088 /** Array initializer of RSIM peripheral base pointers */
6089 #define RSIM_BASE_PTRS                           { RSIM }
6090 
6091 /*!
6092  * @}
6093  */ /* end of group RSIM_Peripheral_Access_Layer */
6094 
6095 
6096 /* ----------------------------------------------------------------------------
6097    -- RTC Peripheral Access Layer
6098    ---------------------------------------------------------------------------- */
6099 
6100 /*!
6101  * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
6102  * @{
6103  */
6104 
6105 /** RTC - Register Layout Typedef */
6106 typedef struct {
6107   __IO uint32_t TSR;                               /**< RTC Time Seconds Register, offset: 0x0 */
6108   __IO uint32_t TPR;                               /**< RTC Time Prescaler Register, offset: 0x4 */
6109   __IO uint32_t TAR;                               /**< RTC Time Alarm Register, offset: 0x8 */
6110   __IO uint32_t TCR;                               /**< RTC Time Compensation Register, offset: 0xC */
6111   __IO uint32_t CR;                                /**< RTC Control Register, offset: 0x10 */
6112   __IO uint32_t SR;                                /**< RTC Status Register, offset: 0x14 */
6113   __IO uint32_t LR;                                /**< RTC Lock Register, offset: 0x18 */
6114   __IO uint32_t IER;                               /**< RTC Interrupt Enable Register, offset: 0x1C */
6115 } RTC_Type;
6116 
6117 /* ----------------------------------------------------------------------------
6118    -- RTC Register Masks
6119    ---------------------------------------------------------------------------- */
6120 
6121 /*!
6122  * @addtogroup RTC_Register_Masks RTC Register Masks
6123  * @{
6124  */
6125 
6126 /*! @name TSR - RTC Time Seconds Register */
6127 #define RTC_TSR_TSR_MASK                         (0xFFFFFFFFU)
6128 #define RTC_TSR_TSR_SHIFT                        (0U)
6129 #define RTC_TSR_TSR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK)
6130 
6131 /*! @name TPR - RTC Time Prescaler Register */
6132 #define RTC_TPR_TPR_MASK                         (0xFFFFU)
6133 #define RTC_TPR_TPR_SHIFT                        (0U)
6134 #define RTC_TPR_TPR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK)
6135 
6136 /*! @name TAR - RTC Time Alarm Register */
6137 #define RTC_TAR_TAR_MASK                         (0xFFFFFFFFU)
6138 #define RTC_TAR_TAR_SHIFT                        (0U)
6139 #define RTC_TAR_TAR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK)
6140 
6141 /*! @name TCR - RTC Time Compensation Register */
6142 #define RTC_TCR_TCR_MASK                         (0xFFU)
6143 #define RTC_TCR_TCR_SHIFT                        (0U)
6144 #define RTC_TCR_TCR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK)
6145 #define RTC_TCR_CIR_MASK                         (0xFF00U)
6146 #define RTC_TCR_CIR_SHIFT                        (8U)
6147 #define RTC_TCR_CIR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK)
6148 #define RTC_TCR_TCV_MASK                         (0xFF0000U)
6149 #define RTC_TCR_TCV_SHIFT                        (16U)
6150 #define RTC_TCR_TCV(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK)
6151 #define RTC_TCR_CIC_MASK                         (0xFF000000U)
6152 #define RTC_TCR_CIC_SHIFT                        (24U)
6153 #define RTC_TCR_CIC(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK)
6154 
6155 /*! @name CR - RTC Control Register */
6156 #define RTC_CR_SWR_MASK                          (0x1U)
6157 #define RTC_CR_SWR_SHIFT                         (0U)
6158 #define RTC_CR_SWR(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK)
6159 #define RTC_CR_WPE_MASK                          (0x2U)
6160 #define RTC_CR_WPE_SHIFT                         (1U)
6161 #define RTC_CR_WPE(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK)
6162 #define RTC_CR_SUP_MASK                          (0x4U)
6163 #define RTC_CR_SUP_SHIFT                         (2U)
6164 #define RTC_CR_SUP(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK)
6165 #define RTC_CR_UM_MASK                           (0x8U)
6166 #define RTC_CR_UM_SHIFT                          (3U)
6167 #define RTC_CR_UM(x)                             (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK)
6168 #define RTC_CR_WPS_MASK                          (0x10U)
6169 #define RTC_CR_WPS_SHIFT                         (4U)
6170 #define RTC_CR_WPS(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPS_SHIFT)) & RTC_CR_WPS_MASK)
6171 #define RTC_CR_OSCE_MASK                         (0x100U)
6172 #define RTC_CR_OSCE_SHIFT                        (8U)
6173 #define RTC_CR_OSCE(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK)
6174 #define RTC_CR_CLKO_MASK                         (0x200U)
6175 #define RTC_CR_CLKO_SHIFT                        (9U)
6176 #define RTC_CR_CLKO(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK)
6177 #define RTC_CR_SC16P_MASK                        (0x400U)
6178 #define RTC_CR_SC16P_SHIFT                       (10U)
6179 #define RTC_CR_SC16P(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK)
6180 #define RTC_CR_SC8P_MASK                         (0x800U)
6181 #define RTC_CR_SC8P_SHIFT                        (11U)
6182 #define RTC_CR_SC8P(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK)
6183 #define RTC_CR_SC4P_MASK                         (0x1000U)
6184 #define RTC_CR_SC4P_SHIFT                        (12U)
6185 #define RTC_CR_SC4P(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK)
6186 #define RTC_CR_SC2P_MASK                         (0x2000U)
6187 #define RTC_CR_SC2P_SHIFT                        (13U)
6188 #define RTC_CR_SC2P(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK)
6189 
6190 /*! @name SR - RTC Status Register */
6191 #define RTC_SR_TIF_MASK                          (0x1U)
6192 #define RTC_SR_TIF_SHIFT                         (0U)
6193 #define RTC_SR_TIF(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK)
6194 #define RTC_SR_TOF_MASK                          (0x2U)
6195 #define RTC_SR_TOF_SHIFT                         (1U)
6196 #define RTC_SR_TOF(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK)
6197 #define RTC_SR_TAF_MASK                          (0x4U)
6198 #define RTC_SR_TAF_SHIFT                         (2U)
6199 #define RTC_SR_TAF(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK)
6200 #define RTC_SR_TCE_MASK                          (0x10U)
6201 #define RTC_SR_TCE_SHIFT                         (4U)
6202 #define RTC_SR_TCE(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK)
6203 
6204 /*! @name LR - RTC Lock Register */
6205 #define RTC_LR_TCL_MASK                          (0x8U)
6206 #define RTC_LR_TCL_SHIFT                         (3U)
6207 #define RTC_LR_TCL(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK)
6208 #define RTC_LR_CRL_MASK                          (0x10U)
6209 #define RTC_LR_CRL_SHIFT                         (4U)
6210 #define RTC_LR_CRL(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK)
6211 #define RTC_LR_SRL_MASK                          (0x20U)
6212 #define RTC_LR_SRL_SHIFT                         (5U)
6213 #define RTC_LR_SRL(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK)
6214 #define RTC_LR_LRL_MASK                          (0x40U)
6215 #define RTC_LR_LRL_SHIFT                         (6U)
6216 #define RTC_LR_LRL(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK)
6217 
6218 /*! @name IER - RTC Interrupt Enable Register */
6219 #define RTC_IER_TIIE_MASK                        (0x1U)
6220 #define RTC_IER_TIIE_SHIFT                       (0U)
6221 #define RTC_IER_TIIE(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK)
6222 #define RTC_IER_TOIE_MASK                        (0x2U)
6223 #define RTC_IER_TOIE_SHIFT                       (1U)
6224 #define RTC_IER_TOIE(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK)
6225 #define RTC_IER_TAIE_MASK                        (0x4U)
6226 #define RTC_IER_TAIE_SHIFT                       (2U)
6227 #define RTC_IER_TAIE(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK)
6228 #define RTC_IER_TSIE_MASK                        (0x10U)
6229 #define RTC_IER_TSIE_SHIFT                       (4U)
6230 #define RTC_IER_TSIE(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK)
6231 #define RTC_IER_WPON_MASK                        (0x80U)
6232 #define RTC_IER_WPON_SHIFT                       (7U)
6233 #define RTC_IER_WPON(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK)
6234 
6235 
6236 /*!
6237  * @}
6238  */ /* end of group RTC_Register_Masks */
6239 
6240 
6241 /* RTC - Peripheral instance base addresses */
6242 /** Peripheral RTC base address */
6243 #define RTC_BASE                                 (0x4003D000u)
6244 /** Peripheral RTC base pointer */
6245 #define RTC                                      ((RTC_Type *)RTC_BASE)
6246 /** Array initializer of RTC peripheral base addresses */
6247 #define RTC_BASE_ADDRS                           { RTC_BASE }
6248 /** Array initializer of RTC peripheral base pointers */
6249 #define RTC_BASE_PTRS                            { RTC }
6250 /** Interrupt vectors for the RTC peripheral type */
6251 #define RTC_IRQS                                 { RTC_IRQn }
6252 #define RTC_SECONDS_IRQS                         { RTC_Seconds_IRQn }
6253 
6254 /*!
6255  * @}
6256  */ /* end of group RTC_Peripheral_Access_Layer */
6257 
6258 
6259 /* ----------------------------------------------------------------------------
6260    -- SIM Peripheral Access Layer
6261    ---------------------------------------------------------------------------- */
6262 
6263 /*!
6264  * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
6265  * @{
6266  */
6267 
6268 /** SIM - Register Layout Typedef */
6269 typedef struct {
6270   __IO uint32_t SOPT1;                             /**< System Options Register 1, offset: 0x0 */
6271        uint8_t RESERVED_0[4096];
6272   __IO uint32_t SOPT2;                             /**< System Options Register 2, offset: 0x1004 */
6273        uint8_t RESERVED_1[4];
6274   __IO uint32_t SOPT4;                             /**< System Options Register 4, offset: 0x100C */
6275   __IO uint32_t SOPT5;                             /**< System Options Register 5, offset: 0x1010 */
6276        uint8_t RESERVED_2[4];
6277   __IO uint32_t SOPT7;                             /**< System Options Register 7, offset: 0x1018 */
6278        uint8_t RESERVED_3[8];
6279   __I  uint32_t SDID;                              /**< System Device Identification Register, offset: 0x1024 */
6280        uint8_t RESERVED_4[12];
6281   __IO uint32_t SCGC4;                             /**< System Clock Gating Control Register 4, offset: 0x1034 */
6282   __IO uint32_t SCGC5;                             /**< System Clock Gating Control Register 5, offset: 0x1038 */
6283   __IO uint32_t SCGC6;                             /**< System Clock Gating Control Register 6, offset: 0x103C */
6284   __IO uint32_t SCGC7;                             /**< System Clock Gating Control Register 7, offset: 0x1040 */
6285   __IO uint32_t CLKDIV1;                           /**< System Clock Divider Register 1, offset: 0x1044 */
6286        uint8_t RESERVED_5[4];
6287   __IO uint32_t FCFG1;                             /**< Flash Configuration Register 1, offset: 0x104C */
6288   __I  uint32_t FCFG2;                             /**< Flash Configuration Register 2, offset: 0x1050 */
6289        uint8_t RESERVED_6[4];
6290   __I  uint32_t UIDMH;                             /**< Unique Identification Register Mid-High, offset: 0x1058 */
6291   __I  uint32_t UIDML;                             /**< Unique Identification Register Mid Low, offset: 0x105C */
6292   __I  uint32_t UIDL;                              /**< Unique Identification Register Low, offset: 0x1060 */
6293        uint8_t RESERVED_7[156];
6294   __IO uint32_t COPC;                              /**< COP Control Register, offset: 0x1100 */
6295   __O  uint32_t SRVCOP;                            /**< Service COP, offset: 0x1104 */
6296 } SIM_Type;
6297 
6298 /* ----------------------------------------------------------------------------
6299    -- SIM Register Masks
6300    ---------------------------------------------------------------------------- */
6301 
6302 /*!
6303  * @addtogroup SIM_Register_Masks SIM Register Masks
6304  * @{
6305  */
6306 
6307 /*! @name SOPT1 - System Options Register 1 */
6308 #define SIM_SOPT1_OSC32KOUT_MASK                 (0x30000U)
6309 #define SIM_SOPT1_OSC32KOUT_SHIFT                (16U)
6310 #define SIM_SOPT1_OSC32KOUT(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KOUT_SHIFT)) & SIM_SOPT1_OSC32KOUT_MASK)
6311 #define SIM_SOPT1_OSC32KSEL_MASK                 (0xC0000U)
6312 #define SIM_SOPT1_OSC32KSEL_SHIFT                (18U)
6313 #define SIM_SOPT1_OSC32KSEL(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK)
6314 
6315 /*! @name SOPT2 - System Options Register 2 */
6316 #define SIM_SOPT2_CLKOUTSEL_MASK                 (0xE0U)
6317 #define SIM_SOPT2_CLKOUTSEL_SHIFT                (5U)
6318 #define SIM_SOPT2_CLKOUTSEL(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK)
6319 #define SIM_SOPT2_TPMSRC_MASK                    (0x3000000U)
6320 #define SIM_SOPT2_TPMSRC_SHIFT                   (24U)
6321 #define SIM_SOPT2_TPMSRC(x)                      (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TPMSRC_SHIFT)) & SIM_SOPT2_TPMSRC_MASK)
6322 #define SIM_SOPT2_LPUART0SRC_MASK                (0xC000000U)
6323 #define SIM_SOPT2_LPUART0SRC_SHIFT               (26U)
6324 #define SIM_SOPT2_LPUART0SRC(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_LPUART0SRC_SHIFT)) & SIM_SOPT2_LPUART0SRC_MASK)
6325 
6326 /*! @name SOPT4 - System Options Register 4 */
6327 #define SIM_SOPT4_TPM1CH0SRC_MASK                (0x40000U)
6328 #define SIM_SOPT4_TPM1CH0SRC_SHIFT               (18U)
6329 #define SIM_SOPT4_TPM1CH0SRC(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM1CH0SRC_SHIFT)) & SIM_SOPT4_TPM1CH0SRC_MASK)
6330 #define SIM_SOPT4_TPM2CH0SRC_MASK                (0x100000U)
6331 #define SIM_SOPT4_TPM2CH0SRC_SHIFT               (20U)
6332 #define SIM_SOPT4_TPM2CH0SRC(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM2CH0SRC_SHIFT)) & SIM_SOPT4_TPM2CH0SRC_MASK)
6333 #define SIM_SOPT4_TPM0CLKSEL_MASK                (0x1000000U)
6334 #define SIM_SOPT4_TPM0CLKSEL_SHIFT               (24U)
6335 #define SIM_SOPT4_TPM0CLKSEL(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM0CLKSEL_SHIFT)) & SIM_SOPT4_TPM0CLKSEL_MASK)
6336 #define SIM_SOPT4_TPM1CLKSEL_MASK                (0x2000000U)
6337 #define SIM_SOPT4_TPM1CLKSEL_SHIFT               (25U)
6338 #define SIM_SOPT4_TPM1CLKSEL(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM1CLKSEL_SHIFT)) & SIM_SOPT4_TPM1CLKSEL_MASK)
6339 #define SIM_SOPT4_TPM2CLKSEL_MASK                (0x4000000U)
6340 #define SIM_SOPT4_TPM2CLKSEL_SHIFT               (26U)
6341 #define SIM_SOPT4_TPM2CLKSEL(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM2CLKSEL_SHIFT)) & SIM_SOPT4_TPM2CLKSEL_MASK)
6342 
6343 /*! @name SOPT5 - System Options Register 5 */
6344 #define SIM_SOPT5_LPUART0TXSRC_MASK              (0x3U)
6345 #define SIM_SOPT5_LPUART0TXSRC_SHIFT             (0U)
6346 #define SIM_SOPT5_LPUART0TXSRC(x)                (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0TXSRC_SHIFT)) & SIM_SOPT5_LPUART0TXSRC_MASK)
6347 #define SIM_SOPT5_LPUART0RXSRC_MASK              (0x4U)
6348 #define SIM_SOPT5_LPUART0RXSRC_SHIFT             (2U)
6349 #define SIM_SOPT5_LPUART0RXSRC(x)                (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0RXSRC_SHIFT)) & SIM_SOPT5_LPUART0RXSRC_MASK)
6350 #define SIM_SOPT5_LPUART0ODE_MASK                (0x10000U)
6351 #define SIM_SOPT5_LPUART0ODE_SHIFT               (16U)
6352 #define SIM_SOPT5_LPUART0ODE(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0ODE_SHIFT)) & SIM_SOPT5_LPUART0ODE_MASK)
6353 
6354 /*! @name SOPT7 - System Options Register 7 */
6355 #define SIM_SOPT7_ADC0TRGSEL_MASK                (0xFU)
6356 #define SIM_SOPT7_ADC0TRGSEL_SHIFT               (0U)
6357 #define SIM_SOPT7_ADC0TRGSEL(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK)
6358 #define SIM_SOPT7_ADC0PRETRGSEL_MASK             (0x10U)
6359 #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT            (4U)
6360 #define SIM_SOPT7_ADC0PRETRGSEL(x)               (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC0PRETRGSEL_MASK)
6361 #define SIM_SOPT7_ADC0ALTTRGEN_MASK              (0x80U)
6362 #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT             (7U)
6363 #define SIM_SOPT7_ADC0ALTTRGEN(x)                (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC0ALTTRGEN_MASK)
6364 
6365 /*! @name SDID - System Device Identification Register */
6366 #define SIM_SDID_PINID_MASK                      (0xFU)
6367 #define SIM_SDID_PINID_SHIFT                     (0U)
6368 #define SIM_SDID_PINID(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK)
6369 #define SIM_SDID_DIEID_MASK                      (0xF80U)
6370 #define SIM_SDID_DIEID_SHIFT                     (7U)
6371 #define SIM_SDID_DIEID(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SDID_DIEID_SHIFT)) & SIM_SDID_DIEID_MASK)
6372 #define SIM_SDID_REVID_MASK                      (0xF000U)
6373 #define SIM_SDID_REVID_SHIFT                     (12U)
6374 #define SIM_SDID_REVID(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK)
6375 #define SIM_SDID_SRAMSIZE_MASK                   (0xF0000U)
6376 #define SIM_SDID_SRAMSIZE_SHIFT                  (16U)
6377 #define SIM_SDID_SRAMSIZE(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SRAMSIZE_SHIFT)) & SIM_SDID_SRAMSIZE_MASK)
6378 #define SIM_SDID_SERIESID_MASK                   (0xF00000U)
6379 #define SIM_SDID_SERIESID_SHIFT                  (20U)
6380 #define SIM_SDID_SERIESID(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK)
6381 #define SIM_SDID_SUBFAMID_MASK                   (0x3000000U)
6382 #define SIM_SDID_SUBFAMID_SHIFT                  (24U)
6383 #define SIM_SDID_SUBFAMID(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK)
6384 #define SIM_SDID_FAMID_MASK                      (0xF0000000U)
6385 #define SIM_SDID_FAMID_SHIFT                     (28U)
6386 #define SIM_SDID_FAMID(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK)
6387 
6388 /*! @name SCGC4 - System Clock Gating Control Register 4 */
6389 #define SIM_SCGC4_CMT_MASK                       (0x4U)
6390 #define SIM_SCGC4_CMT_SHIFT                      (2U)
6391 #define SIM_SCGC4_CMT(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMT_SHIFT)) & SIM_SCGC4_CMT_MASK)
6392 #define SIM_SCGC4_I2C0_MASK                      (0x40U)
6393 #define SIM_SCGC4_I2C0_SHIFT                     (6U)
6394 #define SIM_SCGC4_I2C0(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK)
6395 #define SIM_SCGC4_I2C1_MASK                      (0x80U)
6396 #define SIM_SCGC4_I2C1_SHIFT                     (7U)
6397 #define SIM_SCGC4_I2C1(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C1_SHIFT)) & SIM_SCGC4_I2C1_MASK)
6398 #define SIM_SCGC4_CMP_MASK                       (0x80000U)
6399 #define SIM_SCGC4_CMP_SHIFT                      (19U)
6400 #define SIM_SCGC4_CMP(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
6401 #define SIM_SCGC4_VREF_MASK                      (0x100000U)
6402 #define SIM_SCGC4_VREF_SHIFT                     (20U)
6403 #define SIM_SCGC4_VREF(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_VREF_SHIFT)) & SIM_SCGC4_VREF_MASK)
6404 
6405 /*! @name SCGC5 - System Clock Gating Control Register 5 */
6406 #define SIM_SCGC5_LPTMR_MASK                     (0x1U)
6407 #define SIM_SCGC5_LPTMR_SHIFT                    (0U)
6408 #define SIM_SCGC5_LPTMR(x)                       (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK)
6409 #define SIM_SCGC5_TSI_MASK                       (0x20U)
6410 #define SIM_SCGC5_TSI_SHIFT                      (5U)
6411 #define SIM_SCGC5_TSI(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_TSI_SHIFT)) & SIM_SCGC5_TSI_MASK)
6412 #define SIM_SCGC5_PORTA_MASK                     (0x200U)
6413 #define SIM_SCGC5_PORTA_SHIFT                    (9U)
6414 #define SIM_SCGC5_PORTA(x)                       (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTA_SHIFT)) & SIM_SCGC5_PORTA_MASK)
6415 #define SIM_SCGC5_PORTB_MASK                     (0x400U)
6416 #define SIM_SCGC5_PORTB_SHIFT                    (10U)
6417 #define SIM_SCGC5_PORTB(x)                       (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK)
6418 #define SIM_SCGC5_PORTC_MASK                     (0x800U)
6419 #define SIM_SCGC5_PORTC_SHIFT                    (11U)
6420 #define SIM_SCGC5_PORTC(x)                       (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK)
6421 #define SIM_SCGC5_LPUART0_MASK                   (0x100000U)
6422 #define SIM_SCGC5_LPUART0_SHIFT                  (20U)
6423 #define SIM_SCGC5_LPUART0(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPUART0_SHIFT)) & SIM_SCGC5_LPUART0_MASK)
6424 #define SIM_SCGC5_LTC_MASK                       (0x1000000U)
6425 #define SIM_SCGC5_LTC_SHIFT                      (24U)
6426 #define SIM_SCGC5_LTC(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LTC_SHIFT)) & SIM_SCGC5_LTC_MASK)
6427 #define SIM_SCGC5_RSIM_MASK                      (0x2000000U)
6428 #define SIM_SCGC5_RSIM_SHIFT                     (25U)
6429 #define SIM_SCGC5_RSIM(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_RSIM_SHIFT)) & SIM_SCGC5_RSIM_MASK)
6430 #define SIM_SCGC5_DCDC_MASK                      (0x4000000U)
6431 #define SIM_SCGC5_DCDC_SHIFT                     (26U)
6432 #define SIM_SCGC5_DCDC(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_DCDC_SHIFT)) & SIM_SCGC5_DCDC_MASK)
6433 #define SIM_SCGC5_BTLL_MASK                      (0x8000000U)
6434 #define SIM_SCGC5_BTLL_SHIFT                     (27U)
6435 #define SIM_SCGC5_BTLL(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_BTLL_SHIFT)) & SIM_SCGC5_BTLL_MASK)
6436 #define SIM_SCGC5_PHYDIG_MASK                    (0x10000000U)
6437 #define SIM_SCGC5_PHYDIG_SHIFT                   (28U)
6438 #define SIM_SCGC5_PHYDIG(x)                      (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PHYDIG_SHIFT)) & SIM_SCGC5_PHYDIG_MASK)
6439 #define SIM_SCGC5_ZigBee_MASK                    (0x20000000U)
6440 #define SIM_SCGC5_ZigBee_SHIFT                   (29U)
6441 #define SIM_SCGC5_ZigBee(x)                      (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_ZigBee_SHIFT)) & SIM_SCGC5_ZigBee_MASK)
6442 #define SIM_SCGC5_ANT_MASK                       (0x40000000U)
6443 #define SIM_SCGC5_ANT_SHIFT                      (30U)
6444 #define SIM_SCGC5_ANT(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_ANT_SHIFT)) & SIM_SCGC5_ANT_MASK)
6445 #define SIM_SCGC5_GEN_FSK_MASK                   (0x80000000U)
6446 #define SIM_SCGC5_GEN_FSK_SHIFT                  (31U)
6447 #define SIM_SCGC5_GEN_FSK(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_GEN_FSK_SHIFT)) & SIM_SCGC5_GEN_FSK_MASK)
6448 
6449 /*! @name SCGC6 - System Clock Gating Control Register 6 */
6450 #define SIM_SCGC6_FTF_MASK                       (0x1U)
6451 #define SIM_SCGC6_FTF_SHIFT                      (0U)
6452 #define SIM_SCGC6_FTF(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK)
6453 #define SIM_SCGC6_DMAMUX_MASK                    (0x2U)
6454 #define SIM_SCGC6_DMAMUX_SHIFT                   (1U)
6455 #define SIM_SCGC6_DMAMUX(x)                      (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX_SHIFT)) & SIM_SCGC6_DMAMUX_MASK)
6456 #define SIM_SCGC6_TRNG_MASK                      (0x200U)
6457 #define SIM_SCGC6_TRNG_SHIFT                     (9U)
6458 #define SIM_SCGC6_TRNG(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TRNG_SHIFT)) & SIM_SCGC6_TRNG_MASK)
6459 #define SIM_SCGC6_SPI0_MASK                      (0x1000U)
6460 #define SIM_SCGC6_SPI0_SHIFT                     (12U)
6461 #define SIM_SCGC6_SPI0(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI0_SHIFT)) & SIM_SCGC6_SPI0_MASK)
6462 #define SIM_SCGC6_SPI1_MASK                      (0x2000U)
6463 #define SIM_SCGC6_SPI1_SHIFT                     (13U)
6464 #define SIM_SCGC6_SPI1(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI1_SHIFT)) & SIM_SCGC6_SPI1_MASK)
6465 #define SIM_SCGC6_PIT_MASK                       (0x800000U)
6466 #define SIM_SCGC6_PIT_SHIFT                      (23U)
6467 #define SIM_SCGC6_PIT(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT_SHIFT)) & SIM_SCGC6_PIT_MASK)
6468 #define SIM_SCGC6_TPM0_MASK                      (0x1000000U)
6469 #define SIM_SCGC6_TPM0_SHIFT                     (24U)
6470 #define SIM_SCGC6_TPM0(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM0_SHIFT)) & SIM_SCGC6_TPM0_MASK)
6471 #define SIM_SCGC6_TPM1_MASK                      (0x2000000U)
6472 #define SIM_SCGC6_TPM1_SHIFT                     (25U)
6473 #define SIM_SCGC6_TPM1(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM1_SHIFT)) & SIM_SCGC6_TPM1_MASK)
6474 #define SIM_SCGC6_TPM2_MASK                      (0x4000000U)
6475 #define SIM_SCGC6_TPM2_SHIFT                     (26U)
6476 #define SIM_SCGC6_TPM2(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM2_SHIFT)) & SIM_SCGC6_TPM2_MASK)
6477 #define SIM_SCGC6_ADC0_MASK                      (0x8000000U)
6478 #define SIM_SCGC6_ADC0_SHIFT                     (27U)
6479 #define SIM_SCGC6_ADC0(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK)
6480 #define SIM_SCGC6_RTC_MASK                       (0x20000000U)
6481 #define SIM_SCGC6_RTC_SHIFT                      (29U)
6482 #define SIM_SCGC6_RTC(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RTC_SHIFT)) & SIM_SCGC6_RTC_MASK)
6483 #define SIM_SCGC6_DAC0_MASK                      (0x80000000U)
6484 #define SIM_SCGC6_DAC0_SHIFT                     (31U)
6485 #define SIM_SCGC6_DAC0(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DAC0_SHIFT)) & SIM_SCGC6_DAC0_MASK)
6486 
6487 /*! @name SCGC7 - System Clock Gating Control Register 7 */
6488 #define SIM_SCGC7_DMA_MASK                       (0x100U)
6489 #define SIM_SCGC7_DMA_SHIFT                      (8U)
6490 #define SIM_SCGC7_DMA(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK)
6491 
6492 /*! @name CLKDIV1 - System Clock Divider Register 1 */
6493 #define SIM_CLKDIV1_OUTDIV4_MASK                 (0x70000U)
6494 #define SIM_CLKDIV1_OUTDIV4_SHIFT                (16U)
6495 #define SIM_CLKDIV1_OUTDIV4(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK)
6496 #define SIM_CLKDIV1_OUTDIV1_MASK                 (0xF0000000U)
6497 #define SIM_CLKDIV1_OUTDIV1_SHIFT                (28U)
6498 #define SIM_CLKDIV1_OUTDIV1(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK)
6499 
6500 /*! @name FCFG1 - Flash Configuration Register 1 */
6501 #define SIM_FCFG1_FLASHDIS_MASK                  (0x1U)
6502 #define SIM_FCFG1_FLASHDIS_SHIFT                 (0U)
6503 #define SIM_FCFG1_FLASHDIS(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK)
6504 #define SIM_FCFG1_FLASHDOZE_MASK                 (0x2U)
6505 #define SIM_FCFG1_FLASHDOZE_SHIFT                (1U)
6506 #define SIM_FCFG1_FLASHDOZE(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK)
6507 #define SIM_FCFG1_PFSIZE_MASK                    (0xF000000U)
6508 #define SIM_FCFG1_PFSIZE_SHIFT                   (24U)
6509 #define SIM_FCFG1_PFSIZE(x)                      (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK)
6510 
6511 /*! @name FCFG2 - Flash Configuration Register 2 */
6512 #define SIM_FCFG2_MAXADDR1_MASK                  (0x7F0000U)
6513 #define SIM_FCFG2_MAXADDR1_SHIFT                 (16U)
6514 #define SIM_FCFG2_MAXADDR1(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR1_SHIFT)) & SIM_FCFG2_MAXADDR1_MASK)
6515 #define SIM_FCFG2_MAXADDR0_MASK                  (0x7F000000U)
6516 #define SIM_FCFG2_MAXADDR0_SHIFT                 (24U)
6517 #define SIM_FCFG2_MAXADDR0(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK)
6518 
6519 /*! @name UIDMH - Unique Identification Register Mid-High */
6520 #define SIM_UIDMH_UID_MASK                       (0xFFFFU)
6521 #define SIM_UIDMH_UID_SHIFT                      (0U)
6522 #define SIM_UIDMH_UID(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID_SHIFT)) & SIM_UIDMH_UID_MASK)
6523 
6524 /*! @name UIDML - Unique Identification Register Mid Low */
6525 #define SIM_UIDML_UID_MASK                       (0xFFFFFFFFU)
6526 #define SIM_UIDML_UID_SHIFT                      (0U)
6527 #define SIM_UIDML_UID(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID_SHIFT)) & SIM_UIDML_UID_MASK)
6528 
6529 /*! @name UIDL - Unique Identification Register Low */
6530 #define SIM_UIDL_UID_MASK                        (0xFFFFFFFFU)
6531 #define SIM_UIDL_UID_SHIFT                       (0U)
6532 #define SIM_UIDL_UID(x)                          (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK)
6533 
6534 /*! @name COPC - COP Control Register */
6535 #define SIM_COPC_COPW_MASK                       (0x1U)
6536 #define SIM_COPC_COPW_SHIFT                      (0U)
6537 #define SIM_COPC_COPW(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPW_SHIFT)) & SIM_COPC_COPW_MASK)
6538 #define SIM_COPC_COPCLKS_MASK                    (0x2U)
6539 #define SIM_COPC_COPCLKS_SHIFT                   (1U)
6540 #define SIM_COPC_COPCLKS(x)                      (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPCLKS_SHIFT)) & SIM_COPC_COPCLKS_MASK)
6541 #define SIM_COPC_COPT_MASK                       (0xCU)
6542 #define SIM_COPC_COPT_SHIFT                      (2U)
6543 #define SIM_COPC_COPT(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPT_SHIFT)) & SIM_COPC_COPT_MASK)
6544 #define SIM_COPC_COPSTPEN_MASK                   (0x10U)
6545 #define SIM_COPC_COPSTPEN_SHIFT                  (4U)
6546 #define SIM_COPC_COPSTPEN(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPSTPEN_SHIFT)) & SIM_COPC_COPSTPEN_MASK)
6547 #define SIM_COPC_COPDBGEN_MASK                   (0x20U)
6548 #define SIM_COPC_COPDBGEN_SHIFT                  (5U)
6549 #define SIM_COPC_COPDBGEN(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPDBGEN_SHIFT)) & SIM_COPC_COPDBGEN_MASK)
6550 #define SIM_COPC_COPCLKSEL_MASK                  (0xC0U)
6551 #define SIM_COPC_COPCLKSEL_SHIFT                 (6U)
6552 #define SIM_COPC_COPCLKSEL(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPCLKSEL_SHIFT)) & SIM_COPC_COPCLKSEL_MASK)
6553 
6554 /*! @name SRVCOP - Service COP */
6555 #define SIM_SRVCOP_SRVCOP_MASK                   (0xFFU)
6556 #define SIM_SRVCOP_SRVCOP_SHIFT                  (0U)
6557 #define SIM_SRVCOP_SRVCOP(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SRVCOP_SRVCOP_SHIFT)) & SIM_SRVCOP_SRVCOP_MASK)
6558 
6559 
6560 /*!
6561  * @}
6562  */ /* end of group SIM_Register_Masks */
6563 
6564 
6565 /* SIM - Peripheral instance base addresses */
6566 /** Peripheral SIM base address */
6567 #define SIM_BASE                                 (0x40047000u)
6568 /** Peripheral SIM base pointer */
6569 #define SIM                                      ((SIM_Type *)SIM_BASE)
6570 /** Array initializer of SIM peripheral base addresses */
6571 #define SIM_BASE_ADDRS                           { SIM_BASE }
6572 /** Array initializer of SIM peripheral base pointers */
6573 #define SIM_BASE_PTRS                            { SIM }
6574 
6575 /*!
6576  * @}
6577  */ /* end of group SIM_Peripheral_Access_Layer */
6578 
6579 
6580 /* ----------------------------------------------------------------------------
6581    -- SMC Peripheral Access Layer
6582    ---------------------------------------------------------------------------- */
6583 
6584 /*!
6585  * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
6586  * @{
6587  */
6588 
6589 /** SMC - Register Layout Typedef */
6590 typedef struct {
6591   __IO uint8_t PMPROT;                             /**< Power Mode Protection register, offset: 0x0 */
6592   __IO uint8_t PMCTRL;                             /**< Power Mode Control register, offset: 0x1 */
6593   __IO uint8_t STOPCTRL;                           /**< Stop Control Register, offset: 0x2 */
6594   __I  uint8_t PMSTAT;                             /**< Power Mode Status register, offset: 0x3 */
6595 } SMC_Type;
6596 
6597 /* ----------------------------------------------------------------------------
6598    -- SMC Register Masks
6599    ---------------------------------------------------------------------------- */
6600 
6601 /*!
6602  * @addtogroup SMC_Register_Masks SMC Register Masks
6603  * @{
6604  */
6605 
6606 /*! @name PMPROT - Power Mode Protection register */
6607 #define SMC_PMPROT_AVLLS_MASK                    (0x2U)
6608 #define SMC_PMPROT_AVLLS_SHIFT                   (1U)
6609 #define SMC_PMPROT_AVLLS(x)                      (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLLS_SHIFT)) & SMC_PMPROT_AVLLS_MASK)
6610 #define SMC_PMPROT_ALLS_MASK                     (0x8U)
6611 #define SMC_PMPROT_ALLS_SHIFT                    (3U)
6612 #define SMC_PMPROT_ALLS(x)                       (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_ALLS_SHIFT)) & SMC_PMPROT_ALLS_MASK)
6613 #define SMC_PMPROT_AVLP_MASK                     (0x20U)
6614 #define SMC_PMPROT_AVLP_SHIFT                    (5U)
6615 #define SMC_PMPROT_AVLP(x)                       (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK)
6616 
6617 /*! @name PMCTRL - Power Mode Control register */
6618 #define SMC_PMCTRL_STOPM_MASK                    (0x7U)
6619 #define SMC_PMCTRL_STOPM_SHIFT                   (0U)
6620 #define SMC_PMCTRL_STOPM(x)                      (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK)
6621 #define SMC_PMCTRL_STOPA_MASK                    (0x8U)
6622 #define SMC_PMCTRL_STOPA_SHIFT                   (3U)
6623 #define SMC_PMCTRL_STOPA(x)                      (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPA_SHIFT)) & SMC_PMCTRL_STOPA_MASK)
6624 #define SMC_PMCTRL_RUNM_MASK                     (0x60U)
6625 #define SMC_PMCTRL_RUNM_SHIFT                    (5U)
6626 #define SMC_PMCTRL_RUNM(x)                       (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK)
6627 
6628 /*! @name STOPCTRL - Stop Control Register */
6629 #define SMC_STOPCTRL_LLSM_MASK                   (0x7U)
6630 #define SMC_STOPCTRL_LLSM_SHIFT                  (0U)
6631 #define SMC_STOPCTRL_LLSM(x)                     (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_LLSM_SHIFT)) & SMC_STOPCTRL_LLSM_MASK)
6632 #define SMC_STOPCTRL_RAM2PO_MASK                 (0x10U)
6633 #define SMC_STOPCTRL_RAM2PO_SHIFT                (4U)
6634 #define SMC_STOPCTRL_RAM2PO(x)                   (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_RAM2PO_SHIFT)) & SMC_STOPCTRL_RAM2PO_MASK)
6635 #define SMC_STOPCTRL_PORPO_MASK                  (0x20U)
6636 #define SMC_STOPCTRL_PORPO_SHIFT                 (5U)
6637 #define SMC_STOPCTRL_PORPO(x)                    (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PORPO_SHIFT)) & SMC_STOPCTRL_PORPO_MASK)
6638 #define SMC_STOPCTRL_PSTOPO_MASK                 (0xC0U)
6639 #define SMC_STOPCTRL_PSTOPO_SHIFT                (6U)
6640 #define SMC_STOPCTRL_PSTOPO(x)                   (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PSTOPO_SHIFT)) & SMC_STOPCTRL_PSTOPO_MASK)
6641 
6642 /*! @name PMSTAT - Power Mode Status register */
6643 #define SMC_PMSTAT_PMSTAT_MASK                   (0xFFU)
6644 #define SMC_PMSTAT_PMSTAT_SHIFT                  (0U)
6645 #define SMC_PMSTAT_PMSTAT(x)                     (((uint8_t)(((uint8_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK)
6646 
6647 
6648 /*!
6649  * @}
6650  */ /* end of group SMC_Register_Masks */
6651 
6652 
6653 /* SMC - Peripheral instance base addresses */
6654 /** Peripheral SMC base address */
6655 #define SMC_BASE                                 (0x4007E000u)
6656 /** Peripheral SMC base pointer */
6657 #define SMC                                      ((SMC_Type *)SMC_BASE)
6658 /** Array initializer of SMC peripheral base addresses */
6659 #define SMC_BASE_ADDRS                           { SMC_BASE }
6660 /** Array initializer of SMC peripheral base pointers */
6661 #define SMC_BASE_PTRS                            { SMC }
6662 
6663 /*!
6664  * @}
6665  */ /* end of group SMC_Peripheral_Access_Layer */
6666 
6667 
6668 /* ----------------------------------------------------------------------------
6669    -- SPI Peripheral Access Layer
6670    ---------------------------------------------------------------------------- */
6671 
6672 /*!
6673  * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
6674  * @{
6675  */
6676 
6677 /** SPI - Register Layout Typedef */
6678 typedef struct {
6679   __IO uint32_t MCR;                               /**< Module Configuration Register, offset: 0x0 */
6680        uint8_t RESERVED_0[4];
6681   __IO uint32_t TCR;                               /**< Transfer Count Register, offset: 0x8 */
6682   union {                                          /* offset: 0xC */
6683     __IO uint32_t CTAR[2];                           /**< Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
6684     __IO uint32_t CTAR_SLAVE[1];                     /**< Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */
6685   };
6686        uint8_t RESERVED_1[24];
6687   __IO uint32_t SR;                                /**< Status Register, offset: 0x2C */
6688   __IO uint32_t RSER;                              /**< DMA/Interrupt Request Select and Enable Register, offset: 0x30 */
6689   union {                                          /* offset: 0x34 */
6690     __IO uint32_t PUSHR;                             /**< PUSH TX FIFO Register In Master Mode, offset: 0x34 */
6691     __IO uint32_t PUSHR_SLAVE;                       /**< PUSH TX FIFO Register In Slave Mode, offset: 0x34 */
6692   };
6693   __I  uint32_t POPR;                              /**< POP RX FIFO Register, offset: 0x38 */
6694   __I  uint32_t TXFR0;                             /**< Transmit FIFO Registers, offset: 0x3C */
6695   __I  uint32_t TXFR1;                             /**< Transmit FIFO Registers, offset: 0x40 */
6696   __I  uint32_t TXFR2;                             /**< Transmit FIFO Registers, offset: 0x44 */
6697   __I  uint32_t TXFR3;                             /**< Transmit FIFO Registers, offset: 0x48 */
6698        uint8_t RESERVED_2[48];
6699   __I  uint32_t RXFR0;                             /**< Receive FIFO Registers, offset: 0x7C */
6700   __I  uint32_t RXFR1;                             /**< Receive FIFO Registers, offset: 0x80 */
6701   __I  uint32_t RXFR2;                             /**< Receive FIFO Registers, offset: 0x84 */
6702   __I  uint32_t RXFR3;                             /**< Receive FIFO Registers, offset: 0x88 */
6703 } SPI_Type;
6704 
6705 /* ----------------------------------------------------------------------------
6706    -- SPI Register Masks
6707    ---------------------------------------------------------------------------- */
6708 
6709 /*!
6710  * @addtogroup SPI_Register_Masks SPI Register Masks
6711  * @{
6712  */
6713 
6714 /*! @name MCR - Module Configuration Register */
6715 #define SPI_MCR_HALT_MASK                        (0x1U)
6716 #define SPI_MCR_HALT_SHIFT                       (0U)
6717 #define SPI_MCR_HALT(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_MCR_HALT_SHIFT)) & SPI_MCR_HALT_MASK)
6718 #define SPI_MCR_SMPL_PT_MASK                     (0x300U)
6719 #define SPI_MCR_SMPL_PT_SHIFT                    (8U)
6720 #define SPI_MCR_SMPL_PT(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_MCR_SMPL_PT_SHIFT)) & SPI_MCR_SMPL_PT_MASK)
6721 #define SPI_MCR_CLR_RXF_MASK                     (0x400U)
6722 #define SPI_MCR_CLR_RXF_SHIFT                    (10U)
6723 #define SPI_MCR_CLR_RXF(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_RXF_SHIFT)) & SPI_MCR_CLR_RXF_MASK)
6724 #define SPI_MCR_CLR_TXF_MASK                     (0x800U)
6725 #define SPI_MCR_CLR_TXF_SHIFT                    (11U)
6726 #define SPI_MCR_CLR_TXF(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_TXF_SHIFT)) & SPI_MCR_CLR_TXF_MASK)
6727 #define SPI_MCR_DIS_RXF_MASK                     (0x1000U)
6728 #define SPI_MCR_DIS_RXF_SHIFT                    (12U)
6729 #define SPI_MCR_DIS_RXF(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_RXF_SHIFT)) & SPI_MCR_DIS_RXF_MASK)
6730 #define SPI_MCR_DIS_TXF_MASK                     (0x2000U)
6731 #define SPI_MCR_DIS_TXF_SHIFT                    (13U)
6732 #define SPI_MCR_DIS_TXF(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_TXF_SHIFT)) & SPI_MCR_DIS_TXF_MASK)
6733 #define SPI_MCR_MDIS_MASK                        (0x4000U)
6734 #define SPI_MCR_MDIS_SHIFT                       (14U)
6735 #define SPI_MCR_MDIS(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MDIS_SHIFT)) & SPI_MCR_MDIS_MASK)
6736 #define SPI_MCR_DOZE_MASK                        (0x8000U)
6737 #define SPI_MCR_DOZE_SHIFT                       (15U)
6738 #define SPI_MCR_DOZE(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DOZE_SHIFT)) & SPI_MCR_DOZE_MASK)
6739 #define SPI_MCR_PCSIS_MASK                       (0xF0000U)
6740 #define SPI_MCR_PCSIS_SHIFT                      (16U)
6741 #define SPI_MCR_PCSIS(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSIS_SHIFT)) & SPI_MCR_PCSIS_MASK)
6742 #define SPI_MCR_ROOE_MASK                        (0x1000000U)
6743 #define SPI_MCR_ROOE_SHIFT                       (24U)
6744 #define SPI_MCR_ROOE(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_MCR_ROOE_SHIFT)) & SPI_MCR_ROOE_MASK)
6745 #define SPI_MCR_MTFE_MASK                        (0x4000000U)
6746 #define SPI_MCR_MTFE_SHIFT                       (26U)
6747 #define SPI_MCR_MTFE(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MTFE_SHIFT)) & SPI_MCR_MTFE_MASK)
6748 #define SPI_MCR_FRZ_MASK                         (0x8000000U)
6749 #define SPI_MCR_FRZ_SHIFT                        (27U)
6750 #define SPI_MCR_FRZ(x)                           (((uint32_t)(((uint32_t)(x)) << SPI_MCR_FRZ_SHIFT)) & SPI_MCR_FRZ_MASK)
6751 #define SPI_MCR_DCONF_MASK                       (0x30000000U)
6752 #define SPI_MCR_DCONF_SHIFT                      (28U)
6753 #define SPI_MCR_DCONF(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DCONF_SHIFT)) & SPI_MCR_DCONF_MASK)
6754 #define SPI_MCR_CONT_SCKE_MASK                   (0x40000000U)
6755 #define SPI_MCR_CONT_SCKE_SHIFT                  (30U)
6756 #define SPI_MCR_CONT_SCKE(x)                     (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CONT_SCKE_SHIFT)) & SPI_MCR_CONT_SCKE_MASK)
6757 #define SPI_MCR_MSTR_MASK                        (0x80000000U)
6758 #define SPI_MCR_MSTR_SHIFT                       (31U)
6759 #define SPI_MCR_MSTR(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MSTR_SHIFT)) & SPI_MCR_MSTR_MASK)
6760 
6761 /*! @name TCR - Transfer Count Register */
6762 #define SPI_TCR_SPI_TCNT_MASK                    (0xFFFF0000U)
6763 #define SPI_TCR_SPI_TCNT_SHIFT                   (16U)
6764 #define SPI_TCR_SPI_TCNT(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_TCR_SPI_TCNT_SHIFT)) & SPI_TCR_SPI_TCNT_MASK)
6765 
6766 /*! @name CTAR - Clock and Transfer Attributes Register (In Master Mode) */
6767 #define SPI_CTAR_BR_MASK                         (0xFU)
6768 #define SPI_CTAR_BR_SHIFT                        (0U)
6769 #define SPI_CTAR_BR(x)                           (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_BR_SHIFT)) & SPI_CTAR_BR_MASK)
6770 #define SPI_CTAR_DT_MASK                         (0xF0U)
6771 #define SPI_CTAR_DT_SHIFT                        (4U)
6772 #define SPI_CTAR_DT(x)                           (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DT_SHIFT)) & SPI_CTAR_DT_MASK)
6773 #define SPI_CTAR_ASC_MASK                        (0xF00U)
6774 #define SPI_CTAR_ASC_SHIFT                       (8U)
6775 #define SPI_CTAR_ASC(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_ASC_SHIFT)) & SPI_CTAR_ASC_MASK)
6776 #define SPI_CTAR_CSSCK_MASK                      (0xF000U)
6777 #define SPI_CTAR_CSSCK_SHIFT                     (12U)
6778 #define SPI_CTAR_CSSCK(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CSSCK_SHIFT)) & SPI_CTAR_CSSCK_MASK)
6779 #define SPI_CTAR_PBR_MASK                        (0x30000U)
6780 #define SPI_CTAR_PBR_SHIFT                       (16U)
6781 #define SPI_CTAR_PBR(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PBR_SHIFT)) & SPI_CTAR_PBR_MASK)
6782 #define SPI_CTAR_PDT_MASK                        (0xC0000U)
6783 #define SPI_CTAR_PDT_SHIFT                       (18U)
6784 #define SPI_CTAR_PDT(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PDT_SHIFT)) & SPI_CTAR_PDT_MASK)
6785 #define SPI_CTAR_PASC_MASK                       (0x300000U)
6786 #define SPI_CTAR_PASC_SHIFT                      (20U)
6787 #define SPI_CTAR_PASC(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PASC_SHIFT)) & SPI_CTAR_PASC_MASK)
6788 #define SPI_CTAR_PCSSCK_MASK                     (0xC00000U)
6789 #define SPI_CTAR_PCSSCK_SHIFT                    (22U)
6790 #define SPI_CTAR_PCSSCK(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK)
6791 #define SPI_CTAR_LSBFE_MASK                      (0x1000000U)
6792 #define SPI_CTAR_LSBFE_SHIFT                     (24U)
6793 #define SPI_CTAR_LSBFE(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_LSBFE_SHIFT)) & SPI_CTAR_LSBFE_MASK)
6794 #define SPI_CTAR_CPHA_MASK                       (0x2000000U)
6795 #define SPI_CTAR_CPHA_SHIFT                      (25U)
6796 #define SPI_CTAR_CPHA(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPHA_SHIFT)) & SPI_CTAR_CPHA_MASK)
6797 #define SPI_CTAR_CPOL_MASK                       (0x4000000U)
6798 #define SPI_CTAR_CPOL_SHIFT                      (26U)
6799 #define SPI_CTAR_CPOL(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPOL_SHIFT)) & SPI_CTAR_CPOL_MASK)
6800 #define SPI_CTAR_FMSZ_MASK                       (0x78000000U)
6801 #define SPI_CTAR_FMSZ_SHIFT                      (27U)
6802 #define SPI_CTAR_FMSZ(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_FMSZ_SHIFT)) & SPI_CTAR_FMSZ_MASK)
6803 #define SPI_CTAR_DBR_MASK                        (0x80000000U)
6804 #define SPI_CTAR_DBR_SHIFT                       (31U)
6805 #define SPI_CTAR_DBR(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DBR_SHIFT)) & SPI_CTAR_DBR_MASK)
6806 
6807 /* The count of SPI_CTAR */
6808 #define SPI_CTAR_COUNT                           (2U)
6809 
6810 /*! @name CTAR_SLAVE - Clock and Transfer Attributes Register (In Slave Mode) */
6811 #define SPI_CTAR_SLAVE_CPHA_MASK                 (0x2000000U)
6812 #define SPI_CTAR_SLAVE_CPHA_SHIFT                (25U)
6813 #define SPI_CTAR_SLAVE_CPHA(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPHA_SHIFT)) & SPI_CTAR_SLAVE_CPHA_MASK)
6814 #define SPI_CTAR_SLAVE_CPOL_MASK                 (0x4000000U)
6815 #define SPI_CTAR_SLAVE_CPOL_SHIFT                (26U)
6816 #define SPI_CTAR_SLAVE_CPOL(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPOL_SHIFT)) & SPI_CTAR_SLAVE_CPOL_MASK)
6817 #define SPI_CTAR_SLAVE_FMSZ_MASK                 (0x78000000U)
6818 #define SPI_CTAR_SLAVE_FMSZ_SHIFT                (27U)
6819 #define SPI_CTAR_SLAVE_FMSZ(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_FMSZ_SHIFT)) & SPI_CTAR_SLAVE_FMSZ_MASK)
6820 
6821 /* The count of SPI_CTAR_SLAVE */
6822 #define SPI_CTAR_SLAVE_COUNT                     (1U)
6823 
6824 /*! @name SR - Status Register */
6825 #define SPI_SR_POPNXTPTR_MASK                    (0xFU)
6826 #define SPI_SR_POPNXTPTR_SHIFT                   (0U)
6827 #define SPI_SR_POPNXTPTR(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_SR_POPNXTPTR_SHIFT)) & SPI_SR_POPNXTPTR_MASK)
6828 #define SPI_SR_RXCTR_MASK                        (0xF0U)
6829 #define SPI_SR_RXCTR_SHIFT                       (4U)
6830 #define SPI_SR_RXCTR(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_SR_RXCTR_SHIFT)) & SPI_SR_RXCTR_MASK)
6831 #define SPI_SR_TXNXTPTR_MASK                     (0xF00U)
6832 #define SPI_SR_TXNXTPTR_SHIFT                    (8U)
6833 #define SPI_SR_TXNXTPTR(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXNXTPTR_SHIFT)) & SPI_SR_TXNXTPTR_MASK)
6834 #define SPI_SR_TXCTR_MASK                        (0xF000U)
6835 #define SPI_SR_TXCTR_SHIFT                       (12U)
6836 #define SPI_SR_TXCTR(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXCTR_SHIFT)) & SPI_SR_TXCTR_MASK)
6837 #define SPI_SR_RFDF_MASK                         (0x20000U)
6838 #define SPI_SR_RFDF_SHIFT                        (17U)
6839 #define SPI_SR_RFDF(x)                           (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFDF_SHIFT)) & SPI_SR_RFDF_MASK)
6840 #define SPI_SR_RFOF_MASK                         (0x80000U)
6841 #define SPI_SR_RFOF_SHIFT                        (19U)
6842 #define SPI_SR_RFOF(x)                           (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFOF_SHIFT)) & SPI_SR_RFOF_MASK)
6843 #define SPI_SR_TFFF_MASK                         (0x2000000U)
6844 #define SPI_SR_TFFF_SHIFT                        (25U)
6845 #define SPI_SR_TFFF(x)                           (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK)
6846 #define SPI_SR_TFUF_MASK                         (0x8000000U)
6847 #define SPI_SR_TFUF_SHIFT                        (27U)
6848 #define SPI_SR_TFUF(x)                           (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFUF_SHIFT)) & SPI_SR_TFUF_MASK)
6849 #define SPI_SR_EOQF_MASK                         (0x10000000U)
6850 #define SPI_SR_EOQF_SHIFT                        (28U)
6851 #define SPI_SR_EOQF(x)                           (((uint32_t)(((uint32_t)(x)) << SPI_SR_EOQF_SHIFT)) & SPI_SR_EOQF_MASK)
6852 #define SPI_SR_TXRXS_MASK                        (0x40000000U)
6853 #define SPI_SR_TXRXS_SHIFT                       (30U)
6854 #define SPI_SR_TXRXS(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXRXS_SHIFT)) & SPI_SR_TXRXS_MASK)
6855 #define SPI_SR_TCF_MASK                          (0x80000000U)
6856 #define SPI_SR_TCF_SHIFT                         (31U)
6857 #define SPI_SR_TCF(x)                            (((uint32_t)(((uint32_t)(x)) << SPI_SR_TCF_SHIFT)) & SPI_SR_TCF_MASK)
6858 
6859 /*! @name RSER - DMA/Interrupt Request Select and Enable Register */
6860 #define SPI_RSER_RFDF_DIRS_MASK                  (0x10000U)
6861 #define SPI_RSER_RFDF_DIRS_SHIFT                 (16U)
6862 #define SPI_RSER_RFDF_DIRS(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_DIRS_SHIFT)) & SPI_RSER_RFDF_DIRS_MASK)
6863 #define SPI_RSER_RFDF_RE_MASK                    (0x20000U)
6864 #define SPI_RSER_RFDF_RE_SHIFT                   (17U)
6865 #define SPI_RSER_RFDF_RE(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_RE_SHIFT)) & SPI_RSER_RFDF_RE_MASK)
6866 #define SPI_RSER_RFOF_RE_MASK                    (0x80000U)
6867 #define SPI_RSER_RFOF_RE_SHIFT                   (19U)
6868 #define SPI_RSER_RFOF_RE(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFOF_RE_SHIFT)) & SPI_RSER_RFOF_RE_MASK)
6869 #define SPI_RSER_TFFF_DIRS_MASK                  (0x1000000U)
6870 #define SPI_RSER_TFFF_DIRS_SHIFT                 (24U)
6871 #define SPI_RSER_TFFF_DIRS(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_DIRS_SHIFT)) & SPI_RSER_TFFF_DIRS_MASK)
6872 #define SPI_RSER_TFFF_RE_MASK                    (0x2000000U)
6873 #define SPI_RSER_TFFF_RE_SHIFT                   (25U)
6874 #define SPI_RSER_TFFF_RE(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK)
6875 #define SPI_RSER_TFUF_RE_MASK                    (0x8000000U)
6876 #define SPI_RSER_TFUF_RE_SHIFT                   (27U)
6877 #define SPI_RSER_TFUF_RE(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFUF_RE_SHIFT)) & SPI_RSER_TFUF_RE_MASK)
6878 #define SPI_RSER_EOQF_RE_MASK                    (0x10000000U)
6879 #define SPI_RSER_EOQF_RE_SHIFT                   (28U)
6880 #define SPI_RSER_EOQF_RE(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_RSER_EOQF_RE_SHIFT)) & SPI_RSER_EOQF_RE_MASK)
6881 #define SPI_RSER_TCF_RE_MASK                     (0x80000000U)
6882 #define SPI_RSER_TCF_RE_SHIFT                    (31U)
6883 #define SPI_RSER_TCF_RE(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TCF_RE_SHIFT)) & SPI_RSER_TCF_RE_MASK)
6884 
6885 /*! @name PUSHR - PUSH TX FIFO Register In Master Mode */
6886 #define SPI_PUSHR_TXDATA_MASK                    (0xFFFFU)
6887 #define SPI_PUSHR_TXDATA_SHIFT                   (0U)
6888 #define SPI_PUSHR_TXDATA(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_TXDATA_SHIFT)) & SPI_PUSHR_TXDATA_MASK)
6889 #define SPI_PUSHR_PCS_MASK                       (0xF0000U)
6890 #define SPI_PUSHR_PCS_SHIFT                      (16U)
6891 #define SPI_PUSHR_PCS(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_PCS_SHIFT)) & SPI_PUSHR_PCS_MASK)
6892 #define SPI_PUSHR_CTCNT_MASK                     (0x4000000U)
6893 #define SPI_PUSHR_CTCNT_SHIFT                    (26U)
6894 #define SPI_PUSHR_CTCNT(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTCNT_SHIFT)) & SPI_PUSHR_CTCNT_MASK)
6895 #define SPI_PUSHR_EOQ_MASK                       (0x8000000U)
6896 #define SPI_PUSHR_EOQ_SHIFT                      (27U)
6897 #define SPI_PUSHR_EOQ(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_EOQ_SHIFT)) & SPI_PUSHR_EOQ_MASK)
6898 #define SPI_PUSHR_CTAS_MASK                      (0x70000000U)
6899 #define SPI_PUSHR_CTAS_SHIFT                     (28U)
6900 #define SPI_PUSHR_CTAS(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTAS_SHIFT)) & SPI_PUSHR_CTAS_MASK)
6901 #define SPI_PUSHR_CONT_MASK                      (0x80000000U)
6902 #define SPI_PUSHR_CONT_SHIFT                     (31U)
6903 #define SPI_PUSHR_CONT(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CONT_SHIFT)) & SPI_PUSHR_CONT_MASK)
6904 
6905 /*! @name PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode */
6906 #define SPI_PUSHR_SLAVE_TXDATA_MASK              (0xFFFFU)
6907 #define SPI_PUSHR_SLAVE_TXDATA_SHIFT             (0U)
6908 #define SPI_PUSHR_SLAVE_TXDATA(x)                (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_SLAVE_TXDATA_SHIFT)) & SPI_PUSHR_SLAVE_TXDATA_MASK)
6909 
6910 /*! @name POPR - POP RX FIFO Register */
6911 #define SPI_POPR_RXDATA_MASK                     (0xFFFFFFFFU)
6912 #define SPI_POPR_RXDATA_SHIFT                    (0U)
6913 #define SPI_POPR_RXDATA(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_POPR_RXDATA_SHIFT)) & SPI_POPR_RXDATA_MASK)
6914 
6915 /*! @name TXFR0 - Transmit FIFO Registers */
6916 #define SPI_TXFR0_TXDATA_MASK                    (0xFFFFU)
6917 #define SPI_TXFR0_TXDATA_SHIFT                   (0U)
6918 #define SPI_TXFR0_TXDATA(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXDATA_SHIFT)) & SPI_TXFR0_TXDATA_MASK)
6919 #define SPI_TXFR0_TXCMD_TXDATA_MASK              (0xFFFF0000U)
6920 #define SPI_TXFR0_TXCMD_TXDATA_SHIFT             (16U)
6921 #define SPI_TXFR0_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXCMD_TXDATA_SHIFT)) & SPI_TXFR0_TXCMD_TXDATA_MASK)
6922 
6923 /*! @name TXFR1 - Transmit FIFO Registers */
6924 #define SPI_TXFR1_TXDATA_MASK                    (0xFFFFU)
6925 #define SPI_TXFR1_TXDATA_SHIFT                   (0U)
6926 #define SPI_TXFR1_TXDATA(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXDATA_SHIFT)) & SPI_TXFR1_TXDATA_MASK)
6927 #define SPI_TXFR1_TXCMD_TXDATA_MASK              (0xFFFF0000U)
6928 #define SPI_TXFR1_TXCMD_TXDATA_SHIFT             (16U)
6929 #define SPI_TXFR1_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXCMD_TXDATA_SHIFT)) & SPI_TXFR1_TXCMD_TXDATA_MASK)
6930 
6931 /*! @name TXFR2 - Transmit FIFO Registers */
6932 #define SPI_TXFR2_TXDATA_MASK                    (0xFFFFU)
6933 #define SPI_TXFR2_TXDATA_SHIFT                   (0U)
6934 #define SPI_TXFR2_TXDATA(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXDATA_SHIFT)) & SPI_TXFR2_TXDATA_MASK)
6935 #define SPI_TXFR2_TXCMD_TXDATA_MASK              (0xFFFF0000U)
6936 #define SPI_TXFR2_TXCMD_TXDATA_SHIFT             (16U)
6937 #define SPI_TXFR2_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXCMD_TXDATA_SHIFT)) & SPI_TXFR2_TXCMD_TXDATA_MASK)
6938 
6939 /*! @name TXFR3 - Transmit FIFO Registers */
6940 #define SPI_TXFR3_TXDATA_MASK                    (0xFFFFU)
6941 #define SPI_TXFR3_TXDATA_SHIFT                   (0U)
6942 #define SPI_TXFR3_TXDATA(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXDATA_SHIFT)) & SPI_TXFR3_TXDATA_MASK)
6943 #define SPI_TXFR3_TXCMD_TXDATA_MASK              (0xFFFF0000U)
6944 #define SPI_TXFR3_TXCMD_TXDATA_SHIFT             (16U)
6945 #define SPI_TXFR3_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXCMD_TXDATA_SHIFT)) & SPI_TXFR3_TXCMD_TXDATA_MASK)
6946 
6947 /*! @name RXFR0 - Receive FIFO Registers */
6948 #define SPI_RXFR0_RXDATA_MASK                    (0xFFFFFFFFU)
6949 #define SPI_RXFR0_RXDATA_SHIFT                   (0U)
6950 #define SPI_RXFR0_RXDATA(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_RXFR0_RXDATA_SHIFT)) & SPI_RXFR0_RXDATA_MASK)
6951 
6952 /*! @name RXFR1 - Receive FIFO Registers */
6953 #define SPI_RXFR1_RXDATA_MASK                    (0xFFFFFFFFU)
6954 #define SPI_RXFR1_RXDATA_SHIFT                   (0U)
6955 #define SPI_RXFR1_RXDATA(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_RXFR1_RXDATA_SHIFT)) & SPI_RXFR1_RXDATA_MASK)
6956 
6957 /*! @name RXFR2 - Receive FIFO Registers */
6958 #define SPI_RXFR2_RXDATA_MASK                    (0xFFFFFFFFU)
6959 #define SPI_RXFR2_RXDATA_SHIFT                   (0U)
6960 #define SPI_RXFR2_RXDATA(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_RXFR2_RXDATA_SHIFT)) & SPI_RXFR2_RXDATA_MASK)
6961 
6962 /*! @name RXFR3 - Receive FIFO Registers */
6963 #define SPI_RXFR3_RXDATA_MASK                    (0xFFFFFFFFU)
6964 #define SPI_RXFR3_RXDATA_SHIFT                   (0U)
6965 #define SPI_RXFR3_RXDATA(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_RXFR3_RXDATA_SHIFT)) & SPI_RXFR3_RXDATA_MASK)
6966 
6967 
6968 /*!
6969  * @}
6970  */ /* end of group SPI_Register_Masks */
6971 
6972 
6973 /* SPI - Peripheral instance base addresses */
6974 /** Peripheral SPI0 base address */
6975 #define SPI0_BASE                                (0x4002C000u)
6976 /** Peripheral SPI0 base pointer */
6977 #define SPI0                                     ((SPI_Type *)SPI0_BASE)
6978 /** Peripheral SPI1 base address */
6979 #define SPI1_BASE                                (0x4002D000u)
6980 /** Peripheral SPI1 base pointer */
6981 #define SPI1                                     ((SPI_Type *)SPI1_BASE)
6982 /** Array initializer of SPI peripheral base addresses */
6983 #define SPI_BASE_ADDRS                           { SPI0_BASE, SPI1_BASE }
6984 /** Array initializer of SPI peripheral base pointers */
6985 #define SPI_BASE_PTRS                            { SPI0, SPI1 }
6986 /** Interrupt vectors for the SPI peripheral type */
6987 #define SPI_IRQS                                 { SPI0_IRQn, SPI1_IRQn }
6988 
6989 /*!
6990  * @}
6991  */ /* end of group SPI_Peripheral_Access_Layer */
6992 
6993 
6994 /* ----------------------------------------------------------------------------
6995    -- TPM Peripheral Access Layer
6996    ---------------------------------------------------------------------------- */
6997 
6998 /*!
6999  * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
7000  * @{
7001  */
7002 
7003 /** TPM - Register Layout Typedef */
7004 typedef struct {
7005   __IO uint32_t SC;                                /**< Status and Control, offset: 0x0 */
7006   __IO uint32_t CNT;                               /**< Counter, offset: 0x4 */
7007   __IO uint32_t MOD;                               /**< Modulo, offset: 0x8 */
7008   struct {                                         /* offset: 0xC, array step: 0x8 */
7009     __IO uint32_t CnSC;                              /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
7010     __IO uint32_t CnV;                               /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
7011   } CONTROLS[4];
7012        uint8_t RESERVED_0[36];
7013   __IO uint32_t STATUS;                            /**< Capture and Compare Status, offset: 0x50 */
7014        uint8_t RESERVED_1[16];
7015   __IO uint32_t COMBINE;                           /**< Combine Channel Register, offset: 0x64 */
7016        uint8_t RESERVED_2[8];
7017   __IO uint32_t POL;                               /**< Channel Polarity, offset: 0x70 */
7018        uint8_t RESERVED_3[4];
7019   __IO uint32_t FILTER;                            /**< Filter Control, offset: 0x78 */
7020        uint8_t RESERVED_4[4];
7021   __IO uint32_t QDCTRL;                            /**< Quadrature Decoder Control and Status, offset: 0x80 */
7022   __IO uint32_t CONF;                              /**< Configuration, offset: 0x84 */
7023 } TPM_Type;
7024 
7025 /* ----------------------------------------------------------------------------
7026    -- TPM Register Masks
7027    ---------------------------------------------------------------------------- */
7028 
7029 /*!
7030  * @addtogroup TPM_Register_Masks TPM Register Masks
7031  * @{
7032  */
7033 
7034 /*! @name SC - Status and Control */
7035 #define TPM_SC_PS_MASK                           (0x7U)
7036 #define TPM_SC_PS_SHIFT                          (0U)
7037 #define TPM_SC_PS(x)                             (((uint32_t)(((uint32_t)(x)) << TPM_SC_PS_SHIFT)) & TPM_SC_PS_MASK)
7038 #define TPM_SC_CMOD_MASK                         (0x18U)
7039 #define TPM_SC_CMOD_SHIFT                        (3U)
7040 #define TPM_SC_CMOD(x)                           (((uint32_t)(((uint32_t)(x)) << TPM_SC_CMOD_SHIFT)) & TPM_SC_CMOD_MASK)
7041 #define TPM_SC_CPWMS_MASK                        (0x20U)
7042 #define TPM_SC_CPWMS_SHIFT                       (5U)
7043 #define TPM_SC_CPWMS(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_SC_CPWMS_SHIFT)) & TPM_SC_CPWMS_MASK)
7044 #define TPM_SC_TOIE_MASK                         (0x40U)
7045 #define TPM_SC_TOIE_SHIFT                        (6U)
7046 #define TPM_SC_TOIE(x)                           (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOIE_SHIFT)) & TPM_SC_TOIE_MASK)
7047 #define TPM_SC_TOF_MASK                          (0x80U)
7048 #define TPM_SC_TOF_SHIFT                         (7U)
7049 #define TPM_SC_TOF(x)                            (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOF_SHIFT)) & TPM_SC_TOF_MASK)
7050 #define TPM_SC_DMA_MASK                          (0x100U)
7051 #define TPM_SC_DMA_SHIFT                         (8U)
7052 #define TPM_SC_DMA(x)                            (((uint32_t)(((uint32_t)(x)) << TPM_SC_DMA_SHIFT)) & TPM_SC_DMA_MASK)
7053 
7054 /*! @name CNT - Counter */
7055 #define TPM_CNT_COUNT_MASK                       (0xFFFFU)
7056 #define TPM_CNT_COUNT_SHIFT                      (0U)
7057 #define TPM_CNT_COUNT(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CNT_COUNT_SHIFT)) & TPM_CNT_COUNT_MASK)
7058 
7059 /*! @name MOD - Modulo */
7060 #define TPM_MOD_MOD_MASK                         (0xFFFFU)
7061 #define TPM_MOD_MOD_SHIFT                        (0U)
7062 #define TPM_MOD_MOD(x)                           (((uint32_t)(((uint32_t)(x)) << TPM_MOD_MOD_SHIFT)) & TPM_MOD_MOD_MASK)
7063 
7064 /*! @name CnSC - Channel (n) Status and Control */
7065 #define TPM_CnSC_DMA_MASK                        (0x1U)
7066 #define TPM_CnSC_DMA_SHIFT                       (0U)
7067 #define TPM_CnSC_DMA(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_DMA_SHIFT)) & TPM_CnSC_DMA_MASK)
7068 #define TPM_CnSC_ELSA_MASK                       (0x4U)
7069 #define TPM_CnSC_ELSA_SHIFT                      (2U)
7070 #define TPM_CnSC_ELSA(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSA_SHIFT)) & TPM_CnSC_ELSA_MASK)
7071 #define TPM_CnSC_ELSB_MASK                       (0x8U)
7072 #define TPM_CnSC_ELSB_SHIFT                      (3U)
7073 #define TPM_CnSC_ELSB(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSB_SHIFT)) & TPM_CnSC_ELSB_MASK)
7074 #define TPM_CnSC_MSA_MASK                        (0x10U)
7075 #define TPM_CnSC_MSA_SHIFT                       (4U)
7076 #define TPM_CnSC_MSA(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSA_SHIFT)) & TPM_CnSC_MSA_MASK)
7077 #define TPM_CnSC_MSB_MASK                        (0x20U)
7078 #define TPM_CnSC_MSB_SHIFT                       (5U)
7079 #define TPM_CnSC_MSB(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSB_SHIFT)) & TPM_CnSC_MSB_MASK)
7080 #define TPM_CnSC_CHIE_MASK                       (0x40U)
7081 #define TPM_CnSC_CHIE_SHIFT                      (6U)
7082 #define TPM_CnSC_CHIE(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHIE_SHIFT)) & TPM_CnSC_CHIE_MASK)
7083 #define TPM_CnSC_CHF_MASK                        (0x80U)
7084 #define TPM_CnSC_CHF_SHIFT                       (7U)
7085 #define TPM_CnSC_CHF(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHF_SHIFT)) & TPM_CnSC_CHF_MASK)
7086 
7087 /* The count of TPM_CnSC */
7088 #define TPM_CnSC_COUNT                           (4U)
7089 
7090 /*! @name CnV - Channel (n) Value */
7091 #define TPM_CnV_VAL_MASK                         (0xFFFFU)
7092 #define TPM_CnV_VAL_SHIFT                        (0U)
7093 #define TPM_CnV_VAL(x)                           (((uint32_t)(((uint32_t)(x)) << TPM_CnV_VAL_SHIFT)) & TPM_CnV_VAL_MASK)
7094 
7095 /* The count of TPM_CnV */
7096 #define TPM_CnV_COUNT                            (4U)
7097 
7098 /*! @name STATUS - Capture and Compare Status */
7099 #define TPM_STATUS_CH0F_MASK                     (0x1U)
7100 #define TPM_STATUS_CH0F_SHIFT                    (0U)
7101 #define TPM_STATUS_CH0F(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH0F_SHIFT)) & TPM_STATUS_CH0F_MASK)
7102 #define TPM_STATUS_CH1F_MASK                     (0x2U)
7103 #define TPM_STATUS_CH1F_SHIFT                    (1U)
7104 #define TPM_STATUS_CH1F(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH1F_SHIFT)) & TPM_STATUS_CH1F_MASK)
7105 #define TPM_STATUS_CH2F_MASK                     (0x4U)
7106 #define TPM_STATUS_CH2F_SHIFT                    (2U)
7107 #define TPM_STATUS_CH2F(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH2F_SHIFT)) & TPM_STATUS_CH2F_MASK)
7108 #define TPM_STATUS_CH3F_MASK                     (0x8U)
7109 #define TPM_STATUS_CH3F_SHIFT                    (3U)
7110 #define TPM_STATUS_CH3F(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH3F_SHIFT)) & TPM_STATUS_CH3F_MASK)
7111 #define TPM_STATUS_TOF_MASK                      (0x100U)
7112 #define TPM_STATUS_TOF_SHIFT                     (8U)
7113 #define TPM_STATUS_TOF(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_TOF_SHIFT)) & TPM_STATUS_TOF_MASK)
7114 
7115 /*! @name COMBINE - Combine Channel Register */
7116 #define TPM_COMBINE_COMBINE0_MASK                (0x1U)
7117 #define TPM_COMBINE_COMBINE0_SHIFT               (0U)
7118 #define TPM_COMBINE_COMBINE0(x)                  (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE0_SHIFT)) & TPM_COMBINE_COMBINE0_MASK)
7119 #define TPM_COMBINE_COMSWAP0_MASK                (0x2U)
7120 #define TPM_COMBINE_COMSWAP0_SHIFT               (1U)
7121 #define TPM_COMBINE_COMSWAP0(x)                  (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP0_SHIFT)) & TPM_COMBINE_COMSWAP0_MASK)
7122 #define TPM_COMBINE_COMBINE1_MASK                (0x100U)
7123 #define TPM_COMBINE_COMBINE1_SHIFT               (8U)
7124 #define TPM_COMBINE_COMBINE1(x)                  (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE1_SHIFT)) & TPM_COMBINE_COMBINE1_MASK)
7125 #define TPM_COMBINE_COMSWAP1_MASK                (0x200U)
7126 #define TPM_COMBINE_COMSWAP1_SHIFT               (9U)
7127 #define TPM_COMBINE_COMSWAP1(x)                  (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP1_SHIFT)) & TPM_COMBINE_COMSWAP1_MASK)
7128 
7129 /*! @name POL - Channel Polarity */
7130 #define TPM_POL_POL0_MASK                        (0x1U)
7131 #define TPM_POL_POL0_SHIFT                       (0U)
7132 #define TPM_POL_POL0(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL0_SHIFT)) & TPM_POL_POL0_MASK)
7133 #define TPM_POL_POL1_MASK                        (0x2U)
7134 #define TPM_POL_POL1_SHIFT                       (1U)
7135 #define TPM_POL_POL1(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL1_SHIFT)) & TPM_POL_POL1_MASK)
7136 #define TPM_POL_POL2_MASK                        (0x4U)
7137 #define TPM_POL_POL2_SHIFT                       (2U)
7138 #define TPM_POL_POL2(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL2_SHIFT)) & TPM_POL_POL2_MASK)
7139 #define TPM_POL_POL3_MASK                        (0x8U)
7140 #define TPM_POL_POL3_SHIFT                       (3U)
7141 #define TPM_POL_POL3(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL3_SHIFT)) & TPM_POL_POL3_MASK)
7142 
7143 /*! @name FILTER - Filter Control */
7144 #define TPM_FILTER_CH0FVAL_MASK                  (0xFU)
7145 #define TPM_FILTER_CH0FVAL_SHIFT                 (0U)
7146 #define TPM_FILTER_CH0FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH0FVAL_SHIFT)) & TPM_FILTER_CH0FVAL_MASK)
7147 #define TPM_FILTER_CH1FVAL_MASK                  (0xF0U)
7148 #define TPM_FILTER_CH1FVAL_SHIFT                 (4U)
7149 #define TPM_FILTER_CH1FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH1FVAL_SHIFT)) & TPM_FILTER_CH1FVAL_MASK)
7150 #define TPM_FILTER_CH2FVAL_MASK                  (0xF00U)
7151 #define TPM_FILTER_CH2FVAL_SHIFT                 (8U)
7152 #define TPM_FILTER_CH2FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH2FVAL_SHIFT)) & TPM_FILTER_CH2FVAL_MASK)
7153 #define TPM_FILTER_CH3FVAL_MASK                  (0xF000U)
7154 #define TPM_FILTER_CH3FVAL_SHIFT                 (12U)
7155 #define TPM_FILTER_CH3FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH3FVAL_SHIFT)) & TPM_FILTER_CH3FVAL_MASK)
7156 
7157 /*! @name QDCTRL - Quadrature Decoder Control and Status */
7158 #define TPM_QDCTRL_QUADEN_MASK                   (0x1U)
7159 #define TPM_QDCTRL_QUADEN_SHIFT                  (0U)
7160 #define TPM_QDCTRL_QUADEN(x)                     (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADEN_SHIFT)) & TPM_QDCTRL_QUADEN_MASK)
7161 #define TPM_QDCTRL_TOFDIR_MASK                   (0x2U)
7162 #define TPM_QDCTRL_TOFDIR_SHIFT                  (1U)
7163 #define TPM_QDCTRL_TOFDIR(x)                     (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_TOFDIR_SHIFT)) & TPM_QDCTRL_TOFDIR_MASK)
7164 #define TPM_QDCTRL_QUADIR_MASK                   (0x4U)
7165 #define TPM_QDCTRL_QUADIR_SHIFT                  (2U)
7166 #define TPM_QDCTRL_QUADIR(x)                     (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADIR_SHIFT)) & TPM_QDCTRL_QUADIR_MASK)
7167 #define TPM_QDCTRL_QUADMODE_MASK                 (0x8U)
7168 #define TPM_QDCTRL_QUADMODE_SHIFT                (3U)
7169 #define TPM_QDCTRL_QUADMODE(x)                   (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADMODE_SHIFT)) & TPM_QDCTRL_QUADMODE_MASK)
7170 
7171 /*! @name CONF - Configuration */
7172 #define TPM_CONF_DOZEEN_MASK                     (0x20U)
7173 #define TPM_CONF_DOZEEN_SHIFT                    (5U)
7174 #define TPM_CONF_DOZEEN(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DOZEEN_SHIFT)) & TPM_CONF_DOZEEN_MASK)
7175 #define TPM_CONF_DBGMODE_MASK                    (0xC0U)
7176 #define TPM_CONF_DBGMODE_SHIFT                   (6U)
7177 #define TPM_CONF_DBGMODE(x)                      (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DBGMODE_SHIFT)) & TPM_CONF_DBGMODE_MASK)
7178 #define TPM_CONF_GTBSYNC_MASK                    (0x100U)
7179 #define TPM_CONF_GTBSYNC_SHIFT                   (8U)
7180 #define TPM_CONF_GTBSYNC(x)                      (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBSYNC_SHIFT)) & TPM_CONF_GTBSYNC_MASK)
7181 #define TPM_CONF_GTBEEN_MASK                     (0x200U)
7182 #define TPM_CONF_GTBEEN_SHIFT                    (9U)
7183 #define TPM_CONF_GTBEEN(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBEEN_SHIFT)) & TPM_CONF_GTBEEN_MASK)
7184 #define TPM_CONF_CSOT_MASK                       (0x10000U)
7185 #define TPM_CONF_CSOT_SHIFT                      (16U)
7186 #define TPM_CONF_CSOT(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOT_SHIFT)) & TPM_CONF_CSOT_MASK)
7187 #define TPM_CONF_CSOO_MASK                       (0x20000U)
7188 #define TPM_CONF_CSOO_SHIFT                      (17U)
7189 #define TPM_CONF_CSOO(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOO_SHIFT)) & TPM_CONF_CSOO_MASK)
7190 #define TPM_CONF_CROT_MASK                       (0x40000U)
7191 #define TPM_CONF_CROT_SHIFT                      (18U)
7192 #define TPM_CONF_CROT(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CROT_SHIFT)) & TPM_CONF_CROT_MASK)
7193 #define TPM_CONF_CPOT_MASK                       (0x80000U)
7194 #define TPM_CONF_CPOT_SHIFT                      (19U)
7195 #define TPM_CONF_CPOT(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CPOT_SHIFT)) & TPM_CONF_CPOT_MASK)
7196 #define TPM_CONF_TRGPOL_MASK                     (0x400000U)
7197 #define TPM_CONF_TRGPOL_SHIFT                    (22U)
7198 #define TPM_CONF_TRGPOL(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGPOL_SHIFT)) & TPM_CONF_TRGPOL_MASK)
7199 #define TPM_CONF_TRGSRC_MASK                     (0x800000U)
7200 #define TPM_CONF_TRGSRC_SHIFT                    (23U)
7201 #define TPM_CONF_TRGSRC(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSRC_SHIFT)) & TPM_CONF_TRGSRC_MASK)
7202 #define TPM_CONF_TRGSEL_MASK                     (0xF000000U)
7203 #define TPM_CONF_TRGSEL_SHIFT                    (24U)
7204 #define TPM_CONF_TRGSEL(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSEL_SHIFT)) & TPM_CONF_TRGSEL_MASK)
7205 
7206 
7207 /*!
7208  * @}
7209  */ /* end of group TPM_Register_Masks */
7210 
7211 
7212 /* TPM - Peripheral instance base addresses */
7213 /** Peripheral TPM0 base address */
7214 #define TPM0_BASE                                (0x40038000u)
7215 /** Peripheral TPM0 base pointer */
7216 #define TPM0                                     ((TPM_Type *)TPM0_BASE)
7217 /** Peripheral TPM1 base address */
7218 #define TPM1_BASE                                (0x40039000u)
7219 /** Peripheral TPM1 base pointer */
7220 #define TPM1                                     ((TPM_Type *)TPM1_BASE)
7221 /** Peripheral TPM2 base address */
7222 #define TPM2_BASE                                (0x4003A000u)
7223 /** Peripheral TPM2 base pointer */
7224 #define TPM2                                     ((TPM_Type *)TPM2_BASE)
7225 /** Array initializer of TPM peripheral base addresses */
7226 #define TPM_BASE_ADDRS                           { TPM0_BASE, TPM1_BASE, TPM2_BASE }
7227 /** Array initializer of TPM peripheral base pointers */
7228 #define TPM_BASE_PTRS                            { TPM0, TPM1, TPM2 }
7229 /** Interrupt vectors for the TPM peripheral type */
7230 #define TPM_IRQS                                 { TPM0_IRQn, TPM1_IRQn, TPM2_IRQn }
7231 
7232 /*!
7233  * @}
7234  */ /* end of group TPM_Peripheral_Access_Layer */
7235 
7236 
7237 /* ----------------------------------------------------------------------------
7238    -- TRNG Peripheral Access Layer
7239    ---------------------------------------------------------------------------- */
7240 
7241 /*!
7242  * @addtogroup TRNG_Peripheral_Access_Layer TRNG Peripheral Access Layer
7243  * @{
7244  */
7245 
7246 /** TRNG - Register Layout Typedef */
7247 typedef struct {
7248   __IO uint32_t MCTL;                              /**< Miscellaneous Control Register, offset: 0x0 */
7249   __IO uint32_t SCMISC;                            /**< Statistical Check Miscellaneous Register, offset: 0x4 */
7250   __IO uint32_t PKRRNG;                            /**< Poker Range Register, offset: 0x8 */
7251   union {                                          /* offset: 0xC */
7252     __IO uint32_t PKRMAX;                            /**< Poker Maximum Limit Register, offset: 0xC */
7253     __I  uint32_t PKRSQ;                             /**< Poker Square Calculation Result Register, offset: 0xC */
7254   };
7255   __IO uint32_t SDCTL;                             /**< Seed Control Register, offset: 0x10 */
7256   union {                                          /* offset: 0x14 */
7257     __IO uint32_t SBLIM;                             /**< Sparse Bit Limit Register, offset: 0x14 */
7258     __I  uint32_t TOTSAM;                            /**< Total Samples Register, offset: 0x14 */
7259   };
7260   __IO uint32_t FRQMIN;                            /**< Frequency Count Minimum Limit Register, offset: 0x18 */
7261   union {                                          /* offset: 0x1C */
7262     __I  uint32_t FRQCNT;                            /**< Frequency Count Register, offset: 0x1C */
7263     __IO uint32_t FRQMAX;                            /**< Frequency Count Maximum Limit Register, offset: 0x1C */
7264   };
7265   union {                                          /* offset: 0x20 */
7266     __I  uint32_t SCMC;                              /**< Statistical Check Monobit Count Register, offset: 0x20 */
7267     __IO uint32_t SCML;                              /**< Statistical Check Monobit Limit Register, offset: 0x20 */
7268   };
7269   union {                                          /* offset: 0x24 */
7270     __I  uint32_t SCR1C;                             /**< Statistical Check Run Length 1 Count Register, offset: 0x24 */
7271     __IO uint32_t SCR1L;                             /**< Statistical Check Run Length 1 Limit Register, offset: 0x24 */
7272   };
7273   union {                                          /* offset: 0x28 */
7274     __I  uint32_t SCR2C;                             /**< Statistical Check Run Length 2 Count Register, offset: 0x28 */
7275     __IO uint32_t SCR2L;                             /**< Statistical Check Run Length 2 Limit Register, offset: 0x28 */
7276   };
7277   union {                                          /* offset: 0x2C */
7278     __I  uint32_t SCR3C;                             /**< Statistical Check Run Length 3 Count Register, offset: 0x2C */
7279     __IO uint32_t SCR3L;                             /**< Statistical Check Run Length 3 Limit Register, offset: 0x2C */
7280   };
7281   union {                                          /* offset: 0x30 */
7282     __I  uint32_t SCR4C;                             /**< Statistical Check Run Length 4 Count Register, offset: 0x30 */
7283     __IO uint32_t SCR4L;                             /**< Statistical Check Run Length 4 Limit Register, offset: 0x30 */
7284   };
7285   union {                                          /* offset: 0x34 */
7286     __I  uint32_t SCR5C;                             /**< Statistical Check Run Length 5 Count Register, offset: 0x34 */
7287     __IO uint32_t SCR5L;                             /**< Statistical Check Run Length 5 Limit Register, offset: 0x34 */
7288   };
7289   union {                                          /* offset: 0x38 */
7290     __I  uint32_t SCR6PC;                            /**< Statistical Check Run Length 6+ Count Register, offset: 0x38 */
7291     __IO uint32_t SCR6PL;                            /**< Statistical Check Run Length 6+ Limit Register, offset: 0x38 */
7292   };
7293   __I  uint32_t STATUS;                            /**< Status Register, offset: 0x3C */
7294   __I  uint32_t ENT[16];                           /**< Entropy Read Register, array offset: 0x40, array step: 0x4 */
7295   __I  uint32_t PKRCNT10;                          /**< Statistical Check Poker Count 1 and 0 Register, offset: 0x80 */
7296   __I  uint32_t PKRCNT32;                          /**< Statistical Check Poker Count 3 and 2 Register, offset: 0x84 */
7297   __I  uint32_t PKRCNT54;                          /**< Statistical Check Poker Count 5 and 4 Register, offset: 0x88 */
7298   __I  uint32_t PKRCNT76;                          /**< Statistical Check Poker Count 7 and 6 Register, offset: 0x8C */
7299   __I  uint32_t PKRCNT98;                          /**< Statistical Check Poker Count 9 and 8 Register, offset: 0x90 */
7300   __I  uint32_t PKRCNTBA;                          /**< Statistical Check Poker Count B and A Register, offset: 0x94 */
7301   __I  uint32_t PKRCNTDC;                          /**< Statistical Check Poker Count D and C Register, offset: 0x98 */
7302   __I  uint32_t PKRCNTFE;                          /**< Statistical Check Poker Count F and E Register, offset: 0x9C */
7303        uint8_t RESERVED_0[16];
7304   __IO uint32_t SEC_CFG;                           /**< Security Configuration Register, offset: 0xB0 */
7305   __IO uint32_t INT_CTRL;                          /**< Interrupt Control Register, offset: 0xB4 */
7306   __IO uint32_t INT_MASK;                          /**< Mask Register, offset: 0xB8 */
7307   __IO uint32_t INT_STATUS;                        /**< Interrupt Status Register, offset: 0xBC */
7308        uint8_t RESERVED_1[48];
7309   __I  uint32_t VID1;                              /**< Version ID Register (MS), offset: 0xF0 */
7310   __I  uint32_t VID2;                              /**< Version ID Register (LS), offset: 0xF4 */
7311 } TRNG_Type;
7312 
7313 /* ----------------------------------------------------------------------------
7314    -- TRNG Register Masks
7315    ---------------------------------------------------------------------------- */
7316 
7317 /*!
7318  * @addtogroup TRNG_Register_Masks TRNG Register Masks
7319  * @{
7320  */
7321 
7322 /*! @name MCTL - Miscellaneous Control Register */
7323 #define TRNG_MCTL_SAMP_MODE_MASK                 (0x3U)
7324 #define TRNG_MCTL_SAMP_MODE_SHIFT                (0U)
7325 #define TRNG_MCTL_SAMP_MODE(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_SAMP_MODE_SHIFT)) & TRNG_MCTL_SAMP_MODE_MASK)
7326 #define TRNG_MCTL_OSC_DIV_MASK                   (0xCU)
7327 #define TRNG_MCTL_OSC_DIV_SHIFT                  (2U)
7328 #define TRNG_MCTL_OSC_DIV(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_OSC_DIV_SHIFT)) & TRNG_MCTL_OSC_DIV_MASK)
7329 #define TRNG_MCTL_UNUSED_MASK                    (0x10U)
7330 #define TRNG_MCTL_UNUSED_SHIFT                   (4U)
7331 #define TRNG_MCTL_UNUSED(x)                      (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_UNUSED_SHIFT)) & TRNG_MCTL_UNUSED_MASK)
7332 #define TRNG_MCTL_TRNG_ACC_MASK                  (0x20U)
7333 #define TRNG_MCTL_TRNG_ACC_SHIFT                 (5U)
7334 #define TRNG_MCTL_TRNG_ACC(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TRNG_ACC_SHIFT)) & TRNG_MCTL_TRNG_ACC_MASK)
7335 #define TRNG_MCTL_RST_DEF_MASK                   (0x40U)
7336 #define TRNG_MCTL_RST_DEF_SHIFT                  (6U)
7337 #define TRNG_MCTL_RST_DEF(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_RST_DEF_SHIFT)) & TRNG_MCTL_RST_DEF_MASK)
7338 #define TRNG_MCTL_FOR_SCLK_MASK                  (0x80U)
7339 #define TRNG_MCTL_FOR_SCLK_SHIFT                 (7U)
7340 #define TRNG_MCTL_FOR_SCLK(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FOR_SCLK_SHIFT)) & TRNG_MCTL_FOR_SCLK_MASK)
7341 #define TRNG_MCTL_FCT_FAIL_MASK                  (0x100U)
7342 #define TRNG_MCTL_FCT_FAIL_SHIFT                 (8U)
7343 #define TRNG_MCTL_FCT_FAIL(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_FAIL_SHIFT)) & TRNG_MCTL_FCT_FAIL_MASK)
7344 #define TRNG_MCTL_FCT_VAL_MASK                   (0x200U)
7345 #define TRNG_MCTL_FCT_VAL_SHIFT                  (9U)
7346 #define TRNG_MCTL_FCT_VAL(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_VAL_SHIFT)) & TRNG_MCTL_FCT_VAL_MASK)
7347 #define TRNG_MCTL_ENT_VAL_MASK                   (0x400U)
7348 #define TRNG_MCTL_ENT_VAL_SHIFT                  (10U)
7349 #define TRNG_MCTL_ENT_VAL(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ENT_VAL_SHIFT)) & TRNG_MCTL_ENT_VAL_MASK)
7350 #define TRNG_MCTL_TST_OUT_MASK                   (0x800U)
7351 #define TRNG_MCTL_TST_OUT_SHIFT                  (11U)
7352 #define TRNG_MCTL_TST_OUT(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TST_OUT_SHIFT)) & TRNG_MCTL_TST_OUT_MASK)
7353 #define TRNG_MCTL_ERR_MASK                       (0x1000U)
7354 #define TRNG_MCTL_ERR_SHIFT                      (12U)
7355 #define TRNG_MCTL_ERR(x)                         (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ERR_SHIFT)) & TRNG_MCTL_ERR_MASK)
7356 #define TRNG_MCTL_TSTOP_OK_MASK                  (0x2000U)
7357 #define TRNG_MCTL_TSTOP_OK_SHIFT                 (13U)
7358 #define TRNG_MCTL_TSTOP_OK(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TSTOP_OK_SHIFT)) & TRNG_MCTL_TSTOP_OK_MASK)
7359 #define TRNG_MCTL_PRGM_MASK                      (0x10000U)
7360 #define TRNG_MCTL_PRGM_SHIFT                     (16U)
7361 #define TRNG_MCTL_PRGM(x)                        (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_PRGM_SHIFT)) & TRNG_MCTL_PRGM_MASK)
7362 
7363 /*! @name SCMISC - Statistical Check Miscellaneous Register */
7364 #define TRNG_SCMISC_LRUN_MAX_MASK                (0xFFU)
7365 #define TRNG_SCMISC_LRUN_MAX_SHIFT               (0U)
7366 #define TRNG_SCMISC_LRUN_MAX(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_LRUN_MAX_SHIFT)) & TRNG_SCMISC_LRUN_MAX_MASK)
7367 #define TRNG_SCMISC_RTY_CT_MASK                  (0xF0000U)
7368 #define TRNG_SCMISC_RTY_CT_SHIFT                 (16U)
7369 #define TRNG_SCMISC_RTY_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_RTY_CT_SHIFT)) & TRNG_SCMISC_RTY_CT_MASK)
7370 
7371 /*! @name PKRRNG - Poker Range Register */
7372 #define TRNG_PKRRNG_PKR_RNG_MASK                 (0xFFFFU)
7373 #define TRNG_PKRRNG_PKR_RNG_SHIFT                (0U)
7374 #define TRNG_PKRRNG_PKR_RNG(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_PKRRNG_PKR_RNG_SHIFT)) & TRNG_PKRRNG_PKR_RNG_MASK)
7375 
7376 /*! @name PKRMAX - Poker Maximum Limit Register */
7377 #define TRNG_PKRMAX_PKR_MAX_MASK                 (0xFFFFFFU)
7378 #define TRNG_PKRMAX_PKR_MAX_SHIFT                (0U)
7379 #define TRNG_PKRMAX_PKR_MAX(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_PKRMAX_PKR_MAX_SHIFT)) & TRNG_PKRMAX_PKR_MAX_MASK)
7380 
7381 /*! @name PKRSQ - Poker Square Calculation Result Register */
7382 #define TRNG_PKRSQ_PKR_SQ_MASK                   (0xFFFFFFU)
7383 #define TRNG_PKRSQ_PKR_SQ_SHIFT                  (0U)
7384 #define TRNG_PKRSQ_PKR_SQ(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_PKRSQ_PKR_SQ_SHIFT)) & TRNG_PKRSQ_PKR_SQ_MASK)
7385 
7386 /*! @name SDCTL - Seed Control Register */
7387 #define TRNG_SDCTL_SAMP_SIZE_MASK                (0xFFFFU)
7388 #define TRNG_SDCTL_SAMP_SIZE_SHIFT               (0U)
7389 #define TRNG_SDCTL_SAMP_SIZE(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_SAMP_SIZE_SHIFT)) & TRNG_SDCTL_SAMP_SIZE_MASK)
7390 #define TRNG_SDCTL_ENT_DLY_MASK                  (0xFFFF0000U)
7391 #define TRNG_SDCTL_ENT_DLY_SHIFT                 (16U)
7392 #define TRNG_SDCTL_ENT_DLY(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_ENT_DLY_SHIFT)) & TRNG_SDCTL_ENT_DLY_MASK)
7393 
7394 /*! @name SBLIM - Sparse Bit Limit Register */
7395 #define TRNG_SBLIM_SB_LIM_MASK                   (0x3FFU)
7396 #define TRNG_SBLIM_SB_LIM_SHIFT                  (0U)
7397 #define TRNG_SBLIM_SB_LIM(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_SBLIM_SB_LIM_SHIFT)) & TRNG_SBLIM_SB_LIM_MASK)
7398 
7399 /*! @name TOTSAM - Total Samples Register */
7400 #define TRNG_TOTSAM_TOT_SAM_MASK                 (0xFFFFFU)
7401 #define TRNG_TOTSAM_TOT_SAM_SHIFT                (0U)
7402 #define TRNG_TOTSAM_TOT_SAM(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_TOTSAM_TOT_SAM_SHIFT)) & TRNG_TOTSAM_TOT_SAM_MASK)
7403 
7404 /*! @name FRQMIN - Frequency Count Minimum Limit Register */
7405 #define TRNG_FRQMIN_FRQ_MIN_MASK                 (0x3FFFFFU)
7406 #define TRNG_FRQMIN_FRQ_MIN_SHIFT                (0U)
7407 #define TRNG_FRQMIN_FRQ_MIN(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMIN_FRQ_MIN_SHIFT)) & TRNG_FRQMIN_FRQ_MIN_MASK)
7408 
7409 /*! @name FRQCNT - Frequency Count Register */
7410 #define TRNG_FRQCNT_FRQ_CT_MASK                  (0x3FFFFFU)
7411 #define TRNG_FRQCNT_FRQ_CT_SHIFT                 (0U)
7412 #define TRNG_FRQCNT_FRQ_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_FRQCNT_FRQ_CT_SHIFT)) & TRNG_FRQCNT_FRQ_CT_MASK)
7413 
7414 /*! @name FRQMAX - Frequency Count Maximum Limit Register */
7415 #define TRNG_FRQMAX_FRQ_MAX_MASK                 (0x3FFFFFU)
7416 #define TRNG_FRQMAX_FRQ_MAX_SHIFT                (0U)
7417 #define TRNG_FRQMAX_FRQ_MAX(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMAX_FRQ_MAX_SHIFT)) & TRNG_FRQMAX_FRQ_MAX_MASK)
7418 
7419 /*! @name SCMC - Statistical Check Monobit Count Register */
7420 #define TRNG_SCMC_MONO_CT_MASK                   (0xFFFFU)
7421 #define TRNG_SCMC_MONO_CT_SHIFT                  (0U)
7422 #define TRNG_SCMC_MONO_CT(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_SCMC_MONO_CT_SHIFT)) & TRNG_SCMC_MONO_CT_MASK)
7423 
7424 /*! @name SCML - Statistical Check Monobit Limit Register */
7425 #define TRNG_SCML_MONO_MAX_MASK                  (0xFFFFU)
7426 #define TRNG_SCML_MONO_MAX_SHIFT                 (0U)
7427 #define TRNG_SCML_MONO_MAX(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_MAX_SHIFT)) & TRNG_SCML_MONO_MAX_MASK)
7428 #define TRNG_SCML_MONO_RNG_MASK                  (0xFFFF0000U)
7429 #define TRNG_SCML_MONO_RNG_SHIFT                 (16U)
7430 #define TRNG_SCML_MONO_RNG(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_RNG_SHIFT)) & TRNG_SCML_MONO_RNG_MASK)
7431 
7432 /*! @name SCR1C - Statistical Check Run Length 1 Count Register */
7433 #define TRNG_SCR1C_R1_0_CT_MASK                  (0x7FFFU)
7434 #define TRNG_SCR1C_R1_0_CT_SHIFT                 (0U)
7435 #define TRNG_SCR1C_R1_0_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_0_CT_SHIFT)) & TRNG_SCR1C_R1_0_CT_MASK)
7436 #define TRNG_SCR1C_R1_1_CT_MASK                  (0x7FFF0000U)
7437 #define TRNG_SCR1C_R1_1_CT_SHIFT                 (16U)
7438 #define TRNG_SCR1C_R1_1_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_1_CT_SHIFT)) & TRNG_SCR1C_R1_1_CT_MASK)
7439 
7440 /*! @name SCR1L - Statistical Check Run Length 1 Limit Register */
7441 #define TRNG_SCR1L_RUN1_MAX_MASK                 (0x7FFFU)
7442 #define TRNG_SCR1L_RUN1_MAX_SHIFT                (0U)
7443 #define TRNG_SCR1L_RUN1_MAX(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_MAX_SHIFT)) & TRNG_SCR1L_RUN1_MAX_MASK)
7444 #define TRNG_SCR1L_RUN1_RNG_MASK                 (0x7FFF0000U)
7445 #define TRNG_SCR1L_RUN1_RNG_SHIFT                (16U)
7446 #define TRNG_SCR1L_RUN1_RNG(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_RNG_SHIFT)) & TRNG_SCR1L_RUN1_RNG_MASK)
7447 
7448 /*! @name SCR2C - Statistical Check Run Length 2 Count Register */
7449 #define TRNG_SCR2C_R2_0_CT_MASK                  (0x3FFFU)
7450 #define TRNG_SCR2C_R2_0_CT_SHIFT                 (0U)
7451 #define TRNG_SCR2C_R2_0_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_0_CT_SHIFT)) & TRNG_SCR2C_R2_0_CT_MASK)
7452 #define TRNG_SCR2C_R2_1_CT_MASK                  (0x3FFF0000U)
7453 #define TRNG_SCR2C_R2_1_CT_SHIFT                 (16U)
7454 #define TRNG_SCR2C_R2_1_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_1_CT_SHIFT)) & TRNG_SCR2C_R2_1_CT_MASK)
7455 
7456 /*! @name SCR2L - Statistical Check Run Length 2 Limit Register */
7457 #define TRNG_SCR2L_RUN2_MAX_MASK                 (0x3FFFU)
7458 #define TRNG_SCR2L_RUN2_MAX_SHIFT                (0U)
7459 #define TRNG_SCR2L_RUN2_MAX(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_MAX_SHIFT)) & TRNG_SCR2L_RUN2_MAX_MASK)
7460 #define TRNG_SCR2L_RUN2_RNG_MASK                 (0x3FFF0000U)
7461 #define TRNG_SCR2L_RUN2_RNG_SHIFT                (16U)
7462 #define TRNG_SCR2L_RUN2_RNG(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_RNG_SHIFT)) & TRNG_SCR2L_RUN2_RNG_MASK)
7463 
7464 /*! @name SCR3C - Statistical Check Run Length 3 Count Register */
7465 #define TRNG_SCR3C_R3_0_CT_MASK                  (0x1FFFU)
7466 #define TRNG_SCR3C_R3_0_CT_SHIFT                 (0U)
7467 #define TRNG_SCR3C_R3_0_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_0_CT_SHIFT)) & TRNG_SCR3C_R3_0_CT_MASK)
7468 #define TRNG_SCR3C_R3_1_CT_MASK                  (0x1FFF0000U)
7469 #define TRNG_SCR3C_R3_1_CT_SHIFT                 (16U)
7470 #define TRNG_SCR3C_R3_1_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_1_CT_SHIFT)) & TRNG_SCR3C_R3_1_CT_MASK)
7471 
7472 /*! @name SCR3L - Statistical Check Run Length 3 Limit Register */
7473 #define TRNG_SCR3L_RUN3_MAX_MASK                 (0x1FFFU)
7474 #define TRNG_SCR3L_RUN3_MAX_SHIFT                (0U)
7475 #define TRNG_SCR3L_RUN3_MAX(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_MAX_SHIFT)) & TRNG_SCR3L_RUN3_MAX_MASK)
7476 #define TRNG_SCR3L_RUN3_RNG_MASK                 (0x1FFF0000U)
7477 #define TRNG_SCR3L_RUN3_RNG_SHIFT                (16U)
7478 #define TRNG_SCR3L_RUN3_RNG(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_RNG_SHIFT)) & TRNG_SCR3L_RUN3_RNG_MASK)
7479 
7480 /*! @name SCR4C - Statistical Check Run Length 4 Count Register */
7481 #define TRNG_SCR4C_R4_0_CT_MASK                  (0xFFFU)
7482 #define TRNG_SCR4C_R4_0_CT_SHIFT                 (0U)
7483 #define TRNG_SCR4C_R4_0_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_0_CT_SHIFT)) & TRNG_SCR4C_R4_0_CT_MASK)
7484 #define TRNG_SCR4C_R4_1_CT_MASK                  (0xFFF0000U)
7485 #define TRNG_SCR4C_R4_1_CT_SHIFT                 (16U)
7486 #define TRNG_SCR4C_R4_1_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_1_CT_SHIFT)) & TRNG_SCR4C_R4_1_CT_MASK)
7487 
7488 /*! @name SCR4L - Statistical Check Run Length 4 Limit Register */
7489 #define TRNG_SCR4L_RUN4_MAX_MASK                 (0xFFFU)
7490 #define TRNG_SCR4L_RUN4_MAX_SHIFT                (0U)
7491 #define TRNG_SCR4L_RUN4_MAX(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_MAX_SHIFT)) & TRNG_SCR4L_RUN4_MAX_MASK)
7492 #define TRNG_SCR4L_RUN4_RNG_MASK                 (0xFFF0000U)
7493 #define TRNG_SCR4L_RUN4_RNG_SHIFT                (16U)
7494 #define TRNG_SCR4L_RUN4_RNG(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_RNG_SHIFT)) & TRNG_SCR4L_RUN4_RNG_MASK)
7495 
7496 /*! @name SCR5C - Statistical Check Run Length 5 Count Register */
7497 #define TRNG_SCR5C_R5_0_CT_MASK                  (0x7FFU)
7498 #define TRNG_SCR5C_R5_0_CT_SHIFT                 (0U)
7499 #define TRNG_SCR5C_R5_0_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_0_CT_SHIFT)) & TRNG_SCR5C_R5_0_CT_MASK)
7500 #define TRNG_SCR5C_R5_1_CT_MASK                  (0x7FF0000U)
7501 #define TRNG_SCR5C_R5_1_CT_SHIFT                 (16U)
7502 #define TRNG_SCR5C_R5_1_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_1_CT_SHIFT)) & TRNG_SCR5C_R5_1_CT_MASK)
7503 
7504 /*! @name SCR5L - Statistical Check Run Length 5 Limit Register */
7505 #define TRNG_SCR5L_RUN5_MAX_MASK                 (0x7FFU)
7506 #define TRNG_SCR5L_RUN5_MAX_SHIFT                (0U)
7507 #define TRNG_SCR5L_RUN5_MAX(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_MAX_SHIFT)) & TRNG_SCR5L_RUN5_MAX_MASK)
7508 #define TRNG_SCR5L_RUN5_RNG_MASK                 (0x7FF0000U)
7509 #define TRNG_SCR5L_RUN5_RNG_SHIFT                (16U)
7510 #define TRNG_SCR5L_RUN5_RNG(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_RNG_SHIFT)) & TRNG_SCR5L_RUN5_RNG_MASK)
7511 
7512 /*! @name SCR6PC - Statistical Check Run Length 6+ Count Register */
7513 #define TRNG_SCR6PC_R6P_0_CT_MASK                (0x7FFU)
7514 #define TRNG_SCR6PC_R6P_0_CT_SHIFT               (0U)
7515 #define TRNG_SCR6PC_R6P_0_CT(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_0_CT_SHIFT)) & TRNG_SCR6PC_R6P_0_CT_MASK)
7516 #define TRNG_SCR6PC_R6P_1_CT_MASK                (0x7FF0000U)
7517 #define TRNG_SCR6PC_R6P_1_CT_SHIFT               (16U)
7518 #define TRNG_SCR6PC_R6P_1_CT(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_1_CT_SHIFT)) & TRNG_SCR6PC_R6P_1_CT_MASK)
7519 
7520 /*! @name SCR6PL - Statistical Check Run Length 6+ Limit Register */
7521 #define TRNG_SCR6PL_RUN6P_MAX_MASK               (0x7FFU)
7522 #define TRNG_SCR6PL_RUN6P_MAX_SHIFT              (0U)
7523 #define TRNG_SCR6PL_RUN6P_MAX(x)                 (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_MAX_SHIFT)) & TRNG_SCR6PL_RUN6P_MAX_MASK)
7524 #define TRNG_SCR6PL_RUN6P_RNG_MASK               (0x7FF0000U)
7525 #define TRNG_SCR6PL_RUN6P_RNG_SHIFT              (16U)
7526 #define TRNG_SCR6PL_RUN6P_RNG(x)                 (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_RNG_SHIFT)) & TRNG_SCR6PL_RUN6P_RNG_MASK)
7527 
7528 /*! @name STATUS - Status Register */
7529 #define TRNG_STATUS_TF1BR0_MASK                  (0x1U)
7530 #define TRNG_STATUS_TF1BR0_SHIFT                 (0U)
7531 #define TRNG_STATUS_TF1BR0(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR0_SHIFT)) & TRNG_STATUS_TF1BR0_MASK)
7532 #define TRNG_STATUS_TF1BR1_MASK                  (0x2U)
7533 #define TRNG_STATUS_TF1BR1_SHIFT                 (1U)
7534 #define TRNG_STATUS_TF1BR1(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR1_SHIFT)) & TRNG_STATUS_TF1BR1_MASK)
7535 #define TRNG_STATUS_TF2BR0_MASK                  (0x4U)
7536 #define TRNG_STATUS_TF2BR0_SHIFT                 (2U)
7537 #define TRNG_STATUS_TF2BR0(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR0_SHIFT)) & TRNG_STATUS_TF2BR0_MASK)
7538 #define TRNG_STATUS_TF2BR1_MASK                  (0x8U)
7539 #define TRNG_STATUS_TF2BR1_SHIFT                 (3U)
7540 #define TRNG_STATUS_TF2BR1(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR1_SHIFT)) & TRNG_STATUS_TF2BR1_MASK)
7541 #define TRNG_STATUS_TF3BR0_MASK                  (0x10U)
7542 #define TRNG_STATUS_TF3BR0_SHIFT                 (4U)
7543 #define TRNG_STATUS_TF3BR0(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR0_SHIFT)) & TRNG_STATUS_TF3BR0_MASK)
7544 #define TRNG_STATUS_TF3BR1_MASK                  (0x20U)
7545 #define TRNG_STATUS_TF3BR1_SHIFT                 (5U)
7546 #define TRNG_STATUS_TF3BR1(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR1_SHIFT)) & TRNG_STATUS_TF3BR1_MASK)
7547 #define TRNG_STATUS_TF4BR0_MASK                  (0x40U)
7548 #define TRNG_STATUS_TF4BR0_SHIFT                 (6U)
7549 #define TRNG_STATUS_TF4BR0(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR0_SHIFT)) & TRNG_STATUS_TF4BR0_MASK)
7550 #define TRNG_STATUS_TF4BR1_MASK                  (0x80U)
7551 #define TRNG_STATUS_TF4BR1_SHIFT                 (7U)
7552 #define TRNG_STATUS_TF4BR1(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR1_SHIFT)) & TRNG_STATUS_TF4BR1_MASK)
7553 #define TRNG_STATUS_TF5BR0_MASK                  (0x100U)
7554 #define TRNG_STATUS_TF5BR0_SHIFT                 (8U)
7555 #define TRNG_STATUS_TF5BR0(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR0_SHIFT)) & TRNG_STATUS_TF5BR0_MASK)
7556 #define TRNG_STATUS_TF5BR1_MASK                  (0x200U)
7557 #define TRNG_STATUS_TF5BR1_SHIFT                 (9U)
7558 #define TRNG_STATUS_TF5BR1(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR1_SHIFT)) & TRNG_STATUS_TF5BR1_MASK)
7559 #define TRNG_STATUS_TF6PBR0_MASK                 (0x400U)
7560 #define TRNG_STATUS_TF6PBR0_SHIFT                (10U)
7561 #define TRNG_STATUS_TF6PBR0(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR0_SHIFT)) & TRNG_STATUS_TF6PBR0_MASK)
7562 #define TRNG_STATUS_TF6PBR1_MASK                 (0x800U)
7563 #define TRNG_STATUS_TF6PBR1_SHIFT                (11U)
7564 #define TRNG_STATUS_TF6PBR1(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR1_SHIFT)) & TRNG_STATUS_TF6PBR1_MASK)
7565 #define TRNG_STATUS_TFSB_MASK                    (0x1000U)
7566 #define TRNG_STATUS_TFSB_SHIFT                   (12U)
7567 #define TRNG_STATUS_TFSB(x)                      (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFSB_SHIFT)) & TRNG_STATUS_TFSB_MASK)
7568 #define TRNG_STATUS_TFLR_MASK                    (0x2000U)
7569 #define TRNG_STATUS_TFLR_SHIFT                   (13U)
7570 #define TRNG_STATUS_TFLR(x)                      (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFLR_SHIFT)) & TRNG_STATUS_TFLR_MASK)
7571 #define TRNG_STATUS_TFP_MASK                     (0x4000U)
7572 #define TRNG_STATUS_TFP_SHIFT                    (14U)
7573 #define TRNG_STATUS_TFP(x)                       (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFP_SHIFT)) & TRNG_STATUS_TFP_MASK)
7574 #define TRNG_STATUS_TFMB_MASK                    (0x8000U)
7575 #define TRNG_STATUS_TFMB_SHIFT                   (15U)
7576 #define TRNG_STATUS_TFMB(x)                      (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFMB_SHIFT)) & TRNG_STATUS_TFMB_MASK)
7577 #define TRNG_STATUS_RETRY_CT_MASK                (0xF0000U)
7578 #define TRNG_STATUS_RETRY_CT_SHIFT               (16U)
7579 #define TRNG_STATUS_RETRY_CT(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_RETRY_CT_SHIFT)) & TRNG_STATUS_RETRY_CT_MASK)
7580 
7581 /*! @name ENT - Entropy Read Register */
7582 #define TRNG_ENT_ENT_MASK                        (0xFFFFFFFFU)
7583 #define TRNG_ENT_ENT_SHIFT                       (0U)
7584 #define TRNG_ENT_ENT(x)                          (((uint32_t)(((uint32_t)(x)) << TRNG_ENT_ENT_SHIFT)) & TRNG_ENT_ENT_MASK)
7585 
7586 /* The count of TRNG_ENT */
7587 #define TRNG_ENT_COUNT                           (16U)
7588 
7589 /*! @name PKRCNT10 - Statistical Check Poker Count 1 and 0 Register */
7590 #define TRNG_PKRCNT10_PKR_0_CT_MASK              (0xFFFFU)
7591 #define TRNG_PKRCNT10_PKR_0_CT_SHIFT             (0U)
7592 #define TRNG_PKRCNT10_PKR_0_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_0_CT_SHIFT)) & TRNG_PKRCNT10_PKR_0_CT_MASK)
7593 #define TRNG_PKRCNT10_PKR_1_CT_MASK              (0xFFFF0000U)
7594 #define TRNG_PKRCNT10_PKR_1_CT_SHIFT             (16U)
7595 #define TRNG_PKRCNT10_PKR_1_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_1_CT_SHIFT)) & TRNG_PKRCNT10_PKR_1_CT_MASK)
7596 
7597 /*! @name PKRCNT32 - Statistical Check Poker Count 3 and 2 Register */
7598 #define TRNG_PKRCNT32_PKR_2_CT_MASK              (0xFFFFU)
7599 #define TRNG_PKRCNT32_PKR_2_CT_SHIFT             (0U)
7600 #define TRNG_PKRCNT32_PKR_2_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_2_CT_SHIFT)) & TRNG_PKRCNT32_PKR_2_CT_MASK)
7601 #define TRNG_PKRCNT32_PKR_3_CT_MASK              (0xFFFF0000U)
7602 #define TRNG_PKRCNT32_PKR_3_CT_SHIFT             (16U)
7603 #define TRNG_PKRCNT32_PKR_3_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_3_CT_SHIFT)) & TRNG_PKRCNT32_PKR_3_CT_MASK)
7604 
7605 /*! @name PKRCNT54 - Statistical Check Poker Count 5 and 4 Register */
7606 #define TRNG_PKRCNT54_PKR_4_CT_MASK              (0xFFFFU)
7607 #define TRNG_PKRCNT54_PKR_4_CT_SHIFT             (0U)
7608 #define TRNG_PKRCNT54_PKR_4_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_4_CT_SHIFT)) & TRNG_PKRCNT54_PKR_4_CT_MASK)
7609 #define TRNG_PKRCNT54_PKR_5_CT_MASK              (0xFFFF0000U)
7610 #define TRNG_PKRCNT54_PKR_5_CT_SHIFT             (16U)
7611 #define TRNG_PKRCNT54_PKR_5_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_5_CT_SHIFT)) & TRNG_PKRCNT54_PKR_5_CT_MASK)
7612 
7613 /*! @name PKRCNT76 - Statistical Check Poker Count 7 and 6 Register */
7614 #define TRNG_PKRCNT76_PKR_6_CT_MASK              (0xFFFFU)
7615 #define TRNG_PKRCNT76_PKR_6_CT_SHIFT             (0U)
7616 #define TRNG_PKRCNT76_PKR_6_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_6_CT_SHIFT)) & TRNG_PKRCNT76_PKR_6_CT_MASK)
7617 #define TRNG_PKRCNT76_PKR_7_CT_MASK              (0xFFFF0000U)
7618 #define TRNG_PKRCNT76_PKR_7_CT_SHIFT             (16U)
7619 #define TRNG_PKRCNT76_PKR_7_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_7_CT_SHIFT)) & TRNG_PKRCNT76_PKR_7_CT_MASK)
7620 
7621 /*! @name PKRCNT98 - Statistical Check Poker Count 9 and 8 Register */
7622 #define TRNG_PKRCNT98_PKR_8_CT_MASK              (0xFFFFU)
7623 #define TRNG_PKRCNT98_PKR_8_CT_SHIFT             (0U)
7624 #define TRNG_PKRCNT98_PKR_8_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_8_CT_SHIFT)) & TRNG_PKRCNT98_PKR_8_CT_MASK)
7625 #define TRNG_PKRCNT98_PKR_9_CT_MASK              (0xFFFF0000U)
7626 #define TRNG_PKRCNT98_PKR_9_CT_SHIFT             (16U)
7627 #define TRNG_PKRCNT98_PKR_9_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_9_CT_SHIFT)) & TRNG_PKRCNT98_PKR_9_CT_MASK)
7628 
7629 /*! @name PKRCNTBA - Statistical Check Poker Count B and A Register */
7630 #define TRNG_PKRCNTBA_PKR_A_CT_MASK              (0xFFFFU)
7631 #define TRNG_PKRCNTBA_PKR_A_CT_SHIFT             (0U)
7632 #define TRNG_PKRCNTBA_PKR_A_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_A_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_A_CT_MASK)
7633 #define TRNG_PKRCNTBA_PKR_B_CT_MASK              (0xFFFF0000U)
7634 #define TRNG_PKRCNTBA_PKR_B_CT_SHIFT             (16U)
7635 #define TRNG_PKRCNTBA_PKR_B_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_B_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_B_CT_MASK)
7636 
7637 /*! @name PKRCNTDC - Statistical Check Poker Count D and C Register */
7638 #define TRNG_PKRCNTDC_PKR_C_CT_MASK              (0xFFFFU)
7639 #define TRNG_PKRCNTDC_PKR_C_CT_SHIFT             (0U)
7640 #define TRNG_PKRCNTDC_PKR_C_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_C_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_C_CT_MASK)
7641 #define TRNG_PKRCNTDC_PKR_D_CT_MASK              (0xFFFF0000U)
7642 #define TRNG_PKRCNTDC_PKR_D_CT_SHIFT             (16U)
7643 #define TRNG_PKRCNTDC_PKR_D_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_D_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_D_CT_MASK)
7644 
7645 /*! @name PKRCNTFE - Statistical Check Poker Count F and E Register */
7646 #define TRNG_PKRCNTFE_PKR_E_CT_MASK              (0xFFFFU)
7647 #define TRNG_PKRCNTFE_PKR_E_CT_SHIFT             (0U)
7648 #define TRNG_PKRCNTFE_PKR_E_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_E_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_E_CT_MASK)
7649 #define TRNG_PKRCNTFE_PKR_F_CT_MASK              (0xFFFF0000U)
7650 #define TRNG_PKRCNTFE_PKR_F_CT_SHIFT             (16U)
7651 #define TRNG_PKRCNTFE_PKR_F_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_F_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_F_CT_MASK)
7652 
7653 /*! @name SEC_CFG - Security Configuration Register */
7654 #define TRNG_SEC_CFG_SH0_MASK                    (0x1U)
7655 #define TRNG_SEC_CFG_SH0_SHIFT                   (0U)
7656 #define TRNG_SEC_CFG_SH0(x)                      (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_SH0_SHIFT)) & TRNG_SEC_CFG_SH0_MASK)
7657 #define TRNG_SEC_CFG_NO_PRGM_MASK                (0x2U)
7658 #define TRNG_SEC_CFG_NO_PRGM_SHIFT               (1U)
7659 #define TRNG_SEC_CFG_NO_PRGM(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_NO_PRGM_SHIFT)) & TRNG_SEC_CFG_NO_PRGM_MASK)
7660 #define TRNG_SEC_CFG_SK_VAL_MASK                 (0x4U)
7661 #define TRNG_SEC_CFG_SK_VAL_SHIFT                (2U)
7662 #define TRNG_SEC_CFG_SK_VAL(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_SK_VAL_SHIFT)) & TRNG_SEC_CFG_SK_VAL_MASK)
7663 
7664 /*! @name INT_CTRL - Interrupt Control Register */
7665 #define TRNG_INT_CTRL_HW_ERR_MASK                (0x1U)
7666 #define TRNG_INT_CTRL_HW_ERR_SHIFT               (0U)
7667 #define TRNG_INT_CTRL_HW_ERR(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_HW_ERR_SHIFT)) & TRNG_INT_CTRL_HW_ERR_MASK)
7668 #define TRNG_INT_CTRL_ENT_VAL_MASK               (0x2U)
7669 #define TRNG_INT_CTRL_ENT_VAL_SHIFT              (1U)
7670 #define TRNG_INT_CTRL_ENT_VAL(x)                 (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_ENT_VAL_SHIFT)) & TRNG_INT_CTRL_ENT_VAL_MASK)
7671 #define TRNG_INT_CTRL_FRQ_CT_FAIL_MASK           (0x4U)
7672 #define TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT          (2U)
7673 #define TRNG_INT_CTRL_FRQ_CT_FAIL(x)             (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_CTRL_FRQ_CT_FAIL_MASK)
7674 #define TRNG_INT_CTRL_UNUSED_MASK                (0xFFFFFFF8U)
7675 #define TRNG_INT_CTRL_UNUSED_SHIFT               (3U)
7676 #define TRNG_INT_CTRL_UNUSED(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_UNUSED_SHIFT)) & TRNG_INT_CTRL_UNUSED_MASK)
7677 
7678 /*! @name INT_MASK - Mask Register */
7679 #define TRNG_INT_MASK_HW_ERR_MASK                (0x1U)
7680 #define TRNG_INT_MASK_HW_ERR_SHIFT               (0U)
7681 #define TRNG_INT_MASK_HW_ERR(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_HW_ERR_SHIFT)) & TRNG_INT_MASK_HW_ERR_MASK)
7682 #define TRNG_INT_MASK_ENT_VAL_MASK               (0x2U)
7683 #define TRNG_INT_MASK_ENT_VAL_SHIFT              (1U)
7684 #define TRNG_INT_MASK_ENT_VAL(x)                 (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_ENT_VAL_SHIFT)) & TRNG_INT_MASK_ENT_VAL_MASK)
7685 #define TRNG_INT_MASK_FRQ_CT_FAIL_MASK           (0x4U)
7686 #define TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT          (2U)
7687 #define TRNG_INT_MASK_FRQ_CT_FAIL(x)             (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_MASK_FRQ_CT_FAIL_MASK)
7688 
7689 /*! @name INT_STATUS - Interrupt Status Register */
7690 #define TRNG_INT_STATUS_HW_ERR_MASK              (0x1U)
7691 #define TRNG_INT_STATUS_HW_ERR_SHIFT             (0U)
7692 #define TRNG_INT_STATUS_HW_ERR(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_HW_ERR_SHIFT)) & TRNG_INT_STATUS_HW_ERR_MASK)
7693 #define TRNG_INT_STATUS_ENT_VAL_MASK             (0x2U)
7694 #define TRNG_INT_STATUS_ENT_VAL_SHIFT            (1U)
7695 #define TRNG_INT_STATUS_ENT_VAL(x)               (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_ENT_VAL_SHIFT)) & TRNG_INT_STATUS_ENT_VAL_MASK)
7696 #define TRNG_INT_STATUS_FRQ_CT_FAIL_MASK         (0x4U)
7697 #define TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT        (2U)
7698 #define TRNG_INT_STATUS_FRQ_CT_FAIL(x)           (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_STATUS_FRQ_CT_FAIL_MASK)
7699 
7700 /*! @name VID1 - Version ID Register (MS) */
7701 #define TRNG_VID1_MIN_REV_MASK                   (0xFFU)
7702 #define TRNG_VID1_MIN_REV_SHIFT                  (0U)
7703 #define TRNG_VID1_MIN_REV(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MIN_REV_SHIFT)) & TRNG_VID1_MIN_REV_MASK)
7704 #define TRNG_VID1_MAJ_REV_MASK                   (0xFF00U)
7705 #define TRNG_VID1_MAJ_REV_SHIFT                  (8U)
7706 #define TRNG_VID1_MAJ_REV(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MAJ_REV_SHIFT)) & TRNG_VID1_MAJ_REV_MASK)
7707 #define TRNG_VID1_IP_ID_MASK                     (0xFFFF0000U)
7708 #define TRNG_VID1_IP_ID_SHIFT                    (16U)
7709 #define TRNG_VID1_IP_ID(x)                       (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_IP_ID_SHIFT)) & TRNG_VID1_IP_ID_MASK)
7710 
7711 /*! @name VID2 - Version ID Register (LS) */
7712 #define TRNG_VID2_CONFIG_OPT_MASK                (0xFFU)
7713 #define TRNG_VID2_CONFIG_OPT_SHIFT               (0U)
7714 #define TRNG_VID2_CONFIG_OPT(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_CONFIG_OPT_SHIFT)) & TRNG_VID2_CONFIG_OPT_MASK)
7715 #define TRNG_VID2_ECO_REV_MASK                   (0xFF00U)
7716 #define TRNG_VID2_ECO_REV_SHIFT                  (8U)
7717 #define TRNG_VID2_ECO_REV(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ECO_REV_SHIFT)) & TRNG_VID2_ECO_REV_MASK)
7718 #define TRNG_VID2_INTG_OPT_MASK                  (0xFF0000U)
7719 #define TRNG_VID2_INTG_OPT_SHIFT                 (16U)
7720 #define TRNG_VID2_INTG_OPT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_INTG_OPT_SHIFT)) & TRNG_VID2_INTG_OPT_MASK)
7721 #define TRNG_VID2_ERA_MASK                       (0xFF000000U)
7722 #define TRNG_VID2_ERA_SHIFT                      (24U)
7723 #define TRNG_VID2_ERA(x)                         (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ERA_SHIFT)) & TRNG_VID2_ERA_MASK)
7724 
7725 
7726 /*!
7727  * @}
7728  */ /* end of group TRNG_Register_Masks */
7729 
7730 
7731 /* TRNG - Peripheral instance base addresses */
7732 /** Peripheral TRNG0 base address */
7733 #define TRNG0_BASE                               (0x40029000u)
7734 /** Peripheral TRNG0 base pointer */
7735 #define TRNG0                                    ((TRNG_Type *)TRNG0_BASE)
7736 /** Array initializer of TRNG peripheral base addresses */
7737 #define TRNG_BASE_ADDRS                          { TRNG0_BASE }
7738 /** Array initializer of TRNG peripheral base pointers */
7739 #define TRNG_BASE_PTRS                           { TRNG0 }
7740 /** Interrupt vectors for the TRNG peripheral type */
7741 #define TRNG_IRQS                                { TRNG0_IRQn }
7742 
7743 /*!
7744  * @}
7745  */ /* end of group TRNG_Peripheral_Access_Layer */
7746 
7747 
7748 /* ----------------------------------------------------------------------------
7749    -- TSI Peripheral Access Layer
7750    ---------------------------------------------------------------------------- */
7751 
7752 /*!
7753  * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
7754  * @{
7755  */
7756 
7757 /** TSI - Register Layout Typedef */
7758 typedef struct {
7759   __IO uint32_t GENCS;                             /**< TSI General Control and Status Register, offset: 0x0 */
7760   __IO uint32_t DATA;                              /**< TSI DATA Register, offset: 0x4 */
7761   __IO uint32_t TSHD;                              /**< TSI Threshold Register, offset: 0x8 */
7762 } TSI_Type;
7763 
7764 /* ----------------------------------------------------------------------------
7765    -- TSI Register Masks
7766    ---------------------------------------------------------------------------- */
7767 
7768 /*!
7769  * @addtogroup TSI_Register_Masks TSI Register Masks
7770  * @{
7771  */
7772 
7773 /*! @name GENCS - TSI General Control and Status Register */
7774 #define TSI_GENCS_CURSW_MASK                     (0x2U)
7775 #define TSI_GENCS_CURSW_SHIFT                    (1U)
7776 #define TSI_GENCS_CURSW(x)                       (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_CURSW_SHIFT)) & TSI_GENCS_CURSW_MASK)
7777 #define TSI_GENCS_EOSF_MASK                      (0x4U)
7778 #define TSI_GENCS_EOSF_SHIFT                     (2U)
7779 #define TSI_GENCS_EOSF(x)                        (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EOSF_SHIFT)) & TSI_GENCS_EOSF_MASK)
7780 #define TSI_GENCS_SCNIP_MASK                     (0x8U)
7781 #define TSI_GENCS_SCNIP_SHIFT                    (3U)
7782 #define TSI_GENCS_SCNIP(x)                       (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_SCNIP_SHIFT)) & TSI_GENCS_SCNIP_MASK)
7783 #define TSI_GENCS_STM_MASK                       (0x10U)
7784 #define TSI_GENCS_STM_SHIFT                      (4U)
7785 #define TSI_GENCS_STM(x)                         (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STM_SHIFT)) & TSI_GENCS_STM_MASK)
7786 #define TSI_GENCS_STPE_MASK                      (0x20U)
7787 #define TSI_GENCS_STPE_SHIFT                     (5U)
7788 #define TSI_GENCS_STPE(x)                        (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STPE_SHIFT)) & TSI_GENCS_STPE_MASK)
7789 #define TSI_GENCS_TSIIEN_MASK                    (0x40U)
7790 #define TSI_GENCS_TSIIEN_SHIFT                   (6U)
7791 #define TSI_GENCS_TSIIEN(x)                      (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIIEN_SHIFT)) & TSI_GENCS_TSIIEN_MASK)
7792 #define TSI_GENCS_TSIEN_MASK                     (0x80U)
7793 #define TSI_GENCS_TSIEN_SHIFT                    (7U)
7794 #define TSI_GENCS_TSIEN(x)                       (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIEN_SHIFT)) & TSI_GENCS_TSIEN_MASK)
7795 #define TSI_GENCS_NSCN_MASK                      (0x1F00U)
7796 #define TSI_GENCS_NSCN_SHIFT                     (8U)
7797 #define TSI_GENCS_NSCN(x)                        (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_NSCN_SHIFT)) & TSI_GENCS_NSCN_MASK)
7798 #define TSI_GENCS_PS_MASK                        (0xE000U)
7799 #define TSI_GENCS_PS_SHIFT                       (13U)
7800 #define TSI_GENCS_PS(x)                          (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_PS_SHIFT)) & TSI_GENCS_PS_MASK)
7801 #define TSI_GENCS_EXTCHRG_MASK                   (0x70000U)
7802 #define TSI_GENCS_EXTCHRG_SHIFT                  (16U)
7803 #define TSI_GENCS_EXTCHRG(x)                     (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EXTCHRG_SHIFT)) & TSI_GENCS_EXTCHRG_MASK)
7804 #define TSI_GENCS_DVOLT_MASK                     (0x180000U)
7805 #define TSI_GENCS_DVOLT_SHIFT                    (19U)
7806 #define TSI_GENCS_DVOLT(x)                       (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_DVOLT_SHIFT)) & TSI_GENCS_DVOLT_MASK)
7807 #define TSI_GENCS_REFCHRG_MASK                   (0xE00000U)
7808 #define TSI_GENCS_REFCHRG_SHIFT                  (21U)
7809 #define TSI_GENCS_REFCHRG(x)                     (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_REFCHRG_SHIFT)) & TSI_GENCS_REFCHRG_MASK)
7810 #define TSI_GENCS_MODE_MASK                      (0xF000000U)
7811 #define TSI_GENCS_MODE_SHIFT                     (24U)
7812 #define TSI_GENCS_MODE(x)                        (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_MODE_SHIFT)) & TSI_GENCS_MODE_MASK)
7813 #define TSI_GENCS_ESOR_MASK                      (0x10000000U)
7814 #define TSI_GENCS_ESOR_SHIFT                     (28U)
7815 #define TSI_GENCS_ESOR(x)                        (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_ESOR_SHIFT)) & TSI_GENCS_ESOR_MASK)
7816 #define TSI_GENCS_OUTRGF_MASK                    (0x80000000U)
7817 #define TSI_GENCS_OUTRGF_SHIFT                   (31U)
7818 #define TSI_GENCS_OUTRGF(x)                      (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_OUTRGF_SHIFT)) & TSI_GENCS_OUTRGF_MASK)
7819 
7820 /*! @name DATA - TSI DATA Register */
7821 #define TSI_DATA_TSICNT_MASK                     (0xFFFFU)
7822 #define TSI_DATA_TSICNT_SHIFT                    (0U)
7823 #define TSI_DATA_TSICNT(x)                       (((uint32_t)(((uint32_t)(x)) << TSI_DATA_TSICNT_SHIFT)) & TSI_DATA_TSICNT_MASK)
7824 #define TSI_DATA_SWTS_MASK                       (0x400000U)
7825 #define TSI_DATA_SWTS_SHIFT                      (22U)
7826 #define TSI_DATA_SWTS(x)                         (((uint32_t)(((uint32_t)(x)) << TSI_DATA_SWTS_SHIFT)) & TSI_DATA_SWTS_MASK)
7827 #define TSI_DATA_DMAEN_MASK                      (0x800000U)
7828 #define TSI_DATA_DMAEN_SHIFT                     (23U)
7829 #define TSI_DATA_DMAEN(x)                        (((uint32_t)(((uint32_t)(x)) << TSI_DATA_DMAEN_SHIFT)) & TSI_DATA_DMAEN_MASK)
7830 #define TSI_DATA_TSICH_MASK                      (0xF0000000U)
7831 #define TSI_DATA_TSICH_SHIFT                     (28U)
7832 #define TSI_DATA_TSICH(x)                        (((uint32_t)(((uint32_t)(x)) << TSI_DATA_TSICH_SHIFT)) & TSI_DATA_TSICH_MASK)
7833 
7834 /*! @name TSHD - TSI Threshold Register */
7835 #define TSI_TSHD_THRESL_MASK                     (0xFFFFU)
7836 #define TSI_TSHD_THRESL_SHIFT                    (0U)
7837 #define TSI_TSHD_THRESL(x)                       (((uint32_t)(((uint32_t)(x)) << TSI_TSHD_THRESL_SHIFT)) & TSI_TSHD_THRESL_MASK)
7838 #define TSI_TSHD_THRESH_MASK                     (0xFFFF0000U)
7839 #define TSI_TSHD_THRESH_SHIFT                    (16U)
7840 #define TSI_TSHD_THRESH(x)                       (((uint32_t)(((uint32_t)(x)) << TSI_TSHD_THRESH_SHIFT)) & TSI_TSHD_THRESH_MASK)
7841 
7842 
7843 /*!
7844  * @}
7845  */ /* end of group TSI_Register_Masks */
7846 
7847 
7848 /* TSI - Peripheral instance base addresses */
7849 /** Peripheral TSI0 base address */
7850 #define TSI0_BASE                                (0x40045000u)
7851 /** Peripheral TSI0 base pointer */
7852 #define TSI0                                     ((TSI_Type *)TSI0_BASE)
7853 /** Array initializer of TSI peripheral base addresses */
7854 #define TSI_BASE_ADDRS                           { TSI0_BASE }
7855 /** Array initializer of TSI peripheral base pointers */
7856 #define TSI_BASE_PTRS                            { TSI0 }
7857 /** Interrupt vectors for the TSI peripheral type */
7858 #define TSI_IRQS                                 { TSI0_IRQn }
7859 
7860 /*!
7861  * @}
7862  */ /* end of group TSI_Peripheral_Access_Layer */
7863 
7864 
7865 /* ----------------------------------------------------------------------------
7866    -- VREF Peripheral Access Layer
7867    ---------------------------------------------------------------------------- */
7868 
7869 /*!
7870  * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
7871  * @{
7872  */
7873 
7874 /** VREF - Register Layout Typedef */
7875 typedef struct {
7876   __IO uint8_t TRM;                                /**< VREF Trim Register, offset: 0x0 */
7877   __IO uint8_t SC;                                 /**< VREF Status and Control Register, offset: 0x1 */
7878 } VREF_Type;
7879 
7880 /* ----------------------------------------------------------------------------
7881    -- VREF Register Masks
7882    ---------------------------------------------------------------------------- */
7883 
7884 /*!
7885  * @addtogroup VREF_Register_Masks VREF Register Masks
7886  * @{
7887  */
7888 
7889 /*! @name TRM - VREF Trim Register */
7890 #define VREF_TRM_TRIM_MASK                       (0x3FU)
7891 #define VREF_TRM_TRIM_SHIFT                      (0U)
7892 #define VREF_TRM_TRIM(x)                         (((uint8_t)(((uint8_t)(x)) << VREF_TRM_TRIM_SHIFT)) & VREF_TRM_TRIM_MASK)
7893 #define VREF_TRM_CHOPEN_MASK                     (0x40U)
7894 #define VREF_TRM_CHOPEN_SHIFT                    (6U)
7895 #define VREF_TRM_CHOPEN(x)                       (((uint8_t)(((uint8_t)(x)) << VREF_TRM_CHOPEN_SHIFT)) & VREF_TRM_CHOPEN_MASK)
7896 
7897 /*! @name SC - VREF Status and Control Register */
7898 #define VREF_SC_MODE_LV_MASK                     (0x3U)
7899 #define VREF_SC_MODE_LV_SHIFT                    (0U)
7900 #define VREF_SC_MODE_LV(x)                       (((uint8_t)(((uint8_t)(x)) << VREF_SC_MODE_LV_SHIFT)) & VREF_SC_MODE_LV_MASK)
7901 #define VREF_SC_VREFST_MASK                      (0x4U)
7902 #define VREF_SC_VREFST_SHIFT                     (2U)
7903 #define VREF_SC_VREFST(x)                        (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFST_SHIFT)) & VREF_SC_VREFST_MASK)
7904 #define VREF_SC_ICOMPEN_MASK                     (0x20U)
7905 #define VREF_SC_ICOMPEN_SHIFT                    (5U)
7906 #define VREF_SC_ICOMPEN(x)                       (((uint8_t)(((uint8_t)(x)) << VREF_SC_ICOMPEN_SHIFT)) & VREF_SC_ICOMPEN_MASK)
7907 #define VREF_SC_REGEN_MASK                       (0x40U)
7908 #define VREF_SC_REGEN_SHIFT                      (6U)
7909 #define VREF_SC_REGEN(x)                         (((uint8_t)(((uint8_t)(x)) << VREF_SC_REGEN_SHIFT)) & VREF_SC_REGEN_MASK)
7910 #define VREF_SC_VREFEN_MASK                      (0x80U)
7911 #define VREF_SC_VREFEN_SHIFT                     (7U)
7912 #define VREF_SC_VREFEN(x)                        (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFEN_SHIFT)) & VREF_SC_VREFEN_MASK)
7913 
7914 
7915 /*!
7916  * @}
7917  */ /* end of group VREF_Register_Masks */
7918 
7919 
7920 /* VREF - Peripheral instance base addresses */
7921 /** Peripheral VREF base address */
7922 #define VREF_BASE                                (0x40074000u)
7923 /** Peripheral VREF base pointer */
7924 #define VREF                                     ((VREF_Type *)VREF_BASE)
7925 /** Array initializer of VREF peripheral base addresses */
7926 #define VREF_BASE_ADDRS                          { VREF_BASE }
7927 /** Array initializer of VREF peripheral base pointers */
7928 #define VREF_BASE_PTRS                           { VREF }
7929 
7930 /*!
7931  * @}
7932  */ /* end of group VREF_Peripheral_Access_Layer */
7933 
7934 
7935 /* ----------------------------------------------------------------------------
7936    -- XCVR_ANALOG Peripheral Access Layer
7937    ---------------------------------------------------------------------------- */
7938 
7939 /*!
7940  * @addtogroup XCVR_ANALOG_Peripheral_Access_Layer XCVR_ANALOG Peripheral Access Layer
7941  * @{
7942  */
7943 
7944 /** XCVR_ANALOG - Register Layout Typedef */
7945 typedef struct {
7946   __IO uint32_t BB_LDO_1;                          /**< RF Analog Baseband LDO Control 1, offset: 0x0 */
7947   __IO uint32_t BB_LDO_2;                          /**< RF Analog Baseband LDO Control 2, offset: 0x4 */
7948   __IO uint32_t RX_ADC;                            /**< RF Analog ADC Control, offset: 0x8 */
7949   __IO uint32_t RX_BBA;                            /**< RF Analog BBA Control, offset: 0xC */
7950   __IO uint32_t RX_LNA;                            /**< RF Analog LNA Control, offset: 0x10 */
7951   __IO uint32_t RX_TZA;                            /**< RF Analog TZA Control, offset: 0x14 */
7952   __IO uint32_t RX_AUXPLL;                         /**< RF Analog Aux PLL Control, offset: 0x18 */
7953   __IO uint32_t SY_CTRL_1;                         /**< RF Analog Synthesizer Control 1, offset: 0x1C */
7954   __IO uint32_t SY_CTRL_2;                         /**< RF Analog Synthesizer Control 2, offset: 0x20 */
7955   __IO uint32_t TX_DAC_PA;                         /**< RF Analog TX HPM DAC and PA Control, offset: 0x24 */
7956   __IO uint32_t BALUN_TX;                          /**< RF Analog Balun TX Mode Control, offset: 0x28 */
7957   __IO uint32_t BALUN_RX;                          /**< RF Analog Balun RX Mode Control, offset: 0x2C */
7958   __I  uint32_t DFT_OBSV_1;                        /**< RF Analog DFT Observation Register 1, offset: 0x30 */
7959   __IO uint32_t DFT_OBSV_2;                        /**< RF Analog DFT Observation Register 2, offset: 0x34 */
7960 } XCVR_ANALOG_Type;
7961 
7962 /* ----------------------------------------------------------------------------
7963    -- XCVR_ANALOG Register Masks
7964    ---------------------------------------------------------------------------- */
7965 
7966 /*!
7967  * @addtogroup XCVR_ANALOG_Register_Masks XCVR_ANALOG Register Masks
7968  * @{
7969  */
7970 
7971 /*! @name BB_LDO_1 - RF Analog Baseband LDO Control 1 */
7972 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_BYP_MASK (0x1U)
7973 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_BYP_SHIFT (0U)
7974 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_BYP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_BYP_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_BYP_MASK)
7975 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_DIAGSEL_MASK (0x2U)
7976 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_DIAGSEL_SHIFT (1U)
7977 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_DIAGSEL_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_DIAGSEL_MASK)
7978 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_SPARE_MASK (0xCU)
7979 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_SPARE_SHIFT (2U)
7980 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_SPARE_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_SPARE_MASK)
7981 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_TRIM_MASK (0x70U)
7982 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_TRIM_SHIFT (4U)
7983 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_TRIM(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_TRIM_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_TRIM_MASK)
7984 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_BYP_MASK (0x100U)
7985 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_BYP_SHIFT (8U)
7986 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_BYP(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_BYP_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_BYP_MASK)
7987 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_DIAGSEL_MASK (0x200U)
7988 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_DIAGSEL_SHIFT (9U)
7989 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_DIAGSEL_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_DIAGSEL_MASK)
7990 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_SPARE_MASK (0xC00U)
7991 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_SPARE_SHIFT (10U)
7992 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_SPARE_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_SPARE_MASK)
7993 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_TRIM_MASK (0x7000U)
7994 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_TRIM_SHIFT (12U)
7995 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_TRIM(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_TRIM_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_TRIM_MASK)
7996 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_BYP_MASK (0x10000U)
7997 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_BYP_SHIFT (16U)
7998 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_BYP(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_BYP_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_BYP_MASK)
7999 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_DIAGSEL_MASK (0x20000U)
8000 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_DIAGSEL_SHIFT (17U)
8001 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_DIAGSEL_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_DIAGSEL_MASK)
8002 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_SPARE_MASK (0xC0000U)
8003 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_SPARE_SHIFT (18U)
8004 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_SPARE_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_SPARE_MASK)
8005 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_TRIM_MASK (0x700000U)
8006 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_TRIM_SHIFT (20U)
8007 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_TRIM(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_TRIM_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_TRIM_MASK)
8008 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_BYP_MASK  (0x1000000U)
8009 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_BYP_SHIFT (24U)
8010 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_BYP(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_BYP_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_BYP_MASK)
8011 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_DIAGSEL_MASK (0x2000000U)
8012 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_DIAGSEL_SHIFT (25U)
8013 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_DIAGSEL_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_DIAGSEL_MASK)
8014 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_SPARE_MASK (0xC000000U)
8015 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_SPARE_SHIFT (26U)
8016 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_SPARE(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_SPARE_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_SPARE_MASK)
8017 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_TRIM_MASK (0x70000000U)
8018 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_TRIM_SHIFT (28U)
8019 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_TRIM(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_TRIM_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_TRIM_MASK)
8020 
8021 /*! @name BB_LDO_2 - RF Analog Baseband LDO Control 2 */
8022 #define XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_BYP_MASK  (0x1U)
8023 #define XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_BYP_SHIFT (0U)
8024 #define XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_BYP(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_BYP_SHIFT)) & XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_BYP_MASK)
8025 #define XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_DIAGSEL_MASK (0x2U)
8026 #define XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_DIAGSEL_SHIFT (1U)
8027 #define XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_DIAGSEL_SHIFT)) & XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_DIAGSEL_MASK)
8028 #define XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_SPARE_MASK (0xCU)
8029 #define XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_SPARE_SHIFT (2U)
8030 #define XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_SPARE(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_SPARE_SHIFT)) & XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_SPARE_MASK)
8031 #define XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_TRIM_MASK (0x70U)
8032 #define XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_TRIM_SHIFT (4U)
8033 #define XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_TRIM(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_TRIM_SHIFT)) & XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_TRIM_MASK)
8034 #define XCVR_ANALOG_BB_LDO_2_BB_LDO_VCO_SPARE_MASK (0x300U)
8035 #define XCVR_ANALOG_BB_LDO_2_BB_LDO_VCO_SPARE_SHIFT (8U)
8036 #define XCVR_ANALOG_BB_LDO_2_BB_LDO_VCO_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_2_BB_LDO_VCO_SPARE_SHIFT)) & XCVR_ANALOG_BB_LDO_2_BB_LDO_VCO_SPARE_MASK)
8037 #define XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_BYP_MASK (0x400U)
8038 #define XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_BYP_SHIFT (10U)
8039 #define XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_BYP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_BYP_SHIFT)) & XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_BYP_MASK)
8040 #define XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_DIAGSEL_MASK (0x800U)
8041 #define XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_DIAGSEL_SHIFT (11U)
8042 #define XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_DIAGSEL_SHIFT)) & XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_DIAGSEL_MASK)
8043 #define XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_TRIM_MASK (0x7000U)
8044 #define XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_TRIM_SHIFT (12U)
8045 #define XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_TRIM(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_TRIM_SHIFT)) & XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_TRIM_MASK)
8046 #define XCVR_ANALOG_BB_LDO_2_BB_LDO_VTREF_DIAGSEL_MASK (0x10000U)
8047 #define XCVR_ANALOG_BB_LDO_2_BB_LDO_VTREF_DIAGSEL_SHIFT (16U)
8048 #define XCVR_ANALOG_BB_LDO_2_BB_LDO_VTREF_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_2_BB_LDO_VTREF_DIAGSEL_SHIFT)) & XCVR_ANALOG_BB_LDO_2_BB_LDO_VTREF_DIAGSEL_MASK)
8049 #define XCVR_ANALOG_BB_LDO_2_BB_LDO_VTREF_TC_MASK (0x60000U)
8050 #define XCVR_ANALOG_BB_LDO_2_BB_LDO_VTREF_TC_SHIFT (17U)
8051 #define XCVR_ANALOG_BB_LDO_2_BB_LDO_VTREF_TC(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_2_BB_LDO_VTREF_TC_SHIFT)) & XCVR_ANALOG_BB_LDO_2_BB_LDO_VTREF_TC_MASK)
8052 
8053 /*! @name RX_ADC - RF Analog ADC Control */
8054 #define XCVR_ANALOG_RX_ADC_RX_ADC_BUMP_MASK      (0xFFU)
8055 #define XCVR_ANALOG_RX_ADC_RX_ADC_BUMP_SHIFT     (0U)
8056 #define XCVR_ANALOG_RX_ADC_RX_ADC_BUMP(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_ADC_RX_ADC_BUMP_SHIFT)) & XCVR_ANALOG_RX_ADC_RX_ADC_BUMP_MASK)
8057 #define XCVR_ANALOG_RX_ADC_RX_ADC_FS_SEL_MASK    (0x300U)
8058 #define XCVR_ANALOG_RX_ADC_RX_ADC_FS_SEL_SHIFT   (8U)
8059 #define XCVR_ANALOG_RX_ADC_RX_ADC_FS_SEL(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_ADC_RX_ADC_FS_SEL_SHIFT)) & XCVR_ANALOG_RX_ADC_RX_ADC_FS_SEL_MASK)
8060 #define XCVR_ANALOG_RX_ADC_RX_ADC_I_DIAGSEL_MASK (0x400U)
8061 #define XCVR_ANALOG_RX_ADC_RX_ADC_I_DIAGSEL_SHIFT (10U)
8062 #define XCVR_ANALOG_RX_ADC_RX_ADC_I_DIAGSEL(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_ADC_RX_ADC_I_DIAGSEL_SHIFT)) & XCVR_ANALOG_RX_ADC_RX_ADC_I_DIAGSEL_MASK)
8063 #define XCVR_ANALOG_RX_ADC_RX_ADC_Q_DIAGSEL_MASK (0x800U)
8064 #define XCVR_ANALOG_RX_ADC_RX_ADC_Q_DIAGSEL_SHIFT (11U)
8065 #define XCVR_ANALOG_RX_ADC_RX_ADC_Q_DIAGSEL(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_ADC_RX_ADC_Q_DIAGSEL_SHIFT)) & XCVR_ANALOG_RX_ADC_RX_ADC_Q_DIAGSEL_MASK)
8066 #define XCVR_ANALOG_RX_ADC_RX_ADC_SPARE_MASK     (0xF000U)
8067 #define XCVR_ANALOG_RX_ADC_RX_ADC_SPARE_SHIFT    (12U)
8068 #define XCVR_ANALOG_RX_ADC_RX_ADC_SPARE(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_ADC_RX_ADC_SPARE_SHIFT)) & XCVR_ANALOG_RX_ADC_RX_ADC_SPARE_MASK)
8069 
8070 /*! @name RX_BBA - RF Analog BBA Control */
8071 #define XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK    (0x7U)
8072 #define XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_SHIFT   (0U)
8073 #define XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_SHIFT)) & XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK)
8074 #define XCVR_ANALOG_RX_BBA_RX_BBA_CUR_BUMP_MASK  (0x8U)
8075 #define XCVR_ANALOG_RX_BBA_RX_BBA_CUR_BUMP_SHIFT (3U)
8076 #define XCVR_ANALOG_RX_BBA_RX_BBA_CUR_BUMP(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_BBA_RX_BBA_CUR_BUMP_SHIFT)) & XCVR_ANALOG_RX_BBA_RX_BBA_CUR_BUMP_MASK)
8077 #define XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL1_MASK  (0x10U)
8078 #define XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL1_SHIFT (4U)
8079 #define XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL1(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL1_SHIFT)) & XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL1_MASK)
8080 #define XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL2_MASK  (0x20U)
8081 #define XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL2_SHIFT (5U)
8082 #define XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL2(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL2_SHIFT)) & XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL2_MASK)
8083 #define XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL3_MASK  (0x40U)
8084 #define XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL3_SHIFT (6U)
8085 #define XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL3(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL3_SHIFT)) & XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL3_MASK)
8086 #define XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL4_MASK  (0x80U)
8087 #define XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL4_SHIFT (7U)
8088 #define XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL4(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL4_SHIFT)) & XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL4_MASK)
8089 #define XCVR_ANALOG_RX_BBA_RX_BBA_SPARE_MASK     (0x3F0000U)
8090 #define XCVR_ANALOG_RX_BBA_RX_BBA_SPARE_SHIFT    (16U)
8091 #define XCVR_ANALOG_RX_BBA_RX_BBA_SPARE(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_BBA_RX_BBA_SPARE_SHIFT)) & XCVR_ANALOG_RX_BBA_RX_BBA_SPARE_MASK)
8092 #define XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK   (0x7000000U)
8093 #define XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_SHIFT  (24U)
8094 #define XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_SHIFT)) & XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK)
8095 #define XCVR_ANALOG_RX_BBA_RX_BBA2_SPARE_MASK    (0x70000000U)
8096 #define XCVR_ANALOG_RX_BBA_RX_BBA2_SPARE_SHIFT   (28U)
8097 #define XCVR_ANALOG_RX_BBA_RX_BBA2_SPARE(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_BBA_RX_BBA2_SPARE_SHIFT)) & XCVR_ANALOG_RX_BBA_RX_BBA2_SPARE_MASK)
8098 
8099 /*! @name RX_LNA - RF Analog LNA Control */
8100 #define XCVR_ANALOG_RX_LNA_RX_LNA_BUMP_MASK      (0xFU)
8101 #define XCVR_ANALOG_RX_LNA_RX_LNA_BUMP_SHIFT     (0U)
8102 #define XCVR_ANALOG_RX_LNA_RX_LNA_BUMP(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_LNA_RX_LNA_BUMP_SHIFT)) & XCVR_ANALOG_RX_LNA_RX_LNA_BUMP_MASK)
8103 #define XCVR_ANALOG_RX_LNA_RX_LNA_HG_DIAGSEL_MASK (0x10U)
8104 #define XCVR_ANALOG_RX_LNA_RX_LNA_HG_DIAGSEL_SHIFT (4U)
8105 #define XCVR_ANALOG_RX_LNA_RX_LNA_HG_DIAGSEL(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_LNA_RX_LNA_HG_DIAGSEL_SHIFT)) & XCVR_ANALOG_RX_LNA_RX_LNA_HG_DIAGSEL_MASK)
8106 #define XCVR_ANALOG_RX_LNA_RX_LNA_HIZ_ENABLE_MASK (0x20U)
8107 #define XCVR_ANALOG_RX_LNA_RX_LNA_HIZ_ENABLE_SHIFT (5U)
8108 #define XCVR_ANALOG_RX_LNA_RX_LNA_HIZ_ENABLE(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_LNA_RX_LNA_HIZ_ENABLE_SHIFT)) & XCVR_ANALOG_RX_LNA_RX_LNA_HIZ_ENABLE_MASK)
8109 #define XCVR_ANALOG_RX_LNA_RX_LNA_LG_DIAGSEL_MASK (0x40U)
8110 #define XCVR_ANALOG_RX_LNA_RX_LNA_LG_DIAGSEL_SHIFT (6U)
8111 #define XCVR_ANALOG_RX_LNA_RX_LNA_LG_DIAGSEL(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_LNA_RX_LNA_LG_DIAGSEL_SHIFT)) & XCVR_ANALOG_RX_LNA_RX_LNA_LG_DIAGSEL_MASK)
8112 #define XCVR_ANALOG_RX_LNA_RX_LNA_SPARE_MASK     (0x300U)
8113 #define XCVR_ANALOG_RX_LNA_RX_LNA_SPARE_SHIFT    (8U)
8114 #define XCVR_ANALOG_RX_LNA_RX_LNA_SPARE(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_LNA_RX_LNA_SPARE_SHIFT)) & XCVR_ANALOG_RX_LNA_RX_LNA_SPARE_MASK)
8115 #define XCVR_ANALOG_RX_LNA_RX_MIXER_BUMP_MASK    (0xF0000U)
8116 #define XCVR_ANALOG_RX_LNA_RX_MIXER_BUMP_SHIFT   (16U)
8117 #define XCVR_ANALOG_RX_LNA_RX_MIXER_BUMP(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_LNA_RX_MIXER_BUMP_SHIFT)) & XCVR_ANALOG_RX_LNA_RX_MIXER_BUMP_MASK)
8118 #define XCVR_ANALOG_RX_LNA_RX_MIXER_SPARE_MASK   (0x100000U)
8119 #define XCVR_ANALOG_RX_LNA_RX_MIXER_SPARE_SHIFT  (20U)
8120 #define XCVR_ANALOG_RX_LNA_RX_MIXER_SPARE(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_LNA_RX_MIXER_SPARE_SHIFT)) & XCVR_ANALOG_RX_LNA_RX_MIXER_SPARE_MASK)
8121 
8122 /*! @name RX_TZA - RF Analog TZA Control */
8123 #define XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK    (0x7U)
8124 #define XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_SHIFT   (0U)
8125 #define XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_SHIFT)) & XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK)
8126 #define XCVR_ANALOG_RX_TZA_RX_TZA_CUR_BUMP_MASK  (0x8U)
8127 #define XCVR_ANALOG_RX_TZA_RX_TZA_CUR_BUMP_SHIFT (3U)
8128 #define XCVR_ANALOG_RX_TZA_RX_TZA_CUR_BUMP(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_TZA_RX_TZA_CUR_BUMP_SHIFT)) & XCVR_ANALOG_RX_TZA_RX_TZA_CUR_BUMP_MASK)
8129 #define XCVR_ANALOG_RX_TZA_RX_TZA_GAIN_BUMP_MASK (0x10U)
8130 #define XCVR_ANALOG_RX_TZA_RX_TZA_GAIN_BUMP_SHIFT (4U)
8131 #define XCVR_ANALOG_RX_TZA_RX_TZA_GAIN_BUMP(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_TZA_RX_TZA_GAIN_BUMP_SHIFT)) & XCVR_ANALOG_RX_TZA_RX_TZA_GAIN_BUMP_MASK)
8132 #define XCVR_ANALOG_RX_TZA_RX_TZA_SPARE_MASK     (0x3F0000U)
8133 #define XCVR_ANALOG_RX_TZA_RX_TZA_SPARE_SHIFT    (16U)
8134 #define XCVR_ANALOG_RX_TZA_RX_TZA_SPARE(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_TZA_RX_TZA_SPARE_SHIFT)) & XCVR_ANALOG_RX_TZA_RX_TZA_SPARE_MASK)
8135 #define XCVR_ANALOG_RX_TZA_RX_TZA1_DIAGSEL_MASK  (0x1000000U)
8136 #define XCVR_ANALOG_RX_TZA_RX_TZA1_DIAGSEL_SHIFT (24U)
8137 #define XCVR_ANALOG_RX_TZA_RX_TZA1_DIAGSEL(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_TZA_RX_TZA1_DIAGSEL_SHIFT)) & XCVR_ANALOG_RX_TZA_RX_TZA1_DIAGSEL_MASK)
8138 #define XCVR_ANALOG_RX_TZA_RX_TZA2_DIAGSEL_MASK  (0x2000000U)
8139 #define XCVR_ANALOG_RX_TZA_RX_TZA2_DIAGSEL_SHIFT (25U)
8140 #define XCVR_ANALOG_RX_TZA_RX_TZA2_DIAGSEL(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_TZA_RX_TZA2_DIAGSEL_SHIFT)) & XCVR_ANALOG_RX_TZA_RX_TZA2_DIAGSEL_MASK)
8141 #define XCVR_ANALOG_RX_TZA_RX_TZA3_DIAGSEL_MASK  (0x4000000U)
8142 #define XCVR_ANALOG_RX_TZA_RX_TZA3_DIAGSEL_SHIFT (26U)
8143 #define XCVR_ANALOG_RX_TZA_RX_TZA3_DIAGSEL(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_TZA_RX_TZA3_DIAGSEL_SHIFT)) & XCVR_ANALOG_RX_TZA_RX_TZA3_DIAGSEL_MASK)
8144 #define XCVR_ANALOG_RX_TZA_RX_TZA4_DIAGSEL_MASK  (0x8000000U)
8145 #define XCVR_ANALOG_RX_TZA_RX_TZA4_DIAGSEL_SHIFT (27U)
8146 #define XCVR_ANALOG_RX_TZA_RX_TZA4_DIAGSEL(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_TZA_RX_TZA4_DIAGSEL_SHIFT)) & XCVR_ANALOG_RX_TZA_RX_TZA4_DIAGSEL_MASK)
8147 
8148 /*! @name RX_AUXPLL - RF Analog Aux PLL Control */
8149 #define XCVR_ANALOG_RX_AUXPLL_BIAS_TRIM_MASK     (0x7U)
8150 #define XCVR_ANALOG_RX_AUXPLL_BIAS_TRIM_SHIFT    (0U)
8151 #define XCVR_ANALOG_RX_AUXPLL_BIAS_TRIM(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_AUXPLL_BIAS_TRIM_SHIFT)) & XCVR_ANALOG_RX_AUXPLL_BIAS_TRIM_MASK)
8152 #define XCVR_ANALOG_RX_AUXPLL_DIAGSEL1_MASK      (0x8U)
8153 #define XCVR_ANALOG_RX_AUXPLL_DIAGSEL1_SHIFT     (3U)
8154 #define XCVR_ANALOG_RX_AUXPLL_DIAGSEL1(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_AUXPLL_DIAGSEL1_SHIFT)) & XCVR_ANALOG_RX_AUXPLL_DIAGSEL1_MASK)
8155 #define XCVR_ANALOG_RX_AUXPLL_DIAGSEL2_MASK      (0x10U)
8156 #define XCVR_ANALOG_RX_AUXPLL_DIAGSEL2_SHIFT     (4U)
8157 #define XCVR_ANALOG_RX_AUXPLL_DIAGSEL2(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_AUXPLL_DIAGSEL2_SHIFT)) & XCVR_ANALOG_RX_AUXPLL_DIAGSEL2_MASK)
8158 #define XCVR_ANALOG_RX_AUXPLL_LF_CNTL_MASK       (0xE0U)
8159 #define XCVR_ANALOG_RX_AUXPLL_LF_CNTL_SHIFT      (5U)
8160 #define XCVR_ANALOG_RX_AUXPLL_LF_CNTL(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_AUXPLL_LF_CNTL_SHIFT)) & XCVR_ANALOG_RX_AUXPLL_LF_CNTL_MASK)
8161 #define XCVR_ANALOG_RX_AUXPLL_SPARE_MASK         (0xF00U)
8162 #define XCVR_ANALOG_RX_AUXPLL_SPARE_SHIFT        (8U)
8163 #define XCVR_ANALOG_RX_AUXPLL_SPARE(x)           (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_AUXPLL_SPARE_SHIFT)) & XCVR_ANALOG_RX_AUXPLL_SPARE_MASK)
8164 #define XCVR_ANALOG_RX_AUXPLL_VCO_DAC_REF_ADJUST_MASK (0xF000U)
8165 #define XCVR_ANALOG_RX_AUXPLL_VCO_DAC_REF_ADJUST_SHIFT (12U)
8166 #define XCVR_ANALOG_RX_AUXPLL_VCO_DAC_REF_ADJUST(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_AUXPLL_VCO_DAC_REF_ADJUST_SHIFT)) & XCVR_ANALOG_RX_AUXPLL_VCO_DAC_REF_ADJUST_MASK)
8167 #define XCVR_ANALOG_RX_AUXPLL_VTUNE_TESTMODE_MASK (0x10000U)
8168 #define XCVR_ANALOG_RX_AUXPLL_VTUNE_TESTMODE_SHIFT (16U)
8169 #define XCVR_ANALOG_RX_AUXPLL_VTUNE_TESTMODE(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_AUXPLL_VTUNE_TESTMODE_SHIFT)) & XCVR_ANALOG_RX_AUXPLL_VTUNE_TESTMODE_MASK)
8170 #define XCVR_ANALOG_RX_AUXPLL_RXTX_BAL_BIAST_MASK (0x300000U)
8171 #define XCVR_ANALOG_RX_AUXPLL_RXTX_BAL_BIAST_SHIFT (20U)
8172 #define XCVR_ANALOG_RX_AUXPLL_RXTX_BAL_BIAST(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_AUXPLL_RXTX_BAL_BIAST_SHIFT)) & XCVR_ANALOG_RX_AUXPLL_RXTX_BAL_BIAST_MASK)
8173 #define XCVR_ANALOG_RX_AUXPLL_RXTX_BAL_SPARE_MASK (0x7000000U)
8174 #define XCVR_ANALOG_RX_AUXPLL_RXTX_BAL_SPARE_SHIFT (24U)
8175 #define XCVR_ANALOG_RX_AUXPLL_RXTX_BAL_SPARE(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_AUXPLL_RXTX_BAL_SPARE_SHIFT)) & XCVR_ANALOG_RX_AUXPLL_RXTX_BAL_SPARE_MASK)
8176 #define XCVR_ANALOG_RX_AUXPLL_RXTX_RCCAL_DIAGSEL_MASK (0x10000000U)
8177 #define XCVR_ANALOG_RX_AUXPLL_RXTX_RCCAL_DIAGSEL_SHIFT (28U)
8178 #define XCVR_ANALOG_RX_AUXPLL_RXTX_RCCAL_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_AUXPLL_RXTX_RCCAL_DIAGSEL_SHIFT)) & XCVR_ANALOG_RX_AUXPLL_RXTX_RCCAL_DIAGSEL_MASK)
8179 
8180 /*! @name SY_CTRL_1 - RF Analog Synthesizer Control 1 */
8181 #define XCVR_ANALOG_SY_CTRL_1_SY_DIVN_SPARE_MASK (0x1U)
8182 #define XCVR_ANALOG_SY_CTRL_1_SY_DIVN_SPARE_SHIFT (0U)
8183 #define XCVR_ANALOG_SY_CTRL_1_SY_DIVN_SPARE(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_DIVN_SPARE_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_DIVN_SPARE_MASK)
8184 #define XCVR_ANALOG_SY_CTRL_1_SY_FCAL_SPARE_MASK (0x2U)
8185 #define XCVR_ANALOG_SY_CTRL_1_SY_FCAL_SPARE_SHIFT (1U)
8186 #define XCVR_ANALOG_SY_CTRL_1_SY_FCAL_SPARE(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_FCAL_SPARE_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_FCAL_SPARE_MASK)
8187 #define XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_FDBK_MASK (0x30U)
8188 #define XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_FDBK_SHIFT (4U)
8189 #define XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_FDBK(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_FDBK_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_FDBK_MASK)
8190 #define XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_RX_MASK (0xC0U)
8191 #define XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_RX_SHIFT (6U)
8192 #define XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_RX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_RX_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_RX_MASK)
8193 #define XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_TX_MASK (0x300U)
8194 #define XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_TX_SHIFT (8U)
8195 #define XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_TX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_TX_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_TX_MASK)
8196 #define XCVR_ANALOG_SY_CTRL_1_SY_LO_DIAGSEL_MASK (0x400U)
8197 #define XCVR_ANALOG_SY_CTRL_1_SY_LO_DIAGSEL_SHIFT (10U)
8198 #define XCVR_ANALOG_SY_CTRL_1_SY_LO_DIAGSEL(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_LO_DIAGSEL_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_LO_DIAGSEL_MASK)
8199 #define XCVR_ANALOG_SY_CTRL_1_SY_LO_SPARE_MASK   (0x7000U)
8200 #define XCVR_ANALOG_SY_CTRL_1_SY_LO_SPARE_SHIFT  (12U)
8201 #define XCVR_ANALOG_SY_CTRL_1_SY_LO_SPARE(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_LO_SPARE_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_LO_SPARE_MASK)
8202 #define XCVR_ANALOG_SY_CTRL_1_SY_LPF_FILT_CTRL_MASK (0x70000U)
8203 #define XCVR_ANALOG_SY_CTRL_1_SY_LPF_FILT_CTRL_SHIFT (16U)
8204 #define XCVR_ANALOG_SY_CTRL_1_SY_LPF_FILT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_LPF_FILT_CTRL_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_LPF_FILT_CTRL_MASK)
8205 #define XCVR_ANALOG_SY_CTRL_1_SY_LPF_SPARE_MASK  (0x80000U)
8206 #define XCVR_ANALOG_SY_CTRL_1_SY_LPF_SPARE_SHIFT (19U)
8207 #define XCVR_ANALOG_SY_CTRL_1_SY_LPF_SPARE(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_LPF_SPARE_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_LPF_SPARE_MASK)
8208 #define XCVR_ANALOG_SY_CTRL_1_SY_PD_DIAGSEL_MASK (0x100000U)
8209 #define XCVR_ANALOG_SY_CTRL_1_SY_PD_DIAGSEL_SHIFT (20U)
8210 #define XCVR_ANALOG_SY_CTRL_1_SY_PD_DIAGSEL(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_PD_DIAGSEL_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_PD_DIAGSEL_MASK)
8211 #define XCVR_ANALOG_SY_CTRL_1_SY_PD_PCH_TUNE_MASK (0x600000U)
8212 #define XCVR_ANALOG_SY_CTRL_1_SY_PD_PCH_TUNE_SHIFT (21U)
8213 #define XCVR_ANALOG_SY_CTRL_1_SY_PD_PCH_TUNE(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_PD_PCH_TUNE_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_PD_PCH_TUNE_MASK)
8214 #define XCVR_ANALOG_SY_CTRL_1_SY_PD_PCH_SEL_MASK (0x800000U)
8215 #define XCVR_ANALOG_SY_CTRL_1_SY_PD_PCH_SEL_SHIFT (23U)
8216 #define XCVR_ANALOG_SY_CTRL_1_SY_PD_PCH_SEL(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_PD_PCH_SEL_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_PD_PCH_SEL_MASK)
8217 #define XCVR_ANALOG_SY_CTRL_1_SY_PD_SPARE_MASK   (0x3000000U)
8218 #define XCVR_ANALOG_SY_CTRL_1_SY_PD_SPARE_SHIFT  (24U)
8219 #define XCVR_ANALOG_SY_CTRL_1_SY_PD_SPARE(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_PD_SPARE_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_PD_SPARE_MASK)
8220 #define XCVR_ANALOG_SY_CTRL_1_SY_PD_VTUNE_OVERRIDE_TEST_MODE_MASK (0x10000000U)
8221 #define XCVR_ANALOG_SY_CTRL_1_SY_PD_VTUNE_OVERRIDE_TEST_MODE_SHIFT (28U)
8222 #define XCVR_ANALOG_SY_CTRL_1_SY_PD_VTUNE_OVERRIDE_TEST_MODE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_PD_VTUNE_OVERRIDE_TEST_MODE_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_PD_VTUNE_OVERRIDE_TEST_MODE_MASK)
8223 
8224 /*! @name SY_CTRL_2 - RF Analog Synthesizer Control 2 */
8225 #define XCVR_ANALOG_SY_CTRL_2_SY_VCO_BIAS_MASK   (0x7U)
8226 #define XCVR_ANALOG_SY_CTRL_2_SY_VCO_BIAS_SHIFT  (0U)
8227 #define XCVR_ANALOG_SY_CTRL_2_SY_VCO_BIAS(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_2_SY_VCO_BIAS_SHIFT)) & XCVR_ANALOG_SY_CTRL_2_SY_VCO_BIAS_MASK)
8228 #define XCVR_ANALOG_SY_CTRL_2_SY_VCO_DIAGSEL_MASK (0x8U)
8229 #define XCVR_ANALOG_SY_CTRL_2_SY_VCO_DIAGSEL_SHIFT (3U)
8230 #define XCVR_ANALOG_SY_CTRL_2_SY_VCO_DIAGSEL(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_2_SY_VCO_DIAGSEL_SHIFT)) & XCVR_ANALOG_SY_CTRL_2_SY_VCO_DIAGSEL_MASK)
8231 #define XCVR_ANALOG_SY_CTRL_2_SY_VCO_KV_MASK     (0x70U)
8232 #define XCVR_ANALOG_SY_CTRL_2_SY_VCO_KV_SHIFT    (4U)
8233 #define XCVR_ANALOG_SY_CTRL_2_SY_VCO_KV(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_2_SY_VCO_KV_SHIFT)) & XCVR_ANALOG_SY_CTRL_2_SY_VCO_KV_MASK)
8234 #define XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK    (0x700U)
8235 #define XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_SHIFT   (8U)
8236 #define XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_SHIFT)) & XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK)
8237 #define XCVR_ANALOG_SY_CTRL_2_SY_VCO_PK_DET_ON_MASK (0x1000U)
8238 #define XCVR_ANALOG_SY_CTRL_2_SY_VCO_PK_DET_ON_SHIFT (12U)
8239 #define XCVR_ANALOG_SY_CTRL_2_SY_VCO_PK_DET_ON(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_2_SY_VCO_PK_DET_ON_SHIFT)) & XCVR_ANALOG_SY_CTRL_2_SY_VCO_PK_DET_ON_MASK)
8240 #define XCVR_ANALOG_SY_CTRL_2_SY_VCO_SPARE_MASK  (0x1C000U)
8241 #define XCVR_ANALOG_SY_CTRL_2_SY_VCO_SPARE_SHIFT (14U)
8242 #define XCVR_ANALOG_SY_CTRL_2_SY_VCO_SPARE(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_2_SY_VCO_SPARE_SHIFT)) & XCVR_ANALOG_SY_CTRL_2_SY_VCO_SPARE_MASK)
8243 
8244 /*! @name TX_DAC_PA - RF Analog TX HPM DAC and PA Control */
8245 #define XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_CAP_MASK (0x3U)
8246 #define XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_CAP_SHIFT (0U)
8247 #define XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_CAP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_CAP_SHIFT)) & XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_CAP_MASK)
8248 #define XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_IDAC_MASK (0x18U)
8249 #define XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_IDAC_SHIFT (3U)
8250 #define XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_IDAC(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_IDAC_SHIFT)) & XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_IDAC_MASK)
8251 #define XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_RLOAD_MASK (0xC0U)
8252 #define XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_RLOAD_SHIFT (6U)
8253 #define XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_RLOAD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_RLOAD_SHIFT)) & XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_RLOAD_MASK)
8254 #define XCVR_ANALOG_TX_DAC_PA_TX_DAC_DIAGSEL_MASK (0x200U)
8255 #define XCVR_ANALOG_TX_DAC_PA_TX_DAC_DIAGSEL_SHIFT (9U)
8256 #define XCVR_ANALOG_TX_DAC_PA_TX_DAC_DIAGSEL(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_TX_DAC_PA_TX_DAC_DIAGSEL_SHIFT)) & XCVR_ANALOG_TX_DAC_PA_TX_DAC_DIAGSEL_MASK)
8257 #define XCVR_ANALOG_TX_DAC_PA_TX_DAC_INVERT_CLK_MASK (0x400U)
8258 #define XCVR_ANALOG_TX_DAC_PA_TX_DAC_INVERT_CLK_SHIFT (10U)
8259 #define XCVR_ANALOG_TX_DAC_PA_TX_DAC_INVERT_CLK(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_TX_DAC_PA_TX_DAC_INVERT_CLK_SHIFT)) & XCVR_ANALOG_TX_DAC_PA_TX_DAC_INVERT_CLK_MASK)
8260 #define XCVR_ANALOG_TX_DAC_PA_TX_DAC_OPAMP_DIAGSEL_MASK (0x800U)
8261 #define XCVR_ANALOG_TX_DAC_PA_TX_DAC_OPAMP_DIAGSEL_SHIFT (11U)
8262 #define XCVR_ANALOG_TX_DAC_PA_TX_DAC_OPAMP_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_TX_DAC_PA_TX_DAC_OPAMP_DIAGSEL_SHIFT)) & XCVR_ANALOG_TX_DAC_PA_TX_DAC_OPAMP_DIAGSEL_MASK)
8263 #define XCVR_ANALOG_TX_DAC_PA_TX_DAC_SPARE_MASK  (0xE000U)
8264 #define XCVR_ANALOG_TX_DAC_PA_TX_DAC_SPARE_SHIFT (13U)
8265 #define XCVR_ANALOG_TX_DAC_PA_TX_DAC_SPARE(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_TX_DAC_PA_TX_DAC_SPARE_SHIFT)) & XCVR_ANALOG_TX_DAC_PA_TX_DAC_SPARE_MASK)
8266 #define XCVR_ANALOG_TX_DAC_PA_TX_PA_BUMP_VBIAS_MASK (0xE0000U)
8267 #define XCVR_ANALOG_TX_DAC_PA_TX_PA_BUMP_VBIAS_SHIFT (17U)
8268 #define XCVR_ANALOG_TX_DAC_PA_TX_PA_BUMP_VBIAS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_TX_DAC_PA_TX_PA_BUMP_VBIAS_SHIFT)) & XCVR_ANALOG_TX_DAC_PA_TX_PA_BUMP_VBIAS_MASK)
8269 #define XCVR_ANALOG_TX_DAC_PA_TX_PA_DIAGSEL_MASK (0x200000U)
8270 #define XCVR_ANALOG_TX_DAC_PA_TX_PA_DIAGSEL_SHIFT (21U)
8271 #define XCVR_ANALOG_TX_DAC_PA_TX_PA_DIAGSEL(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_TX_DAC_PA_TX_PA_DIAGSEL_SHIFT)) & XCVR_ANALOG_TX_DAC_PA_TX_PA_DIAGSEL_MASK)
8272 #define XCVR_ANALOG_TX_DAC_PA_TX_PA_SPARE_MASK   (0x3800000U)
8273 #define XCVR_ANALOG_TX_DAC_PA_TX_PA_SPARE_SHIFT  (23U)
8274 #define XCVR_ANALOG_TX_DAC_PA_TX_PA_SPARE(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_TX_DAC_PA_TX_PA_SPARE_SHIFT)) & XCVR_ANALOG_TX_DAC_PA_TX_PA_SPARE_MASK)
8275 
8276 /*! @name BALUN_TX - RF Analog Balun TX Mode Control */
8277 #define XCVR_ANALOG_BALUN_TX_RXTX_BAL_TX_CODE_MASK (0xFFFFFFU)
8278 #define XCVR_ANALOG_BALUN_TX_RXTX_BAL_TX_CODE_SHIFT (0U)
8279 #define XCVR_ANALOG_BALUN_TX_RXTX_BAL_TX_CODE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BALUN_TX_RXTX_BAL_TX_CODE_SHIFT)) & XCVR_ANALOG_BALUN_TX_RXTX_BAL_TX_CODE_MASK)
8280 
8281 /*! @name BALUN_RX - RF Analog Balun RX Mode Control */
8282 #define XCVR_ANALOG_BALUN_RX_RXTX_BAL_RX_CODE_MASK (0xFFFFFFU)
8283 #define XCVR_ANALOG_BALUN_RX_RXTX_BAL_RX_CODE_SHIFT (0U)
8284 #define XCVR_ANALOG_BALUN_RX_RXTX_BAL_RX_CODE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BALUN_RX_RXTX_BAL_RX_CODE_SHIFT)) & XCVR_ANALOG_BALUN_RX_RXTX_BAL_RX_CODE_MASK)
8285 
8286 /*! @name DFT_OBSV_1 - RF Analog DFT Observation Register 1 */
8287 #define XCVR_ANALOG_DFT_OBSV_1_DFT_FREQ_COUNTER_MASK (0x7FFFFU)
8288 #define XCVR_ANALOG_DFT_OBSV_1_DFT_FREQ_COUNTER_SHIFT (0U)
8289 #define XCVR_ANALOG_DFT_OBSV_1_DFT_FREQ_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_DFT_OBSV_1_DFT_FREQ_COUNTER_SHIFT)) & XCVR_ANALOG_DFT_OBSV_1_DFT_FREQ_COUNTER_MASK)
8290 #define XCVR_ANALOG_DFT_OBSV_1_CTUNE_MAX_DIFF_MASK (0xFF00000U)
8291 #define XCVR_ANALOG_DFT_OBSV_1_CTUNE_MAX_DIFF_SHIFT (20U)
8292 #define XCVR_ANALOG_DFT_OBSV_1_CTUNE_MAX_DIFF(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_DFT_OBSV_1_CTUNE_MAX_DIFF_SHIFT)) & XCVR_ANALOG_DFT_OBSV_1_CTUNE_MAX_DIFF_MASK)
8293 
8294 /*! @name DFT_OBSV_2 - RF Analog DFT Observation Register 2 */
8295 #define XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_MAX_DIFF_MASK (0x1FFFFU)
8296 #define XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_MAX_DIFF_SHIFT (0U)
8297 #define XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_MAX_DIFF(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_MAX_DIFF_SHIFT)) & XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_MAX_DIFF_MASK)
8298 #define XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_MAX_DIFF_CH_MASK (0x7F000000U)
8299 #define XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_MAX_DIFF_CH_SHIFT (24U)
8300 #define XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_MAX_DIFF_CH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_MAX_DIFF_CH_SHIFT)) & XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_MAX_DIFF_CH_MASK)
8301 #define XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_IGNORE_FAILS_MASK (0x80000000U)
8302 #define XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_IGNORE_FAILS_SHIFT (31U)
8303 #define XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_IGNORE_FAILS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_IGNORE_FAILS_SHIFT)) & XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_IGNORE_FAILS_MASK)
8304 
8305 
8306 /*!
8307  * @}
8308  */ /* end of group XCVR_ANALOG_Register_Masks */
8309 
8310 
8311 /* XCVR_ANALOG - Peripheral instance base addresses */
8312 /** Peripheral XCVR_ANA base address */
8313 #define XCVR_ANA_BASE                            (0x4005C500u)
8314 /** Peripheral XCVR_ANA base pointer */
8315 #define XCVR_ANA                                 ((XCVR_ANALOG_Type *)XCVR_ANA_BASE)
8316 /** Array initializer of XCVR_ANALOG peripheral base addresses */
8317 #define XCVR_ANALOG_BASE_ADDRS                   { XCVR_ANA_BASE }
8318 /** Array initializer of XCVR_ANALOG peripheral base pointers */
8319 #define XCVR_ANALOG_BASE_PTRS                    { XCVR_ANA }
8320 
8321 /*!
8322  * @}
8323  */ /* end of group XCVR_ANALOG_Peripheral_Access_Layer */
8324 
8325 
8326 /* ----------------------------------------------------------------------------
8327    -- XCVR_CTRL Peripheral Access Layer
8328    ---------------------------------------------------------------------------- */
8329 
8330 /*!
8331  * @addtogroup XCVR_CTRL_Peripheral_Access_Layer XCVR_CTRL Peripheral Access Layer
8332  * @{
8333  */
8334 
8335 /** XCVR_CTRL - Register Layout Typedef */
8336 typedef struct {
8337   __IO uint32_t XCVR_CTRL;                         /**< TRANSCEIVER CONTROL, offset: 0x0 */
8338   __IO uint32_t XCVR_STATUS;                       /**< TRANSCEIVER STATUS, offset: 0x4 */
8339   __IO uint32_t BLE_ARB_CTRL;                      /**< BLE ARBITRATION CONTROL, offset: 0x8 */
8340        uint8_t RESERVED_0[4];
8341   __IO uint32_t OVERWRITE_VER;                     /**< OVERWRITE VERSION, offset: 0x10 */
8342   __IO uint32_t DMA_CTRL;                          /**< TRANSCEIVER DMA CONTROL, offset: 0x14 */
8343   __I  uint32_t DMA_DATA;                          /**< TRANSCEIVER DMA DATA, offset: 0x18 */
8344   __IO uint32_t DTEST_CTRL;                        /**< DIGITAL TEST MUX CONTROL, offset: 0x1C */
8345   __IO uint32_t PACKET_RAM_CTRL;                   /**< PACKET RAM CONTROL, offset: 0x20 */
8346   __IO uint32_t FAD_CTRL;                          /**< FAD CONTROL, offset: 0x24 */
8347   __IO uint32_t LPPS_CTRL;                         /**< LOW POWER PREAMBLE SEARCH CONTROL, offset: 0x28 */
8348   __IO uint32_t RF_NOT_ALLOWED_CTRL;               /**< WIFI COEXISTENCE CONTROL, offset: 0x2C */
8349   __IO uint32_t CRCW_CFG;                          /**< CRC/WHITENER CONTROL, offset: 0x30 */
8350   __I  uint32_t CRC_EC_MASK;                       /**< CRC ERROR CORRECTION MASK, offset: 0x34 */
8351   __I  uint32_t CRC_RES_OUT;                       /**< CRC RESULT, offset: 0x38 */
8352 } XCVR_CTRL_Type;
8353 
8354 /* ----------------------------------------------------------------------------
8355    -- XCVR_CTRL Register Masks
8356    ---------------------------------------------------------------------------- */
8357 
8358 /*!
8359  * @addtogroup XCVR_CTRL_Register_Masks XCVR_CTRL Register Masks
8360  * @{
8361  */
8362 
8363 /*! @name XCVR_CTRL - TRANSCEIVER CONTROL */
8364 #define XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK        (0xFU)
8365 #define XCVR_CTRL_XCVR_CTRL_PROTOCOL_SHIFT       (0U)
8366 #define XCVR_CTRL_XCVR_CTRL_PROTOCOL(x)          (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_CTRL_PROTOCOL_SHIFT)) & XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK)
8367 #define XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK     (0x70U)
8368 #define XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_SHIFT    (4U)
8369 #define XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_SHIFT)) & XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK)
8370 #define XCVR_CTRL_XCVR_CTRL_REF_CLK_FREQ_MASK    (0x300U)
8371 #define XCVR_CTRL_XCVR_CTRL_REF_CLK_FREQ_SHIFT   (8U)
8372 #define XCVR_CTRL_XCVR_CTRL_REF_CLK_FREQ(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_CTRL_REF_CLK_FREQ_SHIFT)) & XCVR_CTRL_XCVR_CTRL_REF_CLK_FREQ_MASK)
8373 #define XCVR_CTRL_XCVR_CTRL_SOC_RF_OSC_CLK_GATE_EN_MASK (0x800U)
8374 #define XCVR_CTRL_XCVR_CTRL_SOC_RF_OSC_CLK_GATE_EN_SHIFT (11U)
8375 #define XCVR_CTRL_XCVR_CTRL_SOC_RF_OSC_CLK_GATE_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_CTRL_SOC_RF_OSC_CLK_GATE_EN_SHIFT)) & XCVR_CTRL_XCVR_CTRL_SOC_RF_OSC_CLK_GATE_EN_MASK)
8376 #define XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK       (0x3000U)
8377 #define XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_SHIFT      (12U)
8378 #define XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_SHIFT)) & XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK)
8379 #define XCVR_CTRL_XCVR_CTRL_RADIO0_IRQ_SEL_MASK  (0x70000U)
8380 #define XCVR_CTRL_XCVR_CTRL_RADIO0_IRQ_SEL_SHIFT (16U)
8381 #define XCVR_CTRL_XCVR_CTRL_RADIO0_IRQ_SEL(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_CTRL_RADIO0_IRQ_SEL_SHIFT)) & XCVR_CTRL_XCVR_CTRL_RADIO0_IRQ_SEL_MASK)
8382 #define XCVR_CTRL_XCVR_CTRL_RADIO1_IRQ_SEL_MASK  (0x700000U)
8383 #define XCVR_CTRL_XCVR_CTRL_RADIO1_IRQ_SEL_SHIFT (20U)
8384 #define XCVR_CTRL_XCVR_CTRL_RADIO1_IRQ_SEL(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_CTRL_RADIO1_IRQ_SEL_SHIFT)) & XCVR_CTRL_XCVR_CTRL_RADIO1_IRQ_SEL_MASK)
8385 
8386 /*! @name XCVR_STATUS - TRANSCEIVER STATUS */
8387 #define XCVR_CTRL_XCVR_STATUS_TSM_COUNT_MASK     (0xFFU)
8388 #define XCVR_CTRL_XCVR_STATUS_TSM_COUNT_SHIFT    (0U)
8389 #define XCVR_CTRL_XCVR_STATUS_TSM_COUNT(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_STATUS_TSM_COUNT_SHIFT)) & XCVR_CTRL_XCVR_STATUS_TSM_COUNT_MASK)
8390 #define XCVR_CTRL_XCVR_STATUS_PLL_SEQ_STATE_MASK (0xF00U)
8391 #define XCVR_CTRL_XCVR_STATUS_PLL_SEQ_STATE_SHIFT (8U)
8392 #define XCVR_CTRL_XCVR_STATUS_PLL_SEQ_STATE(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_STATUS_PLL_SEQ_STATE_SHIFT)) & XCVR_CTRL_XCVR_STATUS_PLL_SEQ_STATE_MASK)
8393 #define XCVR_CTRL_XCVR_STATUS_RX_MODE_MASK       (0x1000U)
8394 #define XCVR_CTRL_XCVR_STATUS_RX_MODE_SHIFT      (12U)
8395 #define XCVR_CTRL_XCVR_STATUS_RX_MODE(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_STATUS_RX_MODE_SHIFT)) & XCVR_CTRL_XCVR_STATUS_RX_MODE_MASK)
8396 #define XCVR_CTRL_XCVR_STATUS_TX_MODE_MASK       (0x2000U)
8397 #define XCVR_CTRL_XCVR_STATUS_TX_MODE_SHIFT      (13U)
8398 #define XCVR_CTRL_XCVR_STATUS_TX_MODE(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_STATUS_TX_MODE_SHIFT)) & XCVR_CTRL_XCVR_STATUS_TX_MODE_MASK)
8399 #define XCVR_CTRL_XCVR_STATUS_BTLE_SYSCLK_REQ_MASK (0x10000U)
8400 #define XCVR_CTRL_XCVR_STATUS_BTLE_SYSCLK_REQ_SHIFT (16U)
8401 #define XCVR_CTRL_XCVR_STATUS_BTLE_SYSCLK_REQ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_STATUS_BTLE_SYSCLK_REQ_SHIFT)) & XCVR_CTRL_XCVR_STATUS_BTLE_SYSCLK_REQ_MASK)
8402 #define XCVR_CTRL_XCVR_STATUS_RIF_LL_ACTIVE_MASK (0x20000U)
8403 #define XCVR_CTRL_XCVR_STATUS_RIF_LL_ACTIVE_SHIFT (17U)
8404 #define XCVR_CTRL_XCVR_STATUS_RIF_LL_ACTIVE(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_STATUS_RIF_LL_ACTIVE_SHIFT)) & XCVR_CTRL_XCVR_STATUS_RIF_LL_ACTIVE_MASK)
8405 #define XCVR_CTRL_XCVR_STATUS_XTAL_READY_MASK    (0x40000U)
8406 #define XCVR_CTRL_XCVR_STATUS_XTAL_READY_SHIFT   (18U)
8407 #define XCVR_CTRL_XCVR_STATUS_XTAL_READY(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_STATUS_XTAL_READY_SHIFT)) & XCVR_CTRL_XCVR_STATUS_XTAL_READY_MASK)
8408 #define XCVR_CTRL_XCVR_STATUS_SOC_USING_RF_OSC_CLK_MASK (0x80000U)
8409 #define XCVR_CTRL_XCVR_STATUS_SOC_USING_RF_OSC_CLK_SHIFT (19U)
8410 #define XCVR_CTRL_XCVR_STATUS_SOC_USING_RF_OSC_CLK(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_STATUS_SOC_USING_RF_OSC_CLK_SHIFT)) & XCVR_CTRL_XCVR_STATUS_SOC_USING_RF_OSC_CLK_MASK)
8411 #define XCVR_CTRL_XCVR_STATUS_TSM_IRQ0_MASK      (0x1000000U)
8412 #define XCVR_CTRL_XCVR_STATUS_TSM_IRQ0_SHIFT     (24U)
8413 #define XCVR_CTRL_XCVR_STATUS_TSM_IRQ0(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_STATUS_TSM_IRQ0_SHIFT)) & XCVR_CTRL_XCVR_STATUS_TSM_IRQ0_MASK)
8414 #define XCVR_CTRL_XCVR_STATUS_TSM_IRQ1_MASK      (0x2000000U)
8415 #define XCVR_CTRL_XCVR_STATUS_TSM_IRQ1_SHIFT     (25U)
8416 #define XCVR_CTRL_XCVR_STATUS_TSM_IRQ1(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_STATUS_TSM_IRQ1_SHIFT)) & XCVR_CTRL_XCVR_STATUS_TSM_IRQ1_MASK)
8417 
8418 /*! @name BLE_ARB_CTRL - BLE ARBITRATION CONTROL */
8419 #define XCVR_CTRL_BLE_ARB_CTRL_BLE_RELINQUISH_MASK (0x1U)
8420 #define XCVR_CTRL_BLE_ARB_CTRL_BLE_RELINQUISH_SHIFT (0U)
8421 #define XCVR_CTRL_BLE_ARB_CTRL_BLE_RELINQUISH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_BLE_ARB_CTRL_BLE_RELINQUISH_SHIFT)) & XCVR_CTRL_BLE_ARB_CTRL_BLE_RELINQUISH_MASK)
8422 #define XCVR_CTRL_BLE_ARB_CTRL_XCVR_BUSY_MASK    (0x2U)
8423 #define XCVR_CTRL_BLE_ARB_CTRL_XCVR_BUSY_SHIFT   (1U)
8424 #define XCVR_CTRL_BLE_ARB_CTRL_XCVR_BUSY(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_BLE_ARB_CTRL_XCVR_BUSY_SHIFT)) & XCVR_CTRL_BLE_ARB_CTRL_XCVR_BUSY_MASK)
8425 
8426 /*! @name OVERWRITE_VER - OVERWRITE VERSION */
8427 #define XCVR_CTRL_OVERWRITE_VER_OVERWRITE_VER_MASK (0xFFU)
8428 #define XCVR_CTRL_OVERWRITE_VER_OVERWRITE_VER_SHIFT (0U)
8429 #define XCVR_CTRL_OVERWRITE_VER_OVERWRITE_VER(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_OVERWRITE_VER_OVERWRITE_VER_SHIFT)) & XCVR_CTRL_OVERWRITE_VER_OVERWRITE_VER_MASK)
8430 
8431 /*! @name DMA_CTRL - TRANSCEIVER DMA CONTROL */
8432 #define XCVR_CTRL_DMA_CTRL_DMA_PAGE_MASK         (0xFU)
8433 #define XCVR_CTRL_DMA_CTRL_DMA_PAGE_SHIFT        (0U)
8434 #define XCVR_CTRL_DMA_CTRL_DMA_PAGE(x)           (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DMA_CTRL_DMA_PAGE_SHIFT)) & XCVR_CTRL_DMA_CTRL_DMA_PAGE_MASK)
8435 #define XCVR_CTRL_DMA_CTRL_SINGLE_REQ_MODE_MASK  (0x10U)
8436 #define XCVR_CTRL_DMA_CTRL_SINGLE_REQ_MODE_SHIFT (4U)
8437 #define XCVR_CTRL_DMA_CTRL_SINGLE_REQ_MODE(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DMA_CTRL_SINGLE_REQ_MODE_SHIFT)) & XCVR_CTRL_DMA_CTRL_SINGLE_REQ_MODE_MASK)
8438 #define XCVR_CTRL_DMA_CTRL_BYPASS_DMA_SYNC_MASK  (0x20U)
8439 #define XCVR_CTRL_DMA_CTRL_BYPASS_DMA_SYNC_SHIFT (5U)
8440 #define XCVR_CTRL_DMA_CTRL_BYPASS_DMA_SYNC(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DMA_CTRL_BYPASS_DMA_SYNC_SHIFT)) & XCVR_CTRL_DMA_CTRL_BYPASS_DMA_SYNC_MASK)
8441 #define XCVR_CTRL_DMA_CTRL_DMA_TRIGGERRED_MASK   (0x40U)
8442 #define XCVR_CTRL_DMA_CTRL_DMA_TRIGGERRED_SHIFT  (6U)
8443 #define XCVR_CTRL_DMA_CTRL_DMA_TRIGGERRED(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DMA_CTRL_DMA_TRIGGERRED_SHIFT)) & XCVR_CTRL_DMA_CTRL_DMA_TRIGGERRED_MASK)
8444 #define XCVR_CTRL_DMA_CTRL_DMA_TIMED_OUT_MASK    (0x80U)
8445 #define XCVR_CTRL_DMA_CTRL_DMA_TIMED_OUT_SHIFT   (7U)
8446 #define XCVR_CTRL_DMA_CTRL_DMA_TIMED_OUT(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DMA_CTRL_DMA_TIMED_OUT_SHIFT)) & XCVR_CTRL_DMA_CTRL_DMA_TIMED_OUT_MASK)
8447 #define XCVR_CTRL_DMA_CTRL_DMA_TIMEOUT_MASK      (0xF00U)
8448 #define XCVR_CTRL_DMA_CTRL_DMA_TIMEOUT_SHIFT     (8U)
8449 #define XCVR_CTRL_DMA_CTRL_DMA_TIMEOUT(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DMA_CTRL_DMA_TIMEOUT_SHIFT)) & XCVR_CTRL_DMA_CTRL_DMA_TIMEOUT_MASK)
8450 
8451 /*! @name DMA_DATA - TRANSCEIVER DMA DATA */
8452 #define XCVR_CTRL_DMA_DATA_DMA_DATA_MASK         (0xFFFFFFFFU)
8453 #define XCVR_CTRL_DMA_DATA_DMA_DATA_SHIFT        (0U)
8454 #define XCVR_CTRL_DMA_DATA_DMA_DATA(x)           (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DMA_DATA_DMA_DATA_SHIFT)) & XCVR_CTRL_DMA_DATA_DMA_DATA_MASK)
8455 
8456 /*! @name DTEST_CTRL - DIGITAL TEST MUX CONTROL */
8457 #define XCVR_CTRL_DTEST_CTRL_DTEST_PAGE_MASK     (0x3FU)
8458 #define XCVR_CTRL_DTEST_CTRL_DTEST_PAGE_SHIFT    (0U)
8459 #define XCVR_CTRL_DTEST_CTRL_DTEST_PAGE(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DTEST_CTRL_DTEST_PAGE_SHIFT)) & XCVR_CTRL_DTEST_CTRL_DTEST_PAGE_MASK)
8460 #define XCVR_CTRL_DTEST_CTRL_DTEST_EN_MASK       (0x80U)
8461 #define XCVR_CTRL_DTEST_CTRL_DTEST_EN_SHIFT      (7U)
8462 #define XCVR_CTRL_DTEST_CTRL_DTEST_EN(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DTEST_CTRL_DTEST_EN_SHIFT)) & XCVR_CTRL_DTEST_CTRL_DTEST_EN_MASK)
8463 #define XCVR_CTRL_DTEST_CTRL_GPIO0_OVLAY_PIN_MASK (0xF00U)
8464 #define XCVR_CTRL_DTEST_CTRL_GPIO0_OVLAY_PIN_SHIFT (8U)
8465 #define XCVR_CTRL_DTEST_CTRL_GPIO0_OVLAY_PIN(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DTEST_CTRL_GPIO0_OVLAY_PIN_SHIFT)) & XCVR_CTRL_DTEST_CTRL_GPIO0_OVLAY_PIN_MASK)
8466 #define XCVR_CTRL_DTEST_CTRL_GPIO1_OVLAY_PIN_MASK (0xF000U)
8467 #define XCVR_CTRL_DTEST_CTRL_GPIO1_OVLAY_PIN_SHIFT (12U)
8468 #define XCVR_CTRL_DTEST_CTRL_GPIO1_OVLAY_PIN(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DTEST_CTRL_GPIO1_OVLAY_PIN_SHIFT)) & XCVR_CTRL_DTEST_CTRL_GPIO1_OVLAY_PIN_MASK)
8469 #define XCVR_CTRL_DTEST_CTRL_TSM_GPIO_OVLAY_MASK (0x30000U)
8470 #define XCVR_CTRL_DTEST_CTRL_TSM_GPIO_OVLAY_SHIFT (16U)
8471 #define XCVR_CTRL_DTEST_CTRL_TSM_GPIO_OVLAY(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DTEST_CTRL_TSM_GPIO_OVLAY_SHIFT)) & XCVR_CTRL_DTEST_CTRL_TSM_GPIO_OVLAY_MASK)
8472 #define XCVR_CTRL_DTEST_CTRL_DTEST_SHFT_MASK     (0x7000000U)
8473 #define XCVR_CTRL_DTEST_CTRL_DTEST_SHFT_SHIFT    (24U)
8474 #define XCVR_CTRL_DTEST_CTRL_DTEST_SHFT(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DTEST_CTRL_DTEST_SHFT_SHIFT)) & XCVR_CTRL_DTEST_CTRL_DTEST_SHFT_MASK)
8475 #define XCVR_CTRL_DTEST_CTRL_RAW_MODE_I_MASK     (0x10000000U)
8476 #define XCVR_CTRL_DTEST_CTRL_RAW_MODE_I_SHIFT    (28U)
8477 #define XCVR_CTRL_DTEST_CTRL_RAW_MODE_I(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DTEST_CTRL_RAW_MODE_I_SHIFT)) & XCVR_CTRL_DTEST_CTRL_RAW_MODE_I_MASK)
8478 #define XCVR_CTRL_DTEST_CTRL_RAW_MODE_Q_MASK     (0x20000000U)
8479 #define XCVR_CTRL_DTEST_CTRL_RAW_MODE_Q_SHIFT    (29U)
8480 #define XCVR_CTRL_DTEST_CTRL_RAW_MODE_Q(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DTEST_CTRL_RAW_MODE_Q_SHIFT)) & XCVR_CTRL_DTEST_CTRL_RAW_MODE_Q_MASK)
8481 
8482 /*! @name PACKET_RAM_CTRL - PACKET RAM CONTROL */
8483 #define XCVR_CTRL_PACKET_RAM_CTRL_DBG_PAGE_MASK  (0xFU)
8484 #define XCVR_CTRL_PACKET_RAM_CTRL_DBG_PAGE_SHIFT (0U)
8485 #define XCVR_CTRL_PACKET_RAM_CTRL_DBG_PAGE(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_DBG_PAGE_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_DBG_PAGE_MASK)
8486 #define XCVR_CTRL_PACKET_RAM_CTRL_PB_PROTECT_MASK (0x10U)
8487 #define XCVR_CTRL_PACKET_RAM_CTRL_PB_PROTECT_SHIFT (4U)
8488 #define XCVR_CTRL_PACKET_RAM_CTRL_PB_PROTECT(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_PB_PROTECT_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_PB_PROTECT_MASK)
8489 #define XCVR_CTRL_PACKET_RAM_CTRL_XCVR_RAM_ALLOW_MASK (0x20U)
8490 #define XCVR_CTRL_PACKET_RAM_CTRL_XCVR_RAM_ALLOW_SHIFT (5U)
8491 #define XCVR_CTRL_PACKET_RAM_CTRL_XCVR_RAM_ALLOW(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_XCVR_RAM_ALLOW_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_XCVR_RAM_ALLOW_MASK)
8492 #define XCVR_CTRL_PACKET_RAM_CTRL_ALL_PROTOCOLS_ALLOW_MASK (0x40U)
8493 #define XCVR_CTRL_PACKET_RAM_CTRL_ALL_PROTOCOLS_ALLOW_SHIFT (6U)
8494 #define XCVR_CTRL_PACKET_RAM_CTRL_ALL_PROTOCOLS_ALLOW(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_ALL_PROTOCOLS_ALLOW_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_ALL_PROTOCOLS_ALLOW_MASK)
8495 #define XCVR_CTRL_PACKET_RAM_CTRL_DBG_TRIGGERRED_MASK (0x80U)
8496 #define XCVR_CTRL_PACKET_RAM_CTRL_DBG_TRIGGERRED_SHIFT (7U)
8497 #define XCVR_CTRL_PACKET_RAM_CTRL_DBG_TRIGGERRED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_DBG_TRIGGERRED_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_DBG_TRIGGERRED_MASK)
8498 #define XCVR_CTRL_PACKET_RAM_CTRL_DBG_RAM_FULL_MASK (0x300U)
8499 #define XCVR_CTRL_PACKET_RAM_CTRL_DBG_RAM_FULL_SHIFT (8U)
8500 #define XCVR_CTRL_PACKET_RAM_CTRL_DBG_RAM_FULL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_DBG_RAM_FULL_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_DBG_RAM_FULL_MASK)
8501 #define XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CLK_ON_OVRD_EN_MASK (0x400U)
8502 #define XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CLK_ON_OVRD_EN_SHIFT (10U)
8503 #define XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CLK_ON_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CLK_ON_OVRD_EN_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CLK_ON_OVRD_EN_MASK)
8504 #define XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CLK_ON_OVRD_MASK (0x800U)
8505 #define XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CLK_ON_OVRD_SHIFT (11U)
8506 #define XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CLK_ON_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CLK_ON_OVRD_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CLK_ON_OVRD_MASK)
8507 #define XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CLK_ON_OVRD_EN_MASK (0x1000U)
8508 #define XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CLK_ON_OVRD_EN_SHIFT (12U)
8509 #define XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CLK_ON_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CLK_ON_OVRD_EN_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CLK_ON_OVRD_EN_MASK)
8510 #define XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CLK_ON_OVRD_MASK (0x2000U)
8511 #define XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CLK_ON_OVRD_SHIFT (13U)
8512 #define XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CLK_ON_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CLK_ON_OVRD_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CLK_ON_OVRD_MASK)
8513 #define XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CE_ON_OVRD_EN_MASK (0x4000U)
8514 #define XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CE_ON_OVRD_EN_SHIFT (14U)
8515 #define XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CE_ON_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CE_ON_OVRD_EN_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CE_ON_OVRD_EN_MASK)
8516 #define XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CE_ON_OVRD_MASK (0x8000U)
8517 #define XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CE_ON_OVRD_SHIFT (15U)
8518 #define XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CE_ON_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CE_ON_OVRD_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CE_ON_OVRD_MASK)
8519 #define XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CE_ON_OVRD_EN_MASK (0x10000U)
8520 #define XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CE_ON_OVRD_EN_SHIFT (16U)
8521 #define XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CE_ON_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CE_ON_OVRD_EN_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CE_ON_OVRD_EN_MASK)
8522 #define XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CE_ON_OVRD_MASK (0x20000U)
8523 #define XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CE_ON_OVRD_SHIFT (17U)
8524 #define XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CE_ON_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CE_ON_OVRD_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CE_ON_OVRD_MASK)
8525 
8526 /*! @name FAD_CTRL - FAD CONTROL */
8527 #define XCVR_CTRL_FAD_CTRL_FAD_EN_MASK           (0x1U)
8528 #define XCVR_CTRL_FAD_CTRL_FAD_EN_SHIFT          (0U)
8529 #define XCVR_CTRL_FAD_CTRL_FAD_EN(x)             (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_FAD_CTRL_FAD_EN_SHIFT)) & XCVR_CTRL_FAD_CTRL_FAD_EN_MASK)
8530 #define XCVR_CTRL_FAD_CTRL_ANTX_MASK             (0x2U)
8531 #define XCVR_CTRL_FAD_CTRL_ANTX_SHIFT            (1U)
8532 #define XCVR_CTRL_FAD_CTRL_ANTX(x)               (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_FAD_CTRL_ANTX_SHIFT)) & XCVR_CTRL_FAD_CTRL_ANTX_MASK)
8533 #define XCVR_CTRL_FAD_CTRL_ANTX_EN_MASK          (0x30U)
8534 #define XCVR_CTRL_FAD_CTRL_ANTX_EN_SHIFT         (4U)
8535 #define XCVR_CTRL_FAD_CTRL_ANTX_EN(x)            (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_FAD_CTRL_ANTX_EN_SHIFT)) & XCVR_CTRL_FAD_CTRL_ANTX_EN_MASK)
8536 #define XCVR_CTRL_FAD_CTRL_ANTX_HZ_MASK          (0x40U)
8537 #define XCVR_CTRL_FAD_CTRL_ANTX_HZ_SHIFT         (6U)
8538 #define XCVR_CTRL_FAD_CTRL_ANTX_HZ(x)            (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_FAD_CTRL_ANTX_HZ_SHIFT)) & XCVR_CTRL_FAD_CTRL_ANTX_HZ_MASK)
8539 #define XCVR_CTRL_FAD_CTRL_ANTX_CTRLMODE_MASK    (0x80U)
8540 #define XCVR_CTRL_FAD_CTRL_ANTX_CTRLMODE_SHIFT   (7U)
8541 #define XCVR_CTRL_FAD_CTRL_ANTX_CTRLMODE(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_FAD_CTRL_ANTX_CTRLMODE_SHIFT)) & XCVR_CTRL_FAD_CTRL_ANTX_CTRLMODE_MASK)
8542 #define XCVR_CTRL_FAD_CTRL_ANTX_POL_MASK         (0xF00U)
8543 #define XCVR_CTRL_FAD_CTRL_ANTX_POL_SHIFT        (8U)
8544 #define XCVR_CTRL_FAD_CTRL_ANTX_POL(x)           (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_FAD_CTRL_ANTX_POL_SHIFT)) & XCVR_CTRL_FAD_CTRL_ANTX_POL_MASK)
8545 #define XCVR_CTRL_FAD_CTRL_FAD_NOT_GPIO_MASK     (0xF000U)
8546 #define XCVR_CTRL_FAD_CTRL_FAD_NOT_GPIO_SHIFT    (12U)
8547 #define XCVR_CTRL_FAD_CTRL_FAD_NOT_GPIO(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_FAD_CTRL_FAD_NOT_GPIO_SHIFT)) & XCVR_CTRL_FAD_CTRL_FAD_NOT_GPIO_MASK)
8548 
8549 /*! @name LPPS_CTRL - LOW POWER PREAMBLE SEARCH CONTROL */
8550 #define XCVR_CTRL_LPPS_CTRL_LPPS_ENABLE_MASK     (0x1U)
8551 #define XCVR_CTRL_LPPS_CTRL_LPPS_ENABLE_SHIFT    (0U)
8552 #define XCVR_CTRL_LPPS_CTRL_LPPS_ENABLE(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_LPPS_CTRL_LPPS_ENABLE_SHIFT)) & XCVR_CTRL_LPPS_CTRL_LPPS_ENABLE_MASK)
8553 #define XCVR_CTRL_LPPS_CTRL_LPPS_TZA_ALLOW_MASK  (0x2U)
8554 #define XCVR_CTRL_LPPS_CTRL_LPPS_TZA_ALLOW_SHIFT (1U)
8555 #define XCVR_CTRL_LPPS_CTRL_LPPS_TZA_ALLOW(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_LPPS_CTRL_LPPS_TZA_ALLOW_SHIFT)) & XCVR_CTRL_LPPS_CTRL_LPPS_TZA_ALLOW_MASK)
8556 #define XCVR_CTRL_LPPS_CTRL_LPPS_BBA_ALLOW_MASK  (0x4U)
8557 #define XCVR_CTRL_LPPS_CTRL_LPPS_BBA_ALLOW_SHIFT (2U)
8558 #define XCVR_CTRL_LPPS_CTRL_LPPS_BBA_ALLOW(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_LPPS_CTRL_LPPS_BBA_ALLOW_SHIFT)) & XCVR_CTRL_LPPS_CTRL_LPPS_BBA_ALLOW_MASK)
8559 #define XCVR_CTRL_LPPS_CTRL_LPPS_ADC_ALLOW_MASK  (0x8U)
8560 #define XCVR_CTRL_LPPS_CTRL_LPPS_ADC_ALLOW_SHIFT (3U)
8561 #define XCVR_CTRL_LPPS_CTRL_LPPS_ADC_ALLOW(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_LPPS_CTRL_LPPS_ADC_ALLOW_SHIFT)) & XCVR_CTRL_LPPS_CTRL_LPPS_ADC_ALLOW_MASK)
8562 #define XCVR_CTRL_LPPS_CTRL_LPPS_DCOC_ALLOW_MASK (0x10U)
8563 #define XCVR_CTRL_LPPS_CTRL_LPPS_DCOC_ALLOW_SHIFT (4U)
8564 #define XCVR_CTRL_LPPS_CTRL_LPPS_DCOC_ALLOW(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_LPPS_CTRL_LPPS_DCOC_ALLOW_SHIFT)) & XCVR_CTRL_LPPS_CTRL_LPPS_DCOC_ALLOW_MASK)
8565 #define XCVR_CTRL_LPPS_CTRL_LPPS_PDET_ALLOW_MASK (0x20U)
8566 #define XCVR_CTRL_LPPS_CTRL_LPPS_PDET_ALLOW_SHIFT (5U)
8567 #define XCVR_CTRL_LPPS_CTRL_LPPS_PDET_ALLOW(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_LPPS_CTRL_LPPS_PDET_ALLOW_SHIFT)) & XCVR_CTRL_LPPS_CTRL_LPPS_PDET_ALLOW_MASK)
8568 #define XCVR_CTRL_LPPS_CTRL_LPPS_SY_LO_ALLOW_MASK (0x40U)
8569 #define XCVR_CTRL_LPPS_CTRL_LPPS_SY_LO_ALLOW_SHIFT (6U)
8570 #define XCVR_CTRL_LPPS_CTRL_LPPS_SY_LO_ALLOW(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_LPPS_CTRL_LPPS_SY_LO_ALLOW_SHIFT)) & XCVR_CTRL_LPPS_CTRL_LPPS_SY_LO_ALLOW_MASK)
8571 #define XCVR_CTRL_LPPS_CTRL_LPPS_SY_LO_BUF_ALLOW_MASK (0x80U)
8572 #define XCVR_CTRL_LPPS_CTRL_LPPS_SY_LO_BUF_ALLOW_SHIFT (7U)
8573 #define XCVR_CTRL_LPPS_CTRL_LPPS_SY_LO_BUF_ALLOW(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_LPPS_CTRL_LPPS_SY_LO_BUF_ALLOW_SHIFT)) & XCVR_CTRL_LPPS_CTRL_LPPS_SY_LO_BUF_ALLOW_MASK)
8574 #define XCVR_CTRL_LPPS_CTRL_LPPS_RX_DIG_ALLOW_MASK (0x100U)
8575 #define XCVR_CTRL_LPPS_CTRL_LPPS_RX_DIG_ALLOW_SHIFT (8U)
8576 #define XCVR_CTRL_LPPS_CTRL_LPPS_RX_DIG_ALLOW(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_LPPS_CTRL_LPPS_RX_DIG_ALLOW_SHIFT)) & XCVR_CTRL_LPPS_CTRL_LPPS_RX_DIG_ALLOW_MASK)
8577 #define XCVR_CTRL_LPPS_CTRL_LPPS_DCOC_DIG_ALLOW_MASK (0x200U)
8578 #define XCVR_CTRL_LPPS_CTRL_LPPS_DCOC_DIG_ALLOW_SHIFT (9U)
8579 #define XCVR_CTRL_LPPS_CTRL_LPPS_DCOC_DIG_ALLOW(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_LPPS_CTRL_LPPS_DCOC_DIG_ALLOW_SHIFT)) & XCVR_CTRL_LPPS_CTRL_LPPS_DCOC_DIG_ALLOW_MASK)
8580 #define XCVR_CTRL_LPPS_CTRL_LPPS_START_RX_MASK   (0xFF0000U)
8581 #define XCVR_CTRL_LPPS_CTRL_LPPS_START_RX_SHIFT  (16U)
8582 #define XCVR_CTRL_LPPS_CTRL_LPPS_START_RX(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_LPPS_CTRL_LPPS_START_RX_SHIFT)) & XCVR_CTRL_LPPS_CTRL_LPPS_START_RX_MASK)
8583 #define XCVR_CTRL_LPPS_CTRL_LPPS_DEST_RX_MASK    (0xFF000000U)
8584 #define XCVR_CTRL_LPPS_CTRL_LPPS_DEST_RX_SHIFT   (24U)
8585 #define XCVR_CTRL_LPPS_CTRL_LPPS_DEST_RX(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_LPPS_CTRL_LPPS_DEST_RX_SHIFT)) & XCVR_CTRL_LPPS_CTRL_LPPS_DEST_RX_MASK)
8586 
8587 /*! @name RF_NOT_ALLOWED_CTRL - WIFI COEXISTENCE CONTROL */
8588 #define XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_NO_TX_MASK (0x1U)
8589 #define XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_NO_TX_SHIFT (0U)
8590 #define XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_NO_TX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_NO_TX_SHIFT)) & XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_NO_TX_MASK)
8591 #define XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_NO_RX_MASK (0x2U)
8592 #define XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_NO_RX_SHIFT (1U)
8593 #define XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_NO_RX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_NO_RX_SHIFT)) & XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_NO_RX_MASK)
8594 #define XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_ASSERTED_MASK (0x4U)
8595 #define XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_ASSERTED_SHIFT (2U)
8596 #define XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_ASSERTED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_ASSERTED_SHIFT)) & XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_ASSERTED_MASK)
8597 #define XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_TX_ABORT_MASK (0x8U)
8598 #define XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_TX_ABORT_SHIFT (3U)
8599 #define XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_TX_ABORT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_TX_ABORT_SHIFT)) & XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_TX_ABORT_MASK)
8600 #define XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_RX_ABORT_MASK (0x10U)
8601 #define XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_RX_ABORT_SHIFT (4U)
8602 #define XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_RX_ABORT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_RX_ABORT_SHIFT)) & XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_RX_ABORT_MASK)
8603 #define XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_MASK (0x20U)
8604 #define XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_SHIFT (5U)
8605 #define XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_SHIFT)) & XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_MASK)
8606 
8607 /*! @name CRCW_CFG - CRC/WHITENER CONTROL */
8608 #define XCVR_CTRL_CRCW_CFG_CRCW_EN_MASK          (0x1U)
8609 #define XCVR_CTRL_CRCW_CFG_CRCW_EN_SHIFT         (0U)
8610 #define XCVR_CTRL_CRCW_CFG_CRCW_EN(x)            (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_CRCW_CFG_CRCW_EN_SHIFT)) & XCVR_CTRL_CRCW_CFG_CRCW_EN_MASK)
8611 #define XCVR_CTRL_CRCW_CFG_CRC_ZERO_MASK         (0x2U)
8612 #define XCVR_CTRL_CRCW_CFG_CRC_ZERO_SHIFT        (1U)
8613 #define XCVR_CTRL_CRCW_CFG_CRC_ZERO(x)           (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_CRCW_CFG_CRC_ZERO_SHIFT)) & XCVR_CTRL_CRCW_CFG_CRC_ZERO_MASK)
8614 #define XCVR_CTRL_CRCW_CFG_CRC_EARLY_FAIL_MASK   (0x4U)
8615 #define XCVR_CTRL_CRCW_CFG_CRC_EARLY_FAIL_SHIFT  (2U)
8616 #define XCVR_CTRL_CRCW_CFG_CRC_EARLY_FAIL(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_CRCW_CFG_CRC_EARLY_FAIL_SHIFT)) & XCVR_CTRL_CRCW_CFG_CRC_EARLY_FAIL_MASK)
8617 #define XCVR_CTRL_CRCW_CFG_CRC_RES_OUT_VLD_MASK  (0x8U)
8618 #define XCVR_CTRL_CRCW_CFG_CRC_RES_OUT_VLD_SHIFT (3U)
8619 #define XCVR_CTRL_CRCW_CFG_CRC_RES_OUT_VLD(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_CRCW_CFG_CRC_RES_OUT_VLD_SHIFT)) & XCVR_CTRL_CRCW_CFG_CRC_RES_OUT_VLD_MASK)
8620 #define XCVR_CTRL_CRCW_CFG_CRC_EC_OFFSET_MASK    (0x7FF0000U)
8621 #define XCVR_CTRL_CRCW_CFG_CRC_EC_OFFSET_SHIFT   (16U)
8622 #define XCVR_CTRL_CRCW_CFG_CRC_EC_OFFSET(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_CRCW_CFG_CRC_EC_OFFSET_SHIFT)) & XCVR_CTRL_CRCW_CFG_CRC_EC_OFFSET_MASK)
8623 #define XCVR_CTRL_CRCW_CFG_CRC_EC_DONE_MASK      (0x10000000U)
8624 #define XCVR_CTRL_CRCW_CFG_CRC_EC_DONE_SHIFT     (28U)
8625 #define XCVR_CTRL_CRCW_CFG_CRC_EC_DONE(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_CRCW_CFG_CRC_EC_DONE_SHIFT)) & XCVR_CTRL_CRCW_CFG_CRC_EC_DONE_MASK)
8626 #define XCVR_CTRL_CRCW_CFG_CRC_EC_FAIL_MASK      (0x20000000U)
8627 #define XCVR_CTRL_CRCW_CFG_CRC_EC_FAIL_SHIFT     (29U)
8628 #define XCVR_CTRL_CRCW_CFG_CRC_EC_FAIL(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_CRCW_CFG_CRC_EC_FAIL_SHIFT)) & XCVR_CTRL_CRCW_CFG_CRC_EC_FAIL_MASK)
8629 
8630 /*! @name CRC_EC_MASK - CRC ERROR CORRECTION MASK */
8631 #define XCVR_CTRL_CRC_EC_MASK_CRC_EC_MASK_MASK   (0xFFFFFFFFU)
8632 #define XCVR_CTRL_CRC_EC_MASK_CRC_EC_MASK_SHIFT  (0U)
8633 #define XCVR_CTRL_CRC_EC_MASK_CRC_EC_MASK(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_CRC_EC_MASK_CRC_EC_MASK_SHIFT)) & XCVR_CTRL_CRC_EC_MASK_CRC_EC_MASK_MASK)
8634 
8635 /*! @name CRC_RES_OUT - CRC RESULT */
8636 #define XCVR_CTRL_CRC_RES_OUT_CRC_RES_OUT_MASK   (0xFFFFFFFFU)
8637 #define XCVR_CTRL_CRC_RES_OUT_CRC_RES_OUT_SHIFT  (0U)
8638 #define XCVR_CTRL_CRC_RES_OUT_CRC_RES_OUT(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_CRC_RES_OUT_CRC_RES_OUT_SHIFT)) & XCVR_CTRL_CRC_RES_OUT_CRC_RES_OUT_MASK)
8639 
8640 
8641 /*!
8642  * @}
8643  */ /* end of group XCVR_CTRL_Register_Masks */
8644 
8645 
8646 /* XCVR_CTRL - Peripheral instance base addresses */
8647 /** Peripheral XCVR_MISC base address */
8648 #define XCVR_MISC_BASE                           (0x4005C280u)
8649 /** Peripheral XCVR_MISC base pointer */
8650 #define XCVR_MISC                                ((XCVR_CTRL_Type *)XCVR_MISC_BASE)
8651 /** Array initializer of XCVR_CTRL peripheral base addresses */
8652 #define XCVR_CTRL_BASE_ADDRS                     { XCVR_MISC_BASE }
8653 /** Array initializer of XCVR_CTRL peripheral base pointers */
8654 #define XCVR_CTRL_BASE_PTRS                      { XCVR_MISC }
8655 
8656 /*!
8657  * @}
8658  */ /* end of group XCVR_CTRL_Peripheral_Access_Layer */
8659 
8660 
8661 /* ----------------------------------------------------------------------------
8662    -- XCVR_PHY Peripheral Access Layer
8663    ---------------------------------------------------------------------------- */
8664 
8665 /*!
8666  * @addtogroup XCVR_PHY_Peripheral_Access_Layer XCVR_PHY Peripheral Access Layer
8667  * @{
8668  */
8669 
8670 /** XCVR_PHY - Register Layout Typedef */
8671 typedef struct {
8672   __IO uint32_t PHY_PRE_REF0;                      /**< PREAMBLE REFERENCE WAVEFORM 0, offset: 0x0 */
8673   __IO uint32_t PRE_REF1;                          /**< PREAMBLE REFERENCE WAVEFORM 1, offset: 0x4 */
8674   __IO uint32_t PRE_REF2;                          /**< PREAMBLE REFERENCE WAVEFORM 2, offset: 0x8 */
8675        uint8_t RESERVED_0[20];
8676   __IO uint32_t CFG1;                              /**< PHY CONFIGURATION REGISTER 1, offset: 0x20 */
8677   __IO uint32_t CFG2;                              /**< PHY CONFIGURATION REGISTER 2, offset: 0x24 */
8678   __IO uint32_t EL_CFG;                            /**< PHY EARLY/LATE CONFIGURATION REGISTER, offset: 0x28 */
8679   __IO uint32_t NTW_ADR_BSM;                       /**< PHY NETWORK ADDRESS FOR BSM, offset: 0x2C */
8680   __I  uint32_t STATUS;                            /**< PHY STATUS REGISTER, offset: 0x30 */
8681 } XCVR_PHY_Type;
8682 
8683 /* ----------------------------------------------------------------------------
8684    -- XCVR_PHY Register Masks
8685    ---------------------------------------------------------------------------- */
8686 
8687 /*!
8688  * @addtogroup XCVR_PHY_Register_Masks XCVR_PHY Register Masks
8689  * @{
8690  */
8691 
8692 /*! @name PHY_PRE_REF0 - PREAMBLE REFERENCE WAVEFORM 0 */
8693 #define XCVR_PHY_PHY_PRE_REF0_FSK_PREAMBLE_REF0_MASK (0xFFFFFFFFU)
8694 #define XCVR_PHY_PHY_PRE_REF0_FSK_PREAMBLE_REF0_SHIFT (0U)
8695 #define XCVR_PHY_PHY_PRE_REF0_FSK_PREAMBLE_REF0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_PRE_REF0_FSK_PREAMBLE_REF0_SHIFT)) & XCVR_PHY_PHY_PRE_REF0_FSK_PREAMBLE_REF0_MASK)
8696 
8697 /*! @name PRE_REF1 - PREAMBLE REFERENCE WAVEFORM 1 */
8698 #define XCVR_PHY_PRE_REF1_FSK_PREAMBLE_REF1_MASK (0xFFFFFFFFU)
8699 #define XCVR_PHY_PRE_REF1_FSK_PREAMBLE_REF1_SHIFT (0U)
8700 #define XCVR_PHY_PRE_REF1_FSK_PREAMBLE_REF1(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PRE_REF1_FSK_PREAMBLE_REF1_SHIFT)) & XCVR_PHY_PRE_REF1_FSK_PREAMBLE_REF1_MASK)
8701 
8702 /*! @name PRE_REF2 - PREAMBLE REFERENCE WAVEFORM 2 */
8703 #define XCVR_PHY_PRE_REF2_FSK_PREAMBLE_REF2_MASK (0xFFFFU)
8704 #define XCVR_PHY_PRE_REF2_FSK_PREAMBLE_REF2_SHIFT (0U)
8705 #define XCVR_PHY_PRE_REF2_FSK_PREAMBLE_REF2(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PRE_REF2_FSK_PREAMBLE_REF2_SHIFT)) & XCVR_PHY_PRE_REF2_FSK_PREAMBLE_REF2_MASK)
8706 
8707 /*! @name CFG1 - PHY CONFIGURATION REGISTER 1 */
8708 #define XCVR_PHY_CFG1_AA_PLAYBACK_MASK           (0x2U)
8709 #define XCVR_PHY_CFG1_AA_PLAYBACK_SHIFT          (1U)
8710 #define XCVR_PHY_CFG1_AA_PLAYBACK(x)             (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG1_AA_PLAYBACK_SHIFT)) & XCVR_PHY_CFG1_AA_PLAYBACK_MASK)
8711 #define XCVR_PHY_CFG1_AA_OUTPUT_SEL_MASK         (0x4U)
8712 #define XCVR_PHY_CFG1_AA_OUTPUT_SEL_SHIFT        (2U)
8713 #define XCVR_PHY_CFG1_AA_OUTPUT_SEL(x)           (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG1_AA_OUTPUT_SEL_SHIFT)) & XCVR_PHY_CFG1_AA_OUTPUT_SEL_MASK)
8714 #define XCVR_PHY_CFG1_FSK_BIT_INVERT_MASK        (0x8U)
8715 #define XCVR_PHY_CFG1_FSK_BIT_INVERT_SHIFT       (3U)
8716 #define XCVR_PHY_CFG1_FSK_BIT_INVERT(x)          (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG1_FSK_BIT_INVERT_SHIFT)) & XCVR_PHY_CFG1_FSK_BIT_INVERT_MASK)
8717 #define XCVR_PHY_CFG1_RFU00_MASK                 (0x10U)
8718 #define XCVR_PHY_CFG1_RFU00_SHIFT                (4U)
8719 #define XCVR_PHY_CFG1_RFU00(x)                   (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG1_RFU00_SHIFT)) & XCVR_PHY_CFG1_RFU00_MASK)
8720 #define XCVR_PHY_CFG1_BSM_EN_BLE_MASK            (0x20U)
8721 #define XCVR_PHY_CFG1_BSM_EN_BLE_SHIFT           (5U)
8722 #define XCVR_PHY_CFG1_BSM_EN_BLE(x)              (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG1_BSM_EN_BLE_SHIFT)) & XCVR_PHY_CFG1_BSM_EN_BLE_MASK)
8723 #define XCVR_PHY_CFG1_DEMOD_CLK_MODE_MASK        (0xC0U)
8724 #define XCVR_PHY_CFG1_DEMOD_CLK_MODE_SHIFT       (6U)
8725 #define XCVR_PHY_CFG1_DEMOD_CLK_MODE(x)          (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG1_DEMOD_CLK_MODE_SHIFT)) & XCVR_PHY_CFG1_DEMOD_CLK_MODE_MASK)
8726 #define XCVR_PHY_CFG1_CTS_THRESH_MASK            (0xFF00U)
8727 #define XCVR_PHY_CFG1_CTS_THRESH_SHIFT           (8U)
8728 #define XCVR_PHY_CFG1_CTS_THRESH(x)              (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG1_CTS_THRESH_SHIFT)) & XCVR_PHY_CFG1_CTS_THRESH_MASK)
8729 #define XCVR_PHY_CFG1_FSK_FTS_TIMEOUT_MASK       (0x700000U)
8730 #define XCVR_PHY_CFG1_FSK_FTS_TIMEOUT_SHIFT      (20U)
8731 #define XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG1_FSK_FTS_TIMEOUT_SHIFT)) & XCVR_PHY_CFG1_FSK_FTS_TIMEOUT_MASK)
8732 #define XCVR_PHY_CFG1_RFU01_MASK                 (0x1000000U)
8733 #define XCVR_PHY_CFG1_RFU01_SHIFT                (24U)
8734 #define XCVR_PHY_CFG1_RFU01(x)                   (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG1_RFU01_SHIFT)) & XCVR_PHY_CFG1_RFU01_MASK)
8735 #define XCVR_PHY_CFG1_RFU02_MASK                 (0x2000000U)
8736 #define XCVR_PHY_CFG1_RFU02_SHIFT                (25U)
8737 #define XCVR_PHY_CFG1_RFU02(x)                   (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG1_RFU02_SHIFT)) & XCVR_PHY_CFG1_RFU02_MASK)
8738 #define XCVR_PHY_CFG1_BLE_NTW_ADR_THR_MASK       (0x70000000U)
8739 #define XCVR_PHY_CFG1_BLE_NTW_ADR_THR_SHIFT      (28U)
8740 #define XCVR_PHY_CFG1_BLE_NTW_ADR_THR(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG1_BLE_NTW_ADR_THR_SHIFT)) & XCVR_PHY_CFG1_BLE_NTW_ADR_THR_MASK)
8741 
8742 /*! @name CFG2 - PHY CONFIGURATION REGISTER 2 */
8743 #define XCVR_PHY_CFG2_PHY_FIFO_PRECHG_MASK       (0xFU)
8744 #define XCVR_PHY_CFG2_PHY_FIFO_PRECHG_SHIFT      (0U)
8745 #define XCVR_PHY_CFG2_PHY_FIFO_PRECHG(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG2_PHY_FIFO_PRECHG_SHIFT)) & XCVR_PHY_CFG2_PHY_FIFO_PRECHG_MASK)
8746 #define XCVR_PHY_CFG2_RFU03_MASK                 (0x10U)
8747 #define XCVR_PHY_CFG2_RFU03_SHIFT                (4U)
8748 #define XCVR_PHY_CFG2_RFU03(x)                   (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG2_RFU03_SHIFT)) & XCVR_PHY_CFG2_RFU03_MASK)
8749 #define XCVR_PHY_CFG2_RFU04_MASK                 (0x20U)
8750 #define XCVR_PHY_CFG2_RFU04_SHIFT                (5U)
8751 #define XCVR_PHY_CFG2_RFU04(x)                   (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG2_RFU04_SHIFT)) & XCVR_PHY_CFG2_RFU04_MASK)
8752 #define XCVR_PHY_CFG2_RFU05_MASK                 (0x40U)
8753 #define XCVR_PHY_CFG2_RFU05_SHIFT                (6U)
8754 #define XCVR_PHY_CFG2_RFU05(x)                   (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG2_RFU05_SHIFT)) & XCVR_PHY_CFG2_RFU05_MASK)
8755 #define XCVR_PHY_CFG2_RFU06_MASK                 (0x80U)
8756 #define XCVR_PHY_CFG2_RFU06_SHIFT                (7U)
8757 #define XCVR_PHY_CFG2_RFU06(x)                   (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG2_RFU06_SHIFT)) & XCVR_PHY_CFG2_RFU06_MASK)
8758 #define XCVR_PHY_CFG2_X2_DEMOD_GAIN_MASK         (0xF00U)
8759 #define XCVR_PHY_CFG2_X2_DEMOD_GAIN_SHIFT        (8U)
8760 #define XCVR_PHY_CFG2_X2_DEMOD_GAIN(x)           (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG2_X2_DEMOD_GAIN_SHIFT)) & XCVR_PHY_CFG2_X2_DEMOD_GAIN_MASK)
8761 #define XCVR_PHY_CFG2_RFU07_MASK                 (0x10000U)
8762 #define XCVR_PHY_CFG2_RFU07_SHIFT                (16U)
8763 #define XCVR_PHY_CFG2_RFU07(x)                   (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG2_RFU07_SHIFT)) & XCVR_PHY_CFG2_RFU07_MASK)
8764 #define XCVR_PHY_CFG2_RFU08_MASK                 (0x20000U)
8765 #define XCVR_PHY_CFG2_RFU08_SHIFT                (17U)
8766 #define XCVR_PHY_CFG2_RFU08(x)                   (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG2_RFU08_SHIFT)) & XCVR_PHY_CFG2_RFU08_MASK)
8767 #define XCVR_PHY_CFG2_RFU09_MASK                 (0x40000U)
8768 #define XCVR_PHY_CFG2_RFU09_SHIFT                (18U)
8769 #define XCVR_PHY_CFG2_RFU09(x)                   (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG2_RFU09_SHIFT)) & XCVR_PHY_CFG2_RFU09_MASK)
8770 #define XCVR_PHY_CFG2_RFU10_MASK                 (0x80000U)
8771 #define XCVR_PHY_CFG2_RFU10_SHIFT                (19U)
8772 #define XCVR_PHY_CFG2_RFU10(x)                   (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG2_RFU10_SHIFT)) & XCVR_PHY_CFG2_RFU10_MASK)
8773 #define XCVR_PHY_CFG2_RFU11_MASK                 (0x100000U)
8774 #define XCVR_PHY_CFG2_RFU11_SHIFT                (20U)
8775 #define XCVR_PHY_CFG2_RFU11(x)                   (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG2_RFU11_SHIFT)) & XCVR_PHY_CFG2_RFU11_MASK)
8776 #define XCVR_PHY_CFG2_RFU12_MASK                 (0x200000U)
8777 #define XCVR_PHY_CFG2_RFU12_SHIFT                (21U)
8778 #define XCVR_PHY_CFG2_RFU12(x)                   (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG2_RFU12_SHIFT)) & XCVR_PHY_CFG2_RFU12_MASK)
8779 #define XCVR_PHY_CFG2_RFU13_MASK                 (0x400000U)
8780 #define XCVR_PHY_CFG2_RFU13_SHIFT                (22U)
8781 #define XCVR_PHY_CFG2_RFU13(x)                   (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG2_RFU13_SHIFT)) & XCVR_PHY_CFG2_RFU13_MASK)
8782 #define XCVR_PHY_CFG2_RFU14_MASK                 (0x800000U)
8783 #define XCVR_PHY_CFG2_RFU14_SHIFT                (23U)
8784 #define XCVR_PHY_CFG2_RFU14(x)                   (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG2_RFU14_SHIFT)) & XCVR_PHY_CFG2_RFU14_MASK)
8785 #define XCVR_PHY_CFG2_RFU15_MASK                 (0x1000000U)
8786 #define XCVR_PHY_CFG2_RFU15_SHIFT                (24U)
8787 #define XCVR_PHY_CFG2_RFU15(x)                   (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG2_RFU15_SHIFT)) & XCVR_PHY_CFG2_RFU15_MASK)
8788 #define XCVR_PHY_CFG2_RFU16_MASK                 (0x2000000U)
8789 #define XCVR_PHY_CFG2_RFU16_SHIFT                (25U)
8790 #define XCVR_PHY_CFG2_RFU16(x)                   (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG2_RFU16_SHIFT)) & XCVR_PHY_CFG2_RFU16_MASK)
8791 #define XCVR_PHY_CFG2_PHY_CLK_ON_MASK            (0x80000000U)
8792 #define XCVR_PHY_CFG2_PHY_CLK_ON_SHIFT           (31U)
8793 #define XCVR_PHY_CFG2_PHY_CLK_ON(x)              (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG2_PHY_CLK_ON_SHIFT)) & XCVR_PHY_CFG2_PHY_CLK_ON_MASK)
8794 
8795 /*! @name EL_CFG - PHY EARLY/LATE CONFIGURATION REGISTER */
8796 #define XCVR_PHY_EL_CFG_EL_ENABLE_MASK           (0x1U)
8797 #define XCVR_PHY_EL_CFG_EL_ENABLE_SHIFT          (0U)
8798 #define XCVR_PHY_EL_CFG_EL_ENABLE(x)             (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_EL_CFG_EL_ENABLE_SHIFT)) & XCVR_PHY_EL_CFG_EL_ENABLE_MASK)
8799 #define XCVR_PHY_EL_CFG_EL_ZB_ENABLE_MASK        (0x2U)
8800 #define XCVR_PHY_EL_CFG_EL_ZB_ENABLE_SHIFT       (1U)
8801 #define XCVR_PHY_EL_CFG_EL_ZB_ENABLE(x)          (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_EL_CFG_EL_ZB_ENABLE_SHIFT)) & XCVR_PHY_EL_CFG_EL_ZB_ENABLE_MASK)
8802 #define XCVR_PHY_EL_CFG_EL_ZB_WIN_SIZE_MASK      (0x4U)
8803 #define XCVR_PHY_EL_CFG_EL_ZB_WIN_SIZE_SHIFT     (2U)
8804 #define XCVR_PHY_EL_CFG_EL_ZB_WIN_SIZE(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_EL_CFG_EL_ZB_WIN_SIZE_SHIFT)) & XCVR_PHY_EL_CFG_EL_ZB_WIN_SIZE_MASK)
8805 #define XCVR_PHY_EL_CFG_EL_WIN_SIZE_MASK         (0xF00U)
8806 #define XCVR_PHY_EL_CFG_EL_WIN_SIZE_SHIFT        (8U)
8807 #define XCVR_PHY_EL_CFG_EL_WIN_SIZE(x)           (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_EL_CFG_EL_WIN_SIZE_SHIFT)) & XCVR_PHY_EL_CFG_EL_WIN_SIZE_MASK)
8808 #define XCVR_PHY_EL_CFG_EL_INTERVAL_MASK         (0x3F0000U)
8809 #define XCVR_PHY_EL_CFG_EL_INTERVAL_SHIFT        (16U)
8810 #define XCVR_PHY_EL_CFG_EL_INTERVAL(x)           (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_EL_CFG_EL_INTERVAL_SHIFT)) & XCVR_PHY_EL_CFG_EL_INTERVAL_MASK)
8811 
8812 /*! @name NTW_ADR_BSM - PHY NETWORK ADDRESS FOR BSM */
8813 #define XCVR_PHY_NTW_ADR_BSM_NTW_ADR_BSM_MASK    (0xFFFFFFFFU)
8814 #define XCVR_PHY_NTW_ADR_BSM_NTW_ADR_BSM_SHIFT   (0U)
8815 #define XCVR_PHY_NTW_ADR_BSM_NTW_ADR_BSM(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_NTW_ADR_BSM_NTW_ADR_BSM_SHIFT)) & XCVR_PHY_NTW_ADR_BSM_NTW_ADR_BSM_MASK)
8816 
8817 /*! @name STATUS - PHY STATUS REGISTER */
8818 #define XCVR_PHY_STATUS_PREAMBLE_FOUND_MASK      (0x1U)
8819 #define XCVR_PHY_STATUS_PREAMBLE_FOUND_SHIFT     (0U)
8820 #define XCVR_PHY_STATUS_PREAMBLE_FOUND(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_STATUS_PREAMBLE_FOUND_SHIFT)) & XCVR_PHY_STATUS_PREAMBLE_FOUND_MASK)
8821 #define XCVR_PHY_STATUS_AA_SFD_MATCHED_MASK      (0x2U)
8822 #define XCVR_PHY_STATUS_AA_SFD_MATCHED_SHIFT     (1U)
8823 #define XCVR_PHY_STATUS_AA_SFD_MATCHED(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_STATUS_AA_SFD_MATCHED_SHIFT)) & XCVR_PHY_STATUS_AA_SFD_MATCHED_MASK)
8824 #define XCVR_PHY_STATUS_AA_MATCHED_MASK          (0xF0U)
8825 #define XCVR_PHY_STATUS_AA_MATCHED_SHIFT         (4U)
8826 #define XCVR_PHY_STATUS_AA_MATCHED(x)            (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_STATUS_AA_MATCHED_SHIFT)) & XCVR_PHY_STATUS_AA_MATCHED_MASK)
8827 #define XCVR_PHY_STATUS_HAMMING_DISTANCE_MASK    (0x700U)
8828 #define XCVR_PHY_STATUS_HAMMING_DISTANCE_SHIFT   (8U)
8829 #define XCVR_PHY_STATUS_HAMMING_DISTANCE(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_STATUS_HAMMING_DISTANCE_SHIFT)) & XCVR_PHY_STATUS_HAMMING_DISTANCE_MASK)
8830 #define XCVR_PHY_STATUS_DATA_FIFO_DEPTH_MASK     (0xF000U)
8831 #define XCVR_PHY_STATUS_DATA_FIFO_DEPTH_SHIFT    (12U)
8832 #define XCVR_PHY_STATUS_DATA_FIFO_DEPTH(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_STATUS_DATA_FIFO_DEPTH_SHIFT)) & XCVR_PHY_STATUS_DATA_FIFO_DEPTH_MASK)
8833 #define XCVR_PHY_STATUS_CFO_ESTIMATE_MASK        (0xFF0000U)
8834 #define XCVR_PHY_STATUS_CFO_ESTIMATE_SHIFT       (16U)
8835 #define XCVR_PHY_STATUS_CFO_ESTIMATE(x)          (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_STATUS_CFO_ESTIMATE_SHIFT)) & XCVR_PHY_STATUS_CFO_ESTIMATE_MASK)
8836 
8837 
8838 /*!
8839  * @}
8840  */ /* end of group XCVR_PHY_Register_Masks */
8841 
8842 
8843 /* XCVR_PHY - Peripheral instance base addresses */
8844 /** Peripheral XCVR_PHY base address */
8845 #define XCVR_PHY_BASE                            (0x4005C400u)
8846 /** Peripheral XCVR_PHY base pointer */
8847 #define XCVR_PHY                                 ((XCVR_PHY_Type *)XCVR_PHY_BASE)
8848 /** Array initializer of XCVR_PHY peripheral base addresses */
8849 #define XCVR_PHY_BASE_ADDRS                      { XCVR_PHY_BASE }
8850 /** Array initializer of XCVR_PHY peripheral base pointers */
8851 #define XCVR_PHY_BASE_PTRS                       { XCVR_PHY }
8852 
8853 /*!
8854  * @}
8855  */ /* end of group XCVR_PHY_Peripheral_Access_Layer */
8856 
8857 
8858 /* ----------------------------------------------------------------------------
8859    -- XCVR_PKT_RAM Peripheral Access Layer
8860    ---------------------------------------------------------------------------- */
8861 
8862 /*!
8863  * @addtogroup XCVR_PKT_RAM_Peripheral_Access_Layer XCVR_PKT_RAM Peripheral Access Layer
8864  * @{
8865  */
8866 
8867 /** XCVR_PKT_RAM - Register Layout Typedef */
8868 typedef struct {
8869   __IO uint16_t PACKET_RAM_0[544];                 /**< Shared Packet RAM for multiple Link Layer usage., array offset: 0x0, array step: 0x2 */
8870   __IO uint16_t PACKET_RAM_1[544];                 /**< Shared Packet RAM for multiple Link Layer usage., array offset: 0x440, array step: 0x2 */
8871 } XCVR_PKT_RAM_Type;
8872 
8873 /* ----------------------------------------------------------------------------
8874    -- XCVR_PKT_RAM Register Masks
8875    ---------------------------------------------------------------------------- */
8876 
8877 /*!
8878  * @addtogroup XCVR_PKT_RAM_Register_Masks XCVR_PKT_RAM Register Masks
8879  * @{
8880  */
8881 
8882 /*! @name PACKET_RAM_0 - Shared Packet RAM for multiple Link Layer usage. */
8883 #define XCVR_PKT_RAM_PACKET_RAM_0_LSBYTE_MASK    (0xFFU)
8884 #define XCVR_PKT_RAM_PACKET_RAM_0_LSBYTE_SHIFT   (0U)
8885 #define XCVR_PKT_RAM_PACKET_RAM_0_LSBYTE(x)      (((uint16_t)(((uint16_t)(x)) << XCVR_PKT_RAM_PACKET_RAM_0_LSBYTE_SHIFT)) & XCVR_PKT_RAM_PACKET_RAM_0_LSBYTE_MASK)
8886 #define XCVR_PKT_RAM_PACKET_RAM_0_MSBYTE_MASK    (0xFF00U)
8887 #define XCVR_PKT_RAM_PACKET_RAM_0_MSBYTE_SHIFT   (8U)
8888 #define XCVR_PKT_RAM_PACKET_RAM_0_MSBYTE(x)      (((uint16_t)(((uint16_t)(x)) << XCVR_PKT_RAM_PACKET_RAM_0_MSBYTE_SHIFT)) & XCVR_PKT_RAM_PACKET_RAM_0_MSBYTE_MASK)
8889 
8890 /* The count of XCVR_PKT_RAM_PACKET_RAM_0 */
8891 #define XCVR_PKT_RAM_PACKET_RAM_0_COUNT          (544U)
8892 
8893 /*! @name PACKET_RAM_1 - Shared Packet RAM for multiple Link Layer usage. */
8894 #define XCVR_PKT_RAM_PACKET_RAM_1_LSBYTE_MASK    (0xFFU)
8895 #define XCVR_PKT_RAM_PACKET_RAM_1_LSBYTE_SHIFT   (0U)
8896 #define XCVR_PKT_RAM_PACKET_RAM_1_LSBYTE(x)      (((uint16_t)(((uint16_t)(x)) << XCVR_PKT_RAM_PACKET_RAM_1_LSBYTE_SHIFT)) & XCVR_PKT_RAM_PACKET_RAM_1_LSBYTE_MASK)
8897 #define XCVR_PKT_RAM_PACKET_RAM_1_MSBYTE_MASK    (0xFF00U)
8898 #define XCVR_PKT_RAM_PACKET_RAM_1_MSBYTE_SHIFT   (8U)
8899 #define XCVR_PKT_RAM_PACKET_RAM_1_MSBYTE(x)      (((uint16_t)(((uint16_t)(x)) << XCVR_PKT_RAM_PACKET_RAM_1_MSBYTE_SHIFT)) & XCVR_PKT_RAM_PACKET_RAM_1_MSBYTE_MASK)
8900 
8901 /* The count of XCVR_PKT_RAM_PACKET_RAM_1 */
8902 #define XCVR_PKT_RAM_PACKET_RAM_1_COUNT          (544U)
8903 
8904 
8905 /*!
8906  * @}
8907  */ /* end of group XCVR_PKT_RAM_Register_Masks */
8908 
8909 
8910 /* XCVR_PKT_RAM - Peripheral instance base addresses */
8911 /** Peripheral XCVR_PKT_RAM base address */
8912 #define XCVR_PKT_RAM_BASE                        (0x4005C700u)
8913 /** Peripheral XCVR_PKT_RAM base pointer */
8914 #define XCVR_PKT_RAM                             ((XCVR_PKT_RAM_Type *)XCVR_PKT_RAM_BASE)
8915 /** Array initializer of XCVR_PKT_RAM peripheral base addresses */
8916 #define XCVR_PKT_RAM_BASE_ADDRS                  { XCVR_PKT_RAM_BASE }
8917 /** Array initializer of XCVR_PKT_RAM peripheral base pointers */
8918 #define XCVR_PKT_RAM_BASE_PTRS                   { XCVR_PKT_RAM }
8919 
8920 /*!
8921  * @}
8922  */ /* end of group XCVR_PKT_RAM_Peripheral_Access_Layer */
8923 
8924 
8925 /* ----------------------------------------------------------------------------
8926    -- XCVR_PLL_DIG Peripheral Access Layer
8927    ---------------------------------------------------------------------------- */
8928 
8929 /*!
8930  * @addtogroup XCVR_PLL_DIG_Peripheral_Access_Layer XCVR_PLL_DIG Peripheral Access Layer
8931  * @{
8932  */
8933 
8934 /** XCVR_PLL_DIG - Register Layout Typedef */
8935 typedef struct {
8936   __IO uint32_t HPM_BUMP;                          /**< PLL HPM Analog Bump Control, offset: 0x0 */
8937   __IO uint32_t MOD_CTRL;                          /**< PLL Modulation Control, offset: 0x4 */
8938   __IO uint32_t CHAN_MAP;                          /**< PLL Channel Mapping, offset: 0x8 */
8939   __IO uint32_t LOCK_DETECT;                       /**< PLL Lock Detect Control, offset: 0xC */
8940   __IO uint32_t HPM_CTRL;                          /**< PLL High Port Modulator Control, offset: 0x10 */
8941   __IO uint32_t HPMCAL_CTRL;                       /**< PLL High Port Calibration Control, offset: 0x14 */
8942   __IO uint32_t HPM_CAL1;                          /**< PLL High Port Calibration Result 1, offset: 0x18 */
8943   __IO uint32_t HPM_CAL2;                          /**< PLL High Port Calibration Result 2, offset: 0x1C */
8944   __IO uint32_t HPM_SDM_RES;                       /**< PLL High Port Sigma Delta Results, offset: 0x20 */
8945   __IO uint32_t LPM_CTRL;                          /**< PLL Low Port Modulator Control, offset: 0x24 */
8946   __IO uint32_t LPM_SDM_CTRL1;                     /**< PLL Low Port Sigma Delta Control 1, offset: 0x28 */
8947   __IO uint32_t LPM_SDM_CTRL2;                     /**< PLL Low Port Sigma Delta Control 2, offset: 0x2C */
8948   __IO uint32_t LPM_SDM_CTRL3;                     /**< PLL Low Port Sigma Delta Control 3, offset: 0x30 */
8949   __I  uint32_t LPM_SDM_RES1;                      /**< PLL Low Port Sigma Delta Result 1, offset: 0x34 */
8950   __I  uint32_t LPM_SDM_RES2;                      /**< PLL Low Port Sigma Delta Result 2, offset: 0x38 */
8951   __IO uint32_t DELAY_MATCH;                       /**< PLL Delay Matching, offset: 0x3C */
8952   __IO uint32_t CTUNE_CTRL;                        /**< PLL Coarse Tune Control, offset: 0x40 */
8953   __I  uint32_t CTUNE_CNT6;                        /**< PLL Coarse Tune Count 6, offset: 0x44 */
8954   __I  uint32_t CTUNE_CNT5_4;                      /**< PLL Coarse Tune Counts 5 and 4, offset: 0x48 */
8955   __I  uint32_t CTUNE_CNT3_2;                      /**< PLL Coarse Tune Counts 3 and 2, offset: 0x4C */
8956   __I  uint32_t CTUNE_CNT1_0;                      /**< PLL Coarse Tune Counts 1 and 0, offset: 0x50 */
8957   __I  uint32_t CTUNE_RES;                         /**< PLL Coarse Tune Results, offset: 0x54 */
8958 } XCVR_PLL_DIG_Type;
8959 
8960 /* ----------------------------------------------------------------------------
8961    -- XCVR_PLL_DIG Register Masks
8962    ---------------------------------------------------------------------------- */
8963 
8964 /*!
8965  * @addtogroup XCVR_PLL_DIG_Register_Masks XCVR_PLL_DIG Register Masks
8966  * @{
8967  */
8968 
8969 /*! @name HPM_BUMP - PLL HPM Analog Bump Control */
8970 #define XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_TX_MASK    (0x7U)
8971 #define XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_TX_SHIFT   (0U)
8972 #define XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_TX(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_TX_SHIFT)) & XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_TX_MASK)
8973 #define XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_CAL_MASK   (0x70U)
8974 #define XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_CAL_SHIFT  (4U)
8975 #define XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_CAL(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_CAL_SHIFT)) & XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_CAL_MASK)
8976 #define XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_TX_MASK (0x300U)
8977 #define XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_TX_SHIFT (8U)
8978 #define XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_TX(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_TX_SHIFT)) & XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_TX_MASK)
8979 #define XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_CAL_MASK (0x3000U)
8980 #define XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_CAL_SHIFT (12U)
8981 #define XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_CAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_CAL_SHIFT)) & XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_CAL_MASK)
8982 
8983 /*! @name MOD_CTRL - PLL Modulation Control */
8984 #define XCVR_PLL_DIG_MOD_CTRL_MODULATION_WORD_MANUAL_MASK (0x1FFFU)
8985 #define XCVR_PLL_DIG_MOD_CTRL_MODULATION_WORD_MANUAL_SHIFT (0U)
8986 #define XCVR_PLL_DIG_MOD_CTRL_MODULATION_WORD_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_MOD_CTRL_MODULATION_WORD_MANUAL_SHIFT)) & XCVR_PLL_DIG_MOD_CTRL_MODULATION_WORD_MANUAL_MASK)
8987 #define XCVR_PLL_DIG_MOD_CTRL_MOD_DISABLE_MASK   (0x8000U)
8988 #define XCVR_PLL_DIG_MOD_CTRL_MOD_DISABLE_SHIFT  (15U)
8989 #define XCVR_PLL_DIG_MOD_CTRL_MOD_DISABLE(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_MOD_CTRL_MOD_DISABLE_SHIFT)) & XCVR_PLL_DIG_MOD_CTRL_MOD_DISABLE_MASK)
8990 #define XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_MANUAL_MASK (0xFF0000U)
8991 #define XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_MANUAL_SHIFT (16U)
8992 #define XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_MANUAL(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_MANUAL_SHIFT)) & XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_MANUAL_MASK)
8993 #define XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_DISABLE_MASK (0x8000000U)
8994 #define XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_DISABLE_SHIFT (27U)
8995 #define XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_DISABLE_SHIFT)) & XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_DISABLE_MASK)
8996 #define XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_MANUAL_MASK (0x30000000U)
8997 #define XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_MANUAL_SHIFT (28U)
8998 #define XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_MANUAL_SHIFT)) & XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_MANUAL_MASK)
8999 #define XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_DISABLE_MASK (0x80000000U)
9000 #define XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_DISABLE_SHIFT (31U)
9001 #define XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_DISABLE_SHIFT)) & XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_DISABLE_MASK)
9002 
9003 /*! @name CHAN_MAP - PLL Channel Mapping */
9004 #define XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM_MASK   (0x7FU)
9005 #define XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM_SHIFT  (0U)
9006 #define XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM_SHIFT)) & XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM_MASK)
9007 #define XCVR_PLL_DIG_CHAN_MAP_BOC_MASK           (0x100U)
9008 #define XCVR_PLL_DIG_CHAN_MAP_BOC_SHIFT          (8U)
9009 #define XCVR_PLL_DIG_CHAN_MAP_BOC(x)             (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CHAN_MAP_BOC_SHIFT)) & XCVR_PLL_DIG_CHAN_MAP_BOC_MASK)
9010 #define XCVR_PLL_DIG_CHAN_MAP_BMR_MASK           (0x200U)
9011 #define XCVR_PLL_DIG_CHAN_MAP_BMR_SHIFT          (9U)
9012 #define XCVR_PLL_DIG_CHAN_MAP_BMR(x)             (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CHAN_MAP_BMR_SHIFT)) & XCVR_PLL_DIG_CHAN_MAP_BMR_MASK)
9013 #define XCVR_PLL_DIG_CHAN_MAP_ZOC_MASK           (0x400U)
9014 #define XCVR_PLL_DIG_CHAN_MAP_ZOC_SHIFT          (10U)
9015 #define XCVR_PLL_DIG_CHAN_MAP_ZOC(x)             (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CHAN_MAP_ZOC_SHIFT)) & XCVR_PLL_DIG_CHAN_MAP_ZOC_MASK)
9016 
9017 /*! @name LOCK_DETECT - PLL Lock Detect Control */
9018 #define XCVR_PLL_DIG_LOCK_DETECT_CT_FAIL_MASK    (0x1U)
9019 #define XCVR_PLL_DIG_LOCK_DETECT_CT_FAIL_SHIFT   (0U)
9020 #define XCVR_PLL_DIG_LOCK_DETECT_CT_FAIL(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_CT_FAIL_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_CT_FAIL_MASK)
9021 #define XCVR_PLL_DIG_LOCK_DETECT_CTFF_MASK       (0x2U)
9022 #define XCVR_PLL_DIG_LOCK_DETECT_CTFF_SHIFT      (1U)
9023 #define XCVR_PLL_DIG_LOCK_DETECT_CTFF(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_CTFF_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_CTFF_MASK)
9024 #define XCVR_PLL_DIG_LOCK_DETECT_CS_FAIL_MASK    (0x4U)
9025 #define XCVR_PLL_DIG_LOCK_DETECT_CS_FAIL_SHIFT   (2U)
9026 #define XCVR_PLL_DIG_LOCK_DETECT_CS_FAIL(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_CS_FAIL_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_CS_FAIL_MASK)
9027 #define XCVR_PLL_DIG_LOCK_DETECT_CSFF_MASK       (0x8U)
9028 #define XCVR_PLL_DIG_LOCK_DETECT_CSFF_SHIFT      (3U)
9029 #define XCVR_PLL_DIG_LOCK_DETECT_CSFF(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_CSFF_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_CSFF_MASK)
9030 #define XCVR_PLL_DIG_LOCK_DETECT_FT_FAIL_MASK    (0x10U)
9031 #define XCVR_PLL_DIG_LOCK_DETECT_FT_FAIL_SHIFT   (4U)
9032 #define XCVR_PLL_DIG_LOCK_DETECT_FT_FAIL(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_FT_FAIL_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_FT_FAIL_MASK)
9033 #define XCVR_PLL_DIG_LOCK_DETECT_FTFF_MASK       (0x20U)
9034 #define XCVR_PLL_DIG_LOCK_DETECT_FTFF_SHIFT      (5U)
9035 #define XCVR_PLL_DIG_LOCK_DETECT_FTFF(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_FTFF_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_FTFF_MASK)
9036 #define XCVR_PLL_DIG_LOCK_DETECT_TAFF_MASK       (0x80U)
9037 #define XCVR_PLL_DIG_LOCK_DETECT_TAFF_SHIFT      (7U)
9038 #define XCVR_PLL_DIG_LOCK_DETECT_TAFF(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_TAFF_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_TAFF_MASK)
9039 #define XCVR_PLL_DIG_LOCK_DETECT_CTUNE_LDF_LEV_MASK (0xF00U)
9040 #define XCVR_PLL_DIG_LOCK_DETECT_CTUNE_LDF_LEV_SHIFT (8U)
9041 #define XCVR_PLL_DIG_LOCK_DETECT_CTUNE_LDF_LEV(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_CTUNE_LDF_LEV_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_CTUNE_LDF_LEV_MASK)
9042 #define XCVR_PLL_DIG_LOCK_DETECT_FTF_RX_THRSH_MASK (0x3F000U)
9043 #define XCVR_PLL_DIG_LOCK_DETECT_FTF_RX_THRSH_SHIFT (12U)
9044 #define XCVR_PLL_DIG_LOCK_DETECT_FTF_RX_THRSH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_FTF_RX_THRSH_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_FTF_RX_THRSH_MASK)
9045 #define XCVR_PLL_DIG_LOCK_DETECT_FTW_RX_MASK     (0x80000U)
9046 #define XCVR_PLL_DIG_LOCK_DETECT_FTW_RX_SHIFT    (19U)
9047 #define XCVR_PLL_DIG_LOCK_DETECT_FTW_RX(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_FTW_RX_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_FTW_RX_MASK)
9048 #define XCVR_PLL_DIG_LOCK_DETECT_FTF_TX_THRSH_MASK (0x3F00000U)
9049 #define XCVR_PLL_DIG_LOCK_DETECT_FTF_TX_THRSH_SHIFT (20U)
9050 #define XCVR_PLL_DIG_LOCK_DETECT_FTF_TX_THRSH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_FTF_TX_THRSH_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_FTF_TX_THRSH_MASK)
9051 #define XCVR_PLL_DIG_LOCK_DETECT_FTW_TX_MASK     (0x8000000U)
9052 #define XCVR_PLL_DIG_LOCK_DETECT_FTW_TX_SHIFT    (27U)
9053 #define XCVR_PLL_DIG_LOCK_DETECT_FTW_TX(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_FTW_TX_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_FTW_TX_MASK)
9054 #define XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_GO_MASK (0x10000000U)
9055 #define XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_GO_SHIFT (28U)
9056 #define XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_GO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_GO_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_GO_MASK)
9057 #define XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_FINISHED_MASK (0x20000000U)
9058 #define XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_FINISHED_SHIFT (29U)
9059 #define XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_FINISHED_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_FINISHED_MASK)
9060 #define XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_TIME_MASK (0xC0000000U)
9061 #define XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_TIME_SHIFT (30U)
9062 #define XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_TIME(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_TIME_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_TIME_MASK)
9063 
9064 /*! @name HPM_CTRL - PLL High Port Modulator Control */
9065 #define XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_MANUAL_MASK (0x3FFU)
9066 #define XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_MANUAL_SHIFT (0U)
9067 #define XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_MANUAL_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_MANUAL_MASK)
9068 #define XCVR_PLL_DIG_HPM_CTRL_HPFF_MASK          (0x2000U)
9069 #define XCVR_PLL_DIG_HPM_CTRL_HPFF_SHIFT         (13U)
9070 #define XCVR_PLL_DIG_HPM_CTRL_HPFF(x)            (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPFF_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPFF_MASK)
9071 #define XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_OUT_INVERT_MASK (0x4000U)
9072 #define XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_OUT_INVERT_SHIFT (14U)
9073 #define XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_OUT_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_OUT_INVERT_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_OUT_INVERT_MASK)
9074 #define XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_DISABLE_MASK (0x8000U)
9075 #define XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_DISABLE_SHIFT (15U)
9076 #define XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_DISABLE_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_DISABLE_MASK)
9077 #define XCVR_PLL_DIG_HPM_CTRL_HPM_LFSR_SIZE_MASK (0x70000U)
9078 #define XCVR_PLL_DIG_HPM_CTRL_HPM_LFSR_SIZE_SHIFT (16U)
9079 #define XCVR_PLL_DIG_HPM_CTRL_HPM_LFSR_SIZE(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPM_LFSR_SIZE_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPM_LFSR_SIZE_MASK)
9080 #define XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_SCL_MASK   (0x100000U)
9081 #define XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_SCL_SHIFT  (20U)
9082 #define XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_SCL(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_SCL_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_SCL_MASK)
9083 #define XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_EN_MASK    (0x800000U)
9084 #define XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_EN_SHIFT   (23U)
9085 #define XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_EN(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_EN_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_EN_MASK)
9086 #define XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_SCALE_MASK (0x3000000U)
9087 #define XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_SCALE_SHIFT (24U)
9088 #define XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_SCALE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_SCALE_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_SCALE_MASK)
9089 #define XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_INVERT_MASK (0x8000000U)
9090 #define XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_INVERT_SHIFT (27U)
9091 #define XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_INVERT_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_INVERT_MASK)
9092 #define XCVR_PLL_DIG_HPM_CTRL_HPM_CAL_INVERT_MASK (0x10000000U)
9093 #define XCVR_PLL_DIG_HPM_CTRL_HPM_CAL_INVERT_SHIFT (28U)
9094 #define XCVR_PLL_DIG_HPM_CTRL_HPM_CAL_INVERT(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPM_CAL_INVERT_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPM_CAL_INVERT_MASK)
9095 #define XCVR_PLL_DIG_HPM_CTRL_HPM_MOD_IN_INVERT_MASK (0x80000000U)
9096 #define XCVR_PLL_DIG_HPM_CTRL_HPM_MOD_IN_INVERT_SHIFT (31U)
9097 #define XCVR_PLL_DIG_HPM_CTRL_HPM_MOD_IN_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPM_MOD_IN_INVERT_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPM_MOD_IN_INVERT_MASK)
9098 
9099 /*! @name HPMCAL_CTRL - PLL High Port Calibration Control */
9100 #define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_FACTOR_MASK (0x1FFFU)
9101 #define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_FACTOR_SHIFT (0U)
9102 #define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_FACTOR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_FACTOR_SHIFT)) & XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_FACTOR_MASK)
9103 #define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_NOT_BUMPED_MASK (0x2000U)
9104 #define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_NOT_BUMPED_SHIFT (13U)
9105 #define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_NOT_BUMPED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_NOT_BUMPED_SHIFT)) & XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_NOT_BUMPED_MASK)
9106 #define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_COUNT_SCALE_MASK (0x4000U)
9107 #define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_COUNT_SCALE_SHIFT (14U)
9108 #define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_COUNT_SCALE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_COUNT_SCALE_SHIFT)) & XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_COUNT_SCALE_MASK)
9109 #define XCVR_PLL_DIG_HPMCAL_CTRL_HP_CAL_DISABLE_MASK (0x8000U)
9110 #define XCVR_PLL_DIG_HPMCAL_CTRL_HP_CAL_DISABLE_SHIFT (15U)
9111 #define XCVR_PLL_DIG_HPMCAL_CTRL_HP_CAL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPMCAL_CTRL_HP_CAL_DISABLE_SHIFT)) & XCVR_PLL_DIG_HPMCAL_CTRL_HP_CAL_DISABLE_MASK)
9112 #define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_FACTOR_MANUAL_MASK (0x1FFF0000U)
9113 #define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_FACTOR_MANUAL_SHIFT (16U)
9114 #define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_FACTOR_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_FACTOR_MANUAL_SHIFT)) & XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_FACTOR_MANUAL_MASK)
9115 #define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_ARRAY_SIZE_MASK (0x40000000U)
9116 #define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_ARRAY_SIZE_SHIFT (30U)
9117 #define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_ARRAY_SIZE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_ARRAY_SIZE_SHIFT)) & XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_ARRAY_SIZE_MASK)
9118 #define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_TIME_MASK (0x80000000U)
9119 #define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_TIME_SHIFT (31U)
9120 #define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_TIME(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_TIME_SHIFT)) & XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_TIME_MASK)
9121 
9122 /*! @name HPM_CAL1 - PLL High Port Calibration Result 1 */
9123 #define XCVR_PLL_DIG_HPM_CAL1_HPM_COUNT_1_MASK   (0x7FFFFU)
9124 #define XCVR_PLL_DIG_HPM_CAL1_HPM_COUNT_1_SHIFT  (0U)
9125 #define XCVR_PLL_DIG_HPM_CAL1_HPM_COUNT_1(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CAL1_HPM_COUNT_1_SHIFT)) & XCVR_PLL_DIG_HPM_CAL1_HPM_COUNT_1_MASK)
9126 #define XCVR_PLL_DIG_HPM_CAL1_CS_WT_MASK         (0x700000U)
9127 #define XCVR_PLL_DIG_HPM_CAL1_CS_WT_SHIFT        (20U)
9128 #define XCVR_PLL_DIG_HPM_CAL1_CS_WT(x)           (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CAL1_CS_WT_SHIFT)) & XCVR_PLL_DIG_HPM_CAL1_CS_WT_MASK)
9129 #define XCVR_PLL_DIG_HPM_CAL1_CS_FW_MASK         (0x7000000U)
9130 #define XCVR_PLL_DIG_HPM_CAL1_CS_FW_SHIFT        (24U)
9131 #define XCVR_PLL_DIG_HPM_CAL1_CS_FW(x)           (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CAL1_CS_FW_SHIFT)) & XCVR_PLL_DIG_HPM_CAL1_CS_FW_MASK)
9132 #define XCVR_PLL_DIG_HPM_CAL1_CS_FCNT_MASK       (0xF0000000U)
9133 #define XCVR_PLL_DIG_HPM_CAL1_CS_FCNT_SHIFT      (28U)
9134 #define XCVR_PLL_DIG_HPM_CAL1_CS_FCNT(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CAL1_CS_FCNT_SHIFT)) & XCVR_PLL_DIG_HPM_CAL1_CS_FCNT_MASK)
9135 
9136 /*! @name HPM_CAL2 - PLL High Port Calibration Result 2 */
9137 #define XCVR_PLL_DIG_HPM_CAL2_HPM_COUNT_2_MASK   (0x7FFFFU)
9138 #define XCVR_PLL_DIG_HPM_CAL2_HPM_COUNT_2_SHIFT  (0U)
9139 #define XCVR_PLL_DIG_HPM_CAL2_HPM_COUNT_2(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CAL2_HPM_COUNT_2_SHIFT)) & XCVR_PLL_DIG_HPM_CAL2_HPM_COUNT_2_MASK)
9140 #define XCVR_PLL_DIG_HPM_CAL2_CS_RC_MASK         (0x100000U)
9141 #define XCVR_PLL_DIG_HPM_CAL2_CS_RC_SHIFT        (20U)
9142 #define XCVR_PLL_DIG_HPM_CAL2_CS_RC(x)           (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CAL2_CS_RC_SHIFT)) & XCVR_PLL_DIG_HPM_CAL2_CS_RC_MASK)
9143 #define XCVR_PLL_DIG_HPM_CAL2_CS_FT_MASK         (0x1F000000U)
9144 #define XCVR_PLL_DIG_HPM_CAL2_CS_FT_SHIFT        (24U)
9145 #define XCVR_PLL_DIG_HPM_CAL2_CS_FT(x)           (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CAL2_CS_FT_SHIFT)) & XCVR_PLL_DIG_HPM_CAL2_CS_FT_MASK)
9146 
9147 /*! @name HPM_SDM_RES - PLL High Port Sigma Delta Results */
9148 #define XCVR_PLL_DIG_HPM_SDM_RES_HPM_NUM_SELECTED_MASK (0x3FFU)
9149 #define XCVR_PLL_DIG_HPM_SDM_RES_HPM_NUM_SELECTED_SHIFT (0U)
9150 #define XCVR_PLL_DIG_HPM_SDM_RES_HPM_NUM_SELECTED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_SDM_RES_HPM_NUM_SELECTED_SHIFT)) & XCVR_PLL_DIG_HPM_SDM_RES_HPM_NUM_SELECTED_MASK)
9151 #define XCVR_PLL_DIG_HPM_SDM_RES_HPM_DENOM_MASK  (0x3FF0000U)
9152 #define XCVR_PLL_DIG_HPM_SDM_RES_HPM_DENOM_SHIFT (16U)
9153 #define XCVR_PLL_DIG_HPM_SDM_RES_HPM_DENOM(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_SDM_RES_HPM_DENOM_SHIFT)) & XCVR_PLL_DIG_HPM_SDM_RES_HPM_DENOM_MASK)
9154 #define XCVR_PLL_DIG_HPM_SDM_RES_HPM_COUNT_ADJUST_MASK (0xF0000000U)
9155 #define XCVR_PLL_DIG_HPM_SDM_RES_HPM_COUNT_ADJUST_SHIFT (28U)
9156 #define XCVR_PLL_DIG_HPM_SDM_RES_HPM_COUNT_ADJUST(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_SDM_RES_HPM_COUNT_ADJUST_SHIFT)) & XCVR_PLL_DIG_HPM_SDM_RES_HPM_COUNT_ADJUST_MASK)
9157 
9158 /*! @name LPM_CTRL - PLL Low Port Modulator Control */
9159 #define XCVR_PLL_DIG_LPM_CTRL_PLL_LD_MANUAL_MASK (0x3FU)
9160 #define XCVR_PLL_DIG_LPM_CTRL_PLL_LD_MANUAL_SHIFT (0U)
9161 #define XCVR_PLL_DIG_LPM_CTRL_PLL_LD_MANUAL(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_CTRL_PLL_LD_MANUAL_SHIFT)) & XCVR_PLL_DIG_LPM_CTRL_PLL_LD_MANUAL_MASK)
9162 #define XCVR_PLL_DIG_LPM_CTRL_PLL_LD_DISABLE_MASK (0x800U)
9163 #define XCVR_PLL_DIG_LPM_CTRL_PLL_LD_DISABLE_SHIFT (11U)
9164 #define XCVR_PLL_DIG_LPM_CTRL_PLL_LD_DISABLE(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_CTRL_PLL_LD_DISABLE_SHIFT)) & XCVR_PLL_DIG_LPM_CTRL_PLL_LD_DISABLE_MASK)
9165 #define XCVR_PLL_DIG_LPM_CTRL_LPFF_MASK          (0x2000U)
9166 #define XCVR_PLL_DIG_LPM_CTRL_LPFF_SHIFT         (13U)
9167 #define XCVR_PLL_DIG_LPM_CTRL_LPFF(x)            (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_CTRL_LPFF_SHIFT)) & XCVR_PLL_DIG_LPM_CTRL_LPFF_MASK)
9168 #define XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_INV_MASK   (0x4000U)
9169 #define XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_INV_SHIFT  (14U)
9170 #define XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_INV(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_INV_SHIFT)) & XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_INV_MASK)
9171 #define XCVR_PLL_DIG_LPM_CTRL_LPM_DISABLE_MASK   (0x8000U)
9172 #define XCVR_PLL_DIG_LPM_CTRL_LPM_DISABLE_SHIFT  (15U)
9173 #define XCVR_PLL_DIG_LPM_CTRL_LPM_DISABLE(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_CTRL_LPM_DISABLE_SHIFT)) & XCVR_PLL_DIG_LPM_CTRL_LPM_DISABLE_MASK)
9174 #define XCVR_PLL_DIG_LPM_CTRL_LPM_DTH_SCL_MASK   (0xF0000U)
9175 #define XCVR_PLL_DIG_LPM_CTRL_LPM_DTH_SCL_SHIFT  (16U)
9176 #define XCVR_PLL_DIG_LPM_CTRL_LPM_DTH_SCL(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_CTRL_LPM_DTH_SCL_SHIFT)) & XCVR_PLL_DIG_LPM_CTRL_LPM_DTH_SCL_MASK)
9177 #define XCVR_PLL_DIG_LPM_CTRL_LPM_D_CTRL_MASK    (0x400000U)
9178 #define XCVR_PLL_DIG_LPM_CTRL_LPM_D_CTRL_SHIFT   (22U)
9179 #define XCVR_PLL_DIG_LPM_CTRL_LPM_D_CTRL(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_CTRL_LPM_D_CTRL_SHIFT)) & XCVR_PLL_DIG_LPM_CTRL_LPM_D_CTRL_MASK)
9180 #define XCVR_PLL_DIG_LPM_CTRL_LPM_D_OVRD_MASK    (0x800000U)
9181 #define XCVR_PLL_DIG_LPM_CTRL_LPM_D_OVRD_SHIFT   (23U)
9182 #define XCVR_PLL_DIG_LPM_CTRL_LPM_D_OVRD(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_CTRL_LPM_D_OVRD_SHIFT)) & XCVR_PLL_DIG_LPM_CTRL_LPM_D_OVRD_MASK)
9183 #define XCVR_PLL_DIG_LPM_CTRL_LPM_SCALE_MASK     (0xF000000U)
9184 #define XCVR_PLL_DIG_LPM_CTRL_LPM_SCALE_SHIFT    (24U)
9185 #define XCVR_PLL_DIG_LPM_CTRL_LPM_SCALE(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_CTRL_LPM_SCALE_SHIFT)) & XCVR_PLL_DIG_LPM_CTRL_LPM_SCALE_MASK)
9186 #define XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_USE_NEG_MASK (0x80000000U)
9187 #define XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_USE_NEG_SHIFT (31U)
9188 #define XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_USE_NEG(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_USE_NEG_SHIFT)) & XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_USE_NEG_MASK)
9189 
9190 /*! @name LPM_SDM_CTRL1 - PLL Low Port Sigma Delta Control 1 */
9191 #define XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SELECTED_MASK (0x7FU)
9192 #define XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SELECTED_SHIFT (0U)
9193 #define XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SELECTED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SELECTED_SHIFT)) & XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SELECTED_MASK)
9194 #define XCVR_PLL_DIG_LPM_SDM_CTRL1_HPM_ARRAY_BIAS_MASK (0x7F00U)
9195 #define XCVR_PLL_DIG_LPM_SDM_CTRL1_HPM_ARRAY_BIAS_SHIFT (8U)
9196 #define XCVR_PLL_DIG_LPM_SDM_CTRL1_HPM_ARRAY_BIAS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_SDM_CTRL1_HPM_ARRAY_BIAS_SHIFT)) & XCVR_PLL_DIG_LPM_SDM_CTRL1_HPM_ARRAY_BIAS_MASK)
9197 #define XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_MASK (0x7F0000U)
9198 #define XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SHIFT (16U)
9199 #define XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SHIFT)) & XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_MASK)
9200 #define XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE_MASK (0x80000000U)
9201 #define XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE_SHIFT (31U)
9202 #define XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE_SHIFT)) & XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE_MASK)
9203 
9204 /*! @name LPM_SDM_CTRL2 - PLL Low Port Sigma Delta Control 2 */
9205 #define XCVR_PLL_DIG_LPM_SDM_CTRL2_LPM_NUM_MASK  (0xFFFFFFFU)
9206 #define XCVR_PLL_DIG_LPM_SDM_CTRL2_LPM_NUM_SHIFT (0U)
9207 #define XCVR_PLL_DIG_LPM_SDM_CTRL2_LPM_NUM(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_SDM_CTRL2_LPM_NUM_SHIFT)) & XCVR_PLL_DIG_LPM_SDM_CTRL2_LPM_NUM_MASK)
9208 
9209 /*! @name LPM_SDM_CTRL3 - PLL Low Port Sigma Delta Control 3 */
9210 #define XCVR_PLL_DIG_LPM_SDM_CTRL3_LPM_DENOM_MASK (0xFFFFFFFU)
9211 #define XCVR_PLL_DIG_LPM_SDM_CTRL3_LPM_DENOM_SHIFT (0U)
9212 #define XCVR_PLL_DIG_LPM_SDM_CTRL3_LPM_DENOM(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_SDM_CTRL3_LPM_DENOM_SHIFT)) & XCVR_PLL_DIG_LPM_SDM_CTRL3_LPM_DENOM_MASK)
9213 
9214 /*! @name LPM_SDM_RES1 - PLL Low Port Sigma Delta Result 1 */
9215 #define XCVR_PLL_DIG_LPM_SDM_RES1_LPM_NUM_SELECTED_MASK (0xFFFFFFFU)
9216 #define XCVR_PLL_DIG_LPM_SDM_RES1_LPM_NUM_SELECTED_SHIFT (0U)
9217 #define XCVR_PLL_DIG_LPM_SDM_RES1_LPM_NUM_SELECTED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_SDM_RES1_LPM_NUM_SELECTED_SHIFT)) & XCVR_PLL_DIG_LPM_SDM_RES1_LPM_NUM_SELECTED_MASK)
9218 
9219 /*! @name LPM_SDM_RES2 - PLL Low Port Sigma Delta Result 2 */
9220 #define XCVR_PLL_DIG_LPM_SDM_RES2_LPM_DENOM_SELECTED_MASK (0xFFFFFFFU)
9221 #define XCVR_PLL_DIG_LPM_SDM_RES2_LPM_DENOM_SELECTED_SHIFT (0U)
9222 #define XCVR_PLL_DIG_LPM_SDM_RES2_LPM_DENOM_SELECTED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_SDM_RES2_LPM_DENOM_SELECTED_SHIFT)) & XCVR_PLL_DIG_LPM_SDM_RES2_LPM_DENOM_SELECTED_MASK)
9223 
9224 /*! @name DELAY_MATCH - PLL Delay Matching */
9225 #define XCVR_PLL_DIG_DELAY_MATCH_LPM_SDM_DELAY_MASK (0xFU)
9226 #define XCVR_PLL_DIG_DELAY_MATCH_LPM_SDM_DELAY_SHIFT (0U)
9227 #define XCVR_PLL_DIG_DELAY_MATCH_LPM_SDM_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_DELAY_MATCH_LPM_SDM_DELAY_SHIFT)) & XCVR_PLL_DIG_DELAY_MATCH_LPM_SDM_DELAY_MASK)
9228 #define XCVR_PLL_DIG_DELAY_MATCH_HPM_SDM_DELAY_MASK (0xF00U)
9229 #define XCVR_PLL_DIG_DELAY_MATCH_HPM_SDM_DELAY_SHIFT (8U)
9230 #define XCVR_PLL_DIG_DELAY_MATCH_HPM_SDM_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_DELAY_MATCH_HPM_SDM_DELAY_SHIFT)) & XCVR_PLL_DIG_DELAY_MATCH_HPM_SDM_DELAY_MASK)
9231 #define XCVR_PLL_DIG_DELAY_MATCH_HPM_INTEGER_DELAY_MASK (0xF0000U)
9232 #define XCVR_PLL_DIG_DELAY_MATCH_HPM_INTEGER_DELAY_SHIFT (16U)
9233 #define XCVR_PLL_DIG_DELAY_MATCH_HPM_INTEGER_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_DELAY_MATCH_HPM_INTEGER_DELAY_SHIFT)) & XCVR_PLL_DIG_DELAY_MATCH_HPM_INTEGER_DELAY_MASK)
9234 
9235 /*! @name CTUNE_CTRL - PLL Coarse Tune Control */
9236 #define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_MANUAL_MASK (0xFFFU)
9237 #define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_MANUAL_SHIFT (0U)
9238 #define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_MANUAL_SHIFT)) & XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_MANUAL_MASK)
9239 #define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_DISABLE_MASK (0x8000U)
9240 #define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_DISABLE_SHIFT (15U)
9241 #define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_DISABLE_SHIFT)) & XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_DISABLE_MASK)
9242 #define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_ADJUST_MASK (0xF0000U)
9243 #define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_ADJUST_SHIFT (16U)
9244 #define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_ADJUST(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_ADJUST_SHIFT)) & XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_ADJUST_MASK)
9245 #define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_MANUAL_MASK (0x7F000000U)
9246 #define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_MANUAL_SHIFT (24U)
9247 #define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_MANUAL(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_MANUAL_SHIFT)) & XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_MANUAL_MASK)
9248 #define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_DISABLE_MASK (0x80000000U)
9249 #define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_DISABLE_SHIFT (31U)
9250 #define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_DISABLE_SHIFT)) & XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_DISABLE_MASK)
9251 
9252 /*! @name CTUNE_CNT6 - PLL Coarse Tune Count 6 */
9253 #define XCVR_PLL_DIG_CTUNE_CNT6_CTUNE_COUNT_6_MASK (0x1FFFU)
9254 #define XCVR_PLL_DIG_CTUNE_CNT6_CTUNE_COUNT_6_SHIFT (0U)
9255 #define XCVR_PLL_DIG_CTUNE_CNT6_CTUNE_COUNT_6(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_CNT6_CTUNE_COUNT_6_SHIFT)) & XCVR_PLL_DIG_CTUNE_CNT6_CTUNE_COUNT_6_MASK)
9256 
9257 /*! @name CTUNE_CNT5_4 - PLL Coarse Tune Counts 5 and 4 */
9258 #define XCVR_PLL_DIG_CTUNE_CNT5_4_CTUNE_COUNT_4_MASK (0x1FFFU)
9259 #define XCVR_PLL_DIG_CTUNE_CNT5_4_CTUNE_COUNT_4_SHIFT (0U)
9260 #define XCVR_PLL_DIG_CTUNE_CNT5_4_CTUNE_COUNT_4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_CNT5_4_CTUNE_COUNT_4_SHIFT)) & XCVR_PLL_DIG_CTUNE_CNT5_4_CTUNE_COUNT_4_MASK)
9261 #define XCVR_PLL_DIG_CTUNE_CNT5_4_CTUNE_COUNT_5_MASK (0x1FFF0000U)
9262 #define XCVR_PLL_DIG_CTUNE_CNT5_4_CTUNE_COUNT_5_SHIFT (16U)
9263 #define XCVR_PLL_DIG_CTUNE_CNT5_4_CTUNE_COUNT_5(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_CNT5_4_CTUNE_COUNT_5_SHIFT)) & XCVR_PLL_DIG_CTUNE_CNT5_4_CTUNE_COUNT_5_MASK)
9264 
9265 /*! @name CTUNE_CNT3_2 - PLL Coarse Tune Counts 3 and 2 */
9266 #define XCVR_PLL_DIG_CTUNE_CNT3_2_CTUNE_COUNT_2_MASK (0x1FFFU)
9267 #define XCVR_PLL_DIG_CTUNE_CNT3_2_CTUNE_COUNT_2_SHIFT (0U)
9268 #define XCVR_PLL_DIG_CTUNE_CNT3_2_CTUNE_COUNT_2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_CNT3_2_CTUNE_COUNT_2_SHIFT)) & XCVR_PLL_DIG_CTUNE_CNT3_2_CTUNE_COUNT_2_MASK)
9269 #define XCVR_PLL_DIG_CTUNE_CNT3_2_CTUNE_COUNT_3_MASK (0x1FFF0000U)
9270 #define XCVR_PLL_DIG_CTUNE_CNT3_2_CTUNE_COUNT_3_SHIFT (16U)
9271 #define XCVR_PLL_DIG_CTUNE_CNT3_2_CTUNE_COUNT_3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_CNT3_2_CTUNE_COUNT_3_SHIFT)) & XCVR_PLL_DIG_CTUNE_CNT3_2_CTUNE_COUNT_3_MASK)
9272 
9273 /*! @name CTUNE_CNT1_0 - PLL Coarse Tune Counts 1 and 0 */
9274 #define XCVR_PLL_DIG_CTUNE_CNT1_0_CTUNE_COUNT_0_MASK (0x1FFFU)
9275 #define XCVR_PLL_DIG_CTUNE_CNT1_0_CTUNE_COUNT_0_SHIFT (0U)
9276 #define XCVR_PLL_DIG_CTUNE_CNT1_0_CTUNE_COUNT_0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_CNT1_0_CTUNE_COUNT_0_SHIFT)) & XCVR_PLL_DIG_CTUNE_CNT1_0_CTUNE_COUNT_0_MASK)
9277 #define XCVR_PLL_DIG_CTUNE_CNT1_0_CTUNE_COUNT_1_MASK (0x1FFF0000U)
9278 #define XCVR_PLL_DIG_CTUNE_CNT1_0_CTUNE_COUNT_1_SHIFT (16U)
9279 #define XCVR_PLL_DIG_CTUNE_CNT1_0_CTUNE_COUNT_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_CNT1_0_CTUNE_COUNT_1_SHIFT)) & XCVR_PLL_DIG_CTUNE_CNT1_0_CTUNE_COUNT_1_MASK)
9280 
9281 /*! @name CTUNE_RES - PLL Coarse Tune Results */
9282 #define XCVR_PLL_DIG_CTUNE_RES_CTUNE_SELECTED_MASK (0x7FU)
9283 #define XCVR_PLL_DIG_CTUNE_RES_CTUNE_SELECTED_SHIFT (0U)
9284 #define XCVR_PLL_DIG_CTUNE_RES_CTUNE_SELECTED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_RES_CTUNE_SELECTED_SHIFT)) & XCVR_PLL_DIG_CTUNE_RES_CTUNE_SELECTED_MASK)
9285 #define XCVR_PLL_DIG_CTUNE_RES_CTUNE_BEST_DIFF_MASK (0xFF00U)
9286 #define XCVR_PLL_DIG_CTUNE_RES_CTUNE_BEST_DIFF_SHIFT (8U)
9287 #define XCVR_PLL_DIG_CTUNE_RES_CTUNE_BEST_DIFF(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_RES_CTUNE_BEST_DIFF_SHIFT)) & XCVR_PLL_DIG_CTUNE_RES_CTUNE_BEST_DIFF_MASK)
9288 #define XCVR_PLL_DIG_CTUNE_RES_CTUNE_FREQ_SELECTED_MASK (0xFFF0000U)
9289 #define XCVR_PLL_DIG_CTUNE_RES_CTUNE_FREQ_SELECTED_SHIFT (16U)
9290 #define XCVR_PLL_DIG_CTUNE_RES_CTUNE_FREQ_SELECTED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_RES_CTUNE_FREQ_SELECTED_SHIFT)) & XCVR_PLL_DIG_CTUNE_RES_CTUNE_FREQ_SELECTED_MASK)
9291 
9292 
9293 /*!
9294  * @}
9295  */ /* end of group XCVR_PLL_DIG_Register_Masks */
9296 
9297 
9298 /* XCVR_PLL_DIG - Peripheral instance base addresses */
9299 /** Peripheral XCVR_PLL_DIG base address */
9300 #define XCVR_PLL_DIG_BASE                        (0x4005C224u)
9301 /** Peripheral XCVR_PLL_DIG base pointer */
9302 #define XCVR_PLL_DIG                             ((XCVR_PLL_DIG_Type *)XCVR_PLL_DIG_BASE)
9303 /** Array initializer of XCVR_PLL_DIG peripheral base addresses */
9304 #define XCVR_PLL_DIG_BASE_ADDRS                  { XCVR_PLL_DIG_BASE }
9305 /** Array initializer of XCVR_PLL_DIG peripheral base pointers */
9306 #define XCVR_PLL_DIG_BASE_PTRS                   { XCVR_PLL_DIG }
9307 
9308 /*!
9309  * @}
9310  */ /* end of group XCVR_PLL_DIG_Peripheral_Access_Layer */
9311 
9312 
9313 /* ----------------------------------------------------------------------------
9314    -- XCVR_RX_DIG Peripheral Access Layer
9315    ---------------------------------------------------------------------------- */
9316 
9317 /*!
9318  * @addtogroup XCVR_RX_DIG_Peripheral_Access_Layer XCVR_RX_DIG Peripheral Access Layer
9319  * @{
9320  */
9321 
9322 /** XCVR_RX_DIG - Register Layout Typedef */
9323 typedef struct {
9324   __IO uint32_t RX_DIG_CTRL;                       /**< RX Digital Control, offset: 0x0 */
9325   __IO uint32_t AGC_CTRL_0;                        /**< AGC Control 0, offset: 0x4 */
9326   __IO uint32_t AGC_CTRL_1;                        /**< AGC Control 1, offset: 0x8 */
9327   __IO uint32_t AGC_CTRL_2;                        /**< AGC Control 2, offset: 0xC */
9328   __IO uint32_t AGC_CTRL_3;                        /**< AGC Control 3, offset: 0x10 */
9329   __I  uint32_t AGC_STAT;                          /**< AGC Status, offset: 0x14 */
9330   __IO uint32_t RSSI_CTRL_0;                       /**< RSSI Control 0, offset: 0x18 */
9331   __I  uint32_t RSSI_CTRL_1;                       /**< RSSI Control 1, offset: 0x1C */
9332   __I  uint32_t RSSI_DFT;                          /**< RSSI DFT, offset: 0x20 */
9333   __IO uint32_t DCOC_CTRL_0;                       /**< DCOC Control 0, offset: 0x24 */
9334   __IO uint32_t DCOC_CTRL_1;                       /**< DCOC Control 1, offset: 0x28 */
9335   __IO uint32_t DCOC_DAC_INIT;                     /**< DCOC DAC Initialization, offset: 0x2C */
9336   __IO uint32_t DCOC_DIG_MAN;                      /**< DCOC Digital Correction Manual Override, offset: 0x30 */
9337   __IO uint32_t DCOC_CAL_GAIN;                     /**< DCOC Calibration Gain, offset: 0x34 */
9338   __I  uint32_t DCOC_STAT;                         /**< DCOC Status, offset: 0x38 */
9339   __I  uint32_t DCOC_DC_EST;                       /**< DCOC DC Estimate, offset: 0x3C */
9340   __IO uint32_t DCOC_CAL_RCP;                      /**< DCOC Calibration Reciprocals, offset: 0x40 */
9341        uint8_t RESERVED_0[4];
9342   __IO uint32_t IQMC_CTRL;                         /**< IQMC Control, offset: 0x48 */
9343   __IO uint32_t IQMC_CAL;                          /**< IQMC Calibration, offset: 0x4C */
9344   __IO uint32_t LNA_GAIN_VAL_3_0;                  /**< LNA_GAIN Step Values 3..0, offset: 0x50 */
9345   __IO uint32_t LNA_GAIN_VAL_7_4;                  /**< LNA_GAIN Step Values 7..4, offset: 0x54 */
9346   __IO uint32_t LNA_GAIN_VAL_8;                    /**< LNA_GAIN Step Values 8, offset: 0x58 */
9347   __IO uint32_t BBA_RES_TUNE_VAL_7_0;              /**< BBA Resistor Tune Values 7..0, offset: 0x5C */
9348   __IO uint32_t BBA_RES_TUNE_VAL_10_8;             /**< BBA Resistor Tune Values 10..8, offset: 0x60 */
9349   __IO uint32_t LNA_GAIN_LIN_VAL_2_0;              /**< LNA Linear Gain Values 2..0, offset: 0x64 */
9350   __IO uint32_t LNA_GAIN_LIN_VAL_5_3;              /**< LNA Linear Gain Values 5..3, offset: 0x68 */
9351   __IO uint32_t LNA_GAIN_LIN_VAL_8_6;              /**< LNA Linear Gain Values 8..6, offset: 0x6C */
9352   __IO uint32_t LNA_GAIN_LIN_VAL_9;                /**< LNA Linear Gain Values 9, offset: 0x70 */
9353   __IO uint32_t BBA_RES_TUNE_LIN_VAL_3_0;          /**< BBA Resistor Tune Values 3..0, offset: 0x74 */
9354   __IO uint32_t BBA_RES_TUNE_LIN_VAL_7_4;          /**< BBA Resistor Tune Values 7..4, offset: 0x78 */
9355   __IO uint32_t BBA_RES_TUNE_LIN_VAL_10_8;         /**< BBA Resistor Tune Values 10..8, offset: 0x7C */
9356   __IO uint32_t AGC_GAIN_TBL_03_00;                /**< AGC Gain Tables Step 03..00, offset: 0x80 */
9357   __IO uint32_t AGC_GAIN_TBL_07_04;                /**< AGC Gain Tables Step 07..04, offset: 0x84 */
9358   __IO uint32_t AGC_GAIN_TBL_11_08;                /**< AGC Gain Tables Step 11..08, offset: 0x88 */
9359   __IO uint32_t AGC_GAIN_TBL_15_12;                /**< AGC Gain Tables Step 15..12, offset: 0x8C */
9360   __IO uint32_t AGC_GAIN_TBL_19_16;                /**< AGC Gain Tables Step 19..16, offset: 0x90 */
9361   __IO uint32_t AGC_GAIN_TBL_23_20;                /**< AGC Gain Tables Step 23..20, offset: 0x94 */
9362   __IO uint32_t AGC_GAIN_TBL_26_24;                /**< AGC Gain Tables Step 26..24, offset: 0x98 */
9363        uint8_t RESERVED_1[4];
9364   __IO uint32_t DCOC_OFFSET[27];                   /**< DCOC Offset, array offset: 0xA0, array step: 0x4 */
9365   __IO uint32_t DCOC_BBA_STEP;                     /**< DCOC BBA DAC Step, offset: 0x10C */
9366   __IO uint32_t DCOC_TZA_STEP_0;                   /**< DCOC TZA DAC Step 0, offset: 0x110 */
9367   __IO uint32_t DCOC_TZA_STEP_1;                   /**< DCOC TZA DAC Step 1, offset: 0x114 */
9368   __IO uint32_t DCOC_TZA_STEP_2;                   /**< DCOC TZA DAC Step 2, offset: 0x118 */
9369   __IO uint32_t DCOC_TZA_STEP_3;                   /**< DCOC TZA DAC Step 3, offset: 0x11C */
9370   __IO uint32_t DCOC_TZA_STEP_4;                   /**< DCOC TZA DAC Step 4, offset: 0x120 */
9371   __IO uint32_t DCOC_TZA_STEP_5;                   /**< DCOC TZA DAC Step 5, offset: 0x124 */
9372   __IO uint32_t DCOC_TZA_STEP_6;                   /**< DCOC TZA DAC Step 6, offset: 0x128 */
9373   __IO uint32_t DCOC_TZA_STEP_7;                   /**< DCOC TZA DAC Step 7, offset: 0x12C */
9374   __IO uint32_t DCOC_TZA_STEP_8;                   /**< DCOC TZA DAC Step 5, offset: 0x130 */
9375   __IO uint32_t DCOC_TZA_STEP_9;                   /**< DCOC TZA DAC Step 9, offset: 0x134 */
9376   __IO uint32_t DCOC_TZA_STEP_10;                  /**< DCOC TZA DAC Step 10, offset: 0x138 */
9377        uint8_t RESERVED_2[44];
9378   __I  uint32_t DCOC_CAL_ALPHA;                    /**< DCOC Calibration Alpha, offset: 0x168 */
9379   __I  uint32_t DCOC_CAL_BETA_Q;                   /**< DCOC Calibration Beta Q, offset: 0x16C */
9380   __I  uint32_t DCOC_CAL_BETA_I;                   /**< DCOC Calibration Beta I, offset: 0x170 */
9381   __I  uint32_t DCOC_CAL_GAMMA;                    /**< DCOC Calibration Gamma, offset: 0x174 */
9382   __IO uint32_t DCOC_CAL_IIR;                      /**< DCOC Calibration IIR, offset: 0x178 */
9383        uint8_t RESERVED_3[4];
9384   __I  uint32_t DCOC_CAL[3];                       /**< DCOC Calibration Result, array offset: 0x180, array step: 0x4 */
9385        uint8_t RESERVED_4[4];
9386   __IO uint32_t CCA_ED_LQI_CTRL_0;                 /**< RX_DIG CCA ED LQI Control Register 0, offset: 0x190 */
9387   __IO uint32_t CCA_ED_LQI_CTRL_1;                 /**< RX_DIG CCA ED LQI Control Register 1, offset: 0x194 */
9388   __I  uint32_t CCA_ED_LQI_STAT_0;                 /**< RX_DIG CCA ED LQI Status Register 0, offset: 0x198 */
9389        uint8_t RESERVED_5[4];
9390   __IO uint32_t RX_CHF_COEF_0;                     /**< Receive Channel Filter Coefficient 0, offset: 0x1A0 */
9391   __IO uint32_t RX_CHF_COEF_1;                     /**< Receive Channel Filter Coefficient 1, offset: 0x1A4 */
9392   __IO uint32_t RX_CHF_COEF_2;                     /**< Receive Channel Filter Coefficient 2, offset: 0x1A8 */
9393   __IO uint32_t RX_CHF_COEF_3;                     /**< Receive Channel Filter Coefficient 3, offset: 0x1AC */
9394   __IO uint32_t RX_CHF_COEF_4;                     /**< Receive Channel Filter Coefficient 4, offset: 0x1B0 */
9395   __IO uint32_t RX_CHF_COEF_5;                     /**< Receive Channel Filter Coefficient 5, offset: 0x1B4 */
9396   __IO uint32_t RX_CHF_COEF_6;                     /**< Receive Channel Filter Coefficient 6, offset: 0x1B8 */
9397   __IO uint32_t RX_CHF_COEF_7;                     /**< Receive Channel Filter Coefficient 7, offset: 0x1BC */
9398   __IO uint32_t RX_CHF_COEF_8;                     /**< Receive Channel Filter Coefficient 8, offset: 0x1C0 */
9399   __IO uint32_t RX_CHF_COEF_9;                     /**< Receive Channel Filter Coefficient 9, offset: 0x1C4 */
9400   __IO uint32_t RX_CHF_COEF_10;                    /**< Receive Channel Filter Coefficient 10, offset: 0x1C8 */
9401   __IO uint32_t RX_CHF_COEF_11;                    /**< Receive Channel Filter Coefficient 11, offset: 0x1CC */
9402   __IO uint32_t AGC_MAN_AGC_IDX;                   /**< AGC Manual AGC Index, offset: 0x1D0 */
9403   __IO uint32_t DC_RESID_CTRL;                     /**< DC Residual Control, offset: 0x1D4 */
9404   __I  uint32_t DC_RESID_EST;                      /**< DC Residual Estimate, offset: 0x1D8 */
9405   __IO uint32_t RX_RCCAL_CTRL0;                    /**< RX RC Calibration Control0, offset: 0x1DC */
9406   __IO uint32_t RX_RCCAL_CTRL1;                    /**< RX RC Calibration Control1, offset: 0x1E0 */
9407   __I  uint32_t RX_RCCAL_STAT;                     /**< RX RC Calibration Status, offset: 0x1E4 */
9408   __IO uint32_t AUXPLL_FCAL_CTRL;                  /**< Aux PLL Frequency Calibration Control, offset: 0x1E8 */
9409   __I  uint32_t AUXPLL_FCAL_CNT6;                  /**< Aux PLL Frequency Calibration Count 6, offset: 0x1EC */
9410   __I  uint32_t AUXPLL_FCAL_CNT5_4;                /**< Aux PLL Frequency Calibration Count 5 and 4, offset: 0x1F0 */
9411   __I  uint32_t AUXPLL_FCAL_CNT3_2;                /**< Aux PLL Frequency Calibration Count 3 and 2, offset: 0x1F4 */
9412   __I  uint32_t AUXPLL_FCAL_CNT1_0;                /**< Aux PLL Frequency Calibration Count 1 and 0, offset: 0x1F8 */
9413   __IO uint32_t RXDIG_DFT;                         /**< RXDIG DFT, offset: 0x1FC */
9414 } XCVR_RX_DIG_Type;
9415 
9416 /* ----------------------------------------------------------------------------
9417    -- XCVR_RX_DIG Register Masks
9418    ---------------------------------------------------------------------------- */
9419 
9420 /*!
9421  * @addtogroup XCVR_RX_DIG_Register_Masks XCVR_RX_DIG Register Masks
9422  * @{
9423  */
9424 
9425 /*! @name RX_DIG_CTRL - RX Digital Control */
9426 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_NEGEDGE_MASK (0x1U)
9427 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_NEGEDGE_SHIFT (0U)
9428 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_NEGEDGE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_NEGEDGE_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_NEGEDGE_MASK)
9429 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_CH_FILT_BYPASS_MASK (0x2U)
9430 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_CH_FILT_BYPASS_SHIFT (1U)
9431 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_CH_FILT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_CH_FILT_BYPASS_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_CH_FILT_BYPASS_MASK)
9432 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_RAW_EN_MASK (0x4U)
9433 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_RAW_EN_SHIFT (2U)
9434 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_RAW_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_RAW_EN_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_RAW_EN_MASK)
9435 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_POL_MASK  (0x8U)
9436 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_POL_SHIFT (3U)
9437 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_POL(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_POL_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_POL_MASK)
9438 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR_MASK (0x70U)
9439 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR_SHIFT (4U)
9440 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR_MASK)
9441 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL_MASK (0x100U)
9442 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL_SHIFT (8U)
9443 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL_MASK)
9444 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_NORM_EN_MASK  (0x200U)
9445 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_NORM_EN_SHIFT (9U)
9446 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_NORM_EN(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_NORM_EN_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_NORM_EN_MASK)
9447 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_EN_MASK  (0x400U)
9448 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_EN_SHIFT (10U)
9449 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_EN(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_EN_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_EN_MASK)
9450 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN_MASK   (0x800U)
9451 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN_SHIFT  (11U)
9452 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN_MASK)
9453 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_EN_MASK  (0x1000U)
9454 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_EN_SHIFT (12U)
9455 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_EN(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_EN_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_EN_MASK)
9456 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN_MASK (0x2000U)
9457 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN_SHIFT (13U)
9458 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN_MASK)
9459 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_IQ_SWAP_MASK  (0x4000U)
9460 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_IQ_SWAP_SHIFT (14U)
9461 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_IQ_SWAP(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_IQ_SWAP_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_IQ_SWAP_MASK)
9462 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN_MASK (0x8000U)
9463 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN_SHIFT (15U)
9464 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN_MASK)
9465 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_EN_MASK   (0x10000U)
9466 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_EN_SHIFT  (16U)
9467 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_EN(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_EN_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_EN_MASK)
9468 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE_MASK (0x20000U)
9469 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE_SHIFT (17U)
9470 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE_MASK)
9471 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_DMA_DTEST_EN_MASK (0x40000U)
9472 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_DMA_DTEST_EN_SHIFT (18U)
9473 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_DMA_DTEST_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_DMA_DTEST_EN_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_DMA_DTEST_EN_MASK)
9474 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN_MASK (0x1F00000U)
9475 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN_SHIFT (20U)
9476 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN_MASK)
9477 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HZD_CORR_DIS_MASK (0x2000000U)
9478 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HZD_CORR_DIS_SHIFT (25U)
9479 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HZD_CORR_DIS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HZD_CORR_DIS_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HZD_CORR_DIS_MASK)
9480 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HAZARD_MASK (0x10000000U)
9481 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HAZARD_SHIFT (28U)
9482 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HAZARD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HAZARD_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HAZARD_MASK)
9483 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_FILT_HAZARD_MASK (0x20000000U)
9484 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_FILT_HAZARD_SHIFT (29U)
9485 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_FILT_HAZARD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_FILT_HAZARD_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_FILT_HAZARD_MASK)
9486 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_SAT_I_MASK (0x40000000U)
9487 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_SAT_I_SHIFT (30U)
9488 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_SAT_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_SAT_I_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_SAT_I_MASK)
9489 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_SAT_Q_MASK (0x80000000U)
9490 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_SAT_Q_SHIFT (31U)
9491 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_SAT_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_SAT_Q_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_SAT_Q_MASK)
9492 
9493 /*! @name AGC_CTRL_0 - AGC Control 0 */
9494 #define XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN_MASK  (0x1U)
9495 #define XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN_SHIFT (0U)
9496 #define XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN_MASK)
9497 #define XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC_MASK (0x6U)
9498 #define XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC_SHIFT (1U)
9499 #define XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC_MASK)
9500 #define XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_EN_MASK (0x8U)
9501 #define XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_EN_SHIFT (3U)
9502 #define XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_EN(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_EN_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_EN_MASK)
9503 #define XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_PRE_OR_AA_MASK (0x10U)
9504 #define XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_PRE_OR_AA_SHIFT (4U)
9505 #define XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_PRE_OR_AA(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_PRE_OR_AA_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_PRE_OR_AA_MASK)
9506 #define XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_EN_MASK    (0x40U)
9507 #define XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_EN_SHIFT   (6U)
9508 #define XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_EN(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_EN_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_EN_MASK)
9509 #define XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_SRC_MASK   (0x80U)
9510 #define XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_SRC_SHIFT  (7U)
9511 #define XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_SRC(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_SRC_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_SRC_MASK)
9512 #define XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_BBA_STEP_SZ_MASK (0xF00U)
9513 #define XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_BBA_STEP_SZ_SHIFT (8U)
9514 #define XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_BBA_STEP_SZ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_BBA_STEP_SZ_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_BBA_STEP_SZ_MASK)
9515 #define XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_LNA_STEP_SZ_MASK (0xF000U)
9516 #define XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_LNA_STEP_SZ_SHIFT (12U)
9517 #define XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_LNA_STEP_SZ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_LNA_STEP_SZ_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_LNA_STEP_SZ_MASK)
9518 #define XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_RSSI_THRESH_MASK (0xFF0000U)
9519 #define XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_RSSI_THRESH_SHIFT (16U)
9520 #define XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_RSSI_THRESH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_RSSI_THRESH_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_RSSI_THRESH_MASK)
9521 #define XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH_MASK (0xFF000000U)
9522 #define XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH_SHIFT (24U)
9523 #define XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH_MASK)
9524 
9525 /*! @name AGC_CTRL_1 - AGC Control 1 */
9526 #define XCVR_RX_DIG_AGC_CTRL_1_BBA_ALT_CODE_MASK (0xFU)
9527 #define XCVR_RX_DIG_AGC_CTRL_1_BBA_ALT_CODE_SHIFT (0U)
9528 #define XCVR_RX_DIG_AGC_CTRL_1_BBA_ALT_CODE(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_1_BBA_ALT_CODE_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_1_BBA_ALT_CODE_MASK)
9529 #define XCVR_RX_DIG_AGC_CTRL_1_LNA_ALT_CODE_MASK (0xFF0U)
9530 #define XCVR_RX_DIG_AGC_CTRL_1_LNA_ALT_CODE_SHIFT (4U)
9531 #define XCVR_RX_DIG_AGC_CTRL_1_LNA_ALT_CODE(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_1_LNA_ALT_CODE_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_1_LNA_ALT_CODE_MASK)
9532 #define XCVR_RX_DIG_AGC_CTRL_1_LNA_USER_GAIN_MASK (0xF000U)
9533 #define XCVR_RX_DIG_AGC_CTRL_1_LNA_USER_GAIN_SHIFT (12U)
9534 #define XCVR_RX_DIG_AGC_CTRL_1_LNA_USER_GAIN(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_1_LNA_USER_GAIN_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_1_LNA_USER_GAIN_MASK)
9535 #define XCVR_RX_DIG_AGC_CTRL_1_BBA_USER_GAIN_MASK (0xF0000U)
9536 #define XCVR_RX_DIG_AGC_CTRL_1_BBA_USER_GAIN_SHIFT (16U)
9537 #define XCVR_RX_DIG_AGC_CTRL_1_BBA_USER_GAIN(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_1_BBA_USER_GAIN_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_1_BBA_USER_GAIN_MASK)
9538 #define XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN_MASK (0x100000U)
9539 #define XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN_SHIFT (20U)
9540 #define XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN_MASK)
9541 #define XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN_MASK (0x200000U)
9542 #define XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN_SHIFT (21U)
9543 #define XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN_MASK)
9544 #define XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN_MASK   (0x400000U)
9545 #define XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN_SHIFT  (22U)
9546 #define XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN_MASK)
9547 #define XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME_MASK (0xFF000000U)
9548 #define XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME_SHIFT (24U)
9549 #define XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME_MASK)
9550 
9551 /*! @name AGC_CTRL_2 - AGC Control 2 */
9552 #define XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_RST_MASK (0x1U)
9553 #define XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_RST_SHIFT (0U)
9554 #define XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_RST(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_RST_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_RST_MASK)
9555 #define XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_RST_MASK (0x2U)
9556 #define XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_RST_SHIFT (1U)
9557 #define XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_RST(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_RST_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_RST_MASK)
9558 #define XCVR_RX_DIG_AGC_CTRL_2_MAN_PDET_RST_MASK (0x4U)
9559 #define XCVR_RX_DIG_AGC_CTRL_2_MAN_PDET_RST_SHIFT (2U)
9560 #define XCVR_RX_DIG_AGC_CTRL_2_MAN_PDET_RST(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_2_MAN_PDET_RST_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_2_MAN_PDET_RST_MASK)
9561 #define XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME_MASK (0xFF0U)
9562 #define XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME_SHIFT (4U)
9563 #define XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME_MASK)
9564 #define XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO_MASK (0x7000U)
9565 #define XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO_SHIFT (12U)
9566 #define XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO_MASK)
9567 #define XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI_MASK (0x38000U)
9568 #define XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI_SHIFT (15U)
9569 #define XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI_MASK)
9570 #define XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO_MASK (0x1C0000U)
9571 #define XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO_SHIFT (18U)
9572 #define XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO_MASK)
9573 #define XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI_MASK (0xE00000U)
9574 #define XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI_SHIFT (21U)
9575 #define XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI_MASK)
9576 #define XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE_MASK (0x3F000000U)
9577 #define XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE_SHIFT (24U)
9578 #define XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE_MASK)
9579 #define XCVR_RX_DIG_AGC_CTRL_2_LNA_LG_ON_OVR_MASK (0x40000000U)
9580 #define XCVR_RX_DIG_AGC_CTRL_2_LNA_LG_ON_OVR_SHIFT (30U)
9581 #define XCVR_RX_DIG_AGC_CTRL_2_LNA_LG_ON_OVR(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_2_LNA_LG_ON_OVR_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_2_LNA_LG_ON_OVR_MASK)
9582 #define XCVR_RX_DIG_AGC_CTRL_2_LNA_HG_ON_OVR_MASK (0x80000000U)
9583 #define XCVR_RX_DIG_AGC_CTRL_2_LNA_HG_ON_OVR_SHIFT (31U)
9584 #define XCVR_RX_DIG_AGC_CTRL_2_LNA_HG_ON_OVR(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_2_LNA_HG_ON_OVR_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_2_LNA_HG_ON_OVR_MASK)
9585 
9586 /*! @name AGC_CTRL_3 - AGC Control 3 */
9587 #define XCVR_RX_DIG_AGC_CTRL_3_AGC_UNFREEZE_TIME_MASK (0x1FFFU)
9588 #define XCVR_RX_DIG_AGC_CTRL_3_AGC_UNFREEZE_TIME_SHIFT (0U)
9589 #define XCVR_RX_DIG_AGC_CTRL_3_AGC_UNFREEZE_TIME(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_3_AGC_UNFREEZE_TIME_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_3_AGC_UNFREEZE_TIME_MASK)
9590 #define XCVR_RX_DIG_AGC_CTRL_3_AGC_PDET_LO_DLY_MASK (0xE000U)
9591 #define XCVR_RX_DIG_AGC_CTRL_3_AGC_PDET_LO_DLY_SHIFT (13U)
9592 #define XCVR_RX_DIG_AGC_CTRL_3_AGC_PDET_LO_DLY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_3_AGC_PDET_LO_DLY_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_3_AGC_PDET_LO_DLY_MASK)
9593 #define XCVR_RX_DIG_AGC_CTRL_3_AGC_RSSI_DELT_H2S_MASK (0x7F0000U)
9594 #define XCVR_RX_DIG_AGC_CTRL_3_AGC_RSSI_DELT_H2S_SHIFT (16U)
9595 #define XCVR_RX_DIG_AGC_CTRL_3_AGC_RSSI_DELT_H2S(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_3_AGC_RSSI_DELT_H2S_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_3_AGC_RSSI_DELT_H2S_MASK)
9596 #define XCVR_RX_DIG_AGC_CTRL_3_AGC_H2S_STEP_SZ_MASK (0xF800000U)
9597 #define XCVR_RX_DIG_AGC_CTRL_3_AGC_H2S_STEP_SZ_SHIFT (23U)
9598 #define XCVR_RX_DIG_AGC_CTRL_3_AGC_H2S_STEP_SZ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_3_AGC_H2S_STEP_SZ_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_3_AGC_H2S_STEP_SZ_MASK)
9599 #define XCVR_RX_DIG_AGC_CTRL_3_AGC_UP_STEP_SZ_MASK (0xF0000000U)
9600 #define XCVR_RX_DIG_AGC_CTRL_3_AGC_UP_STEP_SZ_SHIFT (28U)
9601 #define XCVR_RX_DIG_AGC_CTRL_3_AGC_UP_STEP_SZ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_3_AGC_UP_STEP_SZ_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_3_AGC_UP_STEP_SZ_MASK)
9602 
9603 /*! @name AGC_STAT - AGC Status */
9604 #define XCVR_RX_DIG_AGC_STAT_BBA_PDET_LO_STAT_MASK (0x1U)
9605 #define XCVR_RX_DIG_AGC_STAT_BBA_PDET_LO_STAT_SHIFT (0U)
9606 #define XCVR_RX_DIG_AGC_STAT_BBA_PDET_LO_STAT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_STAT_BBA_PDET_LO_STAT_SHIFT)) & XCVR_RX_DIG_AGC_STAT_BBA_PDET_LO_STAT_MASK)
9607 #define XCVR_RX_DIG_AGC_STAT_BBA_PDET_HI_STAT_MASK (0x2U)
9608 #define XCVR_RX_DIG_AGC_STAT_BBA_PDET_HI_STAT_SHIFT (1U)
9609 #define XCVR_RX_DIG_AGC_STAT_BBA_PDET_HI_STAT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_STAT_BBA_PDET_HI_STAT_SHIFT)) & XCVR_RX_DIG_AGC_STAT_BBA_PDET_HI_STAT_MASK)
9610 #define XCVR_RX_DIG_AGC_STAT_TZA_PDET_LO_STAT_MASK (0x4U)
9611 #define XCVR_RX_DIG_AGC_STAT_TZA_PDET_LO_STAT_SHIFT (2U)
9612 #define XCVR_RX_DIG_AGC_STAT_TZA_PDET_LO_STAT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_STAT_TZA_PDET_LO_STAT_SHIFT)) & XCVR_RX_DIG_AGC_STAT_TZA_PDET_LO_STAT_MASK)
9613 #define XCVR_RX_DIG_AGC_STAT_TZA_PDET_HI_STAT_MASK (0x8U)
9614 #define XCVR_RX_DIG_AGC_STAT_TZA_PDET_HI_STAT_SHIFT (3U)
9615 #define XCVR_RX_DIG_AGC_STAT_TZA_PDET_HI_STAT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_STAT_TZA_PDET_HI_STAT_SHIFT)) & XCVR_RX_DIG_AGC_STAT_TZA_PDET_HI_STAT_MASK)
9616 #define XCVR_RX_DIG_AGC_STAT_CURR_AGC_IDX_MASK   (0x1F0U)
9617 #define XCVR_RX_DIG_AGC_STAT_CURR_AGC_IDX_SHIFT  (4U)
9618 #define XCVR_RX_DIG_AGC_STAT_CURR_AGC_IDX(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_STAT_CURR_AGC_IDX_SHIFT)) & XCVR_RX_DIG_AGC_STAT_CURR_AGC_IDX_MASK)
9619 #define XCVR_RX_DIG_AGC_STAT_AGC_FROZEN_MASK     (0x200U)
9620 #define XCVR_RX_DIG_AGC_STAT_AGC_FROZEN_SHIFT    (9U)
9621 #define XCVR_RX_DIG_AGC_STAT_AGC_FROZEN(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_STAT_AGC_FROZEN_SHIFT)) & XCVR_RX_DIG_AGC_STAT_AGC_FROZEN_MASK)
9622 #define XCVR_RX_DIG_AGC_STAT_RSSI_ADC_RAW_MASK   (0xFF0000U)
9623 #define XCVR_RX_DIG_AGC_STAT_RSSI_ADC_RAW_SHIFT  (16U)
9624 #define XCVR_RX_DIG_AGC_STAT_RSSI_ADC_RAW(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_STAT_RSSI_ADC_RAW_SHIFT)) & XCVR_RX_DIG_AGC_STAT_RSSI_ADC_RAW_MASK)
9625 
9626 /*! @name RSSI_CTRL_0 - RSSI Control 0 */
9627 #define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_USE_VALS_MASK (0x1U)
9628 #define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_USE_VALS_SHIFT (0U)
9629 #define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_USE_VALS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_CTRL_0_RSSI_USE_VALS_SHIFT)) & XCVR_RX_DIG_RSSI_CTRL_0_RSSI_USE_VALS_MASK)
9630 #define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_SRC_MASK (0x6U)
9631 #define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_SRC_SHIFT (1U)
9632 #define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_SRC(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_SRC_SHIFT)) & XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_SRC_MASK)
9633 #define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_EN_MASK (0x8U)
9634 #define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_EN_SHIFT (3U)
9635 #define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_EN(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_EN_SHIFT)) & XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_EN_MASK)
9636 #define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT_MASK (0x60U)
9637 #define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT_SHIFT (5U)
9638 #define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT_SHIFT)) & XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT_MASK)
9639 #define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_N_WINDOW_AVG_MASK (0x300U)
9640 #define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_N_WINDOW_AVG_SHIFT (8U)
9641 #define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_N_WINDOW_AVG(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_CTRL_0_RSSI_N_WINDOW_AVG_SHIFT)) & XCVR_RX_DIG_RSSI_CTRL_0_RSSI_N_WINDOW_AVG_MASK)
9642 #define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_DELAY_MASK (0xFC00U)
9643 #define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_DELAY_SHIFT (10U)
9644 #define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_DELAY_SHIFT)) & XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_DELAY_MASK)
9645 #define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_WEIGHT_MASK (0xF0000U)
9646 #define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_WEIGHT_SHIFT (16U)
9647 #define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_WEIGHT_SHIFT)) & XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_WEIGHT_MASK)
9648 #define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_VLD_SETTLE_MASK (0x700000U)
9649 #define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_VLD_SETTLE_SHIFT (20U)
9650 #define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_VLD_SETTLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_CTRL_0_RSSI_VLD_SETTLE_SHIFT)) & XCVR_RX_DIG_RSSI_CTRL_0_RSSI_VLD_SETTLE_MASK)
9651 #define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ_MASK    (0xFF000000U)
9652 #define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ_SHIFT   (24U)
9653 #define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ_SHIFT)) & XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ_MASK)
9654 
9655 /*! @name RSSI_CTRL_1 - RSSI Control 1 */
9656 #define XCVR_RX_DIG_RSSI_CTRL_1_RSSI_OUT_MASK    (0xFF000000U)
9657 #define XCVR_RX_DIG_RSSI_CTRL_1_RSSI_OUT_SHIFT   (24U)
9658 #define XCVR_RX_DIG_RSSI_CTRL_1_RSSI_OUT(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_CTRL_1_RSSI_OUT_SHIFT)) & XCVR_RX_DIG_RSSI_CTRL_1_RSSI_OUT_MASK)
9659 
9660 /*! @name RSSI_DFT - RSSI DFT */
9661 #define XCVR_RX_DIG_RSSI_DFT_DFT_MAG_MASK        (0x1FFFU)
9662 #define XCVR_RX_DIG_RSSI_DFT_DFT_MAG_SHIFT       (0U)
9663 #define XCVR_RX_DIG_RSSI_DFT_DFT_MAG(x)          (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_DFT_DFT_MAG_SHIFT)) & XCVR_RX_DIG_RSSI_DFT_DFT_MAG_MASK)
9664 #define XCVR_RX_DIG_RSSI_DFT_DFT_NOISE_MASK      (0x1FFF0000U)
9665 #define XCVR_RX_DIG_RSSI_DFT_DFT_NOISE_SHIFT     (16U)
9666 #define XCVR_RX_DIG_RSSI_DFT_DFT_NOISE(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_DFT_DFT_NOISE_SHIFT)) & XCVR_RX_DIG_RSSI_DFT_DFT_NOISE_MASK)
9667 
9668 /*! @name DCOC_CTRL_0 - DCOC Control 0 */
9669 #define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MIDPWR_TRK_DIS_MASK (0x1U)
9670 #define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MIDPWR_TRK_DIS_SHIFT (0U)
9671 #define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MIDPWR_TRK_DIS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MIDPWR_TRK_DIS_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MIDPWR_TRK_DIS_MASK)
9672 #define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MAN_MASK    (0x2U)
9673 #define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MAN_SHIFT   (1U)
9674 #define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MAN(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MAN_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MAN_MASK)
9675 #define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_TRK_EST_OVR_MASK (0x4U)
9676 #define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_TRK_EST_OVR_SHIFT (2U)
9677 #define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_TRK_EST_OVR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_0_DCOC_TRK_EST_OVR_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_0_DCOC_TRK_EST_OVR_MASK)
9678 #define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC_MASK (0x8U)
9679 #define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC_SHIFT (3U)
9680 #define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC_MASK)
9681 #define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_EN_MASK (0x10U)
9682 #define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_EN_SHIFT (4U)
9683 #define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_EN_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_EN_MASK)
9684 #define XCVR_RX_DIG_DCOC_CTRL_0_TRACK_FROM_ZERO_MASK (0x20U)
9685 #define XCVR_RX_DIG_DCOC_CTRL_0_TRACK_FROM_ZERO_SHIFT (5U)
9686 #define XCVR_RX_DIG_DCOC_CTRL_0_TRACK_FROM_ZERO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_0_TRACK_FROM_ZERO_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_0_TRACK_FROM_ZERO_MASK)
9687 #define XCVR_RX_DIG_DCOC_CTRL_0_BBA_CORR_POL_MASK (0x40U)
9688 #define XCVR_RX_DIG_DCOC_CTRL_0_BBA_CORR_POL_SHIFT (6U)
9689 #define XCVR_RX_DIG_DCOC_CTRL_0_BBA_CORR_POL(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_0_BBA_CORR_POL_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_0_BBA_CORR_POL_MASK)
9690 #define XCVR_RX_DIG_DCOC_CTRL_0_TZA_CORR_POL_MASK (0x80U)
9691 #define XCVR_RX_DIG_DCOC_CTRL_0_TZA_CORR_POL_SHIFT (7U)
9692 #define XCVR_RX_DIG_DCOC_CTRL_0_TZA_CORR_POL(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_0_TZA_CORR_POL_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_0_TZA_CORR_POL_MASK)
9693 #define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_DURATION_MASK (0x1F00U)
9694 #define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_DURATION_SHIFT (8U)
9695 #define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_DURATION(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_DURATION_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_DURATION_MASK)
9696 #define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY_MASK (0x1F0000U)
9697 #define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY_SHIFT (16U)
9698 #define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY_MASK)
9699 #define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME_MASK (0x7F000000U)
9700 #define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME_SHIFT (24U)
9701 #define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME_MASK)
9702 
9703 /*! @name DCOC_CTRL_1 - DCOC Control 1 */
9704 #define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX_MASK (0x3U)
9705 #define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX_SHIFT (0U)
9706 #define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX_MASK)
9707 #define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX_MASK (0x1CU)
9708 #define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX_SHIFT (2U)
9709 #define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX_MASK)
9710 #define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX_MASK (0xE0U)
9711 #define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX_SHIFT (5U)
9712 #define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX_MASK)
9713 #define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT_MASK (0x7000U)
9714 #define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT_SHIFT (12U)
9715 #define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT_MASK)
9716 #define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX_MASK (0x30000U)
9717 #define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX_SHIFT (16U)
9718 #define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX_MASK)
9719 #define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX_MASK (0x1C0000U)
9720 #define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX_SHIFT (18U)
9721 #define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX_MASK)
9722 #define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX_MASK (0xE00000U)
9723 #define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX_SHIFT (21U)
9724 #define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX_MASK)
9725 #define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_MIN_AGC_IDX_MASK (0x1F000000U)
9726 #define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_MIN_AGC_IDX_SHIFT (24U)
9727 #define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_MIN_AGC_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_MIN_AGC_IDX_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_MIN_AGC_IDX_MASK)
9728 
9729 /*! @name DCOC_DAC_INIT - DCOC DAC Initialization */
9730 #define XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I_MASK (0x3FU)
9731 #define XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I_SHIFT (0U)
9732 #define XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I_SHIFT)) & XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I_MASK)
9733 #define XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q_MASK (0x3F00U)
9734 #define XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q_SHIFT (8U)
9735 #define XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q_SHIFT)) & XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q_MASK)
9736 #define XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I_MASK (0xFF0000U)
9737 #define XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I_SHIFT (16U)
9738 #define XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I_SHIFT)) & XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I_MASK)
9739 #define XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q_MASK (0xFF000000U)
9740 #define XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q_SHIFT (24U)
9741 #define XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q_SHIFT)) & XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q_MASK)
9742 
9743 /*! @name DCOC_DIG_MAN - DCOC Digital Correction Manual Override */
9744 #define XCVR_RX_DIG_DCOC_DIG_MAN_DIG_DCOC_INIT_I_MASK (0xFFFU)
9745 #define XCVR_RX_DIG_DCOC_DIG_MAN_DIG_DCOC_INIT_I_SHIFT (0U)
9746 #define XCVR_RX_DIG_DCOC_DIG_MAN_DIG_DCOC_INIT_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_DIG_MAN_DIG_DCOC_INIT_I_SHIFT)) & XCVR_RX_DIG_DCOC_DIG_MAN_DIG_DCOC_INIT_I_MASK)
9747 #define XCVR_RX_DIG_DCOC_DIG_MAN_DIG_DCOC_INIT_Q_MASK (0xFFF0000U)
9748 #define XCVR_RX_DIG_DCOC_DIG_MAN_DIG_DCOC_INIT_Q_SHIFT (16U)
9749 #define XCVR_RX_DIG_DCOC_DIG_MAN_DIG_DCOC_INIT_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_DIG_MAN_DIG_DCOC_INIT_Q_SHIFT)) & XCVR_RX_DIG_DCOC_DIG_MAN_DIG_DCOC_INIT_Q_MASK)
9750 
9751 /*! @name DCOC_CAL_GAIN - DCOC Calibration Gain */
9752 #define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN1_MASK (0xF00U)
9753 #define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN1_SHIFT (8U)
9754 #define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN1_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN1_MASK)
9755 #define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN1_MASK (0xF000U)
9756 #define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN1_SHIFT (12U)
9757 #define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN1_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN1_MASK)
9758 #define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN2_MASK (0xF0000U)
9759 #define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN2_SHIFT (16U)
9760 #define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN2_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN2_MASK)
9761 #define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN2_MASK (0xF00000U)
9762 #define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN2_SHIFT (20U)
9763 #define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN2_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN2_MASK)
9764 #define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN3_MASK (0xF000000U)
9765 #define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN3_SHIFT (24U)
9766 #define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN3_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN3_MASK)
9767 #define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN3_MASK (0xF0000000U)
9768 #define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN3_SHIFT (28U)
9769 #define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN3_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN3_MASK)
9770 
9771 /*! @name DCOC_STAT - DCOC Status */
9772 #define XCVR_RX_DIG_DCOC_STAT_BBA_DCOC_I_MASK    (0x3FU)
9773 #define XCVR_RX_DIG_DCOC_STAT_BBA_DCOC_I_SHIFT   (0U)
9774 #define XCVR_RX_DIG_DCOC_STAT_BBA_DCOC_I(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_STAT_BBA_DCOC_I_SHIFT)) & XCVR_RX_DIG_DCOC_STAT_BBA_DCOC_I_MASK)
9775 #define XCVR_RX_DIG_DCOC_STAT_BBA_DCOC_Q_MASK    (0x3F00U)
9776 #define XCVR_RX_DIG_DCOC_STAT_BBA_DCOC_Q_SHIFT   (8U)
9777 #define XCVR_RX_DIG_DCOC_STAT_BBA_DCOC_Q(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_STAT_BBA_DCOC_Q_SHIFT)) & XCVR_RX_DIG_DCOC_STAT_BBA_DCOC_Q_MASK)
9778 #define XCVR_RX_DIG_DCOC_STAT_TZA_DCOC_I_MASK    (0xFF0000U)
9779 #define XCVR_RX_DIG_DCOC_STAT_TZA_DCOC_I_SHIFT   (16U)
9780 #define XCVR_RX_DIG_DCOC_STAT_TZA_DCOC_I(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_STAT_TZA_DCOC_I_SHIFT)) & XCVR_RX_DIG_DCOC_STAT_TZA_DCOC_I_MASK)
9781 #define XCVR_RX_DIG_DCOC_STAT_TZA_DCOC_Q_MASK    (0xFF000000U)
9782 #define XCVR_RX_DIG_DCOC_STAT_TZA_DCOC_Q_SHIFT   (24U)
9783 #define XCVR_RX_DIG_DCOC_STAT_TZA_DCOC_Q(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_STAT_TZA_DCOC_Q_SHIFT)) & XCVR_RX_DIG_DCOC_STAT_TZA_DCOC_Q_MASK)
9784 
9785 /*! @name DCOC_DC_EST - DCOC DC Estimate */
9786 #define XCVR_RX_DIG_DCOC_DC_EST_DC_EST_I_MASK    (0xFFFU)
9787 #define XCVR_RX_DIG_DCOC_DC_EST_DC_EST_I_SHIFT   (0U)
9788 #define XCVR_RX_DIG_DCOC_DC_EST_DC_EST_I(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_DC_EST_DC_EST_I_SHIFT)) & XCVR_RX_DIG_DCOC_DC_EST_DC_EST_I_MASK)
9789 #define XCVR_RX_DIG_DCOC_DC_EST_DC_EST_Q_MASK    (0xFFF0000U)
9790 #define XCVR_RX_DIG_DCOC_DC_EST_DC_EST_Q_SHIFT   (16U)
9791 #define XCVR_RX_DIG_DCOC_DC_EST_DC_EST_Q(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_DC_EST_DC_EST_Q_SHIFT)) & XCVR_RX_DIG_DCOC_DC_EST_DC_EST_Q_MASK)
9792 
9793 /*! @name DCOC_CAL_RCP - DCOC Calibration Reciprocals */
9794 #define XCVR_RX_DIG_DCOC_CAL_RCP_DCOC_TMP_CALC_RECIP_MASK (0x7FFU)
9795 #define XCVR_RX_DIG_DCOC_CAL_RCP_DCOC_TMP_CALC_RECIP_SHIFT (0U)
9796 #define XCVR_RX_DIG_DCOC_CAL_RCP_DCOC_TMP_CALC_RECIP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_RCP_DCOC_TMP_CALC_RECIP_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_RCP_DCOC_TMP_CALC_RECIP_MASK)
9797 #define XCVR_RX_DIG_DCOC_CAL_RCP_ALPHA_CALC_RECIP_MASK (0x7FF0000U)
9798 #define XCVR_RX_DIG_DCOC_CAL_RCP_ALPHA_CALC_RECIP_SHIFT (16U)
9799 #define XCVR_RX_DIG_DCOC_CAL_RCP_ALPHA_CALC_RECIP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_RCP_ALPHA_CALC_RECIP_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_RCP_ALPHA_CALC_RECIP_MASK)
9800 
9801 /*! @name IQMC_CTRL - IQMC Control */
9802 #define XCVR_RX_DIG_IQMC_CTRL_IQMC_CAL_EN_MASK   (0x1U)
9803 #define XCVR_RX_DIG_IQMC_CTRL_IQMC_CAL_EN_SHIFT  (0U)
9804 #define XCVR_RX_DIG_IQMC_CTRL_IQMC_CAL_EN(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_IQMC_CTRL_IQMC_CAL_EN_SHIFT)) & XCVR_RX_DIG_IQMC_CTRL_IQMC_CAL_EN_MASK)
9805 #define XCVR_RX_DIG_IQMC_CTRL_IQMC_NUM_ITER_MASK (0xFF00U)
9806 #define XCVR_RX_DIG_IQMC_CTRL_IQMC_NUM_ITER_SHIFT (8U)
9807 #define XCVR_RX_DIG_IQMC_CTRL_IQMC_NUM_ITER(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_IQMC_CTRL_IQMC_NUM_ITER_SHIFT)) & XCVR_RX_DIG_IQMC_CTRL_IQMC_NUM_ITER_MASK)
9808 #define XCVR_RX_DIG_IQMC_CTRL_IQMC_DC_GAIN_ADJ_MASK (0x7FF0000U)
9809 #define XCVR_RX_DIG_IQMC_CTRL_IQMC_DC_GAIN_ADJ_SHIFT (16U)
9810 #define XCVR_RX_DIG_IQMC_CTRL_IQMC_DC_GAIN_ADJ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_IQMC_CTRL_IQMC_DC_GAIN_ADJ_SHIFT)) & XCVR_RX_DIG_IQMC_CTRL_IQMC_DC_GAIN_ADJ_MASK)
9811 
9812 /*! @name IQMC_CAL - IQMC Calibration */
9813 #define XCVR_RX_DIG_IQMC_CAL_IQMC_GAIN_ADJ_MASK  (0x7FFU)
9814 #define XCVR_RX_DIG_IQMC_CAL_IQMC_GAIN_ADJ_SHIFT (0U)
9815 #define XCVR_RX_DIG_IQMC_CAL_IQMC_GAIN_ADJ(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_IQMC_CAL_IQMC_GAIN_ADJ_SHIFT)) & XCVR_RX_DIG_IQMC_CAL_IQMC_GAIN_ADJ_MASK)
9816 #define XCVR_RX_DIG_IQMC_CAL_IQMC_PHASE_ADJ_MASK (0xFFF0000U)
9817 #define XCVR_RX_DIG_IQMC_CAL_IQMC_PHASE_ADJ_SHIFT (16U)
9818 #define XCVR_RX_DIG_IQMC_CAL_IQMC_PHASE_ADJ(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_IQMC_CAL_IQMC_PHASE_ADJ_SHIFT)) & XCVR_RX_DIG_IQMC_CAL_IQMC_PHASE_ADJ_MASK)
9819 
9820 /*! @name LNA_GAIN_VAL_3_0 - LNA_GAIN Step Values 3..0 */
9821 #define XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_0_MASK (0xFFU)
9822 #define XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_0_SHIFT (0U)
9823 #define XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_0_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_0_MASK)
9824 #define XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_1_MASK (0xFF00U)
9825 #define XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_1_SHIFT (8U)
9826 #define XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_1_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_1_MASK)
9827 #define XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_2_MASK (0xFF0000U)
9828 #define XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_2_SHIFT (16U)
9829 #define XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_2_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_2_MASK)
9830 #define XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_3_MASK (0xFF000000U)
9831 #define XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_3_SHIFT (24U)
9832 #define XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_3_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_3_MASK)
9833 
9834 /*! @name LNA_GAIN_VAL_7_4 - LNA_GAIN Step Values 7..4 */
9835 #define XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_4_MASK (0xFFU)
9836 #define XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_4_SHIFT (0U)
9837 #define XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_4_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_4_MASK)
9838 #define XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_5_MASK (0xFF00U)
9839 #define XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_5_SHIFT (8U)
9840 #define XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_5(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_5_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_5_MASK)
9841 #define XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_6_MASK (0xFF0000U)
9842 #define XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_6_SHIFT (16U)
9843 #define XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_6(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_6_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_6_MASK)
9844 #define XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_7_MASK (0xFF000000U)
9845 #define XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_7_SHIFT (24U)
9846 #define XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_7(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_7_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_7_MASK)
9847 
9848 /*! @name LNA_GAIN_VAL_8 - LNA_GAIN Step Values 8 */
9849 #define XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_8_MASK (0xFFU)
9850 #define XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_8_SHIFT (0U)
9851 #define XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_8(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_8_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_8_MASK)
9852 #define XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_9_MASK (0xFF00U)
9853 #define XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_9_SHIFT (8U)
9854 #define XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_9(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_9_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_9_MASK)
9855 
9856 /*! @name BBA_RES_TUNE_VAL_7_0 - BBA Resistor Tune Values 7..0 */
9857 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_0_MASK (0xFU)
9858 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_0_SHIFT (0U)
9859 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_0_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_0_MASK)
9860 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_1_MASK (0xF0U)
9861 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_1_SHIFT (4U)
9862 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_1_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_1_MASK)
9863 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_2_MASK (0xF00U)
9864 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_2_SHIFT (8U)
9865 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_2_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_2_MASK)
9866 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_3_MASK (0xF000U)
9867 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_3_SHIFT (12U)
9868 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_3_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_3_MASK)
9869 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_4_MASK (0xF0000U)
9870 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_4_SHIFT (16U)
9871 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_4_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_4_MASK)
9872 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_5_MASK (0xF00000U)
9873 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_5_SHIFT (20U)
9874 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_5(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_5_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_5_MASK)
9875 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_6_MASK (0xF000000U)
9876 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_6_SHIFT (24U)
9877 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_6(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_6_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_6_MASK)
9878 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_7_MASK (0xF0000000U)
9879 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_7_SHIFT (28U)
9880 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_7(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_7_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_7_MASK)
9881 
9882 /*! @name BBA_RES_TUNE_VAL_10_8 - BBA Resistor Tune Values 10..8 */
9883 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_8_MASK (0xFU)
9884 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_8_SHIFT (0U)
9885 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_8(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_8_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_8_MASK)
9886 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_9_MASK (0xF0U)
9887 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_9_SHIFT (4U)
9888 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_9(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_9_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_9_MASK)
9889 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_10_MASK (0xF00U)
9890 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_10_SHIFT (8U)
9891 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_10(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_10_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_10_MASK)
9892 
9893 /*! @name LNA_GAIN_LIN_VAL_2_0 - LNA Linear Gain Values 2..0 */
9894 #define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_0_MASK (0x3FFU)
9895 #define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_0_SHIFT (0U)
9896 #define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_0_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_0_MASK)
9897 #define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_1_MASK (0xFFC00U)
9898 #define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_1_SHIFT (10U)
9899 #define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_1_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_1_MASK)
9900 #define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_2_MASK (0x3FF00000U)
9901 #define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_2_SHIFT (20U)
9902 #define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_2_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_2_MASK)
9903 
9904 /*! @name LNA_GAIN_LIN_VAL_5_3 - LNA Linear Gain Values 5..3 */
9905 #define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_3_MASK (0x3FFU)
9906 #define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_3_SHIFT (0U)
9907 #define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_3_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_3_MASK)
9908 #define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_4_MASK (0xFFC00U)
9909 #define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_4_SHIFT (10U)
9910 #define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_4_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_4_MASK)
9911 #define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_5_MASK (0x3FF00000U)
9912 #define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_5_SHIFT (20U)
9913 #define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_5(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_5_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_5_MASK)
9914 
9915 /*! @name LNA_GAIN_LIN_VAL_8_6 - LNA Linear Gain Values 8..6 */
9916 #define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_6_MASK (0x3FFU)
9917 #define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_6_SHIFT (0U)
9918 #define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_6(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_6_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_6_MASK)
9919 #define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_7_MASK (0xFFC00U)
9920 #define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_7_SHIFT (10U)
9921 #define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_7(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_7_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_7_MASK)
9922 #define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_8_MASK (0x3FF00000U)
9923 #define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_8_SHIFT (20U)
9924 #define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_8(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_8_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_8_MASK)
9925 
9926 /*! @name LNA_GAIN_LIN_VAL_9 - LNA Linear Gain Values 9 */
9927 #define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_9_LNA_GAIN_LIN_VAL_9_MASK (0x3FFU)
9928 #define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_9_LNA_GAIN_LIN_VAL_9_SHIFT (0U)
9929 #define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_9_LNA_GAIN_LIN_VAL_9(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_LIN_VAL_9_LNA_GAIN_LIN_VAL_9_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_LIN_VAL_9_LNA_GAIN_LIN_VAL_9_MASK)
9930 
9931 /*! @name BBA_RES_TUNE_LIN_VAL_3_0 - BBA Resistor Tune Values 3..0 */
9932 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_0_MASK (0xFFU)
9933 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_0_SHIFT (0U)
9934 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_0_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_0_MASK)
9935 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_1_MASK (0xFF00U)
9936 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_1_SHIFT (8U)
9937 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_1_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_1_MASK)
9938 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_2_MASK (0xFF0000U)
9939 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_2_SHIFT (16U)
9940 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_2_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_2_MASK)
9941 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_3_MASK (0xFF000000U)
9942 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_3_SHIFT (24U)
9943 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_3_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_3_MASK)
9944 
9945 /*! @name BBA_RES_TUNE_LIN_VAL_7_4 - BBA Resistor Tune Values 7..4 */
9946 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_4_MASK (0xFFU)
9947 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_4_SHIFT (0U)
9948 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_4_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_4_MASK)
9949 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_5_MASK (0xFF00U)
9950 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_5_SHIFT (8U)
9951 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_5(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_5_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_5_MASK)
9952 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_6_MASK (0xFF0000U)
9953 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_6_SHIFT (16U)
9954 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_6(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_6_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_6_MASK)
9955 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_7_MASK (0xFF000000U)
9956 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_7_SHIFT (24U)
9957 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_7(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_7_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_7_MASK)
9958 
9959 /*! @name BBA_RES_TUNE_LIN_VAL_10_8 - BBA Resistor Tune Values 10..8 */
9960 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_8_MASK (0x3FFU)
9961 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_8_SHIFT (0U)
9962 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_8(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_8_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_8_MASK)
9963 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_9_MASK (0xFFC00U)
9964 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_9_SHIFT (10U)
9965 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_9(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_9_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_9_MASK)
9966 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_10_MASK (0x3FF00000U)
9967 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_10_SHIFT (20U)
9968 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_10(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_10_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_10_MASK)
9969 
9970 /*! @name AGC_GAIN_TBL_03_00 - AGC Gain Tables Step 03..00 */
9971 #define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_00_MASK (0xFU)
9972 #define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_00_SHIFT (0U)
9973 #define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_00(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_00_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_00_MASK)
9974 #define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_00_MASK (0xF0U)
9975 #define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_00_SHIFT (4U)
9976 #define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_00(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_00_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_00_MASK)
9977 #define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_01_MASK (0xF00U)
9978 #define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_01_SHIFT (8U)
9979 #define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_01(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_01_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_01_MASK)
9980 #define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_01_MASK (0xF000U)
9981 #define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_01_SHIFT (12U)
9982 #define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_01(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_01_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_01_MASK)
9983 #define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_02_MASK (0xF0000U)
9984 #define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_02_SHIFT (16U)
9985 #define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_02(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_02_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_02_MASK)
9986 #define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_02_MASK (0xF00000U)
9987 #define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_02_SHIFT (20U)
9988 #define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_02(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_02_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_02_MASK)
9989 #define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_03_MASK (0xF000000U)
9990 #define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_03_SHIFT (24U)
9991 #define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_03(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_03_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_03_MASK)
9992 #define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_03_MASK (0xF0000000U)
9993 #define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_03_SHIFT (28U)
9994 #define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_03(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_03_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_03_MASK)
9995 
9996 /*! @name AGC_GAIN_TBL_07_04 - AGC Gain Tables Step 07..04 */
9997 #define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_04_MASK (0xFU)
9998 #define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_04_SHIFT (0U)
9999 #define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_04(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_04_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_04_MASK)
10000 #define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_04_MASK (0xF0U)
10001 #define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_04_SHIFT (4U)
10002 #define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_04(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_04_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_04_MASK)
10003 #define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_05_MASK (0xF00U)
10004 #define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_05_SHIFT (8U)
10005 #define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_05(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_05_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_05_MASK)
10006 #define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_05_MASK (0xF000U)
10007 #define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_05_SHIFT (12U)
10008 #define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_05(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_05_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_05_MASK)
10009 #define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_06_MASK (0xF0000U)
10010 #define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_06_SHIFT (16U)
10011 #define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_06(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_06_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_06_MASK)
10012 #define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_06_MASK (0xF00000U)
10013 #define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_06_SHIFT (20U)
10014 #define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_06(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_06_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_06_MASK)
10015 #define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_07_MASK (0xF000000U)
10016 #define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_07_SHIFT (24U)
10017 #define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_07(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_07_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_07_MASK)
10018 #define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_07_MASK (0xF0000000U)
10019 #define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_07_SHIFT (28U)
10020 #define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_07(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_07_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_07_MASK)
10021 
10022 /*! @name AGC_GAIN_TBL_11_08 - AGC Gain Tables Step 11..08 */
10023 #define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_08_MASK (0xFU)
10024 #define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_08_SHIFT (0U)
10025 #define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_08(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_08_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_08_MASK)
10026 #define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_08_MASK (0xF0U)
10027 #define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_08_SHIFT (4U)
10028 #define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_08(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_08_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_08_MASK)
10029 #define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_09_MASK (0xF00U)
10030 #define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_09_SHIFT (8U)
10031 #define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_09(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_09_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_09_MASK)
10032 #define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_09_MASK (0xF000U)
10033 #define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_09_SHIFT (12U)
10034 #define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_09(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_09_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_09_MASK)
10035 #define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_10_MASK (0xF0000U)
10036 #define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_10_SHIFT (16U)
10037 #define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_10(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_10_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_10_MASK)
10038 #define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_10_MASK (0xF00000U)
10039 #define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_10_SHIFT (20U)
10040 #define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_10(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_10_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_10_MASK)
10041 #define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_11_MASK (0xF000000U)
10042 #define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_11_SHIFT (24U)
10043 #define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_11(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_11_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_11_MASK)
10044 #define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_11_MASK (0xF0000000U)
10045 #define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_11_SHIFT (28U)
10046 #define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_11(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_11_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_11_MASK)
10047 
10048 /*! @name AGC_GAIN_TBL_15_12 - AGC Gain Tables Step 15..12 */
10049 #define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_12_MASK (0xFU)
10050 #define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_12_SHIFT (0U)
10051 #define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_12(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_12_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_12_MASK)
10052 #define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_12_MASK (0xF0U)
10053 #define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_12_SHIFT (4U)
10054 #define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_12(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_12_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_12_MASK)
10055 #define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_13_MASK (0xF00U)
10056 #define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_13_SHIFT (8U)
10057 #define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_13(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_13_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_13_MASK)
10058 #define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_13_MASK (0xF000U)
10059 #define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_13_SHIFT (12U)
10060 #define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_13(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_13_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_13_MASK)
10061 #define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_14_MASK (0xF0000U)
10062 #define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_14_SHIFT (16U)
10063 #define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_14(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_14_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_14_MASK)
10064 #define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_14_MASK (0xF00000U)
10065 #define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_14_SHIFT (20U)
10066 #define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_14(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_14_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_14_MASK)
10067 #define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_15_MASK (0xF000000U)
10068 #define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_15_SHIFT (24U)
10069 #define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_15(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_15_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_15_MASK)
10070 #define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_15_MASK (0xF0000000U)
10071 #define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_15_SHIFT (28U)
10072 #define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_15(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_15_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_15_MASK)
10073 
10074 /*! @name AGC_GAIN_TBL_19_16 - AGC Gain Tables Step 19..16 */
10075 #define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_16_MASK (0xFU)
10076 #define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_16_SHIFT (0U)
10077 #define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_16(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_16_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_16_MASK)
10078 #define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_16_MASK (0xF0U)
10079 #define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_16_SHIFT (4U)
10080 #define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_16(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_16_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_16_MASK)
10081 #define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_17_MASK (0xF00U)
10082 #define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_17_SHIFT (8U)
10083 #define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_17(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_17_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_17_MASK)
10084 #define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_17_MASK (0xF000U)
10085 #define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_17_SHIFT (12U)
10086 #define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_17(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_17_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_17_MASK)
10087 #define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_18_MASK (0xF0000U)
10088 #define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_18_SHIFT (16U)
10089 #define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_18(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_18_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_18_MASK)
10090 #define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_18_MASK (0xF00000U)
10091 #define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_18_SHIFT (20U)
10092 #define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_18(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_18_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_18_MASK)
10093 #define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_19_MASK (0xF000000U)
10094 #define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_19_SHIFT (24U)
10095 #define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_19(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_19_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_19_MASK)
10096 #define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_19_MASK (0xF0000000U)
10097 #define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_19_SHIFT (28U)
10098 #define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_19(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_19_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_19_MASK)
10099 
10100 /*! @name AGC_GAIN_TBL_23_20 - AGC Gain Tables Step 23..20 */
10101 #define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_20_MASK (0xFU)
10102 #define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_20_SHIFT (0U)
10103 #define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_20(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_20_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_20_MASK)
10104 #define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_20_MASK (0xF0U)
10105 #define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_20_SHIFT (4U)
10106 #define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_20(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_20_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_20_MASK)
10107 #define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_21_MASK (0xF00U)
10108 #define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_21_SHIFT (8U)
10109 #define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_21(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_21_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_21_MASK)
10110 #define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_21_MASK (0xF000U)
10111 #define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_21_SHIFT (12U)
10112 #define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_21(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_21_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_21_MASK)
10113 #define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_22_MASK (0xF0000U)
10114 #define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_22_SHIFT (16U)
10115 #define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_22(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_22_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_22_MASK)
10116 #define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_22_MASK (0xF00000U)
10117 #define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_22_SHIFT (20U)
10118 #define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_22(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_22_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_22_MASK)
10119 #define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_23_MASK (0xF000000U)
10120 #define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_23_SHIFT (24U)
10121 #define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_23(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_23_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_23_MASK)
10122 #define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_23_MASK (0xF0000000U)
10123 #define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_23_SHIFT (28U)
10124 #define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_23(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_23_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_23_MASK)
10125 
10126 /*! @name AGC_GAIN_TBL_26_24 - AGC Gain Tables Step 26..24 */
10127 #define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_24_MASK (0xFU)
10128 #define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_24_SHIFT (0U)
10129 #define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_24(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_24_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_24_MASK)
10130 #define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_24_MASK (0xF0U)
10131 #define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_24_SHIFT (4U)
10132 #define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_24(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_24_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_24_MASK)
10133 #define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_25_MASK (0xF00U)
10134 #define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_25_SHIFT (8U)
10135 #define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_25(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_25_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_25_MASK)
10136 #define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_25_MASK (0xF000U)
10137 #define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_25_SHIFT (12U)
10138 #define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_25(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_25_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_25_MASK)
10139 #define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_26_MASK (0xF0000U)
10140 #define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_26_SHIFT (16U)
10141 #define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_26(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_26_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_26_MASK)
10142 #define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_26_MASK (0xF00000U)
10143 #define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_26_SHIFT (20U)
10144 #define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_26(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_26_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_26_MASK)
10145 
10146 /*! @name DCOC_OFFSET - DCOC Offset */
10147 #define XCVR_RX_DIG_DCOC_OFFSET_DCOC_BBA_OFFSET_I_MASK (0x3FU)
10148 #define XCVR_RX_DIG_DCOC_OFFSET_DCOC_BBA_OFFSET_I_SHIFT (0U)
10149 #define XCVR_RX_DIG_DCOC_OFFSET_DCOC_BBA_OFFSET_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_OFFSET_DCOC_BBA_OFFSET_I_SHIFT)) & XCVR_RX_DIG_DCOC_OFFSET_DCOC_BBA_OFFSET_I_MASK)
10150 #define XCVR_RX_DIG_DCOC_OFFSET_DCOC_BBA_OFFSET_Q_MASK (0x3F00U)
10151 #define XCVR_RX_DIG_DCOC_OFFSET_DCOC_BBA_OFFSET_Q_SHIFT (8U)
10152 #define XCVR_RX_DIG_DCOC_OFFSET_DCOC_BBA_OFFSET_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_OFFSET_DCOC_BBA_OFFSET_Q_SHIFT)) & XCVR_RX_DIG_DCOC_OFFSET_DCOC_BBA_OFFSET_Q_MASK)
10153 #define XCVR_RX_DIG_DCOC_OFFSET_DCOC_TZA_OFFSET_I_MASK (0xFF0000U)
10154 #define XCVR_RX_DIG_DCOC_OFFSET_DCOC_TZA_OFFSET_I_SHIFT (16U)
10155 #define XCVR_RX_DIG_DCOC_OFFSET_DCOC_TZA_OFFSET_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_OFFSET_DCOC_TZA_OFFSET_I_SHIFT)) & XCVR_RX_DIG_DCOC_OFFSET_DCOC_TZA_OFFSET_I_MASK)
10156 #define XCVR_RX_DIG_DCOC_OFFSET_DCOC_TZA_OFFSET_Q_MASK (0xFF000000U)
10157 #define XCVR_RX_DIG_DCOC_OFFSET_DCOC_TZA_OFFSET_Q_SHIFT (24U)
10158 #define XCVR_RX_DIG_DCOC_OFFSET_DCOC_TZA_OFFSET_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_OFFSET_DCOC_TZA_OFFSET_Q_SHIFT)) & XCVR_RX_DIG_DCOC_OFFSET_DCOC_TZA_OFFSET_Q_MASK)
10159 
10160 /* The count of XCVR_RX_DIG_DCOC_OFFSET */
10161 #define XCVR_RX_DIG_DCOC_OFFSET_COUNT            (27U)
10162 
10163 /*! @name DCOC_BBA_STEP - DCOC BBA DAC Step */
10164 #define XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_RECIP_MASK (0x1FFFU)
10165 #define XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_RECIP_SHIFT (0U)
10166 #define XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_RECIP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_RECIP_SHIFT)) & XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_RECIP_MASK)
10167 #define XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_MASK (0x1FF0000U)
10168 #define XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_SHIFT (16U)
10169 #define XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_SHIFT)) & XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_MASK)
10170 
10171 /*! @name DCOC_TZA_STEP_0 - DCOC TZA DAC Step 0 */
10172 #define XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_RCP_0_MASK (0x1FFFU)
10173 #define XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_RCP_0_SHIFT (0U)
10174 #define XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_RCP_0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_RCP_0_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_RCP_0_MASK)
10175 #define XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0_MASK (0xFFF0000U)
10176 #define XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0_SHIFT (16U)
10177 #define XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0_MASK)
10178 
10179 /*! @name DCOC_TZA_STEP_1 - DCOC TZA DAC Step 1 */
10180 #define XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_RCP_1_MASK (0x1FFFU)
10181 #define XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_RCP_1_SHIFT (0U)
10182 #define XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_RCP_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_RCP_1_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_RCP_1_MASK)
10183 #define XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_GAIN_1_MASK (0xFFF0000U)
10184 #define XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_GAIN_1_SHIFT (16U)
10185 #define XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_GAIN_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_GAIN_1_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_GAIN_1_MASK)
10186 
10187 /*! @name DCOC_TZA_STEP_2 - DCOC TZA DAC Step 2 */
10188 #define XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_RCP_2_MASK (0x1FFFU)
10189 #define XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_RCP_2_SHIFT (0U)
10190 #define XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_RCP_2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_RCP_2_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_RCP_2_MASK)
10191 #define XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_GAIN_2_MASK (0xFFF0000U)
10192 #define XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_GAIN_2_SHIFT (16U)
10193 #define XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_GAIN_2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_GAIN_2_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_GAIN_2_MASK)
10194 
10195 /*! @name DCOC_TZA_STEP_3 - DCOC TZA DAC Step 3 */
10196 #define XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_RCP_3_MASK (0x1FFFU)
10197 #define XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_RCP_3_SHIFT (0U)
10198 #define XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_RCP_3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_RCP_3_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_RCP_3_MASK)
10199 #define XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_GAIN_3_MASK (0xFFF0000U)
10200 #define XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_GAIN_3_SHIFT (16U)
10201 #define XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_GAIN_3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_GAIN_3_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_GAIN_3_MASK)
10202 
10203 /*! @name DCOC_TZA_STEP_4 - DCOC TZA DAC Step 4 */
10204 #define XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_RCP_4_MASK (0x1FFFU)
10205 #define XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_RCP_4_SHIFT (0U)
10206 #define XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_RCP_4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_RCP_4_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_RCP_4_MASK)
10207 #define XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_GAIN_4_MASK (0xFFF0000U)
10208 #define XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_GAIN_4_SHIFT (16U)
10209 #define XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_GAIN_4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_GAIN_4_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_GAIN_4_MASK)
10210 
10211 /*! @name DCOC_TZA_STEP_5 - DCOC TZA DAC Step 5 */
10212 #define XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_RCP_5_MASK (0x1FFFU)
10213 #define XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_RCP_5_SHIFT (0U)
10214 #define XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_RCP_5(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_RCP_5_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_RCP_5_MASK)
10215 #define XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_GAIN_5_MASK (0xFFF0000U)
10216 #define XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_GAIN_5_SHIFT (16U)
10217 #define XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_GAIN_5(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_GAIN_5_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_GAIN_5_MASK)
10218 
10219 /*! @name DCOC_TZA_STEP_6 - DCOC TZA DAC Step 6 */
10220 #define XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_RCP_6_MASK (0x1FFFU)
10221 #define XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_RCP_6_SHIFT (0U)
10222 #define XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_RCP_6(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_RCP_6_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_RCP_6_MASK)
10223 #define XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_GAIN_6_MASK (0xFFF0000U)
10224 #define XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_GAIN_6_SHIFT (16U)
10225 #define XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_GAIN_6(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_GAIN_6_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_GAIN_6_MASK)
10226 
10227 /*! @name DCOC_TZA_STEP_7 - DCOC TZA DAC Step 7 */
10228 #define XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_RCP_7_MASK (0x1FFFU)
10229 #define XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_RCP_7_SHIFT (0U)
10230 #define XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_RCP_7(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_RCP_7_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_RCP_7_MASK)
10231 #define XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_GAIN_7_MASK (0x1FFF0000U)
10232 #define XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_GAIN_7_SHIFT (16U)
10233 #define XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_GAIN_7(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_GAIN_7_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_GAIN_7_MASK)
10234 
10235 /*! @name DCOC_TZA_STEP_8 - DCOC TZA DAC Step 5 */
10236 #define XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_RCP_8_MASK (0x1FFFU)
10237 #define XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_RCP_8_SHIFT (0U)
10238 #define XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_RCP_8(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_RCP_8_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_RCP_8_MASK)
10239 #define XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_GAIN_8_MASK (0x1FFF0000U)
10240 #define XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_GAIN_8_SHIFT (16U)
10241 #define XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_GAIN_8(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_GAIN_8_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_GAIN_8_MASK)
10242 
10243 /*! @name DCOC_TZA_STEP_9 - DCOC TZA DAC Step 9 */
10244 #define XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_RCP_9_MASK (0x1FFFU)
10245 #define XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_RCP_9_SHIFT (0U)
10246 #define XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_RCP_9(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_RCP_9_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_RCP_9_MASK)
10247 #define XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_GAIN_9_MASK (0x3FFF0000U)
10248 #define XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_GAIN_9_SHIFT (16U)
10249 #define XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_GAIN_9(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_GAIN_9_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_GAIN_9_MASK)
10250 
10251 /*! @name DCOC_TZA_STEP_10 - DCOC TZA DAC Step 10 */
10252 #define XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_RCP_10_MASK (0x1FFFU)
10253 #define XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_RCP_10_SHIFT (0U)
10254 #define XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_RCP_10(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_RCP_10_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_RCP_10_MASK)
10255 #define XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_GAIN_10_MASK (0x3FFF0000U)
10256 #define XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_GAIN_10_SHIFT (16U)
10257 #define XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_GAIN_10(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_GAIN_10_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_GAIN_10_MASK)
10258 
10259 /*! @name DCOC_CAL_ALPHA - DCOC Calibration Alpha */
10260 #define XCVR_RX_DIG_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_I_MASK (0x7FFU)
10261 #define XCVR_RX_DIG_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_I_SHIFT (0U)
10262 #define XCVR_RX_DIG_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_I_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_I_MASK)
10263 #define XCVR_RX_DIG_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_Q_MASK (0x7FF0000U)
10264 #define XCVR_RX_DIG_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_Q_SHIFT (16U)
10265 #define XCVR_RX_DIG_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_Q_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_Q_MASK)
10266 
10267 /*! @name DCOC_CAL_BETA_Q - DCOC Calibration Beta Q */
10268 #define XCVR_RX_DIG_DCOC_CAL_BETA_Q_DCOC_CAL_BETA_Q_MASK (0x1FFFFU)
10269 #define XCVR_RX_DIG_DCOC_CAL_BETA_Q_DCOC_CAL_BETA_Q_SHIFT (0U)
10270 #define XCVR_RX_DIG_DCOC_CAL_BETA_Q_DCOC_CAL_BETA_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_BETA_Q_DCOC_CAL_BETA_Q_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_BETA_Q_DCOC_CAL_BETA_Q_MASK)
10271 
10272 /*! @name DCOC_CAL_BETA_I - DCOC Calibration Beta I */
10273 #define XCVR_RX_DIG_DCOC_CAL_BETA_I_DCOC_CAL_BETA_I_MASK (0x1FFFFU)
10274 #define XCVR_RX_DIG_DCOC_CAL_BETA_I_DCOC_CAL_BETA_I_SHIFT (0U)
10275 #define XCVR_RX_DIG_DCOC_CAL_BETA_I_DCOC_CAL_BETA_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_BETA_I_DCOC_CAL_BETA_I_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_BETA_I_DCOC_CAL_BETA_I_MASK)
10276 
10277 /*! @name DCOC_CAL_GAMMA - DCOC Calibration Gamma */
10278 #define XCVR_RX_DIG_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_I_MASK (0xFFFFU)
10279 #define XCVR_RX_DIG_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_I_SHIFT (0U)
10280 #define XCVR_RX_DIG_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_I_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_I_MASK)
10281 #define XCVR_RX_DIG_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_Q_MASK (0xFFFF0000U)
10282 #define XCVR_RX_DIG_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_Q_SHIFT (16U)
10283 #define XCVR_RX_DIG_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_Q_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_Q_MASK)
10284 
10285 /*! @name DCOC_CAL_IIR - DCOC Calibration IIR */
10286 #define XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX_MASK (0x3U)
10287 #define XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX_SHIFT (0U)
10288 #define XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX_MASK)
10289 #define XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX_MASK (0xCU)
10290 #define XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX_SHIFT (2U)
10291 #define XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX_MASK)
10292 #define XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX_MASK (0x30U)
10293 #define XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX_SHIFT (4U)
10294 #define XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX_MASK)
10295 
10296 /*! @name DCOC_CAL - DCOC Calibration Result */
10297 #define XCVR_RX_DIG_DCOC_CAL_DCOC_CAL_RES_I_MASK (0xFFFU)
10298 #define XCVR_RX_DIG_DCOC_CAL_DCOC_CAL_RES_I_SHIFT (0U)
10299 #define XCVR_RX_DIG_DCOC_CAL_DCOC_CAL_RES_I(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_DCOC_CAL_RES_I_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_DCOC_CAL_RES_I_MASK)
10300 #define XCVR_RX_DIG_DCOC_CAL_DCOC_CAL_RES_Q_MASK (0xFFF0000U)
10301 #define XCVR_RX_DIG_DCOC_CAL_DCOC_CAL_RES_Q_SHIFT (16U)
10302 #define XCVR_RX_DIG_DCOC_CAL_DCOC_CAL_RES_Q(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_DCOC_CAL_RES_Q_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_DCOC_CAL_RES_Q_MASK)
10303 
10304 /* The count of XCVR_RX_DIG_DCOC_CAL */
10305 #define XCVR_RX_DIG_DCOC_CAL_COUNT               (3U)
10306 
10307 /*! @name CCA_ED_LQI_CTRL_0 - RX_DIG CCA ED LQI Control Register 0 */
10308 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CORR_THRESH_MASK (0xFFU)
10309 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CORR_THRESH_SHIFT (0U)
10310 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CORR_THRESH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CORR_THRESH_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CORR_THRESH_MASK)
10311 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_CORR_CNTR_THRESH_MASK (0xFF00U)
10312 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_CORR_CNTR_THRESH_SHIFT (8U)
10313 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_CORR_CNTR_THRESH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_CORR_CNTR_THRESH_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_CORR_CNTR_THRESH_MASK)
10314 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CNTR_MASK (0xFF0000U)
10315 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CNTR_SHIFT (16U)
10316 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CNTR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CNTR_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CNTR_MASK)
10317 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_SNR_ADJ_MASK (0x3F000000U)
10318 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_SNR_ADJ_SHIFT (24U)
10319 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_SNR_ADJ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_SNR_ADJ_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_SNR_ADJ_MASK)
10320 
10321 /*! @name CCA_ED_LQI_CTRL_1 - RX_DIG CCA ED LQI Control Register 1 */
10322 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_DELAY_MASK (0x3FU)
10323 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_DELAY_SHIFT (0U)
10324 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_DELAY_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_DELAY_MASK)
10325 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_FACTOR_MASK (0x1C0U)
10326 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_FACTOR_SHIFT (6U)
10327 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_FACTOR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_FACTOR_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_FACTOR_MASK)
10328 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_WEIGHT_MASK (0xE00U)
10329 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_WEIGHT_SHIFT (9U)
10330 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_WEIGHT_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_WEIGHT_MASK)
10331 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_SENS_MASK (0xF000U)
10332 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_SENS_SHIFT (12U)
10333 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_SENS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_SENS_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_SENS_MASK)
10334 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_DIS_MASK (0x10000U)
10335 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_DIS_SHIFT (16U)
10336 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_DIS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_DIS_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_DIS_MASK)
10337 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SEL_SNR_MODE_MASK (0x20000U)
10338 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SEL_SNR_MODE_SHIFT (17U)
10339 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SEL_SNR_MODE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SEL_SNR_MODE_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SEL_SNR_MODE_MASK)
10340 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MEAS_TRANS_TO_IDLE_MASK (0x40000U)
10341 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MEAS_TRANS_TO_IDLE_SHIFT (18U)
10342 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MEAS_TRANS_TO_IDLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MEAS_TRANS_TO_IDLE_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MEAS_TRANS_TO_IDLE_MASK)
10343 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_CCA1_ED_EN_DIS_MASK (0x80000U)
10344 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_CCA1_ED_EN_DIS_SHIFT (19U)
10345 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_CCA1_ED_EN_DIS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_CCA1_ED_EN_DIS_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_CCA1_ED_EN_DIS_MASK)
10346 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MAN_MEAS_COMPLETE_MASK (0x100000U)
10347 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MAN_MEAS_COMPLETE_SHIFT (20U)
10348 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MAN_MEAS_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MAN_MEAS_COMPLETE_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MAN_MEAS_COMPLETE_MASK)
10349 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MAN_AA_MATCH_MASK (0x200000U)
10350 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MAN_AA_MATCH_SHIFT (21U)
10351 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MAN_AA_MATCH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MAN_AA_MATCH_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MAN_AA_MATCH_MASK)
10352 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_WEIGHT_MASK (0xF000000U)
10353 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_WEIGHT_SHIFT (24U)
10354 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_WEIGHT_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_WEIGHT_MASK)
10355 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_BIAS_MASK (0xF0000000U)
10356 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_BIAS_SHIFT (28U)
10357 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_BIAS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_BIAS_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_BIAS_MASK)
10358 
10359 /*! @name CCA_ED_LQI_STAT_0 - RX_DIG CCA ED LQI Status Register 0 */
10360 #define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_LQI_OUT_MASK (0xFFU)
10361 #define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_LQI_OUT_SHIFT (0U)
10362 #define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_LQI_OUT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_STAT_0_LQI_OUT_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_STAT_0_LQI_OUT_MASK)
10363 #define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_ED_OUT_MASK (0xFF00U)
10364 #define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_ED_OUT_SHIFT (8U)
10365 #define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_ED_OUT(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_STAT_0_ED_OUT_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_STAT_0_ED_OUT_MASK)
10366 #define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_SNR_OUT_MASK (0xFF0000U)
10367 #define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_SNR_OUT_SHIFT (16U)
10368 #define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_SNR_OUT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_STAT_0_SNR_OUT_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_STAT_0_SNR_OUT_MASK)
10369 #define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_CCA1_STATE_MASK (0x1000000U)
10370 #define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_CCA1_STATE_SHIFT (24U)
10371 #define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_CCA1_STATE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_STAT_0_CCA1_STATE_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_STAT_0_CCA1_STATE_MASK)
10372 #define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_MEAS_COMPLETE_MASK (0x2000000U)
10373 #define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_MEAS_COMPLETE_SHIFT (25U)
10374 #define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_MEAS_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_STAT_0_MEAS_COMPLETE_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_STAT_0_MEAS_COMPLETE_MASK)
10375 
10376 /*! @name RX_CHF_COEF_0 - Receive Channel Filter Coefficient 0 */
10377 #define XCVR_RX_DIG_RX_CHF_COEF_0_RX_CH_FILT_H0_MASK (0x3FU)
10378 #define XCVR_RX_DIG_RX_CHF_COEF_0_RX_CH_FILT_H0_SHIFT (0U)
10379 #define XCVR_RX_DIG_RX_CHF_COEF_0_RX_CH_FILT_H0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_CHF_COEF_0_RX_CH_FILT_H0_SHIFT)) & XCVR_RX_DIG_RX_CHF_COEF_0_RX_CH_FILT_H0_MASK)
10380 
10381 /*! @name RX_CHF_COEF_1 - Receive Channel Filter Coefficient 1 */
10382 #define XCVR_RX_DIG_RX_CHF_COEF_1_RX_CH_FILT_H1_MASK (0x3FU)
10383 #define XCVR_RX_DIG_RX_CHF_COEF_1_RX_CH_FILT_H1_SHIFT (0U)
10384 #define XCVR_RX_DIG_RX_CHF_COEF_1_RX_CH_FILT_H1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_CHF_COEF_1_RX_CH_FILT_H1_SHIFT)) & XCVR_RX_DIG_RX_CHF_COEF_1_RX_CH_FILT_H1_MASK)
10385 
10386 /*! @name RX_CHF_COEF_2 - Receive Channel Filter Coefficient 2 */
10387 #define XCVR_RX_DIG_RX_CHF_COEF_2_RX_CH_FILT_H2_MASK (0x7FU)
10388 #define XCVR_RX_DIG_RX_CHF_COEF_2_RX_CH_FILT_H2_SHIFT (0U)
10389 #define XCVR_RX_DIG_RX_CHF_COEF_2_RX_CH_FILT_H2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_CHF_COEF_2_RX_CH_FILT_H2_SHIFT)) & XCVR_RX_DIG_RX_CHF_COEF_2_RX_CH_FILT_H2_MASK)
10390 
10391 /*! @name RX_CHF_COEF_3 - Receive Channel Filter Coefficient 3 */
10392 #define XCVR_RX_DIG_RX_CHF_COEF_3_RX_CH_FILT_H3_MASK (0x7FU)
10393 #define XCVR_RX_DIG_RX_CHF_COEF_3_RX_CH_FILT_H3_SHIFT (0U)
10394 #define XCVR_RX_DIG_RX_CHF_COEF_3_RX_CH_FILT_H3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_CHF_COEF_3_RX_CH_FILT_H3_SHIFT)) & XCVR_RX_DIG_RX_CHF_COEF_3_RX_CH_FILT_H3_MASK)
10395 
10396 /*! @name RX_CHF_COEF_4 - Receive Channel Filter Coefficient 4 */
10397 #define XCVR_RX_DIG_RX_CHF_COEF_4_RX_CH_FILT_H4_MASK (0x7FU)
10398 #define XCVR_RX_DIG_RX_CHF_COEF_4_RX_CH_FILT_H4_SHIFT (0U)
10399 #define XCVR_RX_DIG_RX_CHF_COEF_4_RX_CH_FILT_H4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_CHF_COEF_4_RX_CH_FILT_H4_SHIFT)) & XCVR_RX_DIG_RX_CHF_COEF_4_RX_CH_FILT_H4_MASK)
10400 
10401 /*! @name RX_CHF_COEF_5 - Receive Channel Filter Coefficient 5 */
10402 #define XCVR_RX_DIG_RX_CHF_COEF_5_RX_CH_FILT_H5_MASK (0x7FU)
10403 #define XCVR_RX_DIG_RX_CHF_COEF_5_RX_CH_FILT_H5_SHIFT (0U)
10404 #define XCVR_RX_DIG_RX_CHF_COEF_5_RX_CH_FILT_H5(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_CHF_COEF_5_RX_CH_FILT_H5_SHIFT)) & XCVR_RX_DIG_RX_CHF_COEF_5_RX_CH_FILT_H5_MASK)
10405 
10406 /*! @name RX_CHF_COEF_6 - Receive Channel Filter Coefficient 6 */
10407 #define XCVR_RX_DIG_RX_CHF_COEF_6_RX_CH_FILT_H6_MASK (0xFFU)
10408 #define XCVR_RX_DIG_RX_CHF_COEF_6_RX_CH_FILT_H6_SHIFT (0U)
10409 #define XCVR_RX_DIG_RX_CHF_COEF_6_RX_CH_FILT_H6(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_CHF_COEF_6_RX_CH_FILT_H6_SHIFT)) & XCVR_RX_DIG_RX_CHF_COEF_6_RX_CH_FILT_H6_MASK)
10410 
10411 /*! @name RX_CHF_COEF_7 - Receive Channel Filter Coefficient 7 */
10412 #define XCVR_RX_DIG_RX_CHF_COEF_7_RX_CH_FILT_H7_MASK (0xFFU)
10413 #define XCVR_RX_DIG_RX_CHF_COEF_7_RX_CH_FILT_H7_SHIFT (0U)
10414 #define XCVR_RX_DIG_RX_CHF_COEF_7_RX_CH_FILT_H7(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_CHF_COEF_7_RX_CH_FILT_H7_SHIFT)) & XCVR_RX_DIG_RX_CHF_COEF_7_RX_CH_FILT_H7_MASK)
10415 
10416 /*! @name RX_CHF_COEF_8 - Receive Channel Filter Coefficient 8 */
10417 #define XCVR_RX_DIG_RX_CHF_COEF_8_RX_CH_FILT_H8_MASK (0x1FFU)
10418 #define XCVR_RX_DIG_RX_CHF_COEF_8_RX_CH_FILT_H8_SHIFT (0U)
10419 #define XCVR_RX_DIG_RX_CHF_COEF_8_RX_CH_FILT_H8(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_CHF_COEF_8_RX_CH_FILT_H8_SHIFT)) & XCVR_RX_DIG_RX_CHF_COEF_8_RX_CH_FILT_H8_MASK)
10420 
10421 /*! @name RX_CHF_COEF_9 - Receive Channel Filter Coefficient 9 */
10422 #define XCVR_RX_DIG_RX_CHF_COEF_9_RX_CH_FILT_H9_MASK (0x1FFU)
10423 #define XCVR_RX_DIG_RX_CHF_COEF_9_RX_CH_FILT_H9_SHIFT (0U)
10424 #define XCVR_RX_DIG_RX_CHF_COEF_9_RX_CH_FILT_H9(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_CHF_COEF_9_RX_CH_FILT_H9_SHIFT)) & XCVR_RX_DIG_RX_CHF_COEF_9_RX_CH_FILT_H9_MASK)
10425 
10426 /*! @name RX_CHF_COEF_10 - Receive Channel Filter Coefficient 10 */
10427 #define XCVR_RX_DIG_RX_CHF_COEF_10_RX_CH_FILT_H10_MASK (0x3FFU)
10428 #define XCVR_RX_DIG_RX_CHF_COEF_10_RX_CH_FILT_H10_SHIFT (0U)
10429 #define XCVR_RX_DIG_RX_CHF_COEF_10_RX_CH_FILT_H10(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_CHF_COEF_10_RX_CH_FILT_H10_SHIFT)) & XCVR_RX_DIG_RX_CHF_COEF_10_RX_CH_FILT_H10_MASK)
10430 
10431 /*! @name RX_CHF_COEF_11 - Receive Channel Filter Coefficient 11 */
10432 #define XCVR_RX_DIG_RX_CHF_COEF_11_RX_CH_FILT_H11_MASK (0x3FFU)
10433 #define XCVR_RX_DIG_RX_CHF_COEF_11_RX_CH_FILT_H11_SHIFT (0U)
10434 #define XCVR_RX_DIG_RX_CHF_COEF_11_RX_CH_FILT_H11(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_CHF_COEF_11_RX_CH_FILT_H11_SHIFT)) & XCVR_RX_DIG_RX_CHF_COEF_11_RX_CH_FILT_H11_MASK)
10435 
10436 /*! @name AGC_MAN_AGC_IDX - AGC Manual AGC Index */
10437 #define XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_MAN_IDX_MASK (0x1F0000U)
10438 #define XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_MAN_IDX_SHIFT (16U)
10439 #define XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_MAN_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_MAN_IDX_SHIFT)) & XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_MAN_IDX_MASK)
10440 #define XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_MAN_IDX_EN_MASK (0x1000000U)
10441 #define XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_MAN_IDX_EN_SHIFT (24U)
10442 #define XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_MAN_IDX_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_MAN_IDX_EN_SHIFT)) & XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_MAN_IDX_EN_MASK)
10443 #define XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_DCOC_START_PT_MASK (0x2000000U)
10444 #define XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_DCOC_START_PT_SHIFT (25U)
10445 #define XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_DCOC_START_PT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_DCOC_START_PT_SHIFT)) & XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_DCOC_START_PT_MASK)
10446 
10447 /*! @name DC_RESID_CTRL - DC Residual Control */
10448 #define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN_MASK (0x7FU)
10449 #define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN_SHIFT (0U)
10450 #define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN_SHIFT)) & XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN_MASK)
10451 #define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ITER_FREEZE_MASK (0xF00U)
10452 #define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ITER_FREEZE_SHIFT (8U)
10453 #define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ITER_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ITER_FREEZE_SHIFT)) & XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ITER_FREEZE_MASK)
10454 #define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ALPHA_MASK (0x7000U)
10455 #define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ALPHA_SHIFT (12U)
10456 #define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ALPHA_SHIFT)) & XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ALPHA_MASK)
10457 #define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY_MASK (0x70000U)
10458 #define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY_SHIFT (16U)
10459 #define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY_SHIFT)) & XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY_MASK)
10460 #define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_EXT_DC_EN_MASK (0x100000U)
10461 #define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_EXT_DC_EN_SHIFT (20U)
10462 #define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_EXT_DC_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_EXT_DC_EN_SHIFT)) & XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_EXT_DC_EN_MASK)
10463 #define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_MIN_AGC_IDX_MASK (0x1F000000U)
10464 #define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_MIN_AGC_IDX_SHIFT (24U)
10465 #define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_MIN_AGC_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_MIN_AGC_IDX_SHIFT)) & XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_MIN_AGC_IDX_MASK)
10466 
10467 /*! @name DC_RESID_EST - DC Residual Estimate */
10468 #define XCVR_RX_DIG_DC_RESID_EST_DC_RESID_OFFSET_I_MASK (0x1FFFU)
10469 #define XCVR_RX_DIG_DC_RESID_EST_DC_RESID_OFFSET_I_SHIFT (0U)
10470 #define XCVR_RX_DIG_DC_RESID_EST_DC_RESID_OFFSET_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_EST_DC_RESID_OFFSET_I_SHIFT)) & XCVR_RX_DIG_DC_RESID_EST_DC_RESID_OFFSET_I_MASK)
10471 #define XCVR_RX_DIG_DC_RESID_EST_DC_RESID_OFFSET_Q_MASK (0x1FFF0000U)
10472 #define XCVR_RX_DIG_DC_RESID_EST_DC_RESID_OFFSET_Q_SHIFT (16U)
10473 #define XCVR_RX_DIG_DC_RESID_EST_DC_RESID_OFFSET_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_EST_DC_RESID_OFFSET_Q_SHIFT)) & XCVR_RX_DIG_DC_RESID_EST_DC_RESID_OFFSET_Q_MASK)
10474 
10475 /*! @name RX_RCCAL_CTRL0 - RX RC Calibration Control0 */
10476 #define XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET_MASK (0xFU)
10477 #define XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET_SHIFT (0U)
10478 #define XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET_MASK)
10479 #define XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL_MASK (0x1F0U)
10480 #define XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL_SHIFT (4U)
10481 #define XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL_MASK)
10482 #define XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS_MASK (0x200U)
10483 #define XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS_SHIFT (9U)
10484 #define XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS_MASK)
10485 #define XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY_MASK (0x3000U)
10486 #define XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY_SHIFT (12U)
10487 #define XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY_MASK)
10488 #define XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV_MASK (0x8000U)
10489 #define XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV_SHIFT (15U)
10490 #define XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV_MASK)
10491 #define XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET_MASK (0xF0000U)
10492 #define XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET_SHIFT (16U)
10493 #define XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET_MASK)
10494 #define XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL_MASK (0x1F00000U)
10495 #define XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL_SHIFT (20U)
10496 #define XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL_MASK)
10497 #define XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS_MASK (0x2000000U)
10498 #define XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS_SHIFT (25U)
10499 #define XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS_MASK)
10500 
10501 /*! @name RX_RCCAL_CTRL1 - RX RC Calibration Control1 */
10502 #define XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET_MASK (0xFU)
10503 #define XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET_SHIFT (0U)
10504 #define XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET_MASK)
10505 #define XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL_MASK (0x1F0U)
10506 #define XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL_SHIFT (4U)
10507 #define XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL_MASK)
10508 #define XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS_MASK (0x200U)
10509 #define XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS_SHIFT (9U)
10510 #define XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS_MASK)
10511 #define XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET_MASK (0xF0000U)
10512 #define XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET_SHIFT (16U)
10513 #define XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET_MASK)
10514 #define XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL_MASK (0x1F00000U)
10515 #define XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL_SHIFT (20U)
10516 #define XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL_MASK)
10517 #define XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS_MASK (0x2000000U)
10518 #define XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS_SHIFT (25U)
10519 #define XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS_MASK)
10520 
10521 /*! @name RX_RCCAL_STAT - RX RC Calibration Status */
10522 #define XCVR_RX_DIG_RX_RCCAL_STAT_RCCAL_CODE_MASK (0x1FU)
10523 #define XCVR_RX_DIG_RX_RCCAL_STAT_RCCAL_CODE_SHIFT (0U)
10524 #define XCVR_RX_DIG_RX_RCCAL_STAT_RCCAL_CODE(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_STAT_RCCAL_CODE_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_STAT_RCCAL_CODE_MASK)
10525 #define XCVR_RX_DIG_RX_RCCAL_STAT_ADC_RCCAL_MASK (0x3E0U)
10526 #define XCVR_RX_DIG_RX_RCCAL_STAT_ADC_RCCAL_SHIFT (5U)
10527 #define XCVR_RX_DIG_RX_RCCAL_STAT_ADC_RCCAL(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_STAT_ADC_RCCAL_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_STAT_ADC_RCCAL_MASK)
10528 #define XCVR_RX_DIG_RX_RCCAL_STAT_BBA2_RCCAL_MASK (0x7C00U)
10529 #define XCVR_RX_DIG_RX_RCCAL_STAT_BBA2_RCCAL_SHIFT (10U)
10530 #define XCVR_RX_DIG_RX_RCCAL_STAT_BBA2_RCCAL(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_STAT_BBA2_RCCAL_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_STAT_BBA2_RCCAL_MASK)
10531 #define XCVR_RX_DIG_RX_RCCAL_STAT_BBA_RCCAL_MASK (0x1F0000U)
10532 #define XCVR_RX_DIG_RX_RCCAL_STAT_BBA_RCCAL_SHIFT (16U)
10533 #define XCVR_RX_DIG_RX_RCCAL_STAT_BBA_RCCAL(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_STAT_BBA_RCCAL_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_STAT_BBA_RCCAL_MASK)
10534 #define XCVR_RX_DIG_RX_RCCAL_STAT_TZA_RCCAL_MASK (0x3E00000U)
10535 #define XCVR_RX_DIG_RX_RCCAL_STAT_TZA_RCCAL_SHIFT (21U)
10536 #define XCVR_RX_DIG_RX_RCCAL_STAT_TZA_RCCAL(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_STAT_TZA_RCCAL_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_STAT_TZA_RCCAL_MASK)
10537 
10538 /*! @name AUXPLL_FCAL_CTRL - Aux PLL Frequency Calibration Control */
10539 #define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_DAC_CAL_ADJUST_MANUAL_MASK (0x7FU)
10540 #define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_DAC_CAL_ADJUST_MANUAL_SHIFT (0U)
10541 #define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_DAC_CAL_ADJUST_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CTRL_DAC_CAL_ADJUST_MANUAL_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CTRL_DAC_CAL_ADJUST_MANUAL_MASK)
10542 #define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_AUXPLL_DAC_CAL_ADJUST_DIS_MASK (0x80U)
10543 #define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_AUXPLL_DAC_CAL_ADJUST_DIS_SHIFT (7U)
10544 #define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_AUXPLL_DAC_CAL_ADJUST_DIS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CTRL_AUXPLL_DAC_CAL_ADJUST_DIS_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CTRL_AUXPLL_DAC_CAL_ADJUST_DIS_MASK)
10545 #define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_RUN_CNT_MASK (0x100U)
10546 #define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_RUN_CNT_SHIFT (8U)
10547 #define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_RUN_CNT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_RUN_CNT_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_RUN_CNT_MASK)
10548 #define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_COMP_INV_MASK (0x200U)
10549 #define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_COMP_INV_SHIFT (9U)
10550 #define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_COMP_INV(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_COMP_INV_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_COMP_INV_MASK)
10551 #define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_SMP_DLY_MASK (0xC00U)
10552 #define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_SMP_DLY_SHIFT (10U)
10553 #define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_SMP_DLY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_SMP_DLY_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_SMP_DLY_MASK)
10554 #define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_DAC_CAL_ADJUST_MASK (0x7F0000U)
10555 #define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_DAC_CAL_ADJUST_SHIFT (16U)
10556 #define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_DAC_CAL_ADJUST(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CTRL_DAC_CAL_ADJUST_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CTRL_DAC_CAL_ADJUST_MASK)
10557 
10558 /*! @name AUXPLL_FCAL_CNT6 - Aux PLL Frequency Calibration Count 6 */
10559 #define XCVR_RX_DIG_AUXPLL_FCAL_CNT6_FCAL_COUNT_6_MASK (0x3FFU)
10560 #define XCVR_RX_DIG_AUXPLL_FCAL_CNT6_FCAL_COUNT_6_SHIFT (0U)
10561 #define XCVR_RX_DIG_AUXPLL_FCAL_CNT6_FCAL_COUNT_6(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CNT6_FCAL_COUNT_6_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CNT6_FCAL_COUNT_6_MASK)
10562 #define XCVR_RX_DIG_AUXPLL_FCAL_CNT6_FCAL_BESTDIFF_MASK (0x3FF0000U)
10563 #define XCVR_RX_DIG_AUXPLL_FCAL_CNT6_FCAL_BESTDIFF_SHIFT (16U)
10564 #define XCVR_RX_DIG_AUXPLL_FCAL_CNT6_FCAL_BESTDIFF(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CNT6_FCAL_BESTDIFF_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CNT6_FCAL_BESTDIFF_MASK)
10565 
10566 /*! @name AUXPLL_FCAL_CNT5_4 - Aux PLL Frequency Calibration Count 5 and 4 */
10567 #define XCVR_RX_DIG_AUXPLL_FCAL_CNT5_4_FCAL_COUNT_4_MASK (0x3FFU)
10568 #define XCVR_RX_DIG_AUXPLL_FCAL_CNT5_4_FCAL_COUNT_4_SHIFT (0U)
10569 #define XCVR_RX_DIG_AUXPLL_FCAL_CNT5_4_FCAL_COUNT_4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CNT5_4_FCAL_COUNT_4_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CNT5_4_FCAL_COUNT_4_MASK)
10570 #define XCVR_RX_DIG_AUXPLL_FCAL_CNT5_4_FCAL_COUNT_5_MASK (0x3FF0000U)
10571 #define XCVR_RX_DIG_AUXPLL_FCAL_CNT5_4_FCAL_COUNT_5_SHIFT (16U)
10572 #define XCVR_RX_DIG_AUXPLL_FCAL_CNT5_4_FCAL_COUNT_5(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CNT5_4_FCAL_COUNT_5_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CNT5_4_FCAL_COUNT_5_MASK)
10573 
10574 /*! @name AUXPLL_FCAL_CNT3_2 - Aux PLL Frequency Calibration Count 3 and 2 */
10575 #define XCVR_RX_DIG_AUXPLL_FCAL_CNT3_2_FCAL_COUNT_2_MASK (0x3FFU)
10576 #define XCVR_RX_DIG_AUXPLL_FCAL_CNT3_2_FCAL_COUNT_2_SHIFT (0U)
10577 #define XCVR_RX_DIG_AUXPLL_FCAL_CNT3_2_FCAL_COUNT_2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CNT3_2_FCAL_COUNT_2_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CNT3_2_FCAL_COUNT_2_MASK)
10578 #define XCVR_RX_DIG_AUXPLL_FCAL_CNT3_2_FCAL_COUNT_3_MASK (0x3FF0000U)
10579 #define XCVR_RX_DIG_AUXPLL_FCAL_CNT3_2_FCAL_COUNT_3_SHIFT (16U)
10580 #define XCVR_RX_DIG_AUXPLL_FCAL_CNT3_2_FCAL_COUNT_3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CNT3_2_FCAL_COUNT_3_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CNT3_2_FCAL_COUNT_3_MASK)
10581 
10582 /*! @name AUXPLL_FCAL_CNT1_0 - Aux PLL Frequency Calibration Count 1 and 0 */
10583 #define XCVR_RX_DIG_AUXPLL_FCAL_CNT1_0_FCAL_COUNT_0_MASK (0x3FFU)
10584 #define XCVR_RX_DIG_AUXPLL_FCAL_CNT1_0_FCAL_COUNT_0_SHIFT (0U)
10585 #define XCVR_RX_DIG_AUXPLL_FCAL_CNT1_0_FCAL_COUNT_0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CNT1_0_FCAL_COUNT_0_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CNT1_0_FCAL_COUNT_0_MASK)
10586 #define XCVR_RX_DIG_AUXPLL_FCAL_CNT1_0_FCAL_COUNT_1_MASK (0x3FF0000U)
10587 #define XCVR_RX_DIG_AUXPLL_FCAL_CNT1_0_FCAL_COUNT_1_SHIFT (16U)
10588 #define XCVR_RX_DIG_AUXPLL_FCAL_CNT1_0_FCAL_COUNT_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CNT1_0_FCAL_COUNT_1_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CNT1_0_FCAL_COUNT_1_MASK)
10589 
10590 /*! @name RXDIG_DFT - RXDIG DFT */
10591 #define XCVR_RX_DIG_RXDIG_DFT_DFT_TONE_FREQ_MASK (0x7U)
10592 #define XCVR_RX_DIG_RXDIG_DFT_DFT_TONE_FREQ_SHIFT (0U)
10593 #define XCVR_RX_DIG_RXDIG_DFT_DFT_TONE_FREQ(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RXDIG_DFT_DFT_TONE_FREQ_SHIFT)) & XCVR_RX_DIG_RXDIG_DFT_DFT_TONE_FREQ_MASK)
10594 #define XCVR_RX_DIG_RXDIG_DFT_DFT_TONE_SCALE_MASK (0x8U)
10595 #define XCVR_RX_DIG_RXDIG_DFT_DFT_TONE_SCALE_SHIFT (3U)
10596 #define XCVR_RX_DIG_RXDIG_DFT_DFT_TONE_SCALE(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RXDIG_DFT_DFT_TONE_SCALE_SHIFT)) & XCVR_RX_DIG_RXDIG_DFT_DFT_TONE_SCALE_MASK)
10597 #define XCVR_RX_DIG_RXDIG_DFT_DFT_TONE_TZA_EN_MASK (0x10U)
10598 #define XCVR_RX_DIG_RXDIG_DFT_DFT_TONE_TZA_EN_SHIFT (4U)
10599 #define XCVR_RX_DIG_RXDIG_DFT_DFT_TONE_TZA_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RXDIG_DFT_DFT_TONE_TZA_EN_SHIFT)) & XCVR_RX_DIG_RXDIG_DFT_DFT_TONE_TZA_EN_MASK)
10600 #define XCVR_RX_DIG_RXDIG_DFT_DFT_TONE_BBA_EN_MASK (0x20U)
10601 #define XCVR_RX_DIG_RXDIG_DFT_DFT_TONE_BBA_EN_SHIFT (5U)
10602 #define XCVR_RX_DIG_RXDIG_DFT_DFT_TONE_BBA_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RXDIG_DFT_DFT_TONE_BBA_EN_SHIFT)) & XCVR_RX_DIG_RXDIG_DFT_DFT_TONE_BBA_EN_MASK)
10603 
10604 
10605 /*!
10606  * @}
10607  */ /* end of group XCVR_RX_DIG_Register_Masks */
10608 
10609 
10610 /* XCVR_RX_DIG - Peripheral instance base addresses */
10611 /** Peripheral XCVR_RX_DIG base address */
10612 #define XCVR_RX_DIG_BASE                         (0x4005C000u)
10613 /** Peripheral XCVR_RX_DIG base pointer */
10614 #define XCVR_RX_DIG                              ((XCVR_RX_DIG_Type *)XCVR_RX_DIG_BASE)
10615 /** Array initializer of XCVR_RX_DIG peripheral base addresses */
10616 #define XCVR_RX_DIG_BASE_ADDRS                   { XCVR_RX_DIG_BASE }
10617 /** Array initializer of XCVR_RX_DIG peripheral base pointers */
10618 #define XCVR_RX_DIG_BASE_PTRS                    { XCVR_RX_DIG }
10619 
10620 /*!
10621  * @}
10622  */ /* end of group XCVR_RX_DIG_Peripheral_Access_Layer */
10623 
10624 
10625 /* ----------------------------------------------------------------------------
10626    -- XCVR_TSM Peripheral Access Layer
10627    ---------------------------------------------------------------------------- */
10628 
10629 /*!
10630  * @addtogroup XCVR_TSM_Peripheral_Access_Layer XCVR_TSM Peripheral Access Layer
10631  * @{
10632  */
10633 
10634 /** XCVR_TSM - Register Layout Typedef */
10635 typedef struct {
10636   __IO uint32_t CTRL;                              /**< TRANSCEIVER SEQUENCE MANAGER CONTROL, offset: 0x0 */
10637   __IO uint32_t END_OF_SEQ;                        /**< TSM END OF SEQUENCE, offset: 0x4 */
10638   __IO uint32_t OVRD0;                             /**< TSM OVERRIDE REGISTER 0, offset: 0x8 */
10639   __IO uint32_t OVRD1;                             /**< TSM OVERRIDE REGISTER 1, offset: 0xC */
10640   __IO uint32_t OVRD2;                             /**< TSM OVERRIDE REGISTER 2, offset: 0x10 */
10641   __IO uint32_t OVRD3;                             /**< TSM OVERRIDE REGISTER 3, offset: 0x14 */
10642   __IO uint32_t PA_POWER;                          /**< PA POWER, offset: 0x18 */
10643   __IO uint32_t PA_RAMP_TBL0;                      /**< PA RAMP TABLE 0, offset: 0x1C */
10644   __IO uint32_t PA_RAMP_TBL1;                      /**< PA RAMP TABLE 1, offset: 0x20 */
10645   __IO uint32_t RECYCLE_COUNT;                     /**< TSM RECYCLE COUNT, offset: 0x24 */
10646   __IO uint32_t FAST_CTRL1;                        /**< TSM FAST WARMUP CONTROL REGISTER 1, offset: 0x28 */
10647   __IO uint32_t FAST_CTRL2;                        /**< TSM FAST WARMUP CONTROL REGISTER 2, offset: 0x2C */
10648   __IO uint32_t TIMING00;                          /**< TSM_TIMING00, offset: 0x30 */
10649   __IO uint32_t TIMING01;                          /**< TSM_TIMING01, offset: 0x34 */
10650   __IO uint32_t TIMING02;                          /**< TSM_TIMING02, offset: 0x38 */
10651   __IO uint32_t TIMING03;                          /**< TSM_TIMING03, offset: 0x3C */
10652   __IO uint32_t TIMING04;                          /**< TSM_TIMING04, offset: 0x40 */
10653   __IO uint32_t TIMING05;                          /**< TSM_TIMING05, offset: 0x44 */
10654   __IO uint32_t TIMING06;                          /**< TSM_TIMING06, offset: 0x48 */
10655   __IO uint32_t TIMING07;                          /**< TSM_TIMING07, offset: 0x4C */
10656   __IO uint32_t TIMING08;                          /**< TSM_TIMING08, offset: 0x50 */
10657   __IO uint32_t TIMING09;                          /**< TSM_TIMING09, offset: 0x54 */
10658   __IO uint32_t TIMING10;                          /**< TSM_TIMING10, offset: 0x58 */
10659   __IO uint32_t TIMING11;                          /**< TSM_TIMING11, offset: 0x5C */
10660   __IO uint32_t TIMING12;                          /**< TSM_TIMING12, offset: 0x60 */
10661   __IO uint32_t TIMING13;                          /**< TSM_TIMING13, offset: 0x64 */
10662   __IO uint32_t TIMING14;                          /**< TSM_TIMING14, offset: 0x68 */
10663   __IO uint32_t TIMING15;                          /**< TSM_TIMING15, offset: 0x6C */
10664   __IO uint32_t TIMING16;                          /**< TSM_TIMING16, offset: 0x70 */
10665   __IO uint32_t TIMING17;                          /**< TSM_TIMING17, offset: 0x74 */
10666   __IO uint32_t TIMING18;                          /**< TSM_TIMING18, offset: 0x78 */
10667   __IO uint32_t TIMING19;                          /**< TSM_TIMING19, offset: 0x7C */
10668   __IO uint32_t TIMING20;                          /**< TSM_TIMING20, offset: 0x80 */
10669   __IO uint32_t TIMING21;                          /**< TSM_TIMING21, offset: 0x84 */
10670   __IO uint32_t TIMING22;                          /**< TSM_TIMING22, offset: 0x88 */
10671   __IO uint32_t TIMING23;                          /**< TSM_TIMING23, offset: 0x8C */
10672   __IO uint32_t TIMING24;                          /**< TSM_TIMING24, offset: 0x90 */
10673   __IO uint32_t TIMING25;                          /**< TSM_TIMING25, offset: 0x94 */
10674   __IO uint32_t TIMING26;                          /**< TSM_TIMING26, offset: 0x98 */
10675   __IO uint32_t TIMING27;                          /**< TSM_TIMING27, offset: 0x9C */
10676   __IO uint32_t TIMING28;                          /**< TSM_TIMING28, offset: 0xA0 */
10677   __IO uint32_t TIMING29;                          /**< TSM_TIMING29, offset: 0xA4 */
10678   __IO uint32_t TIMING30;                          /**< TSM_TIMING30, offset: 0xA8 */
10679   __IO uint32_t TIMING31;                          /**< TSM_TIMING31, offset: 0xAC */
10680   __IO uint32_t TIMING32;                          /**< TSM_TIMING32, offset: 0xB0 */
10681   __IO uint32_t TIMING33;                          /**< TSM_TIMING33, offset: 0xB4 */
10682   __IO uint32_t TIMING34;                          /**< TSM_TIMING34, offset: 0xB8 */
10683   __IO uint32_t TIMING35;                          /**< TSM_TIMING35, offset: 0xBC */
10684   __IO uint32_t TIMING36;                          /**< TSM_TIMING36, offset: 0xC0 */
10685   __IO uint32_t TIMING37;                          /**< TSM_TIMING37, offset: 0xC4 */
10686   __IO uint32_t TIMING38;                          /**< TSM_TIMING38, offset: 0xC8 */
10687   __IO uint32_t TIMING39;                          /**< TSM_TIMING39, offset: 0xCC */
10688   __IO uint32_t TIMING40;                          /**< TSM_TIMING40, offset: 0xD0 */
10689   __IO uint32_t TIMING41;                          /**< TSM_TIMING41, offset: 0xD4 */
10690   __IO uint32_t TIMING42;                          /**< TSM_TIMING42, offset: 0xD8 */
10691   __IO uint32_t TIMING43;                          /**< TSM_TIMING43, offset: 0xDC */
10692   __IO uint32_t TIMING44;                          /**< TSM_TIMING44, offset: 0xE0 */
10693   __IO uint32_t TIMING45;                          /**< TSM_TIMING45, offset: 0xE4 */
10694   __IO uint32_t TIMING46;                          /**< TSM_TIMING46, offset: 0xE8 */
10695   __IO uint32_t TIMING47;                          /**< TSM_TIMING47, offset: 0xEC */
10696   __IO uint32_t TIMING48;                          /**< TSM_TIMING48, offset: 0xF0 */
10697   __IO uint32_t TIMING49;                          /**< TSM_TIMING49, offset: 0xF4 */
10698   __IO uint32_t TIMING50;                          /**< TSM_TIMING50, offset: 0xF8 */
10699   __IO uint32_t TIMING51;                          /**< TSM_TIMING51, offset: 0xFC */
10700   __IO uint32_t TIMING52;                          /**< TSM_TIMING52, offset: 0x100 */
10701   __IO uint32_t TIMING53;                          /**< TSM_TIMING53, offset: 0x104 */
10702   __IO uint32_t TIMING54;                          /**< TSM_TIMING54, offset: 0x108 */
10703   __IO uint32_t TIMING55;                          /**< TSM_TIMING55, offset: 0x10C */
10704   __IO uint32_t TIMING56;                          /**< TSM_TIMING56, offset: 0x110 */
10705   __IO uint32_t TIMING57;                          /**< TSM_TIMING57, offset: 0x114 */
10706   __IO uint32_t TIMING58;                          /**< TSM_TIMING58, offset: 0x118 */
10707 } XCVR_TSM_Type;
10708 
10709 /* ----------------------------------------------------------------------------
10710    -- XCVR_TSM Register Masks
10711    ---------------------------------------------------------------------------- */
10712 
10713 /*!
10714  * @addtogroup XCVR_TSM_Register_Masks XCVR_TSM Register Masks
10715  * @{
10716  */
10717 
10718 /*! @name CTRL - TRANSCEIVER SEQUENCE MANAGER CONTROL */
10719 #define XCVR_TSM_CTRL_FORCE_TX_EN_MASK           (0x4U)
10720 #define XCVR_TSM_CTRL_FORCE_TX_EN_SHIFT          (2U)
10721 #define XCVR_TSM_CTRL_FORCE_TX_EN(x)             (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_FORCE_TX_EN_SHIFT)) & XCVR_TSM_CTRL_FORCE_TX_EN_MASK)
10722 #define XCVR_TSM_CTRL_FORCE_RX_EN_MASK           (0x8U)
10723 #define XCVR_TSM_CTRL_FORCE_RX_EN_SHIFT          (3U)
10724 #define XCVR_TSM_CTRL_FORCE_RX_EN(x)             (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_FORCE_RX_EN_SHIFT)) & XCVR_TSM_CTRL_FORCE_RX_EN_MASK)
10725 #define XCVR_TSM_CTRL_PA_RAMP_SEL_MASK           (0x30U)
10726 #define XCVR_TSM_CTRL_PA_RAMP_SEL_SHIFT          (4U)
10727 #define XCVR_TSM_CTRL_PA_RAMP_SEL(x)             (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_PA_RAMP_SEL_SHIFT)) & XCVR_TSM_CTRL_PA_RAMP_SEL_MASK)
10728 #define XCVR_TSM_CTRL_DATA_PADDING_EN_MASK       (0xC0U)
10729 #define XCVR_TSM_CTRL_DATA_PADDING_EN_SHIFT      (6U)
10730 #define XCVR_TSM_CTRL_DATA_PADDING_EN(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_DATA_PADDING_EN_SHIFT)) & XCVR_TSM_CTRL_DATA_PADDING_EN_MASK)
10731 #define XCVR_TSM_CTRL_TSM_IRQ0_EN_MASK           (0x100U)
10732 #define XCVR_TSM_CTRL_TSM_IRQ0_EN_SHIFT          (8U)
10733 #define XCVR_TSM_CTRL_TSM_IRQ0_EN(x)             (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_TSM_IRQ0_EN_SHIFT)) & XCVR_TSM_CTRL_TSM_IRQ0_EN_MASK)
10734 #define XCVR_TSM_CTRL_TSM_IRQ1_EN_MASK           (0x200U)
10735 #define XCVR_TSM_CTRL_TSM_IRQ1_EN_SHIFT          (9U)
10736 #define XCVR_TSM_CTRL_TSM_IRQ1_EN(x)             (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_TSM_IRQ1_EN_SHIFT)) & XCVR_TSM_CTRL_TSM_IRQ1_EN_MASK)
10737 #define XCVR_TSM_CTRL_RAMP_DN_DELAY_MASK         (0xF000U)
10738 #define XCVR_TSM_CTRL_RAMP_DN_DELAY_SHIFT        (12U)
10739 #define XCVR_TSM_CTRL_RAMP_DN_DELAY(x)           (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_RAMP_DN_DELAY_SHIFT)) & XCVR_TSM_CTRL_RAMP_DN_DELAY_MASK)
10740 #define XCVR_TSM_CTRL_TX_ABORT_DIS_MASK          (0x10000U)
10741 #define XCVR_TSM_CTRL_TX_ABORT_DIS_SHIFT         (16U)
10742 #define XCVR_TSM_CTRL_TX_ABORT_DIS(x)            (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_TX_ABORT_DIS_SHIFT)) & XCVR_TSM_CTRL_TX_ABORT_DIS_MASK)
10743 #define XCVR_TSM_CTRL_RX_ABORT_DIS_MASK          (0x20000U)
10744 #define XCVR_TSM_CTRL_RX_ABORT_DIS_SHIFT         (17U)
10745 #define XCVR_TSM_CTRL_RX_ABORT_DIS(x)            (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_RX_ABORT_DIS_SHIFT)) & XCVR_TSM_CTRL_RX_ABORT_DIS_MASK)
10746 #define XCVR_TSM_CTRL_ABORT_ON_CTUNE_MASK        (0x40000U)
10747 #define XCVR_TSM_CTRL_ABORT_ON_CTUNE_SHIFT       (18U)
10748 #define XCVR_TSM_CTRL_ABORT_ON_CTUNE(x)          (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_ABORT_ON_CTUNE_SHIFT)) & XCVR_TSM_CTRL_ABORT_ON_CTUNE_MASK)
10749 #define XCVR_TSM_CTRL_ABORT_ON_CYCLE_SLIP_MASK   (0x80000U)
10750 #define XCVR_TSM_CTRL_ABORT_ON_CYCLE_SLIP_SHIFT  (19U)
10751 #define XCVR_TSM_CTRL_ABORT_ON_CYCLE_SLIP(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_ABORT_ON_CYCLE_SLIP_SHIFT)) & XCVR_TSM_CTRL_ABORT_ON_CYCLE_SLIP_MASK)
10752 #define XCVR_TSM_CTRL_ABORT_ON_FREQ_TARG_MASK    (0x100000U)
10753 #define XCVR_TSM_CTRL_ABORT_ON_FREQ_TARG_SHIFT   (20U)
10754 #define XCVR_TSM_CTRL_ABORT_ON_FREQ_TARG(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_ABORT_ON_FREQ_TARG_SHIFT)) & XCVR_TSM_CTRL_ABORT_ON_FREQ_TARG_MASK)
10755 #define XCVR_TSM_CTRL_BKPT_MASK                  (0xFF000000U)
10756 #define XCVR_TSM_CTRL_BKPT_SHIFT                 (24U)
10757 #define XCVR_TSM_CTRL_BKPT(x)                    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_BKPT_SHIFT)) & XCVR_TSM_CTRL_BKPT_MASK)
10758 
10759 /*! @name END_OF_SEQ - TSM END OF SEQUENCE */
10760 #define XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_MASK    (0xFFU)
10761 #define XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_SHIFT   (0U)
10762 #define XCVR_TSM_END_OF_SEQ_END_OF_TX_WU(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_SHIFT)) & XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_MASK)
10763 #define XCVR_TSM_END_OF_SEQ_END_OF_TX_WD_MASK    (0xFF00U)
10764 #define XCVR_TSM_END_OF_SEQ_END_OF_TX_WD_SHIFT   (8U)
10765 #define XCVR_TSM_END_OF_SEQ_END_OF_TX_WD(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_END_OF_SEQ_END_OF_TX_WD_SHIFT)) & XCVR_TSM_END_OF_SEQ_END_OF_TX_WD_MASK)
10766 #define XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK    (0xFF0000U)
10767 #define XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT   (16U)
10768 #define XCVR_TSM_END_OF_SEQ_END_OF_RX_WU(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT)) & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK)
10769 #define XCVR_TSM_END_OF_SEQ_END_OF_RX_WD_MASK    (0xFF000000U)
10770 #define XCVR_TSM_END_OF_SEQ_END_OF_RX_WD_SHIFT   (24U)
10771 #define XCVR_TSM_END_OF_SEQ_END_OF_RX_WD(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_END_OF_SEQ_END_OF_RX_WD_SHIFT)) & XCVR_TSM_END_OF_SEQ_END_OF_RX_WD_MASK)
10772 
10773 /*! @name OVRD0 - TSM OVERRIDE REGISTER 0 */
10774 #define XCVR_TSM_OVRD0_BB_LDO_HF_EN_OVRD_EN_MASK (0x1U)
10775 #define XCVR_TSM_OVRD0_BB_LDO_HF_EN_OVRD_EN_SHIFT (0U)
10776 #define XCVR_TSM_OVRD0_BB_LDO_HF_EN_OVRD_EN(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_HF_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_HF_EN_OVRD_EN_MASK)
10777 #define XCVR_TSM_OVRD0_BB_LDO_HF_EN_OVRD_MASK    (0x2U)
10778 #define XCVR_TSM_OVRD0_BB_LDO_HF_EN_OVRD_SHIFT   (1U)
10779 #define XCVR_TSM_OVRD0_BB_LDO_HF_EN_OVRD(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_HF_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_HF_EN_OVRD_MASK)
10780 #define XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD_EN_MASK (0x4U)
10781 #define XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD_EN_SHIFT (2U)
10782 #define XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD_EN_MASK)
10783 #define XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD_MASK (0x8U)
10784 #define XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD_SHIFT (3U)
10785 #define XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD_MASK)
10786 #define XCVR_TSM_OVRD0_BB_LDO_BBA_EN_OVRD_EN_MASK (0x10U)
10787 #define XCVR_TSM_OVRD0_BB_LDO_BBA_EN_OVRD_EN_SHIFT (4U)
10788 #define XCVR_TSM_OVRD0_BB_LDO_BBA_EN_OVRD_EN(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_BBA_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_BBA_EN_OVRD_EN_MASK)
10789 #define XCVR_TSM_OVRD0_BB_LDO_BBA_EN_OVRD_MASK   (0x20U)
10790 #define XCVR_TSM_OVRD0_BB_LDO_BBA_EN_OVRD_SHIFT  (5U)
10791 #define XCVR_TSM_OVRD0_BB_LDO_BBA_EN_OVRD(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_BBA_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_BBA_EN_OVRD_MASK)
10792 #define XCVR_TSM_OVRD0_BB_LDO_PD_EN_OVRD_EN_MASK (0x40U)
10793 #define XCVR_TSM_OVRD0_BB_LDO_PD_EN_OVRD_EN_SHIFT (6U)
10794 #define XCVR_TSM_OVRD0_BB_LDO_PD_EN_OVRD_EN(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_PD_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_PD_EN_OVRD_EN_MASK)
10795 #define XCVR_TSM_OVRD0_BB_LDO_PD_EN_OVRD_MASK    (0x80U)
10796 #define XCVR_TSM_OVRD0_BB_LDO_PD_EN_OVRD_SHIFT   (7U)
10797 #define XCVR_TSM_OVRD0_BB_LDO_PD_EN_OVRD(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_PD_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_PD_EN_OVRD_MASK)
10798 #define XCVR_TSM_OVRD0_BB_LDO_FDBK_EN_OVRD_EN_MASK (0x100U)
10799 #define XCVR_TSM_OVRD0_BB_LDO_FDBK_EN_OVRD_EN_SHIFT (8U)
10800 #define XCVR_TSM_OVRD0_BB_LDO_FDBK_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_FDBK_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_FDBK_EN_OVRD_EN_MASK)
10801 #define XCVR_TSM_OVRD0_BB_LDO_FDBK_EN_OVRD_MASK  (0x200U)
10802 #define XCVR_TSM_OVRD0_BB_LDO_FDBK_EN_OVRD_SHIFT (9U)
10803 #define XCVR_TSM_OVRD0_BB_LDO_FDBK_EN_OVRD(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_FDBK_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_FDBK_EN_OVRD_MASK)
10804 #define XCVR_TSM_OVRD0_BB_LDO_VCOLO_EN_OVRD_EN_MASK (0x400U)
10805 #define XCVR_TSM_OVRD0_BB_LDO_VCOLO_EN_OVRD_EN_SHIFT (10U)
10806 #define XCVR_TSM_OVRD0_BB_LDO_VCOLO_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_VCOLO_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_VCOLO_EN_OVRD_EN_MASK)
10807 #define XCVR_TSM_OVRD0_BB_LDO_VCOLO_EN_OVRD_MASK (0x800U)
10808 #define XCVR_TSM_OVRD0_BB_LDO_VCOLO_EN_OVRD_SHIFT (11U)
10809 #define XCVR_TSM_OVRD0_BB_LDO_VCOLO_EN_OVRD(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_VCOLO_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_VCOLO_EN_OVRD_MASK)
10810 #define XCVR_TSM_OVRD0_BB_LDO_VTREF_EN_OVRD_EN_MASK (0x1000U)
10811 #define XCVR_TSM_OVRD0_BB_LDO_VTREF_EN_OVRD_EN_SHIFT (12U)
10812 #define XCVR_TSM_OVRD0_BB_LDO_VTREF_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_VTREF_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_VTREF_EN_OVRD_EN_MASK)
10813 #define XCVR_TSM_OVRD0_BB_LDO_VTREF_EN_OVRD_MASK (0x2000U)
10814 #define XCVR_TSM_OVRD0_BB_LDO_VTREF_EN_OVRD_SHIFT (13U)
10815 #define XCVR_TSM_OVRD0_BB_LDO_VTREF_EN_OVRD(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_VTREF_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_VTREF_EN_OVRD_MASK)
10816 #define XCVR_TSM_OVRD0_BB_LDO_FDBK_BLEED_EN_OVRD_EN_MASK (0x4000U)
10817 #define XCVR_TSM_OVRD0_BB_LDO_FDBK_BLEED_EN_OVRD_EN_SHIFT (14U)
10818 #define XCVR_TSM_OVRD0_BB_LDO_FDBK_BLEED_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_FDBK_BLEED_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_FDBK_BLEED_EN_OVRD_EN_MASK)
10819 #define XCVR_TSM_OVRD0_BB_LDO_FDBK_BLEED_EN_OVRD_MASK (0x8000U)
10820 #define XCVR_TSM_OVRD0_BB_LDO_FDBK_BLEED_EN_OVRD_SHIFT (15U)
10821 #define XCVR_TSM_OVRD0_BB_LDO_FDBK_BLEED_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_FDBK_BLEED_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_FDBK_BLEED_EN_OVRD_MASK)
10822 #define XCVR_TSM_OVRD0_BB_LDO_VCOLO_BLEED_EN_OVRD_EN_MASK (0x10000U)
10823 #define XCVR_TSM_OVRD0_BB_LDO_VCOLO_BLEED_EN_OVRD_EN_SHIFT (16U)
10824 #define XCVR_TSM_OVRD0_BB_LDO_VCOLO_BLEED_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_VCOLO_BLEED_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_VCOLO_BLEED_EN_OVRD_EN_MASK)
10825 #define XCVR_TSM_OVRD0_BB_LDO_VCOLO_BLEED_EN_OVRD_MASK (0x20000U)
10826 #define XCVR_TSM_OVRD0_BB_LDO_VCOLO_BLEED_EN_OVRD_SHIFT (17U)
10827 #define XCVR_TSM_OVRD0_BB_LDO_VCOLO_BLEED_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_VCOLO_BLEED_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_VCOLO_BLEED_EN_OVRD_MASK)
10828 #define XCVR_TSM_OVRD0_BB_LDO_VCOLO_FASTCHARGE_EN_OVRD_EN_MASK (0x40000U)
10829 #define XCVR_TSM_OVRD0_BB_LDO_VCOLO_FASTCHARGE_EN_OVRD_EN_SHIFT (18U)
10830 #define XCVR_TSM_OVRD0_BB_LDO_VCOLO_FASTCHARGE_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_VCOLO_FASTCHARGE_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_VCOLO_FASTCHARGE_EN_OVRD_EN_MASK)
10831 #define XCVR_TSM_OVRD0_BB_LDO_VCOLO_FASTCHARGE_EN_OVRD_MASK (0x80000U)
10832 #define XCVR_TSM_OVRD0_BB_LDO_VCOLO_FASTCHARGE_EN_OVRD_SHIFT (19U)
10833 #define XCVR_TSM_OVRD0_BB_LDO_VCOLO_FASTCHARGE_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_VCOLO_FASTCHARGE_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_VCOLO_FASTCHARGE_EN_OVRD_MASK)
10834 #define XCVR_TSM_OVRD0_BB_XTAL_PLL_REF_CLK_EN_OVRD_EN_MASK (0x100000U)
10835 #define XCVR_TSM_OVRD0_BB_XTAL_PLL_REF_CLK_EN_OVRD_EN_SHIFT (20U)
10836 #define XCVR_TSM_OVRD0_BB_XTAL_PLL_REF_CLK_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_XTAL_PLL_REF_CLK_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_XTAL_PLL_REF_CLK_EN_OVRD_EN_MASK)
10837 #define XCVR_TSM_OVRD0_BB_XTAL_PLL_REF_CLK_EN_OVRD_MASK (0x200000U)
10838 #define XCVR_TSM_OVRD0_BB_XTAL_PLL_REF_CLK_EN_OVRD_SHIFT (21U)
10839 #define XCVR_TSM_OVRD0_BB_XTAL_PLL_REF_CLK_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_XTAL_PLL_REF_CLK_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_XTAL_PLL_REF_CLK_EN_OVRD_MASK)
10840 #define XCVR_TSM_OVRD0_BB_XTAL_DAC_REF_CLK_EN_OVRD_EN_MASK (0x400000U)
10841 #define XCVR_TSM_OVRD0_BB_XTAL_DAC_REF_CLK_EN_OVRD_EN_SHIFT (22U)
10842 #define XCVR_TSM_OVRD0_BB_XTAL_DAC_REF_CLK_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_XTAL_DAC_REF_CLK_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_XTAL_DAC_REF_CLK_EN_OVRD_EN_MASK)
10843 #define XCVR_TSM_OVRD0_BB_XTAL_DAC_REF_CLK_EN_OVRD_MASK (0x800000U)
10844 #define XCVR_TSM_OVRD0_BB_XTAL_DAC_REF_CLK_EN_OVRD_SHIFT (23U)
10845 #define XCVR_TSM_OVRD0_BB_XTAL_DAC_REF_CLK_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_XTAL_DAC_REF_CLK_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_XTAL_DAC_REF_CLK_EN_OVRD_MASK)
10846 #define XCVR_TSM_OVRD0_BB_XTAL_AUXPLL_REF_CLK_EN_OVRD_EN_MASK (0x1000000U)
10847 #define XCVR_TSM_OVRD0_BB_XTAL_AUXPLL_REF_CLK_EN_OVRD_EN_SHIFT (24U)
10848 #define XCVR_TSM_OVRD0_BB_XTAL_AUXPLL_REF_CLK_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_XTAL_AUXPLL_REF_CLK_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_XTAL_AUXPLL_REF_CLK_EN_OVRD_EN_MASK)
10849 #define XCVR_TSM_OVRD0_BB_XTAL_AUXPLL_REF_CLK_EN_OVRD_MASK (0x2000000U)
10850 #define XCVR_TSM_OVRD0_BB_XTAL_AUXPLL_REF_CLK_EN_OVRD_SHIFT (25U)
10851 #define XCVR_TSM_OVRD0_BB_XTAL_AUXPLL_REF_CLK_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_XTAL_AUXPLL_REF_CLK_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_XTAL_AUXPLL_REF_CLK_EN_OVRD_MASK)
10852 #define XCVR_TSM_OVRD0_SY_VCO_AUTOTUNE_EN_OVRD_EN_MASK (0x4000000U)
10853 #define XCVR_TSM_OVRD0_SY_VCO_AUTOTUNE_EN_OVRD_EN_SHIFT (26U)
10854 #define XCVR_TSM_OVRD0_SY_VCO_AUTOTUNE_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_SY_VCO_AUTOTUNE_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_SY_VCO_AUTOTUNE_EN_OVRD_EN_MASK)
10855 #define XCVR_TSM_OVRD0_SY_VCO_AUTOTUNE_EN_OVRD_MASK (0x8000000U)
10856 #define XCVR_TSM_OVRD0_SY_VCO_AUTOTUNE_EN_OVRD_SHIFT (27U)
10857 #define XCVR_TSM_OVRD0_SY_VCO_AUTOTUNE_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_SY_VCO_AUTOTUNE_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_SY_VCO_AUTOTUNE_EN_OVRD_MASK)
10858 #define XCVR_TSM_OVRD0_SY_PD_CYCLE_SLIP_LD_EN_OVRD_EN_MASK (0x10000000U)
10859 #define XCVR_TSM_OVRD0_SY_PD_CYCLE_SLIP_LD_EN_OVRD_EN_SHIFT (28U)
10860 #define XCVR_TSM_OVRD0_SY_PD_CYCLE_SLIP_LD_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_SY_PD_CYCLE_SLIP_LD_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_SY_PD_CYCLE_SLIP_LD_EN_OVRD_EN_MASK)
10861 #define XCVR_TSM_OVRD0_SY_PD_CYCLE_SLIP_LD_EN_OVRD_MASK (0x20000000U)
10862 #define XCVR_TSM_OVRD0_SY_PD_CYCLE_SLIP_LD_EN_OVRD_SHIFT (29U)
10863 #define XCVR_TSM_OVRD0_SY_PD_CYCLE_SLIP_LD_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_SY_PD_CYCLE_SLIP_LD_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_SY_PD_CYCLE_SLIP_LD_EN_OVRD_MASK)
10864 #define XCVR_TSM_OVRD0_SY_VCO_EN_OVRD_EN_MASK    (0x40000000U)
10865 #define XCVR_TSM_OVRD0_SY_VCO_EN_OVRD_EN_SHIFT   (30U)
10866 #define XCVR_TSM_OVRD0_SY_VCO_EN_OVRD_EN(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_SY_VCO_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_SY_VCO_EN_OVRD_EN_MASK)
10867 #define XCVR_TSM_OVRD0_SY_VCO_EN_OVRD_MASK       (0x80000000U)
10868 #define XCVR_TSM_OVRD0_SY_VCO_EN_OVRD_SHIFT      (31U)
10869 #define XCVR_TSM_OVRD0_SY_VCO_EN_OVRD(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_SY_VCO_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_SY_VCO_EN_OVRD_MASK)
10870 
10871 /*! @name OVRD1 - TSM OVERRIDE REGISTER 1 */
10872 #define XCVR_TSM_OVRD1_SY_LO_RX_BUF_EN_OVRD_EN_MASK (0x1U)
10873 #define XCVR_TSM_OVRD1_SY_LO_RX_BUF_EN_OVRD_EN_SHIFT (0U)
10874 #define XCVR_TSM_OVRD1_SY_LO_RX_BUF_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_LO_RX_BUF_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_SY_LO_RX_BUF_EN_OVRD_EN_MASK)
10875 #define XCVR_TSM_OVRD1_SY_LO_RX_BUF_EN_OVRD_MASK (0x2U)
10876 #define XCVR_TSM_OVRD1_SY_LO_RX_BUF_EN_OVRD_SHIFT (1U)
10877 #define XCVR_TSM_OVRD1_SY_LO_RX_BUF_EN_OVRD(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_LO_RX_BUF_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_SY_LO_RX_BUF_EN_OVRD_MASK)
10878 #define XCVR_TSM_OVRD1_SY_LO_TX_BUF_EN_OVRD_EN_MASK (0x4U)
10879 #define XCVR_TSM_OVRD1_SY_LO_TX_BUF_EN_OVRD_EN_SHIFT (2U)
10880 #define XCVR_TSM_OVRD1_SY_LO_TX_BUF_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_LO_TX_BUF_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_SY_LO_TX_BUF_EN_OVRD_EN_MASK)
10881 #define XCVR_TSM_OVRD1_SY_LO_TX_BUF_EN_OVRD_MASK (0x8U)
10882 #define XCVR_TSM_OVRD1_SY_LO_TX_BUF_EN_OVRD_SHIFT (3U)
10883 #define XCVR_TSM_OVRD1_SY_LO_TX_BUF_EN_OVRD(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_LO_TX_BUF_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_SY_LO_TX_BUF_EN_OVRD_MASK)
10884 #define XCVR_TSM_OVRD1_SY_DIVN_EN_OVRD_EN_MASK   (0x10U)
10885 #define XCVR_TSM_OVRD1_SY_DIVN_EN_OVRD_EN_SHIFT  (4U)
10886 #define XCVR_TSM_OVRD1_SY_DIVN_EN_OVRD_EN(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_DIVN_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_SY_DIVN_EN_OVRD_EN_MASK)
10887 #define XCVR_TSM_OVRD1_SY_DIVN_EN_OVRD_MASK      (0x20U)
10888 #define XCVR_TSM_OVRD1_SY_DIVN_EN_OVRD_SHIFT     (5U)
10889 #define XCVR_TSM_OVRD1_SY_DIVN_EN_OVRD(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_DIVN_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_SY_DIVN_EN_OVRD_MASK)
10890 #define XCVR_TSM_OVRD1_SY_PD_FILTER_CHARGE_EN_OVRD_EN_MASK (0x40U)
10891 #define XCVR_TSM_OVRD1_SY_PD_FILTER_CHARGE_EN_OVRD_EN_SHIFT (6U)
10892 #define XCVR_TSM_OVRD1_SY_PD_FILTER_CHARGE_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_PD_FILTER_CHARGE_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_SY_PD_FILTER_CHARGE_EN_OVRD_EN_MASK)
10893 #define XCVR_TSM_OVRD1_SY_PD_FILTER_CHARGE_EN_OVRD_MASK (0x80U)
10894 #define XCVR_TSM_OVRD1_SY_PD_FILTER_CHARGE_EN_OVRD_SHIFT (7U)
10895 #define XCVR_TSM_OVRD1_SY_PD_FILTER_CHARGE_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_PD_FILTER_CHARGE_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_SY_PD_FILTER_CHARGE_EN_OVRD_MASK)
10896 #define XCVR_TSM_OVRD1_SY_PD_EN_OVRD_EN_MASK     (0x100U)
10897 #define XCVR_TSM_OVRD1_SY_PD_EN_OVRD_EN_SHIFT    (8U)
10898 #define XCVR_TSM_OVRD1_SY_PD_EN_OVRD_EN(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_PD_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_SY_PD_EN_OVRD_EN_MASK)
10899 #define XCVR_TSM_OVRD1_SY_PD_EN_OVRD_MASK        (0x200U)
10900 #define XCVR_TSM_OVRD1_SY_PD_EN_OVRD_SHIFT       (9U)
10901 #define XCVR_TSM_OVRD1_SY_PD_EN_OVRD(x)          (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_PD_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_SY_PD_EN_OVRD_MASK)
10902 #define XCVR_TSM_OVRD1_SY_LO_DIVN_EN_OVRD_EN_MASK (0x400U)
10903 #define XCVR_TSM_OVRD1_SY_LO_DIVN_EN_OVRD_EN_SHIFT (10U)
10904 #define XCVR_TSM_OVRD1_SY_LO_DIVN_EN_OVRD_EN(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_LO_DIVN_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_SY_LO_DIVN_EN_OVRD_EN_MASK)
10905 #define XCVR_TSM_OVRD1_SY_LO_DIVN_EN_OVRD_MASK   (0x800U)
10906 #define XCVR_TSM_OVRD1_SY_LO_DIVN_EN_OVRD_SHIFT  (11U)
10907 #define XCVR_TSM_OVRD1_SY_LO_DIVN_EN_OVRD(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_LO_DIVN_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_SY_LO_DIVN_EN_OVRD_MASK)
10908 #define XCVR_TSM_OVRD1_SY_LO_RX_EN_OVRD_EN_MASK  (0x1000U)
10909 #define XCVR_TSM_OVRD1_SY_LO_RX_EN_OVRD_EN_SHIFT (12U)
10910 #define XCVR_TSM_OVRD1_SY_LO_RX_EN_OVRD_EN(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_LO_RX_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_SY_LO_RX_EN_OVRD_EN_MASK)
10911 #define XCVR_TSM_OVRD1_SY_LO_RX_EN_OVRD_MASK     (0x2000U)
10912 #define XCVR_TSM_OVRD1_SY_LO_RX_EN_OVRD_SHIFT    (13U)
10913 #define XCVR_TSM_OVRD1_SY_LO_RX_EN_OVRD(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_LO_RX_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_SY_LO_RX_EN_OVRD_MASK)
10914 #define XCVR_TSM_OVRD1_SY_LO_TX_EN_OVRD_EN_MASK  (0x4000U)
10915 #define XCVR_TSM_OVRD1_SY_LO_TX_EN_OVRD_EN_SHIFT (14U)
10916 #define XCVR_TSM_OVRD1_SY_LO_TX_EN_OVRD_EN(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_LO_TX_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_SY_LO_TX_EN_OVRD_EN_MASK)
10917 #define XCVR_TSM_OVRD1_SY_LO_TX_EN_OVRD_MASK     (0x8000U)
10918 #define XCVR_TSM_OVRD1_SY_LO_TX_EN_OVRD_SHIFT    (15U)
10919 #define XCVR_TSM_OVRD1_SY_LO_TX_EN_OVRD(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_LO_TX_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_SY_LO_TX_EN_OVRD_MASK)
10920 #define XCVR_TSM_OVRD1_SY_DIVN_CAL_EN_OVRD_EN_MASK (0x10000U)
10921 #define XCVR_TSM_OVRD1_SY_DIVN_CAL_EN_OVRD_EN_SHIFT (16U)
10922 #define XCVR_TSM_OVRD1_SY_DIVN_CAL_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_DIVN_CAL_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_SY_DIVN_CAL_EN_OVRD_EN_MASK)
10923 #define XCVR_TSM_OVRD1_SY_DIVN_CAL_EN_OVRD_MASK  (0x20000U)
10924 #define XCVR_TSM_OVRD1_SY_DIVN_CAL_EN_OVRD_SHIFT (17U)
10925 #define XCVR_TSM_OVRD1_SY_DIVN_CAL_EN_OVRD(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_DIVN_CAL_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_SY_DIVN_CAL_EN_OVRD_MASK)
10926 #define XCVR_TSM_OVRD1_RX_MIXER_EN_OVRD_EN_MASK  (0x40000U)
10927 #define XCVR_TSM_OVRD1_RX_MIXER_EN_OVRD_EN_SHIFT (18U)
10928 #define XCVR_TSM_OVRD1_RX_MIXER_EN_OVRD_EN(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_RX_MIXER_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_RX_MIXER_EN_OVRD_EN_MASK)
10929 #define XCVR_TSM_OVRD1_RX_MIXER_EN_OVRD_MASK     (0x80000U)
10930 #define XCVR_TSM_OVRD1_RX_MIXER_EN_OVRD_SHIFT    (19U)
10931 #define XCVR_TSM_OVRD1_RX_MIXER_EN_OVRD(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_RX_MIXER_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_RX_MIXER_EN_OVRD_MASK)
10932 #define XCVR_TSM_OVRD1_TX_PA_EN_OVRD_EN_MASK     (0x100000U)
10933 #define XCVR_TSM_OVRD1_TX_PA_EN_OVRD_EN_SHIFT    (20U)
10934 #define XCVR_TSM_OVRD1_TX_PA_EN_OVRD_EN(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_TX_PA_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_TX_PA_EN_OVRD_EN_MASK)
10935 #define XCVR_TSM_OVRD1_TX_PA_EN_OVRD_MASK        (0x200000U)
10936 #define XCVR_TSM_OVRD1_TX_PA_EN_OVRD_SHIFT       (21U)
10937 #define XCVR_TSM_OVRD1_TX_PA_EN_OVRD(x)          (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_TX_PA_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_TX_PA_EN_OVRD_MASK)
10938 #define XCVR_TSM_OVRD1_RX_ADC_I_EN_OVRD_EN_MASK  (0x400000U)
10939 #define XCVR_TSM_OVRD1_RX_ADC_I_EN_OVRD_EN_SHIFT (22U)
10940 #define XCVR_TSM_OVRD1_RX_ADC_I_EN_OVRD_EN(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_RX_ADC_I_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_RX_ADC_I_EN_OVRD_EN_MASK)
10941 #define XCVR_TSM_OVRD1_RX_ADC_I_EN_OVRD_MASK     (0x800000U)
10942 #define XCVR_TSM_OVRD1_RX_ADC_I_EN_OVRD_SHIFT    (23U)
10943 #define XCVR_TSM_OVRD1_RX_ADC_I_EN_OVRD(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_RX_ADC_I_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_RX_ADC_I_EN_OVRD_MASK)
10944 #define XCVR_TSM_OVRD1_RX_ADC_Q_EN_OVRD_EN_MASK  (0x1000000U)
10945 #define XCVR_TSM_OVRD1_RX_ADC_Q_EN_OVRD_EN_SHIFT (24U)
10946 #define XCVR_TSM_OVRD1_RX_ADC_Q_EN_OVRD_EN(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_RX_ADC_Q_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_RX_ADC_Q_EN_OVRD_EN_MASK)
10947 #define XCVR_TSM_OVRD1_RX_ADC_Q_EN_OVRD_MASK     (0x2000000U)
10948 #define XCVR_TSM_OVRD1_RX_ADC_Q_EN_OVRD_SHIFT    (25U)
10949 #define XCVR_TSM_OVRD1_RX_ADC_Q_EN_OVRD(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_RX_ADC_Q_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_RX_ADC_Q_EN_OVRD_MASK)
10950 #define XCVR_TSM_OVRD1_RX_ADC_RESET_EN_OVRD_EN_MASK (0x4000000U)
10951 #define XCVR_TSM_OVRD1_RX_ADC_RESET_EN_OVRD_EN_SHIFT (26U)
10952 #define XCVR_TSM_OVRD1_RX_ADC_RESET_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_RX_ADC_RESET_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_RX_ADC_RESET_EN_OVRD_EN_MASK)
10953 #define XCVR_TSM_OVRD1_RX_ADC_RESET_EN_OVRD_MASK (0x8000000U)
10954 #define XCVR_TSM_OVRD1_RX_ADC_RESET_EN_OVRD_SHIFT (27U)
10955 #define XCVR_TSM_OVRD1_RX_ADC_RESET_EN_OVRD(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_RX_ADC_RESET_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_RX_ADC_RESET_EN_OVRD_MASK)
10956 #define XCVR_TSM_OVRD1_RX_BBA_I_EN_OVRD_EN_MASK  (0x10000000U)
10957 #define XCVR_TSM_OVRD1_RX_BBA_I_EN_OVRD_EN_SHIFT (28U)
10958 #define XCVR_TSM_OVRD1_RX_BBA_I_EN_OVRD_EN(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_RX_BBA_I_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_RX_BBA_I_EN_OVRD_EN_MASK)
10959 #define XCVR_TSM_OVRD1_RX_BBA_I_EN_OVRD_MASK     (0x20000000U)
10960 #define XCVR_TSM_OVRD1_RX_BBA_I_EN_OVRD_SHIFT    (29U)
10961 #define XCVR_TSM_OVRD1_RX_BBA_I_EN_OVRD(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_RX_BBA_I_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_RX_BBA_I_EN_OVRD_MASK)
10962 #define XCVR_TSM_OVRD1_RX_BBA_Q_EN_OVRD_EN_MASK  (0x40000000U)
10963 #define XCVR_TSM_OVRD1_RX_BBA_Q_EN_OVRD_EN_SHIFT (30U)
10964 #define XCVR_TSM_OVRD1_RX_BBA_Q_EN_OVRD_EN(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_RX_BBA_Q_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_RX_BBA_Q_EN_OVRD_EN_MASK)
10965 #define XCVR_TSM_OVRD1_RX_BBA_Q_EN_OVRD_MASK     (0x80000000U)
10966 #define XCVR_TSM_OVRD1_RX_BBA_Q_EN_OVRD_SHIFT    (31U)
10967 #define XCVR_TSM_OVRD1_RX_BBA_Q_EN_OVRD(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_RX_BBA_Q_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_RX_BBA_Q_EN_OVRD_MASK)
10968 
10969 /*! @name OVRD2 - TSM OVERRIDE REGISTER 2 */
10970 #define XCVR_TSM_OVRD2_RX_BBA_PDET_EN_OVRD_EN_MASK (0x1U)
10971 #define XCVR_TSM_OVRD2_RX_BBA_PDET_EN_OVRD_EN_SHIFT (0U)
10972 #define XCVR_TSM_OVRD2_RX_BBA_PDET_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_BBA_PDET_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_RX_BBA_PDET_EN_OVRD_EN_MASK)
10973 #define XCVR_TSM_OVRD2_RX_BBA_PDET_EN_OVRD_MASK  (0x2U)
10974 #define XCVR_TSM_OVRD2_RX_BBA_PDET_EN_OVRD_SHIFT (1U)
10975 #define XCVR_TSM_OVRD2_RX_BBA_PDET_EN_OVRD(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_BBA_PDET_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_RX_BBA_PDET_EN_OVRD_MASK)
10976 #define XCVR_TSM_OVRD2_RX_BBA_DCOC_EN_OVRD_EN_MASK (0x4U)
10977 #define XCVR_TSM_OVRD2_RX_BBA_DCOC_EN_OVRD_EN_SHIFT (2U)
10978 #define XCVR_TSM_OVRD2_RX_BBA_DCOC_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_BBA_DCOC_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_RX_BBA_DCOC_EN_OVRD_EN_MASK)
10979 #define XCVR_TSM_OVRD2_RX_BBA_DCOC_EN_OVRD_MASK  (0x8U)
10980 #define XCVR_TSM_OVRD2_RX_BBA_DCOC_EN_OVRD_SHIFT (3U)
10981 #define XCVR_TSM_OVRD2_RX_BBA_DCOC_EN_OVRD(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_BBA_DCOC_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_RX_BBA_DCOC_EN_OVRD_MASK)
10982 #define XCVR_TSM_OVRD2_RX_LNA_EN_OVRD_EN_MASK    (0x10U)
10983 #define XCVR_TSM_OVRD2_RX_LNA_EN_OVRD_EN_SHIFT   (4U)
10984 #define XCVR_TSM_OVRD2_RX_LNA_EN_OVRD_EN(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_LNA_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_RX_LNA_EN_OVRD_EN_MASK)
10985 #define XCVR_TSM_OVRD2_RX_LNA_EN_OVRD_MASK       (0x20U)
10986 #define XCVR_TSM_OVRD2_RX_LNA_EN_OVRD_SHIFT      (5U)
10987 #define XCVR_TSM_OVRD2_RX_LNA_EN_OVRD(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_LNA_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_RX_LNA_EN_OVRD_MASK)
10988 #define XCVR_TSM_OVRD2_RX_TZA_I_EN_OVRD_EN_MASK  (0x40U)
10989 #define XCVR_TSM_OVRD2_RX_TZA_I_EN_OVRD_EN_SHIFT (6U)
10990 #define XCVR_TSM_OVRD2_RX_TZA_I_EN_OVRD_EN(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_TZA_I_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_RX_TZA_I_EN_OVRD_EN_MASK)
10991 #define XCVR_TSM_OVRD2_RX_TZA_I_EN_OVRD_MASK     (0x80U)
10992 #define XCVR_TSM_OVRD2_RX_TZA_I_EN_OVRD_SHIFT    (7U)
10993 #define XCVR_TSM_OVRD2_RX_TZA_I_EN_OVRD(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_TZA_I_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_RX_TZA_I_EN_OVRD_MASK)
10994 #define XCVR_TSM_OVRD2_RX_TZA_Q_EN_OVRD_EN_MASK  (0x100U)
10995 #define XCVR_TSM_OVRD2_RX_TZA_Q_EN_OVRD_EN_SHIFT (8U)
10996 #define XCVR_TSM_OVRD2_RX_TZA_Q_EN_OVRD_EN(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_TZA_Q_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_RX_TZA_Q_EN_OVRD_EN_MASK)
10997 #define XCVR_TSM_OVRD2_RX_TZA_Q_EN_OVRD_MASK     (0x200U)
10998 #define XCVR_TSM_OVRD2_RX_TZA_Q_EN_OVRD_SHIFT    (9U)
10999 #define XCVR_TSM_OVRD2_RX_TZA_Q_EN_OVRD(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_TZA_Q_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_RX_TZA_Q_EN_OVRD_MASK)
11000 #define XCVR_TSM_OVRD2_RX_TZA_PDET_EN_OVRD_EN_MASK (0x400U)
11001 #define XCVR_TSM_OVRD2_RX_TZA_PDET_EN_OVRD_EN_SHIFT (10U)
11002 #define XCVR_TSM_OVRD2_RX_TZA_PDET_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_TZA_PDET_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_RX_TZA_PDET_EN_OVRD_EN_MASK)
11003 #define XCVR_TSM_OVRD2_RX_TZA_PDET_EN_OVRD_MASK  (0x800U)
11004 #define XCVR_TSM_OVRD2_RX_TZA_PDET_EN_OVRD_SHIFT (11U)
11005 #define XCVR_TSM_OVRD2_RX_TZA_PDET_EN_OVRD(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_TZA_PDET_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_RX_TZA_PDET_EN_OVRD_MASK)
11006 #define XCVR_TSM_OVRD2_RX_TZA_DCOC_EN_OVRD_EN_MASK (0x1000U)
11007 #define XCVR_TSM_OVRD2_RX_TZA_DCOC_EN_OVRD_EN_SHIFT (12U)
11008 #define XCVR_TSM_OVRD2_RX_TZA_DCOC_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_TZA_DCOC_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_RX_TZA_DCOC_EN_OVRD_EN_MASK)
11009 #define XCVR_TSM_OVRD2_RX_TZA_DCOC_EN_OVRD_MASK  (0x2000U)
11010 #define XCVR_TSM_OVRD2_RX_TZA_DCOC_EN_OVRD_SHIFT (13U)
11011 #define XCVR_TSM_OVRD2_RX_TZA_DCOC_EN_OVRD(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_TZA_DCOC_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_RX_TZA_DCOC_EN_OVRD_MASK)
11012 #define XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD_EN_MASK   (0x4000U)
11013 #define XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD_EN_SHIFT  (14U)
11014 #define XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD_EN(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD_EN_MASK)
11015 #define XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD_MASK      (0x8000U)
11016 #define XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD_SHIFT     (15U)
11017 #define XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD_MASK)
11018 #define XCVR_TSM_OVRD2_TX_DIG_EN_OVRD_EN_MASK    (0x10000U)
11019 #define XCVR_TSM_OVRD2_TX_DIG_EN_OVRD_EN_SHIFT   (16U)
11020 #define XCVR_TSM_OVRD2_TX_DIG_EN_OVRD_EN(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_TX_DIG_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_TX_DIG_EN_OVRD_EN_MASK)
11021 #define XCVR_TSM_OVRD2_TX_DIG_EN_OVRD_MASK       (0x20000U)
11022 #define XCVR_TSM_OVRD2_TX_DIG_EN_OVRD_SHIFT      (17U)
11023 #define XCVR_TSM_OVRD2_TX_DIG_EN_OVRD(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_TX_DIG_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_TX_DIG_EN_OVRD_MASK)
11024 #define XCVR_TSM_OVRD2_RX_DIG_EN_OVRD_EN_MASK    (0x40000U)
11025 #define XCVR_TSM_OVRD2_RX_DIG_EN_OVRD_EN_SHIFT   (18U)
11026 #define XCVR_TSM_OVRD2_RX_DIG_EN_OVRD_EN(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_DIG_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_RX_DIG_EN_OVRD_EN_MASK)
11027 #define XCVR_TSM_OVRD2_RX_DIG_EN_OVRD_MASK       (0x80000U)
11028 #define XCVR_TSM_OVRD2_RX_DIG_EN_OVRD_SHIFT      (19U)
11029 #define XCVR_TSM_OVRD2_RX_DIG_EN_OVRD(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_DIG_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_RX_DIG_EN_OVRD_MASK)
11030 #define XCVR_TSM_OVRD2_RX_INIT_OVRD_EN_MASK      (0x100000U)
11031 #define XCVR_TSM_OVRD2_RX_INIT_OVRD_EN_SHIFT     (20U)
11032 #define XCVR_TSM_OVRD2_RX_INIT_OVRD_EN(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_INIT_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_RX_INIT_OVRD_EN_MASK)
11033 #define XCVR_TSM_OVRD2_RX_INIT_OVRD_MASK         (0x200000U)
11034 #define XCVR_TSM_OVRD2_RX_INIT_OVRD_SHIFT        (21U)
11035 #define XCVR_TSM_OVRD2_RX_INIT_OVRD(x)           (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_INIT_OVRD_SHIFT)) & XCVR_TSM_OVRD2_RX_INIT_OVRD_MASK)
11036 #define XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_EN_MASK (0x400000U)
11037 #define XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_EN_SHIFT (22U)
11038 #define XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_EN_MASK)
11039 #define XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_MASK  (0x800000U)
11040 #define XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_SHIFT (23U)
11041 #define XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_MASK)
11042 #define XCVR_TSM_OVRD2_RX_PHY_EN_OVRD_EN_MASK    (0x1000000U)
11043 #define XCVR_TSM_OVRD2_RX_PHY_EN_OVRD_EN_SHIFT   (24U)
11044 #define XCVR_TSM_OVRD2_RX_PHY_EN_OVRD_EN(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_PHY_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_RX_PHY_EN_OVRD_EN_MASK)
11045 #define XCVR_TSM_OVRD2_RX_PHY_EN_OVRD_MASK       (0x2000000U)
11046 #define XCVR_TSM_OVRD2_RX_PHY_EN_OVRD_SHIFT      (25U)
11047 #define XCVR_TSM_OVRD2_RX_PHY_EN_OVRD(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_PHY_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_RX_PHY_EN_OVRD_MASK)
11048 #define XCVR_TSM_OVRD2_DCOC_EN_OVRD_EN_MASK      (0x4000000U)
11049 #define XCVR_TSM_OVRD2_DCOC_EN_OVRD_EN_SHIFT     (26U)
11050 #define XCVR_TSM_OVRD2_DCOC_EN_OVRD_EN(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_DCOC_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_DCOC_EN_OVRD_EN_MASK)
11051 #define XCVR_TSM_OVRD2_DCOC_EN_OVRD_MASK         (0x8000000U)
11052 #define XCVR_TSM_OVRD2_DCOC_EN_OVRD_SHIFT        (27U)
11053 #define XCVR_TSM_OVRD2_DCOC_EN_OVRD(x)           (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_DCOC_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_DCOC_EN_OVRD_MASK)
11054 #define XCVR_TSM_OVRD2_DCOC_INIT_OVRD_EN_MASK    (0x10000000U)
11055 #define XCVR_TSM_OVRD2_DCOC_INIT_OVRD_EN_SHIFT   (28U)
11056 #define XCVR_TSM_OVRD2_DCOC_INIT_OVRD_EN(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_DCOC_INIT_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_DCOC_INIT_OVRD_EN_MASK)
11057 #define XCVR_TSM_OVRD2_DCOC_INIT_OVRD_MASK       (0x20000000U)
11058 #define XCVR_TSM_OVRD2_DCOC_INIT_OVRD_SHIFT      (29U)
11059 #define XCVR_TSM_OVRD2_DCOC_INIT_OVRD(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_DCOC_INIT_OVRD_SHIFT)) & XCVR_TSM_OVRD2_DCOC_INIT_OVRD_MASK)
11060 #define XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_EN_MASK (0x40000000U)
11061 #define XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_EN_SHIFT (30U)
11062 #define XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_EN_MASK)
11063 #define XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_MASK (0x80000000U)
11064 #define XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_SHIFT (31U)
11065 #define XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_MASK)
11066 
11067 /*! @name OVRD3 - TSM OVERRIDE REGISTER 3 */
11068 #define XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_EN_MASK (0x1U)
11069 #define XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_EN_SHIFT (0U)
11070 #define XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_EN(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_EN_MASK)
11071 #define XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_MASK   (0x2U)
11072 #define XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_SHIFT  (1U)
11073 #define XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_MASK)
11074 #define XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_EN_MASK (0x4U)
11075 #define XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_EN_SHIFT (2U)
11076 #define XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_EN(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_EN_MASK)
11077 #define XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_MASK   (0x8U)
11078 #define XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_SHIFT  (3U)
11079 #define XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_MASK)
11080 #define XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_EN_MASK (0x10U)
11081 #define XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_EN_SHIFT (4U)
11082 #define XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_EN(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_EN_MASK)
11083 #define XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_MASK   (0x20U)
11084 #define XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_SHIFT  (5U)
11085 #define XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_MASK)
11086 #define XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_EN_MASK (0x40U)
11087 #define XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_EN_SHIFT (6U)
11088 #define XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_EN(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_EN_MASK)
11089 #define XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_MASK   (0x80U)
11090 #define XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_SHIFT  (7U)
11091 #define XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_MASK)
11092 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_BIAS_EN_OVRD_EN_MASK (0x100U)
11093 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_BIAS_EN_OVRD_EN_SHIFT (8U)
11094 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_BIAS_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_BIAS_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_BIAS_EN_OVRD_EN_MASK)
11095 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_BIAS_EN_OVRD_MASK (0x200U)
11096 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_BIAS_EN_OVRD_SHIFT (9U)
11097 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_BIAS_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_BIAS_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_BIAS_EN_OVRD_MASK)
11098 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_VCO_EN_OVRD_EN_MASK (0x400U)
11099 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_VCO_EN_OVRD_EN_SHIFT (10U)
11100 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_VCO_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_VCO_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_VCO_EN_OVRD_EN_MASK)
11101 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_VCO_EN_OVRD_MASK (0x800U)
11102 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_VCO_EN_OVRD_SHIFT (11U)
11103 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_VCO_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_VCO_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_VCO_EN_OVRD_MASK)
11104 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_FCAL_EN_OVRD_EN_MASK (0x1000U)
11105 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_FCAL_EN_OVRD_EN_SHIFT (12U)
11106 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_FCAL_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_FCAL_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_FCAL_EN_OVRD_EN_MASK)
11107 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_FCAL_EN_OVRD_MASK (0x2000U)
11108 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_FCAL_EN_OVRD_SHIFT (13U)
11109 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_FCAL_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_FCAL_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_FCAL_EN_OVRD_MASK)
11110 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_LF_EN_OVRD_EN_MASK (0x4000U)
11111 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_LF_EN_OVRD_EN_SHIFT (14U)
11112 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_LF_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_LF_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_LF_EN_OVRD_EN_MASK)
11113 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_LF_EN_OVRD_MASK (0x8000U)
11114 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_LF_EN_OVRD_SHIFT (15U)
11115 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_LF_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_LF_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_LF_EN_OVRD_MASK)
11116 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_EN_OVRD_EN_MASK (0x10000U)
11117 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_EN_OVRD_EN_SHIFT (16U)
11118 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_EN_OVRD_EN_MASK)
11119 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_EN_OVRD_MASK (0x20000U)
11120 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_EN_OVRD_SHIFT (17U)
11121 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_EN_OVRD_MASK)
11122 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_OVRD_EN_MASK (0x40000U)
11123 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_OVRD_EN_SHIFT (18U)
11124 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_OVRD_EN_MASK)
11125 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_OVRD_MASK (0x80000U)
11126 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_OVRD_SHIFT (19U)
11127 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_OVRD_MASK)
11128 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_ADC_BUF_EN_OVRD_EN_MASK (0x100000U)
11129 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_ADC_BUF_EN_OVRD_EN_SHIFT (20U)
11130 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_ADC_BUF_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_ADC_BUF_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_ADC_BUF_EN_OVRD_EN_MASK)
11131 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_ADC_BUF_EN_OVRD_MASK (0x200000U)
11132 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_ADC_BUF_EN_OVRD_SHIFT (21U)
11133 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_ADC_BUF_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_ADC_BUF_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_ADC_BUF_EN_OVRD_MASK)
11134 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_DIG_BUF_EN_OVRD_EN_MASK (0x400000U)
11135 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_DIG_BUF_EN_OVRD_EN_SHIFT (22U)
11136 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_DIG_BUF_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_DIG_BUF_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_DIG_BUF_EN_OVRD_EN_MASK)
11137 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_DIG_BUF_EN_OVRD_MASK (0x800000U)
11138 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_DIG_BUF_EN_OVRD_SHIFT (23U)
11139 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_DIG_BUF_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_DIG_BUF_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_DIG_BUF_EN_OVRD_MASK)
11140 #define XCVR_TSM_OVRD3_RXTX_RCCAL_EN_OVRD_EN_MASK (0x1000000U)
11141 #define XCVR_TSM_OVRD3_RXTX_RCCAL_EN_OVRD_EN_SHIFT (24U)
11142 #define XCVR_TSM_OVRD3_RXTX_RCCAL_EN_OVRD_EN(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_RCCAL_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_RXTX_RCCAL_EN_OVRD_EN_MASK)
11143 #define XCVR_TSM_OVRD3_RXTX_RCCAL_EN_OVRD_MASK   (0x2000000U)
11144 #define XCVR_TSM_OVRD3_RXTX_RCCAL_EN_OVRD_SHIFT  (25U)
11145 #define XCVR_TSM_OVRD3_RXTX_RCCAL_EN_OVRD(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_RCCAL_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_RXTX_RCCAL_EN_OVRD_MASK)
11146 #define XCVR_TSM_OVRD3_TX_HPM_DAC_EN_OVRD_EN_MASK (0x4000000U)
11147 #define XCVR_TSM_OVRD3_TX_HPM_DAC_EN_OVRD_EN_SHIFT (26U)
11148 #define XCVR_TSM_OVRD3_TX_HPM_DAC_EN_OVRD_EN(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_TX_HPM_DAC_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_TX_HPM_DAC_EN_OVRD_EN_MASK)
11149 #define XCVR_TSM_OVRD3_TX_HPM_DAC_EN_OVRD_MASK   (0x8000000U)
11150 #define XCVR_TSM_OVRD3_TX_HPM_DAC_EN_OVRD_SHIFT  (27U)
11151 #define XCVR_TSM_OVRD3_TX_HPM_DAC_EN_OVRD(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_TX_HPM_DAC_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_TX_HPM_DAC_EN_OVRD_MASK)
11152 #define XCVR_TSM_OVRD3_TX_MODE_OVRD_EN_MASK      (0x10000000U)
11153 #define XCVR_TSM_OVRD3_TX_MODE_OVRD_EN_SHIFT     (28U)
11154 #define XCVR_TSM_OVRD3_TX_MODE_OVRD_EN(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_TX_MODE_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_TX_MODE_OVRD_EN_MASK)
11155 #define XCVR_TSM_OVRD3_TX_MODE_OVRD_MASK         (0x20000000U)
11156 #define XCVR_TSM_OVRD3_TX_MODE_OVRD_SHIFT        (29U)
11157 #define XCVR_TSM_OVRD3_TX_MODE_OVRD(x)           (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_TX_MODE_OVRD_SHIFT)) & XCVR_TSM_OVRD3_TX_MODE_OVRD_MASK)
11158 #define XCVR_TSM_OVRD3_RX_MODE_OVRD_EN_MASK      (0x40000000U)
11159 #define XCVR_TSM_OVRD3_RX_MODE_OVRD_EN_SHIFT     (30U)
11160 #define XCVR_TSM_OVRD3_RX_MODE_OVRD_EN(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RX_MODE_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_RX_MODE_OVRD_EN_MASK)
11161 #define XCVR_TSM_OVRD3_RX_MODE_OVRD_MASK         (0x80000000U)
11162 #define XCVR_TSM_OVRD3_RX_MODE_OVRD_SHIFT        (31U)
11163 #define XCVR_TSM_OVRD3_RX_MODE_OVRD(x)           (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RX_MODE_OVRD_SHIFT)) & XCVR_TSM_OVRD3_RX_MODE_OVRD_MASK)
11164 
11165 /*! @name PA_POWER - PA POWER */
11166 #define XCVR_TSM_PA_POWER_PA_POWER_MASK          (0x3FU)
11167 #define XCVR_TSM_PA_POWER_PA_POWER_SHIFT         (0U)
11168 #define XCVR_TSM_PA_POWER_PA_POWER(x)            (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_PA_POWER_PA_POWER_SHIFT)) & XCVR_TSM_PA_POWER_PA_POWER_MASK)
11169 
11170 /*! @name PA_RAMP_TBL0 - PA RAMP TABLE 0 */
11171 #define XCVR_TSM_PA_RAMP_TBL0_PA_RAMP0_MASK      (0x3FU)
11172 #define XCVR_TSM_PA_RAMP_TBL0_PA_RAMP0_SHIFT     (0U)
11173 #define XCVR_TSM_PA_RAMP_TBL0_PA_RAMP0(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_PA_RAMP_TBL0_PA_RAMP0_SHIFT)) & XCVR_TSM_PA_RAMP_TBL0_PA_RAMP0_MASK)
11174 #define XCVR_TSM_PA_RAMP_TBL0_PA_RAMP1_MASK      (0x3F00U)
11175 #define XCVR_TSM_PA_RAMP_TBL0_PA_RAMP1_SHIFT     (8U)
11176 #define XCVR_TSM_PA_RAMP_TBL0_PA_RAMP1(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_PA_RAMP_TBL0_PA_RAMP1_SHIFT)) & XCVR_TSM_PA_RAMP_TBL0_PA_RAMP1_MASK)
11177 #define XCVR_TSM_PA_RAMP_TBL0_PA_RAMP2_MASK      (0x3F0000U)
11178 #define XCVR_TSM_PA_RAMP_TBL0_PA_RAMP2_SHIFT     (16U)
11179 #define XCVR_TSM_PA_RAMP_TBL0_PA_RAMP2(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_PA_RAMP_TBL0_PA_RAMP2_SHIFT)) & XCVR_TSM_PA_RAMP_TBL0_PA_RAMP2_MASK)
11180 #define XCVR_TSM_PA_RAMP_TBL0_PA_RAMP3_MASK      (0x3F000000U)
11181 #define XCVR_TSM_PA_RAMP_TBL0_PA_RAMP3_SHIFT     (24U)
11182 #define XCVR_TSM_PA_RAMP_TBL0_PA_RAMP3(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_PA_RAMP_TBL0_PA_RAMP3_SHIFT)) & XCVR_TSM_PA_RAMP_TBL0_PA_RAMP3_MASK)
11183 
11184 /*! @name PA_RAMP_TBL1 - PA RAMP TABLE 1 */
11185 #define XCVR_TSM_PA_RAMP_TBL1_PA_RAMP4_MASK      (0x3FU)
11186 #define XCVR_TSM_PA_RAMP_TBL1_PA_RAMP4_SHIFT     (0U)
11187 #define XCVR_TSM_PA_RAMP_TBL1_PA_RAMP4(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_PA_RAMP_TBL1_PA_RAMP4_SHIFT)) & XCVR_TSM_PA_RAMP_TBL1_PA_RAMP4_MASK)
11188 #define XCVR_TSM_PA_RAMP_TBL1_PA_RAMP5_MASK      (0x3F00U)
11189 #define XCVR_TSM_PA_RAMP_TBL1_PA_RAMP5_SHIFT     (8U)
11190 #define XCVR_TSM_PA_RAMP_TBL1_PA_RAMP5(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_PA_RAMP_TBL1_PA_RAMP5_SHIFT)) & XCVR_TSM_PA_RAMP_TBL1_PA_RAMP5_MASK)
11191 #define XCVR_TSM_PA_RAMP_TBL1_PA_RAMP6_MASK      (0x3F0000U)
11192 #define XCVR_TSM_PA_RAMP_TBL1_PA_RAMP6_SHIFT     (16U)
11193 #define XCVR_TSM_PA_RAMP_TBL1_PA_RAMP6(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_PA_RAMP_TBL1_PA_RAMP6_SHIFT)) & XCVR_TSM_PA_RAMP_TBL1_PA_RAMP6_MASK)
11194 #define XCVR_TSM_PA_RAMP_TBL1_PA_RAMP7_MASK      (0x3F000000U)
11195 #define XCVR_TSM_PA_RAMP_TBL1_PA_RAMP7_SHIFT     (24U)
11196 #define XCVR_TSM_PA_RAMP_TBL1_PA_RAMP7(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_PA_RAMP_TBL1_PA_RAMP7_SHIFT)) & XCVR_TSM_PA_RAMP_TBL1_PA_RAMP7_MASK)
11197 
11198 /*! @name RECYCLE_COUNT - TSM RECYCLE COUNT */
11199 #define XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT0_MASK (0xFFU)
11200 #define XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT0_SHIFT (0U)
11201 #define XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT0_SHIFT)) & XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT0_MASK)
11202 #define XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT1_MASK (0xFF00U)
11203 #define XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT1_SHIFT (8U)
11204 #define XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT1_SHIFT)) & XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT1_MASK)
11205 #define XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT2_MASK (0xFF0000U)
11206 #define XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT2_SHIFT (16U)
11207 #define XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT2_SHIFT)) & XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT2_MASK)
11208 
11209 /*! @name FAST_CTRL1 - TSM FAST WARMUP CONTROL REGISTER 1 */
11210 #define XCVR_TSM_FAST_CTRL1_FAST_TX_WU_EN_MASK   (0x1U)
11211 #define XCVR_TSM_FAST_CTRL1_FAST_TX_WU_EN_SHIFT  (0U)
11212 #define XCVR_TSM_FAST_CTRL1_FAST_TX_WU_EN(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_FAST_CTRL1_FAST_TX_WU_EN_SHIFT)) & XCVR_TSM_FAST_CTRL1_FAST_TX_WU_EN_MASK)
11213 #define XCVR_TSM_FAST_CTRL1_FAST_RX_WU_EN_MASK   (0x2U)
11214 #define XCVR_TSM_FAST_CTRL1_FAST_RX_WU_EN_SHIFT  (1U)
11215 #define XCVR_TSM_FAST_CTRL1_FAST_RX_WU_EN(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_FAST_CTRL1_FAST_RX_WU_EN_SHIFT)) & XCVR_TSM_FAST_CTRL1_FAST_RX_WU_EN_MASK)
11216 #define XCVR_TSM_FAST_CTRL1_FAST_RX2TX_EN_MASK   (0x4U)
11217 #define XCVR_TSM_FAST_CTRL1_FAST_RX2TX_EN_SHIFT  (2U)
11218 #define XCVR_TSM_FAST_CTRL1_FAST_RX2TX_EN(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_FAST_CTRL1_FAST_RX2TX_EN_SHIFT)) & XCVR_TSM_FAST_CTRL1_FAST_RX2TX_EN_MASK)
11219 #define XCVR_TSM_FAST_CTRL1_FAST_WU_CLEAR_MASK   (0x8U)
11220 #define XCVR_TSM_FAST_CTRL1_FAST_WU_CLEAR_SHIFT  (3U)
11221 #define XCVR_TSM_FAST_CTRL1_FAST_WU_CLEAR(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_FAST_CTRL1_FAST_WU_CLEAR_SHIFT)) & XCVR_TSM_FAST_CTRL1_FAST_WU_CLEAR_MASK)
11222 #define XCVR_TSM_FAST_CTRL1_FAST_RX2TX_START_MASK (0xFF00U)
11223 #define XCVR_TSM_FAST_CTRL1_FAST_RX2TX_START_SHIFT (8U)
11224 #define XCVR_TSM_FAST_CTRL1_FAST_RX2TX_START(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_FAST_CTRL1_FAST_RX2TX_START_SHIFT)) & XCVR_TSM_FAST_CTRL1_FAST_RX2TX_START_MASK)
11225 
11226 /*! @name FAST_CTRL2 - TSM FAST WARMUP CONTROL REGISTER 2 */
11227 #define XCVR_TSM_FAST_CTRL2_FAST_START_TX_MASK   (0xFFU)
11228 #define XCVR_TSM_FAST_CTRL2_FAST_START_TX_SHIFT  (0U)
11229 #define XCVR_TSM_FAST_CTRL2_FAST_START_TX(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_FAST_CTRL2_FAST_START_TX_SHIFT)) & XCVR_TSM_FAST_CTRL2_FAST_START_TX_MASK)
11230 #define XCVR_TSM_FAST_CTRL2_FAST_DEST_TX_MASK    (0xFF00U)
11231 #define XCVR_TSM_FAST_CTRL2_FAST_DEST_TX_SHIFT   (8U)
11232 #define XCVR_TSM_FAST_CTRL2_FAST_DEST_TX(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_FAST_CTRL2_FAST_DEST_TX_SHIFT)) & XCVR_TSM_FAST_CTRL2_FAST_DEST_TX_MASK)
11233 #define XCVR_TSM_FAST_CTRL2_FAST_START_RX_MASK   (0xFF0000U)
11234 #define XCVR_TSM_FAST_CTRL2_FAST_START_RX_SHIFT  (16U)
11235 #define XCVR_TSM_FAST_CTRL2_FAST_START_RX(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_FAST_CTRL2_FAST_START_RX_SHIFT)) & XCVR_TSM_FAST_CTRL2_FAST_START_RX_MASK)
11236 #define XCVR_TSM_FAST_CTRL2_FAST_DEST_RX_MASK    (0xFF000000U)
11237 #define XCVR_TSM_FAST_CTRL2_FAST_DEST_RX_SHIFT   (24U)
11238 #define XCVR_TSM_FAST_CTRL2_FAST_DEST_RX(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_FAST_CTRL2_FAST_DEST_RX_SHIFT)) & XCVR_TSM_FAST_CTRL2_FAST_DEST_RX_MASK)
11239 
11240 /*! @name TIMING00 - TSM_TIMING00 */
11241 #define XCVR_TSM_TIMING00_BB_LDO_HF_EN_TX_HI_MASK (0xFFU)
11242 #define XCVR_TSM_TIMING00_BB_LDO_HF_EN_TX_HI_SHIFT (0U)
11243 #define XCVR_TSM_TIMING00_BB_LDO_HF_EN_TX_HI(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING00_BB_LDO_HF_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING00_BB_LDO_HF_EN_TX_HI_MASK)
11244 #define XCVR_TSM_TIMING00_BB_LDO_HF_EN_TX_LO_MASK (0xFF00U)
11245 #define XCVR_TSM_TIMING00_BB_LDO_HF_EN_TX_LO_SHIFT (8U)
11246 #define XCVR_TSM_TIMING00_BB_LDO_HF_EN_TX_LO(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING00_BB_LDO_HF_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING00_BB_LDO_HF_EN_TX_LO_MASK)
11247 #define XCVR_TSM_TIMING00_BB_LDO_HF_EN_RX_HI_MASK (0xFF0000U)
11248 #define XCVR_TSM_TIMING00_BB_LDO_HF_EN_RX_HI_SHIFT (16U)
11249 #define XCVR_TSM_TIMING00_BB_LDO_HF_EN_RX_HI(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING00_BB_LDO_HF_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING00_BB_LDO_HF_EN_RX_HI_MASK)
11250 #define XCVR_TSM_TIMING00_BB_LDO_HF_EN_RX_LO_MASK (0xFF000000U)
11251 #define XCVR_TSM_TIMING00_BB_LDO_HF_EN_RX_LO_SHIFT (24U)
11252 #define XCVR_TSM_TIMING00_BB_LDO_HF_EN_RX_LO(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING00_BB_LDO_HF_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING00_BB_LDO_HF_EN_RX_LO_MASK)
11253 
11254 /*! @name TIMING01 - TSM_TIMING01 */
11255 #define XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_TX_HI_MASK (0xFFU)
11256 #define XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_TX_HI_SHIFT (0U)
11257 #define XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_TX_HI_MASK)
11258 #define XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_TX_LO_MASK (0xFF00U)
11259 #define XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_TX_LO_SHIFT (8U)
11260 #define XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_TX_LO_MASK)
11261 #define XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_RX_HI_MASK (0xFF0000U)
11262 #define XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_RX_HI_SHIFT (16U)
11263 #define XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_RX_HI_MASK)
11264 #define XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_RX_LO_MASK (0xFF000000U)
11265 #define XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_RX_LO_SHIFT (24U)
11266 #define XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_RX_LO_MASK)
11267 
11268 /*! @name TIMING02 - TSM_TIMING02 */
11269 #define XCVR_TSM_TIMING02_BB_LDO_BBA_EN_RX_HI_MASK (0xFF0000U)
11270 #define XCVR_TSM_TIMING02_BB_LDO_BBA_EN_RX_HI_SHIFT (16U)
11271 #define XCVR_TSM_TIMING02_BB_LDO_BBA_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING02_BB_LDO_BBA_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING02_BB_LDO_BBA_EN_RX_HI_MASK)
11272 #define XCVR_TSM_TIMING02_BB_LDO_BBA_EN_RX_LO_MASK (0xFF000000U)
11273 #define XCVR_TSM_TIMING02_BB_LDO_BBA_EN_RX_LO_SHIFT (24U)
11274 #define XCVR_TSM_TIMING02_BB_LDO_BBA_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING02_BB_LDO_BBA_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING02_BB_LDO_BBA_EN_RX_LO_MASK)
11275 
11276 /*! @name TIMING03 - TSM_TIMING03 */
11277 #define XCVR_TSM_TIMING03_BB_LDO_PD_EN_TX_HI_MASK (0xFFU)
11278 #define XCVR_TSM_TIMING03_BB_LDO_PD_EN_TX_HI_SHIFT (0U)
11279 #define XCVR_TSM_TIMING03_BB_LDO_PD_EN_TX_HI(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING03_BB_LDO_PD_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING03_BB_LDO_PD_EN_TX_HI_MASK)
11280 #define XCVR_TSM_TIMING03_BB_LDO_PD_EN_TX_LO_MASK (0xFF00U)
11281 #define XCVR_TSM_TIMING03_BB_LDO_PD_EN_TX_LO_SHIFT (8U)
11282 #define XCVR_TSM_TIMING03_BB_LDO_PD_EN_TX_LO(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING03_BB_LDO_PD_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING03_BB_LDO_PD_EN_TX_LO_MASK)
11283 #define XCVR_TSM_TIMING03_BB_LDO_PD_EN_RX_HI_MASK (0xFF0000U)
11284 #define XCVR_TSM_TIMING03_BB_LDO_PD_EN_RX_HI_SHIFT (16U)
11285 #define XCVR_TSM_TIMING03_BB_LDO_PD_EN_RX_HI(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING03_BB_LDO_PD_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING03_BB_LDO_PD_EN_RX_HI_MASK)
11286 #define XCVR_TSM_TIMING03_BB_LDO_PD_EN_RX_LO_MASK (0xFF000000U)
11287 #define XCVR_TSM_TIMING03_BB_LDO_PD_EN_RX_LO_SHIFT (24U)
11288 #define XCVR_TSM_TIMING03_BB_LDO_PD_EN_RX_LO(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING03_BB_LDO_PD_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING03_BB_LDO_PD_EN_RX_LO_MASK)
11289 
11290 /*! @name TIMING04 - TSM_TIMING04 */
11291 #define XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_TX_HI_MASK (0xFFU)
11292 #define XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_TX_HI_SHIFT (0U)
11293 #define XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_TX_HI_MASK)
11294 #define XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_TX_LO_MASK (0xFF00U)
11295 #define XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_TX_LO_SHIFT (8U)
11296 #define XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_TX_LO_MASK)
11297 #define XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_RX_HI_MASK (0xFF0000U)
11298 #define XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_RX_HI_SHIFT (16U)
11299 #define XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_RX_HI_MASK)
11300 #define XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_RX_LO_MASK (0xFF000000U)
11301 #define XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_RX_LO_SHIFT (24U)
11302 #define XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_RX_LO_MASK)
11303 
11304 /*! @name TIMING05 - TSM_TIMING05 */
11305 #define XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_TX_HI_MASK (0xFFU)
11306 #define XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_TX_HI_SHIFT (0U)
11307 #define XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_TX_HI_MASK)
11308 #define XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_TX_LO_MASK (0xFF00U)
11309 #define XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_TX_LO_SHIFT (8U)
11310 #define XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_TX_LO_MASK)
11311 #define XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_RX_HI_MASK (0xFF0000U)
11312 #define XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_RX_HI_SHIFT (16U)
11313 #define XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_RX_HI_MASK)
11314 #define XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_RX_LO_MASK (0xFF000000U)
11315 #define XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_RX_LO_SHIFT (24U)
11316 #define XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_RX_LO_MASK)
11317 
11318 /*! @name TIMING06 - TSM_TIMING06 */
11319 #define XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_TX_HI_MASK (0xFFU)
11320 #define XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_TX_HI_SHIFT (0U)
11321 #define XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_TX_HI_MASK)
11322 #define XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_TX_LO_MASK (0xFF00U)
11323 #define XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_TX_LO_SHIFT (8U)
11324 #define XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_TX_LO_MASK)
11325 #define XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_RX_HI_MASK (0xFF0000U)
11326 #define XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_RX_HI_SHIFT (16U)
11327 #define XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_RX_HI_MASK)
11328 #define XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_RX_LO_MASK (0xFF000000U)
11329 #define XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_RX_LO_SHIFT (24U)
11330 #define XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_RX_LO_MASK)
11331 
11332 /*! @name TIMING07 - TSM_TIMING07 */
11333 #define XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_TX_HI_MASK (0xFFU)
11334 #define XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_TX_HI_SHIFT (0U)
11335 #define XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_TX_HI_MASK)
11336 #define XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_TX_LO_MASK (0xFF00U)
11337 #define XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_TX_LO_SHIFT (8U)
11338 #define XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_TX_LO_MASK)
11339 #define XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_RX_HI_MASK (0xFF0000U)
11340 #define XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_RX_HI_SHIFT (16U)
11341 #define XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_RX_HI_MASK)
11342 #define XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_RX_LO_MASK (0xFF000000U)
11343 #define XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_RX_LO_SHIFT (24U)
11344 #define XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_RX_LO_MASK)
11345 
11346 /*! @name TIMING08 - TSM_TIMING08 */
11347 #define XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_TX_HI_MASK (0xFFU)
11348 #define XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_TX_HI_SHIFT (0U)
11349 #define XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_TX_HI_MASK)
11350 #define XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_TX_LO_MASK (0xFF00U)
11351 #define XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_TX_LO_SHIFT (8U)
11352 #define XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_TX_LO_MASK)
11353 #define XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_RX_HI_MASK (0xFF0000U)
11354 #define XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_RX_HI_SHIFT (16U)
11355 #define XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_RX_HI_MASK)
11356 #define XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_RX_LO_MASK (0xFF000000U)
11357 #define XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_RX_LO_SHIFT (24U)
11358 #define XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_RX_LO_MASK)
11359 
11360 /*! @name TIMING09 - TSM_TIMING09 */
11361 #define XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_TX_HI_MASK (0xFFU)
11362 #define XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_TX_HI_SHIFT (0U)
11363 #define XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_TX_HI_MASK)
11364 #define XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_TX_LO_MASK (0xFF00U)
11365 #define XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_TX_LO_SHIFT (8U)
11366 #define XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_TX_LO_MASK)
11367 #define XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_RX_HI_MASK (0xFF0000U)
11368 #define XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_RX_HI_SHIFT (16U)
11369 #define XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_RX_HI_MASK)
11370 #define XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_RX_LO_MASK (0xFF000000U)
11371 #define XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_RX_LO_SHIFT (24U)
11372 #define XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_RX_LO_MASK)
11373 
11374 /*! @name TIMING10 - TSM_TIMING10 */
11375 #define XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_TX_HI_MASK (0xFFU)
11376 #define XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_TX_HI_SHIFT (0U)
11377 #define XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_TX_HI_MASK)
11378 #define XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_TX_LO_MASK (0xFF00U)
11379 #define XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_TX_LO_SHIFT (8U)
11380 #define XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_TX_LO_MASK)
11381 #define XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_RX_HI_MASK (0xFF0000U)
11382 #define XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_RX_HI_SHIFT (16U)
11383 #define XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_RX_HI_MASK)
11384 #define XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_RX_LO_MASK (0xFF000000U)
11385 #define XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_RX_LO_SHIFT (24U)
11386 #define XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_RX_LO_MASK)
11387 
11388 /*! @name TIMING11 - TSM_TIMING11 */
11389 #define XCVR_TSM_TIMING11_BB_XTAL_DAC_REF_CLK_EN_TX_HI_MASK (0xFFU)
11390 #define XCVR_TSM_TIMING11_BB_XTAL_DAC_REF_CLK_EN_TX_HI_SHIFT (0U)
11391 #define XCVR_TSM_TIMING11_BB_XTAL_DAC_REF_CLK_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING11_BB_XTAL_DAC_REF_CLK_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING11_BB_XTAL_DAC_REF_CLK_EN_TX_HI_MASK)
11392 #define XCVR_TSM_TIMING11_BB_XTAL_DAC_REF_CLK_EN_TX_LO_MASK (0xFF00U)
11393 #define XCVR_TSM_TIMING11_BB_XTAL_DAC_REF_CLK_EN_TX_LO_SHIFT (8U)
11394 #define XCVR_TSM_TIMING11_BB_XTAL_DAC_REF_CLK_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING11_BB_XTAL_DAC_REF_CLK_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING11_BB_XTAL_DAC_REF_CLK_EN_TX_LO_MASK)
11395 
11396 /*! @name TIMING12 - TSM_TIMING12 */
11397 #define XCVR_TSM_TIMING12_RXTX_AUXPLL_VCO_REF_CLK_EN_RX_HI_MASK (0xFF0000U)
11398 #define XCVR_TSM_TIMING12_RXTX_AUXPLL_VCO_REF_CLK_EN_RX_HI_SHIFT (16U)
11399 #define XCVR_TSM_TIMING12_RXTX_AUXPLL_VCO_REF_CLK_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING12_RXTX_AUXPLL_VCO_REF_CLK_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING12_RXTX_AUXPLL_VCO_REF_CLK_EN_RX_HI_MASK)
11400 #define XCVR_TSM_TIMING12_RXTX_AUXPLL_VCO_REF_CLK_EN_RX_LO_MASK (0xFF000000U)
11401 #define XCVR_TSM_TIMING12_RXTX_AUXPLL_VCO_REF_CLK_EN_RX_LO_SHIFT (24U)
11402 #define XCVR_TSM_TIMING12_RXTX_AUXPLL_VCO_REF_CLK_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING12_RXTX_AUXPLL_VCO_REF_CLK_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING12_RXTX_AUXPLL_VCO_REF_CLK_EN_RX_LO_MASK)
11403 
11404 /*! @name TIMING13 - TSM_TIMING13 */
11405 #define XCVR_TSM_TIMING13_SY_VCO_AUTOTUNE_EN_TX_HI_MASK (0xFFU)
11406 #define XCVR_TSM_TIMING13_SY_VCO_AUTOTUNE_EN_TX_HI_SHIFT (0U)
11407 #define XCVR_TSM_TIMING13_SY_VCO_AUTOTUNE_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING13_SY_VCO_AUTOTUNE_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING13_SY_VCO_AUTOTUNE_EN_TX_HI_MASK)
11408 #define XCVR_TSM_TIMING13_SY_VCO_AUTOTUNE_EN_TX_LO_MASK (0xFF00U)
11409 #define XCVR_TSM_TIMING13_SY_VCO_AUTOTUNE_EN_TX_LO_SHIFT (8U)
11410 #define XCVR_TSM_TIMING13_SY_VCO_AUTOTUNE_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING13_SY_VCO_AUTOTUNE_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING13_SY_VCO_AUTOTUNE_EN_TX_LO_MASK)
11411 #define XCVR_TSM_TIMING13_SY_VCO_AUTOTUNE_EN_RX_HI_MASK (0xFF0000U)
11412 #define XCVR_TSM_TIMING13_SY_VCO_AUTOTUNE_EN_RX_HI_SHIFT (16U)
11413 #define XCVR_TSM_TIMING13_SY_VCO_AUTOTUNE_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING13_SY_VCO_AUTOTUNE_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING13_SY_VCO_AUTOTUNE_EN_RX_HI_MASK)
11414 #define XCVR_TSM_TIMING13_SY_VCO_AUTOTUNE_EN_RX_LO_MASK (0xFF000000U)
11415 #define XCVR_TSM_TIMING13_SY_VCO_AUTOTUNE_EN_RX_LO_SHIFT (24U)
11416 #define XCVR_TSM_TIMING13_SY_VCO_AUTOTUNE_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING13_SY_VCO_AUTOTUNE_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING13_SY_VCO_AUTOTUNE_EN_RX_LO_MASK)
11417 
11418 /*! @name TIMING14 - TSM_TIMING14 */
11419 #define XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_TX_HI_MASK (0xFFU)
11420 #define XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_TX_HI_SHIFT (0U)
11421 #define XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_TX_HI_MASK)
11422 #define XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_TX_LO_MASK (0xFF00U)
11423 #define XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_TX_LO_SHIFT (8U)
11424 #define XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_TX_LO_MASK)
11425 #define XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_RX_HI_MASK (0xFF0000U)
11426 #define XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_RX_HI_SHIFT (16U)
11427 #define XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_RX_HI_MASK)
11428 #define XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_RX_LO_MASK (0xFF000000U)
11429 #define XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_RX_LO_SHIFT (24U)
11430 #define XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_RX_LO_MASK)
11431 
11432 /*! @name TIMING15 - TSM_TIMING15 */
11433 #define XCVR_TSM_TIMING15_SY_VCO_EN_TX_HI_MASK   (0xFFU)
11434 #define XCVR_TSM_TIMING15_SY_VCO_EN_TX_HI_SHIFT  (0U)
11435 #define XCVR_TSM_TIMING15_SY_VCO_EN_TX_HI(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING15_SY_VCO_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING15_SY_VCO_EN_TX_HI_MASK)
11436 #define XCVR_TSM_TIMING15_SY_VCO_EN_TX_LO_MASK   (0xFF00U)
11437 #define XCVR_TSM_TIMING15_SY_VCO_EN_TX_LO_SHIFT  (8U)
11438 #define XCVR_TSM_TIMING15_SY_VCO_EN_TX_LO(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING15_SY_VCO_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING15_SY_VCO_EN_TX_LO_MASK)
11439 #define XCVR_TSM_TIMING15_SY_VCO_EN_RX_HI_MASK   (0xFF0000U)
11440 #define XCVR_TSM_TIMING15_SY_VCO_EN_RX_HI_SHIFT  (16U)
11441 #define XCVR_TSM_TIMING15_SY_VCO_EN_RX_HI(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING15_SY_VCO_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING15_SY_VCO_EN_RX_HI_MASK)
11442 #define XCVR_TSM_TIMING15_SY_VCO_EN_RX_LO_MASK   (0xFF000000U)
11443 #define XCVR_TSM_TIMING15_SY_VCO_EN_RX_LO_SHIFT  (24U)
11444 #define XCVR_TSM_TIMING15_SY_VCO_EN_RX_LO(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING15_SY_VCO_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING15_SY_VCO_EN_RX_LO_MASK)
11445 
11446 /*! @name TIMING16 - TSM_TIMING16 */
11447 #define XCVR_TSM_TIMING16_SY_LO_RX_BUF_EN_RX_HI_MASK (0xFF0000U)
11448 #define XCVR_TSM_TIMING16_SY_LO_RX_BUF_EN_RX_HI_SHIFT (16U)
11449 #define XCVR_TSM_TIMING16_SY_LO_RX_BUF_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING16_SY_LO_RX_BUF_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING16_SY_LO_RX_BUF_EN_RX_HI_MASK)
11450 #define XCVR_TSM_TIMING16_SY_LO_RX_BUF_EN_RX_LO_MASK (0xFF000000U)
11451 #define XCVR_TSM_TIMING16_SY_LO_RX_BUF_EN_RX_LO_SHIFT (24U)
11452 #define XCVR_TSM_TIMING16_SY_LO_RX_BUF_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING16_SY_LO_RX_BUF_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING16_SY_LO_RX_BUF_EN_RX_LO_MASK)
11453 
11454 /*! @name TIMING17 - TSM_TIMING17 */
11455 #define XCVR_TSM_TIMING17_SY_LO_TX_BUF_EN_TX_HI_MASK (0xFFU)
11456 #define XCVR_TSM_TIMING17_SY_LO_TX_BUF_EN_TX_HI_SHIFT (0U)
11457 #define XCVR_TSM_TIMING17_SY_LO_TX_BUF_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING17_SY_LO_TX_BUF_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING17_SY_LO_TX_BUF_EN_TX_HI_MASK)
11458 #define XCVR_TSM_TIMING17_SY_LO_TX_BUF_EN_TX_LO_MASK (0xFF00U)
11459 #define XCVR_TSM_TIMING17_SY_LO_TX_BUF_EN_TX_LO_SHIFT (8U)
11460 #define XCVR_TSM_TIMING17_SY_LO_TX_BUF_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING17_SY_LO_TX_BUF_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING17_SY_LO_TX_BUF_EN_TX_LO_MASK)
11461 
11462 /*! @name TIMING18 - TSM_TIMING18 */
11463 #define XCVR_TSM_TIMING18_SY_DIVN_EN_TX_HI_MASK  (0xFFU)
11464 #define XCVR_TSM_TIMING18_SY_DIVN_EN_TX_HI_SHIFT (0U)
11465 #define XCVR_TSM_TIMING18_SY_DIVN_EN_TX_HI(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING18_SY_DIVN_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING18_SY_DIVN_EN_TX_HI_MASK)
11466 #define XCVR_TSM_TIMING18_SY_DIVN_EN_TX_LO_MASK  (0xFF00U)
11467 #define XCVR_TSM_TIMING18_SY_DIVN_EN_TX_LO_SHIFT (8U)
11468 #define XCVR_TSM_TIMING18_SY_DIVN_EN_TX_LO(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING18_SY_DIVN_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING18_SY_DIVN_EN_TX_LO_MASK)
11469 #define XCVR_TSM_TIMING18_SY_DIVN_EN_RX_HI_MASK  (0xFF0000U)
11470 #define XCVR_TSM_TIMING18_SY_DIVN_EN_RX_HI_SHIFT (16U)
11471 #define XCVR_TSM_TIMING18_SY_DIVN_EN_RX_HI(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING18_SY_DIVN_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING18_SY_DIVN_EN_RX_HI_MASK)
11472 #define XCVR_TSM_TIMING18_SY_DIVN_EN_RX_LO_MASK  (0xFF000000U)
11473 #define XCVR_TSM_TIMING18_SY_DIVN_EN_RX_LO_SHIFT (24U)
11474 #define XCVR_TSM_TIMING18_SY_DIVN_EN_RX_LO(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING18_SY_DIVN_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING18_SY_DIVN_EN_RX_LO_MASK)
11475 
11476 /*! @name TIMING19 - TSM_TIMING19 */
11477 #define XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_TX_HI_MASK (0xFFU)
11478 #define XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_TX_HI_SHIFT (0U)
11479 #define XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_TX_HI_MASK)
11480 #define XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_TX_LO_MASK (0xFF00U)
11481 #define XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_TX_LO_SHIFT (8U)
11482 #define XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_TX_LO_MASK)
11483 #define XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_RX_HI_MASK (0xFF0000U)
11484 #define XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_RX_HI_SHIFT (16U)
11485 #define XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_RX_HI_MASK)
11486 #define XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_RX_LO_MASK (0xFF000000U)
11487 #define XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_RX_LO_SHIFT (24U)
11488 #define XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_RX_LO_MASK)
11489 
11490 /*! @name TIMING20 - TSM_TIMING20 */
11491 #define XCVR_TSM_TIMING20_SY_PD_EN_TX_HI_MASK    (0xFFU)
11492 #define XCVR_TSM_TIMING20_SY_PD_EN_TX_HI_SHIFT   (0U)
11493 #define XCVR_TSM_TIMING20_SY_PD_EN_TX_HI(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING20_SY_PD_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING20_SY_PD_EN_TX_HI_MASK)
11494 #define XCVR_TSM_TIMING20_SY_PD_EN_TX_LO_MASK    (0xFF00U)
11495 #define XCVR_TSM_TIMING20_SY_PD_EN_TX_LO_SHIFT   (8U)
11496 #define XCVR_TSM_TIMING20_SY_PD_EN_TX_LO(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING20_SY_PD_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING20_SY_PD_EN_TX_LO_MASK)
11497 #define XCVR_TSM_TIMING20_SY_PD_EN_RX_HI_MASK    (0xFF0000U)
11498 #define XCVR_TSM_TIMING20_SY_PD_EN_RX_HI_SHIFT   (16U)
11499 #define XCVR_TSM_TIMING20_SY_PD_EN_RX_HI(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING20_SY_PD_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING20_SY_PD_EN_RX_HI_MASK)
11500 #define XCVR_TSM_TIMING20_SY_PD_EN_RX_LO_MASK    (0xFF000000U)
11501 #define XCVR_TSM_TIMING20_SY_PD_EN_RX_LO_SHIFT   (24U)
11502 #define XCVR_TSM_TIMING20_SY_PD_EN_RX_LO(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING20_SY_PD_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING20_SY_PD_EN_RX_LO_MASK)
11503 
11504 /*! @name TIMING21 - TSM_TIMING21 */
11505 #define XCVR_TSM_TIMING21_SY_LO_DIVN_EN_TX_HI_MASK (0xFFU)
11506 #define XCVR_TSM_TIMING21_SY_LO_DIVN_EN_TX_HI_SHIFT (0U)
11507 #define XCVR_TSM_TIMING21_SY_LO_DIVN_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING21_SY_LO_DIVN_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING21_SY_LO_DIVN_EN_TX_HI_MASK)
11508 #define XCVR_TSM_TIMING21_SY_LO_DIVN_EN_TX_LO_MASK (0xFF00U)
11509 #define XCVR_TSM_TIMING21_SY_LO_DIVN_EN_TX_LO_SHIFT (8U)
11510 #define XCVR_TSM_TIMING21_SY_LO_DIVN_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING21_SY_LO_DIVN_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING21_SY_LO_DIVN_EN_TX_LO_MASK)
11511 #define XCVR_TSM_TIMING21_SY_LO_DIVN_EN_RX_HI_MASK (0xFF0000U)
11512 #define XCVR_TSM_TIMING21_SY_LO_DIVN_EN_RX_HI_SHIFT (16U)
11513 #define XCVR_TSM_TIMING21_SY_LO_DIVN_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING21_SY_LO_DIVN_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING21_SY_LO_DIVN_EN_RX_HI_MASK)
11514 #define XCVR_TSM_TIMING21_SY_LO_DIVN_EN_RX_LO_MASK (0xFF000000U)
11515 #define XCVR_TSM_TIMING21_SY_LO_DIVN_EN_RX_LO_SHIFT (24U)
11516 #define XCVR_TSM_TIMING21_SY_LO_DIVN_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING21_SY_LO_DIVN_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING21_SY_LO_DIVN_EN_RX_LO_MASK)
11517 
11518 /*! @name TIMING22 - TSM_TIMING22 */
11519 #define XCVR_TSM_TIMING22_SY_LO_RX_EN_RX_HI_MASK (0xFF0000U)
11520 #define XCVR_TSM_TIMING22_SY_LO_RX_EN_RX_HI_SHIFT (16U)
11521 #define XCVR_TSM_TIMING22_SY_LO_RX_EN_RX_HI(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING22_SY_LO_RX_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING22_SY_LO_RX_EN_RX_HI_MASK)
11522 #define XCVR_TSM_TIMING22_SY_LO_RX_EN_RX_LO_MASK (0xFF000000U)
11523 #define XCVR_TSM_TIMING22_SY_LO_RX_EN_RX_LO_SHIFT (24U)
11524 #define XCVR_TSM_TIMING22_SY_LO_RX_EN_RX_LO(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING22_SY_LO_RX_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING22_SY_LO_RX_EN_RX_LO_MASK)
11525 
11526 /*! @name TIMING23 - TSM_TIMING23 */
11527 #define XCVR_TSM_TIMING23_SY_LO_TX_EN_TX_HI_MASK (0xFFU)
11528 #define XCVR_TSM_TIMING23_SY_LO_TX_EN_TX_HI_SHIFT (0U)
11529 #define XCVR_TSM_TIMING23_SY_LO_TX_EN_TX_HI(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING23_SY_LO_TX_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING23_SY_LO_TX_EN_TX_HI_MASK)
11530 #define XCVR_TSM_TIMING23_SY_LO_TX_EN_TX_LO_MASK (0xFF00U)
11531 #define XCVR_TSM_TIMING23_SY_LO_TX_EN_TX_LO_SHIFT (8U)
11532 #define XCVR_TSM_TIMING23_SY_LO_TX_EN_TX_LO(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING23_SY_LO_TX_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING23_SY_LO_TX_EN_TX_LO_MASK)
11533 
11534 /*! @name TIMING24 - TSM_TIMING24 */
11535 #define XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_TX_HI_MASK (0xFFU)
11536 #define XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_TX_HI_SHIFT (0U)
11537 #define XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_TX_HI_MASK)
11538 #define XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_TX_LO_MASK (0xFF00U)
11539 #define XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_TX_LO_SHIFT (8U)
11540 #define XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_TX_LO_MASK)
11541 #define XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_RX_HI_MASK (0xFF0000U)
11542 #define XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_RX_HI_SHIFT (16U)
11543 #define XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_RX_HI_MASK)
11544 #define XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_RX_LO_MASK (0xFF000000U)
11545 #define XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_RX_LO_SHIFT (24U)
11546 #define XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_RX_LO_MASK)
11547 
11548 /*! @name TIMING25 - TSM_TIMING25 */
11549 #define XCVR_TSM_TIMING25_RX_LNA_MIXER_EN_RX_HI_MASK (0xFF0000U)
11550 #define XCVR_TSM_TIMING25_RX_LNA_MIXER_EN_RX_HI_SHIFT (16U)
11551 #define XCVR_TSM_TIMING25_RX_LNA_MIXER_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING25_RX_LNA_MIXER_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING25_RX_LNA_MIXER_EN_RX_HI_MASK)
11552 #define XCVR_TSM_TIMING25_RX_LNA_MIXER_EN_RX_LO_MASK (0xFF000000U)
11553 #define XCVR_TSM_TIMING25_RX_LNA_MIXER_EN_RX_LO_SHIFT (24U)
11554 #define XCVR_TSM_TIMING25_RX_LNA_MIXER_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING25_RX_LNA_MIXER_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING25_RX_LNA_MIXER_EN_RX_LO_MASK)
11555 
11556 /*! @name TIMING26 - TSM_TIMING26 */
11557 #define XCVR_TSM_TIMING26_TX_PA_EN_TX_HI_MASK    (0xFFU)
11558 #define XCVR_TSM_TIMING26_TX_PA_EN_TX_HI_SHIFT   (0U)
11559 #define XCVR_TSM_TIMING26_TX_PA_EN_TX_HI(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING26_TX_PA_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING26_TX_PA_EN_TX_HI_MASK)
11560 #define XCVR_TSM_TIMING26_TX_PA_EN_TX_LO_MASK    (0xFF00U)
11561 #define XCVR_TSM_TIMING26_TX_PA_EN_TX_LO_SHIFT   (8U)
11562 #define XCVR_TSM_TIMING26_TX_PA_EN_TX_LO(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING26_TX_PA_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING26_TX_PA_EN_TX_LO_MASK)
11563 
11564 /*! @name TIMING27 - TSM_TIMING27 */
11565 #define XCVR_TSM_TIMING27_RX_ADC_I_Q_EN_RX_HI_MASK (0xFF0000U)
11566 #define XCVR_TSM_TIMING27_RX_ADC_I_Q_EN_RX_HI_SHIFT (16U)
11567 #define XCVR_TSM_TIMING27_RX_ADC_I_Q_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING27_RX_ADC_I_Q_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING27_RX_ADC_I_Q_EN_RX_HI_MASK)
11568 #define XCVR_TSM_TIMING27_RX_ADC_I_Q_EN_RX_LO_MASK (0xFF000000U)
11569 #define XCVR_TSM_TIMING27_RX_ADC_I_Q_EN_RX_LO_SHIFT (24U)
11570 #define XCVR_TSM_TIMING27_RX_ADC_I_Q_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING27_RX_ADC_I_Q_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING27_RX_ADC_I_Q_EN_RX_LO_MASK)
11571 
11572 /*! @name TIMING28 - TSM_TIMING28 */
11573 #define XCVR_TSM_TIMING28_RX_ADC_RESET_EN_RX_HI_MASK (0xFF0000U)
11574 #define XCVR_TSM_TIMING28_RX_ADC_RESET_EN_RX_HI_SHIFT (16U)
11575 #define XCVR_TSM_TIMING28_RX_ADC_RESET_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING28_RX_ADC_RESET_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING28_RX_ADC_RESET_EN_RX_HI_MASK)
11576 #define XCVR_TSM_TIMING28_RX_ADC_RESET_EN_RX_LO_MASK (0xFF000000U)
11577 #define XCVR_TSM_TIMING28_RX_ADC_RESET_EN_RX_LO_SHIFT (24U)
11578 #define XCVR_TSM_TIMING28_RX_ADC_RESET_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING28_RX_ADC_RESET_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING28_RX_ADC_RESET_EN_RX_LO_MASK)
11579 
11580 /*! @name TIMING29 - TSM_TIMING29 */
11581 #define XCVR_TSM_TIMING29_RX_BBA_I_Q_EN_RX_HI_MASK (0xFF0000U)
11582 #define XCVR_TSM_TIMING29_RX_BBA_I_Q_EN_RX_HI_SHIFT (16U)
11583 #define XCVR_TSM_TIMING29_RX_BBA_I_Q_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING29_RX_BBA_I_Q_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING29_RX_BBA_I_Q_EN_RX_HI_MASK)
11584 #define XCVR_TSM_TIMING29_RX_BBA_I_Q_EN_RX_LO_MASK (0xFF000000U)
11585 #define XCVR_TSM_TIMING29_RX_BBA_I_Q_EN_RX_LO_SHIFT (24U)
11586 #define XCVR_TSM_TIMING29_RX_BBA_I_Q_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING29_RX_BBA_I_Q_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING29_RX_BBA_I_Q_EN_RX_LO_MASK)
11587 
11588 /*! @name TIMING30 - TSM_TIMING30 */
11589 #define XCVR_TSM_TIMING30_RX_BBA_PDET_EN_RX_HI_MASK (0xFF0000U)
11590 #define XCVR_TSM_TIMING30_RX_BBA_PDET_EN_RX_HI_SHIFT (16U)
11591 #define XCVR_TSM_TIMING30_RX_BBA_PDET_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING30_RX_BBA_PDET_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING30_RX_BBA_PDET_EN_RX_HI_MASK)
11592 #define XCVR_TSM_TIMING30_RX_BBA_PDET_EN_RX_LO_MASK (0xFF000000U)
11593 #define XCVR_TSM_TIMING30_RX_BBA_PDET_EN_RX_LO_SHIFT (24U)
11594 #define XCVR_TSM_TIMING30_RX_BBA_PDET_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING30_RX_BBA_PDET_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING30_RX_BBA_PDET_EN_RX_LO_MASK)
11595 
11596 /*! @name TIMING31 - TSM_TIMING31 */
11597 #define XCVR_TSM_TIMING31_RX_BBA_TZA_DCOC_EN_RX_HI_MASK (0xFF0000U)
11598 #define XCVR_TSM_TIMING31_RX_BBA_TZA_DCOC_EN_RX_HI_SHIFT (16U)
11599 #define XCVR_TSM_TIMING31_RX_BBA_TZA_DCOC_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING31_RX_BBA_TZA_DCOC_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING31_RX_BBA_TZA_DCOC_EN_RX_HI_MASK)
11600 #define XCVR_TSM_TIMING31_RX_BBA_TZA_DCOC_EN_RX_LO_MASK (0xFF000000U)
11601 #define XCVR_TSM_TIMING31_RX_BBA_TZA_DCOC_EN_RX_LO_SHIFT (24U)
11602 #define XCVR_TSM_TIMING31_RX_BBA_TZA_DCOC_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING31_RX_BBA_TZA_DCOC_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING31_RX_BBA_TZA_DCOC_EN_RX_LO_MASK)
11603 
11604 /*! @name TIMING32 - TSM_TIMING32 */
11605 #define XCVR_TSM_TIMING32_RX_TZA_I_Q_EN_RX_HI_MASK (0xFF0000U)
11606 #define XCVR_TSM_TIMING32_RX_TZA_I_Q_EN_RX_HI_SHIFT (16U)
11607 #define XCVR_TSM_TIMING32_RX_TZA_I_Q_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING32_RX_TZA_I_Q_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING32_RX_TZA_I_Q_EN_RX_HI_MASK)
11608 #define XCVR_TSM_TIMING32_RX_TZA_I_Q_EN_RX_LO_MASK (0xFF000000U)
11609 #define XCVR_TSM_TIMING32_RX_TZA_I_Q_EN_RX_LO_SHIFT (24U)
11610 #define XCVR_TSM_TIMING32_RX_TZA_I_Q_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING32_RX_TZA_I_Q_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING32_RX_TZA_I_Q_EN_RX_LO_MASK)
11611 
11612 /*! @name TIMING33 - TSM_TIMING33 */
11613 #define XCVR_TSM_TIMING33_RX_TZA_PDET_EN_RX_HI_MASK (0xFF0000U)
11614 #define XCVR_TSM_TIMING33_RX_TZA_PDET_EN_RX_HI_SHIFT (16U)
11615 #define XCVR_TSM_TIMING33_RX_TZA_PDET_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING33_RX_TZA_PDET_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING33_RX_TZA_PDET_EN_RX_HI_MASK)
11616 #define XCVR_TSM_TIMING33_RX_TZA_PDET_EN_RX_LO_MASK (0xFF000000U)
11617 #define XCVR_TSM_TIMING33_RX_TZA_PDET_EN_RX_LO_SHIFT (24U)
11618 #define XCVR_TSM_TIMING33_RX_TZA_PDET_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING33_RX_TZA_PDET_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING33_RX_TZA_PDET_EN_RX_LO_MASK)
11619 
11620 /*! @name TIMING34 - TSM_TIMING34 */
11621 #define XCVR_TSM_TIMING34_PLL_DIG_EN_TX_HI_MASK  (0xFFU)
11622 #define XCVR_TSM_TIMING34_PLL_DIG_EN_TX_HI_SHIFT (0U)
11623 #define XCVR_TSM_TIMING34_PLL_DIG_EN_TX_HI(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING34_PLL_DIG_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING34_PLL_DIG_EN_TX_HI_MASK)
11624 #define XCVR_TSM_TIMING34_PLL_DIG_EN_TX_LO_MASK  (0xFF00U)
11625 #define XCVR_TSM_TIMING34_PLL_DIG_EN_TX_LO_SHIFT (8U)
11626 #define XCVR_TSM_TIMING34_PLL_DIG_EN_TX_LO(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING34_PLL_DIG_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING34_PLL_DIG_EN_TX_LO_MASK)
11627 #define XCVR_TSM_TIMING34_PLL_DIG_EN_RX_HI_MASK  (0xFF0000U)
11628 #define XCVR_TSM_TIMING34_PLL_DIG_EN_RX_HI_SHIFT (16U)
11629 #define XCVR_TSM_TIMING34_PLL_DIG_EN_RX_HI(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING34_PLL_DIG_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING34_PLL_DIG_EN_RX_HI_MASK)
11630 #define XCVR_TSM_TIMING34_PLL_DIG_EN_RX_LO_MASK  (0xFF000000U)
11631 #define XCVR_TSM_TIMING34_PLL_DIG_EN_RX_LO_SHIFT (24U)
11632 #define XCVR_TSM_TIMING34_PLL_DIG_EN_RX_LO(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING34_PLL_DIG_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING34_PLL_DIG_EN_RX_LO_MASK)
11633 
11634 /*! @name TIMING35 - TSM_TIMING35 */
11635 #define XCVR_TSM_TIMING35_TX_DIG_EN_TX_HI_MASK   (0xFFU)
11636 #define XCVR_TSM_TIMING35_TX_DIG_EN_TX_HI_SHIFT  (0U)
11637 #define XCVR_TSM_TIMING35_TX_DIG_EN_TX_HI(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING35_TX_DIG_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING35_TX_DIG_EN_TX_HI_MASK)
11638 #define XCVR_TSM_TIMING35_TX_DIG_EN_TX_LO_MASK   (0xFF00U)
11639 #define XCVR_TSM_TIMING35_TX_DIG_EN_TX_LO_SHIFT  (8U)
11640 #define XCVR_TSM_TIMING35_TX_DIG_EN_TX_LO(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING35_TX_DIG_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING35_TX_DIG_EN_TX_LO_MASK)
11641 
11642 /*! @name TIMING36 - TSM_TIMING36 */
11643 #define XCVR_TSM_TIMING36_RX_DIG_EN_RX_HI_MASK   (0xFF0000U)
11644 #define XCVR_TSM_TIMING36_RX_DIG_EN_RX_HI_SHIFT  (16U)
11645 #define XCVR_TSM_TIMING36_RX_DIG_EN_RX_HI(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING36_RX_DIG_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING36_RX_DIG_EN_RX_HI_MASK)
11646 #define XCVR_TSM_TIMING36_RX_DIG_EN_RX_LO_MASK   (0xFF000000U)
11647 #define XCVR_TSM_TIMING36_RX_DIG_EN_RX_LO_SHIFT  (24U)
11648 #define XCVR_TSM_TIMING36_RX_DIG_EN_RX_LO(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING36_RX_DIG_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING36_RX_DIG_EN_RX_LO_MASK)
11649 
11650 /*! @name TIMING37 - TSM_TIMING37 */
11651 #define XCVR_TSM_TIMING37_RX_INIT_RX_HI_MASK     (0xFF0000U)
11652 #define XCVR_TSM_TIMING37_RX_INIT_RX_HI_SHIFT    (16U)
11653 #define XCVR_TSM_TIMING37_RX_INIT_RX_HI(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING37_RX_INIT_RX_HI_SHIFT)) & XCVR_TSM_TIMING37_RX_INIT_RX_HI_MASK)
11654 #define XCVR_TSM_TIMING37_RX_INIT_RX_LO_MASK     (0xFF000000U)
11655 #define XCVR_TSM_TIMING37_RX_INIT_RX_LO_SHIFT    (24U)
11656 #define XCVR_TSM_TIMING37_RX_INIT_RX_LO(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING37_RX_INIT_RX_LO_SHIFT)) & XCVR_TSM_TIMING37_RX_INIT_RX_LO_MASK)
11657 
11658 /*! @name TIMING38 - TSM_TIMING38 */
11659 #define XCVR_TSM_TIMING38_SIGMA_DELTA_EN_TX_HI_MASK (0xFFU)
11660 #define XCVR_TSM_TIMING38_SIGMA_DELTA_EN_TX_HI_SHIFT (0U)
11661 #define XCVR_TSM_TIMING38_SIGMA_DELTA_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING38_SIGMA_DELTA_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING38_SIGMA_DELTA_EN_TX_HI_MASK)
11662 #define XCVR_TSM_TIMING38_SIGMA_DELTA_EN_TX_LO_MASK (0xFF00U)
11663 #define XCVR_TSM_TIMING38_SIGMA_DELTA_EN_TX_LO_SHIFT (8U)
11664 #define XCVR_TSM_TIMING38_SIGMA_DELTA_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING38_SIGMA_DELTA_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING38_SIGMA_DELTA_EN_TX_LO_MASK)
11665 #define XCVR_TSM_TIMING38_SIGMA_DELTA_EN_RX_HI_MASK (0xFF0000U)
11666 #define XCVR_TSM_TIMING38_SIGMA_DELTA_EN_RX_HI_SHIFT (16U)
11667 #define XCVR_TSM_TIMING38_SIGMA_DELTA_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING38_SIGMA_DELTA_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING38_SIGMA_DELTA_EN_RX_HI_MASK)
11668 #define XCVR_TSM_TIMING38_SIGMA_DELTA_EN_RX_LO_MASK (0xFF000000U)
11669 #define XCVR_TSM_TIMING38_SIGMA_DELTA_EN_RX_LO_SHIFT (24U)
11670 #define XCVR_TSM_TIMING38_SIGMA_DELTA_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING38_SIGMA_DELTA_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING38_SIGMA_DELTA_EN_RX_LO_MASK)
11671 
11672 /*! @name TIMING39 - TSM_TIMING39 */
11673 #define XCVR_TSM_TIMING39_RX_PHY_EN_RX_HI_MASK   (0xFF0000U)
11674 #define XCVR_TSM_TIMING39_RX_PHY_EN_RX_HI_SHIFT  (16U)
11675 #define XCVR_TSM_TIMING39_RX_PHY_EN_RX_HI(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING39_RX_PHY_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING39_RX_PHY_EN_RX_HI_MASK)
11676 #define XCVR_TSM_TIMING39_RX_PHY_EN_RX_LO_MASK   (0xFF000000U)
11677 #define XCVR_TSM_TIMING39_RX_PHY_EN_RX_LO_SHIFT  (24U)
11678 #define XCVR_TSM_TIMING39_RX_PHY_EN_RX_LO(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING39_RX_PHY_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING39_RX_PHY_EN_RX_LO_MASK)
11679 
11680 /*! @name TIMING40 - TSM_TIMING40 */
11681 #define XCVR_TSM_TIMING40_DCOC_EN_RX_HI_MASK     (0xFF0000U)
11682 #define XCVR_TSM_TIMING40_DCOC_EN_RX_HI_SHIFT    (16U)
11683 #define XCVR_TSM_TIMING40_DCOC_EN_RX_HI(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING40_DCOC_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING40_DCOC_EN_RX_HI_MASK)
11684 #define XCVR_TSM_TIMING40_DCOC_EN_RX_LO_MASK     (0xFF000000U)
11685 #define XCVR_TSM_TIMING40_DCOC_EN_RX_LO_SHIFT    (24U)
11686 #define XCVR_TSM_TIMING40_DCOC_EN_RX_LO(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING40_DCOC_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING40_DCOC_EN_RX_LO_MASK)
11687 
11688 /*! @name TIMING41 - TSM_TIMING41 */
11689 #define XCVR_TSM_TIMING41_DCOC_INIT_RX_HI_MASK   (0xFF0000U)
11690 #define XCVR_TSM_TIMING41_DCOC_INIT_RX_HI_SHIFT  (16U)
11691 #define XCVR_TSM_TIMING41_DCOC_INIT_RX_HI(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING41_DCOC_INIT_RX_HI_SHIFT)) & XCVR_TSM_TIMING41_DCOC_INIT_RX_HI_MASK)
11692 #define XCVR_TSM_TIMING41_DCOC_INIT_RX_LO_MASK   (0xFF000000U)
11693 #define XCVR_TSM_TIMING41_DCOC_INIT_RX_LO_SHIFT  (24U)
11694 #define XCVR_TSM_TIMING41_DCOC_INIT_RX_LO(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING41_DCOC_INIT_RX_LO_SHIFT)) & XCVR_TSM_TIMING41_DCOC_INIT_RX_LO_MASK)
11695 
11696 /*! @name TIMING42 - TSM_TIMING42 */
11697 #define XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_TX_HI_MASK (0xFFU)
11698 #define XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_TX_HI_SHIFT (0U)
11699 #define XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_TX_HI_MASK)
11700 #define XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_TX_LO_MASK (0xFF00U)
11701 #define XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_TX_LO_SHIFT (8U)
11702 #define XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_TX_LO_MASK)
11703 #define XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_RX_HI_MASK (0xFF0000U)
11704 #define XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_RX_HI_SHIFT (16U)
11705 #define XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_RX_HI_MASK)
11706 #define XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_RX_LO_MASK (0xFF000000U)
11707 #define XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_RX_LO_SHIFT (24U)
11708 #define XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_RX_LO_MASK)
11709 
11710 /*! @name TIMING43 - TSM_TIMING43 */
11711 #define XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_HI_MASK (0xFFU)
11712 #define XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_HI_SHIFT (0U)
11713 #define XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_HI_MASK)
11714 #define XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_LO_MASK (0xFF00U)
11715 #define XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_LO_SHIFT (8U)
11716 #define XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_LO_MASK)
11717 #define XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_HI_MASK (0xFF0000U)
11718 #define XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_HI_SHIFT (16U)
11719 #define XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_HI_MASK)
11720 #define XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_LO_MASK (0xFF000000U)
11721 #define XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_LO_SHIFT (24U)
11722 #define XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_LO_MASK)
11723 
11724 /*! @name TIMING44 - TSM_TIMING44 */
11725 #define XCVR_TSM_TIMING44_TSM_SPARE1_EN_TX_HI_MASK (0xFFU)
11726 #define XCVR_TSM_TIMING44_TSM_SPARE1_EN_TX_HI_SHIFT (0U)
11727 #define XCVR_TSM_TIMING44_TSM_SPARE1_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING44_TSM_SPARE1_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING44_TSM_SPARE1_EN_TX_HI_MASK)
11728 #define XCVR_TSM_TIMING44_TSM_SPARE1_EN_TX_LO_MASK (0xFF00U)
11729 #define XCVR_TSM_TIMING44_TSM_SPARE1_EN_TX_LO_SHIFT (8U)
11730 #define XCVR_TSM_TIMING44_TSM_SPARE1_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING44_TSM_SPARE1_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING44_TSM_SPARE1_EN_TX_LO_MASK)
11731 #define XCVR_TSM_TIMING44_TSM_SPARE1_EN_RX_HI_MASK (0xFF0000U)
11732 #define XCVR_TSM_TIMING44_TSM_SPARE1_EN_RX_HI_SHIFT (16U)
11733 #define XCVR_TSM_TIMING44_TSM_SPARE1_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING44_TSM_SPARE1_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING44_TSM_SPARE1_EN_RX_HI_MASK)
11734 #define XCVR_TSM_TIMING44_TSM_SPARE1_EN_RX_LO_MASK (0xFF000000U)
11735 #define XCVR_TSM_TIMING44_TSM_SPARE1_EN_RX_LO_SHIFT (24U)
11736 #define XCVR_TSM_TIMING44_TSM_SPARE1_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING44_TSM_SPARE1_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING44_TSM_SPARE1_EN_RX_LO_MASK)
11737 
11738 /*! @name TIMING45 - TSM_TIMING45 */
11739 #define XCVR_TSM_TIMING45_TSM_SPARE2_EN_TX_HI_MASK (0xFFU)
11740 #define XCVR_TSM_TIMING45_TSM_SPARE2_EN_TX_HI_SHIFT (0U)
11741 #define XCVR_TSM_TIMING45_TSM_SPARE2_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING45_TSM_SPARE2_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING45_TSM_SPARE2_EN_TX_HI_MASK)
11742 #define XCVR_TSM_TIMING45_TSM_SPARE2_EN_TX_LO_MASK (0xFF00U)
11743 #define XCVR_TSM_TIMING45_TSM_SPARE2_EN_TX_LO_SHIFT (8U)
11744 #define XCVR_TSM_TIMING45_TSM_SPARE2_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING45_TSM_SPARE2_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING45_TSM_SPARE2_EN_TX_LO_MASK)
11745 #define XCVR_TSM_TIMING45_TSM_SPARE2_EN_RX_HI_MASK (0xFF0000U)
11746 #define XCVR_TSM_TIMING45_TSM_SPARE2_EN_RX_HI_SHIFT (16U)
11747 #define XCVR_TSM_TIMING45_TSM_SPARE2_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING45_TSM_SPARE2_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING45_TSM_SPARE2_EN_RX_HI_MASK)
11748 #define XCVR_TSM_TIMING45_TSM_SPARE2_EN_RX_LO_MASK (0xFF000000U)
11749 #define XCVR_TSM_TIMING45_TSM_SPARE2_EN_RX_LO_SHIFT (24U)
11750 #define XCVR_TSM_TIMING45_TSM_SPARE2_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING45_TSM_SPARE2_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING45_TSM_SPARE2_EN_RX_LO_MASK)
11751 
11752 /*! @name TIMING46 - TSM_TIMING46 */
11753 #define XCVR_TSM_TIMING46_TSM_SPARE3_EN_TX_HI_MASK (0xFFU)
11754 #define XCVR_TSM_TIMING46_TSM_SPARE3_EN_TX_HI_SHIFT (0U)
11755 #define XCVR_TSM_TIMING46_TSM_SPARE3_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING46_TSM_SPARE3_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING46_TSM_SPARE3_EN_TX_HI_MASK)
11756 #define XCVR_TSM_TIMING46_TSM_SPARE3_EN_TX_LO_MASK (0xFF00U)
11757 #define XCVR_TSM_TIMING46_TSM_SPARE3_EN_TX_LO_SHIFT (8U)
11758 #define XCVR_TSM_TIMING46_TSM_SPARE3_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING46_TSM_SPARE3_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING46_TSM_SPARE3_EN_TX_LO_MASK)
11759 #define XCVR_TSM_TIMING46_TSM_SPARE3_EN_RX_HI_MASK (0xFF0000U)
11760 #define XCVR_TSM_TIMING46_TSM_SPARE3_EN_RX_HI_SHIFT (16U)
11761 #define XCVR_TSM_TIMING46_TSM_SPARE3_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING46_TSM_SPARE3_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING46_TSM_SPARE3_EN_RX_HI_MASK)
11762 #define XCVR_TSM_TIMING46_TSM_SPARE3_EN_RX_LO_MASK (0xFF000000U)
11763 #define XCVR_TSM_TIMING46_TSM_SPARE3_EN_RX_LO_SHIFT (24U)
11764 #define XCVR_TSM_TIMING46_TSM_SPARE3_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING46_TSM_SPARE3_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING46_TSM_SPARE3_EN_RX_LO_MASK)
11765 
11766 /*! @name TIMING47 - TSM_TIMING47 */
11767 #define XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK (0xFFU)
11768 #define XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_SHIFT (0U)
11769 #define XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK)
11770 #define XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_LO_MASK (0xFF00U)
11771 #define XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_LO_SHIFT (8U)
11772 #define XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_LO_MASK)
11773 #define XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK (0xFF0000U)
11774 #define XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_SHIFT (16U)
11775 #define XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK)
11776 #define XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_LO_MASK (0xFF000000U)
11777 #define XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_LO_SHIFT (24U)
11778 #define XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_LO_MASK)
11779 
11780 /*! @name TIMING48 - TSM_TIMING48 */
11781 #define XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_MASK (0xFFU)
11782 #define XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_SHIFT (0U)
11783 #define XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_MASK)
11784 #define XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_LO_MASK (0xFF00U)
11785 #define XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_LO_SHIFT (8U)
11786 #define XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_LO_MASK)
11787 #define XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_MASK (0xFF0000U)
11788 #define XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_SHIFT (16U)
11789 #define XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_MASK)
11790 #define XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_LO_MASK (0xFF000000U)
11791 #define XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_LO_SHIFT (24U)
11792 #define XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_LO_MASK)
11793 
11794 /*! @name TIMING49 - TSM_TIMING49 */
11795 #define XCVR_TSM_TIMING49_GPIO2_TRIG_EN_TX_HI_MASK (0xFFU)
11796 #define XCVR_TSM_TIMING49_GPIO2_TRIG_EN_TX_HI_SHIFT (0U)
11797 #define XCVR_TSM_TIMING49_GPIO2_TRIG_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING49_GPIO2_TRIG_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING49_GPIO2_TRIG_EN_TX_HI_MASK)
11798 #define XCVR_TSM_TIMING49_GPIO2_TRIG_EN_TX_LO_MASK (0xFF00U)
11799 #define XCVR_TSM_TIMING49_GPIO2_TRIG_EN_TX_LO_SHIFT (8U)
11800 #define XCVR_TSM_TIMING49_GPIO2_TRIG_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING49_GPIO2_TRIG_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING49_GPIO2_TRIG_EN_TX_LO_MASK)
11801 #define XCVR_TSM_TIMING49_GPIO2_TRIG_EN_RX_HI_MASK (0xFF0000U)
11802 #define XCVR_TSM_TIMING49_GPIO2_TRIG_EN_RX_HI_SHIFT (16U)
11803 #define XCVR_TSM_TIMING49_GPIO2_TRIG_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING49_GPIO2_TRIG_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING49_GPIO2_TRIG_EN_RX_HI_MASK)
11804 #define XCVR_TSM_TIMING49_GPIO2_TRIG_EN_RX_LO_MASK (0xFF000000U)
11805 #define XCVR_TSM_TIMING49_GPIO2_TRIG_EN_RX_LO_SHIFT (24U)
11806 #define XCVR_TSM_TIMING49_GPIO2_TRIG_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING49_GPIO2_TRIG_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING49_GPIO2_TRIG_EN_RX_LO_MASK)
11807 
11808 /*! @name TIMING50 - TSM_TIMING50 */
11809 #define XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_MASK (0xFFU)
11810 #define XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_SHIFT (0U)
11811 #define XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_MASK)
11812 #define XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_LO_MASK (0xFF00U)
11813 #define XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_LO_SHIFT (8U)
11814 #define XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_LO_MASK)
11815 #define XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_MASK (0xFF0000U)
11816 #define XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_SHIFT (16U)
11817 #define XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_MASK)
11818 #define XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_MASK (0xFF000000U)
11819 #define XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_SHIFT (24U)
11820 #define XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_MASK)
11821 
11822 /*! @name TIMING51 - TSM_TIMING51 */
11823 #define XCVR_TSM_TIMING51_RXTX_AUXPLL_BIAS_EN_RX_HI_MASK (0xFF0000U)
11824 #define XCVR_TSM_TIMING51_RXTX_AUXPLL_BIAS_EN_RX_HI_SHIFT (16U)
11825 #define XCVR_TSM_TIMING51_RXTX_AUXPLL_BIAS_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING51_RXTX_AUXPLL_BIAS_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING51_RXTX_AUXPLL_BIAS_EN_RX_HI_MASK)
11826 #define XCVR_TSM_TIMING51_RXTX_AUXPLL_BIAS_EN_RX_LO_MASK (0xFF000000U)
11827 #define XCVR_TSM_TIMING51_RXTX_AUXPLL_BIAS_EN_RX_LO_SHIFT (24U)
11828 #define XCVR_TSM_TIMING51_RXTX_AUXPLL_BIAS_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING51_RXTX_AUXPLL_BIAS_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING51_RXTX_AUXPLL_BIAS_EN_RX_LO_MASK)
11829 
11830 /*! @name TIMING52 - TSM_TIMING52 */
11831 #define XCVR_TSM_TIMING52_RXTX_AUXPLL_FCAL_EN_RX_HI_MASK (0xFF0000U)
11832 #define XCVR_TSM_TIMING52_RXTX_AUXPLL_FCAL_EN_RX_HI_SHIFT (16U)
11833 #define XCVR_TSM_TIMING52_RXTX_AUXPLL_FCAL_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING52_RXTX_AUXPLL_FCAL_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING52_RXTX_AUXPLL_FCAL_EN_RX_HI_MASK)
11834 #define XCVR_TSM_TIMING52_RXTX_AUXPLL_FCAL_EN_RX_LO_MASK (0xFF000000U)
11835 #define XCVR_TSM_TIMING52_RXTX_AUXPLL_FCAL_EN_RX_LO_SHIFT (24U)
11836 #define XCVR_TSM_TIMING52_RXTX_AUXPLL_FCAL_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING52_RXTX_AUXPLL_FCAL_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING52_RXTX_AUXPLL_FCAL_EN_RX_LO_MASK)
11837 
11838 /*! @name TIMING53 - TSM_TIMING53 */
11839 #define XCVR_TSM_TIMING53_RXTX_AUXPLL_LF_PD_EN_RX_HI_MASK (0xFF0000U)
11840 #define XCVR_TSM_TIMING53_RXTX_AUXPLL_LF_PD_EN_RX_HI_SHIFT (16U)
11841 #define XCVR_TSM_TIMING53_RXTX_AUXPLL_LF_PD_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING53_RXTX_AUXPLL_LF_PD_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING53_RXTX_AUXPLL_LF_PD_EN_RX_HI_MASK)
11842 #define XCVR_TSM_TIMING53_RXTX_AUXPLL_LF_PD_EN_RX_LO_MASK (0xFF000000U)
11843 #define XCVR_TSM_TIMING53_RXTX_AUXPLL_LF_PD_EN_RX_LO_SHIFT (24U)
11844 #define XCVR_TSM_TIMING53_RXTX_AUXPLL_LF_PD_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING53_RXTX_AUXPLL_LF_PD_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING53_RXTX_AUXPLL_LF_PD_EN_RX_LO_MASK)
11845 
11846 /*! @name TIMING54 - TSM_TIMING54 */
11847 #define XCVR_TSM_TIMING54_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_RX_HI_MASK (0xFF0000U)
11848 #define XCVR_TSM_TIMING54_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_RX_HI_SHIFT (16U)
11849 #define XCVR_TSM_TIMING54_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING54_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING54_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_RX_HI_MASK)
11850 #define XCVR_TSM_TIMING54_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_RX_LO_MASK (0xFF000000U)
11851 #define XCVR_TSM_TIMING54_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_RX_LO_SHIFT (24U)
11852 #define XCVR_TSM_TIMING54_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING54_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING54_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_RX_LO_MASK)
11853 
11854 /*! @name TIMING55 - TSM_TIMING55 */
11855 #define XCVR_TSM_TIMING55_RXTX_AUXPLL_ADC_BUF_EN_RX_HI_MASK (0xFF0000U)
11856 #define XCVR_TSM_TIMING55_RXTX_AUXPLL_ADC_BUF_EN_RX_HI_SHIFT (16U)
11857 #define XCVR_TSM_TIMING55_RXTX_AUXPLL_ADC_BUF_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING55_RXTX_AUXPLL_ADC_BUF_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING55_RXTX_AUXPLL_ADC_BUF_EN_RX_HI_MASK)
11858 #define XCVR_TSM_TIMING55_RXTX_AUXPLL_ADC_BUF_EN_RX_LO_MASK (0xFF000000U)
11859 #define XCVR_TSM_TIMING55_RXTX_AUXPLL_ADC_BUF_EN_RX_LO_SHIFT (24U)
11860 #define XCVR_TSM_TIMING55_RXTX_AUXPLL_ADC_BUF_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING55_RXTX_AUXPLL_ADC_BUF_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING55_RXTX_AUXPLL_ADC_BUF_EN_RX_LO_MASK)
11861 
11862 /*! @name TIMING56 - TSM_TIMING56 */
11863 #define XCVR_TSM_TIMING56_RXTX_AUXPLL_DIG_BUF_EN_RX_HI_MASK (0xFF0000U)
11864 #define XCVR_TSM_TIMING56_RXTX_AUXPLL_DIG_BUF_EN_RX_HI_SHIFT (16U)
11865 #define XCVR_TSM_TIMING56_RXTX_AUXPLL_DIG_BUF_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING56_RXTX_AUXPLL_DIG_BUF_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING56_RXTX_AUXPLL_DIG_BUF_EN_RX_HI_MASK)
11866 #define XCVR_TSM_TIMING56_RXTX_AUXPLL_DIG_BUF_EN_RX_LO_MASK (0xFF000000U)
11867 #define XCVR_TSM_TIMING56_RXTX_AUXPLL_DIG_BUF_EN_RX_LO_SHIFT (24U)
11868 #define XCVR_TSM_TIMING56_RXTX_AUXPLL_DIG_BUF_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING56_RXTX_AUXPLL_DIG_BUF_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING56_RXTX_AUXPLL_DIG_BUF_EN_RX_LO_MASK)
11869 
11870 /*! @name TIMING57 - TSM_TIMING57 */
11871 #define XCVR_TSM_TIMING57_RXTX_RCCAL_EN_RX_HI_MASK (0xFF0000U)
11872 #define XCVR_TSM_TIMING57_RXTX_RCCAL_EN_RX_HI_SHIFT (16U)
11873 #define XCVR_TSM_TIMING57_RXTX_RCCAL_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING57_RXTX_RCCAL_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING57_RXTX_RCCAL_EN_RX_HI_MASK)
11874 #define XCVR_TSM_TIMING57_RXTX_RCCAL_EN_RX_LO_MASK (0xFF000000U)
11875 #define XCVR_TSM_TIMING57_RXTX_RCCAL_EN_RX_LO_SHIFT (24U)
11876 #define XCVR_TSM_TIMING57_RXTX_RCCAL_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING57_RXTX_RCCAL_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING57_RXTX_RCCAL_EN_RX_LO_MASK)
11877 
11878 /*! @name TIMING58 - TSM_TIMING58 */
11879 #define XCVR_TSM_TIMING58_TX_HPM_DAC_EN_TX_HI_MASK (0xFFU)
11880 #define XCVR_TSM_TIMING58_TX_HPM_DAC_EN_TX_HI_SHIFT (0U)
11881 #define XCVR_TSM_TIMING58_TX_HPM_DAC_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING58_TX_HPM_DAC_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING58_TX_HPM_DAC_EN_TX_HI_MASK)
11882 #define XCVR_TSM_TIMING58_TX_HPM_DAC_EN_TX_LO_MASK (0xFF00U)
11883 #define XCVR_TSM_TIMING58_TX_HPM_DAC_EN_TX_LO_SHIFT (8U)
11884 #define XCVR_TSM_TIMING58_TX_HPM_DAC_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING58_TX_HPM_DAC_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING58_TX_HPM_DAC_EN_TX_LO_MASK)
11885 
11886 
11887 /*!
11888  * @}
11889  */ /* end of group XCVR_TSM_Register_Masks */
11890 
11891 
11892 /* XCVR_TSM - Peripheral instance base addresses */
11893 /** Peripheral XCVR_TSM base address */
11894 #define XCVR_TSM_BASE                            (0x4005C2C0u)
11895 /** Peripheral XCVR_TSM base pointer */
11896 #define XCVR_TSM                                 ((XCVR_TSM_Type *)XCVR_TSM_BASE)
11897 /** Array initializer of XCVR_TSM peripheral base addresses */
11898 #define XCVR_TSM_BASE_ADDRS                      { XCVR_TSM_BASE }
11899 /** Array initializer of XCVR_TSM peripheral base pointers */
11900 #define XCVR_TSM_BASE_PTRS                       { XCVR_TSM }
11901 
11902 /*!
11903  * @}
11904  */ /* end of group XCVR_TSM_Peripheral_Access_Layer */
11905 
11906 
11907 /* ----------------------------------------------------------------------------
11908    -- XCVR_TX_DIG Peripheral Access Layer
11909    ---------------------------------------------------------------------------- */
11910 
11911 /*!
11912  * @addtogroup XCVR_TX_DIG_Peripheral_Access_Layer XCVR_TX_DIG Peripheral Access Layer
11913  * @{
11914  */
11915 
11916 /** XCVR_TX_DIG - Register Layout Typedef */
11917 typedef struct {
11918   __IO uint32_t CTRL;                              /**< TX Digital Control, offset: 0x0 */
11919   __IO uint32_t DATA_PADDING;                      /**< TX Data Padding, offset: 0x4 */
11920   __IO uint32_t GFSK_CTRL;                         /**< TX GFSK Modulator Control, offset: 0x8 */
11921   __IO uint32_t GFSK_COEFF2;                       /**< TX GFSK Filter Coefficients 2, offset: 0xC */
11922   __IO uint32_t GFSK_COEFF1;                       /**< TX GFSK Filter Coefficients 1, offset: 0x10 */
11923   __IO uint32_t FSK_SCALE;                         /**< TX FSK Modulation Levels, offset: 0x14 */
11924   __IO uint32_t DFT_PATTERN;                       /**< TX DFT Modulation Pattern, offset: 0x18 */
11925   __IO uint32_t RF_DFT_BIST_1;                     /**< TX DFT Control 1, offset: 0x1C */
11926   __IO uint32_t RF_DFT_BIST_2;                     /**< TX DFT Control 2, offset: 0x20 */
11927 } XCVR_TX_DIG_Type;
11928 
11929 /* ----------------------------------------------------------------------------
11930    -- XCVR_TX_DIG Register Masks
11931    ---------------------------------------------------------------------------- */
11932 
11933 /*!
11934  * @addtogroup XCVR_TX_DIG_Register_Masks XCVR_TX_DIG Register Masks
11935  * @{
11936  */
11937 
11938 /*! @name CTRL - TX Digital Control */
11939 #define XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK     (0xFU)
11940 #define XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_SHIFT    (0U)
11941 #define XCVR_TX_DIG_CTRL_RADIO_DFT_MODE(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_SHIFT)) & XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK)
11942 #define XCVR_TX_DIG_CTRL_LFSR_LENGTH_MASK        (0x70U)
11943 #define XCVR_TX_DIG_CTRL_LFSR_LENGTH_SHIFT       (4U)
11944 #define XCVR_TX_DIG_CTRL_LFSR_LENGTH(x)          (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_CTRL_LFSR_LENGTH_SHIFT)) & XCVR_TX_DIG_CTRL_LFSR_LENGTH_MASK)
11945 #define XCVR_TX_DIG_CTRL_LFSR_EN_MASK            (0x80U)
11946 #define XCVR_TX_DIG_CTRL_LFSR_EN_SHIFT           (7U)
11947 #define XCVR_TX_DIG_CTRL_LFSR_EN(x)              (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_CTRL_LFSR_EN_SHIFT)) & XCVR_TX_DIG_CTRL_LFSR_EN_MASK)
11948 #define XCVR_TX_DIG_CTRL_DFT_CLK_SEL_MASK        (0x700U)
11949 #define XCVR_TX_DIG_CTRL_DFT_CLK_SEL_SHIFT       (8U)
11950 #define XCVR_TX_DIG_CTRL_DFT_CLK_SEL(x)          (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_CTRL_DFT_CLK_SEL_SHIFT)) & XCVR_TX_DIG_CTRL_DFT_CLK_SEL_MASK)
11951 #define XCVR_TX_DIG_CTRL_TX_DFT_EN_MASK          (0x800U)
11952 #define XCVR_TX_DIG_CTRL_TX_DFT_EN_SHIFT         (11U)
11953 #define XCVR_TX_DIG_CTRL_TX_DFT_EN(x)            (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_CTRL_TX_DFT_EN_SHIFT)) & XCVR_TX_DIG_CTRL_TX_DFT_EN_MASK)
11954 #define XCVR_TX_DIG_CTRL_SOC_TEST_SEL_MASK       (0x3000U)
11955 #define XCVR_TX_DIG_CTRL_SOC_TEST_SEL_SHIFT      (12U)
11956 #define XCVR_TX_DIG_CTRL_SOC_TEST_SEL(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_CTRL_SOC_TEST_SEL_SHIFT)) & XCVR_TX_DIG_CTRL_SOC_TEST_SEL_MASK)
11957 #define XCVR_TX_DIG_CTRL_TX_CAPTURE_POL_MASK     (0x10000U)
11958 #define XCVR_TX_DIG_CTRL_TX_CAPTURE_POL_SHIFT    (16U)
11959 #define XCVR_TX_DIG_CTRL_TX_CAPTURE_POL(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_CTRL_TX_CAPTURE_POL_SHIFT)) & XCVR_TX_DIG_CTRL_TX_CAPTURE_POL_MASK)
11960 #define XCVR_TX_DIG_CTRL_FREQ_WORD_ADJ_MASK      (0xFFC00000U)
11961 #define XCVR_TX_DIG_CTRL_FREQ_WORD_ADJ_SHIFT     (22U)
11962 #define XCVR_TX_DIG_CTRL_FREQ_WORD_ADJ(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_CTRL_FREQ_WORD_ADJ_SHIFT)) & XCVR_TX_DIG_CTRL_FREQ_WORD_ADJ_MASK)
11963 
11964 /*! @name DATA_PADDING - TX Data Padding */
11965 #define XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_0_MASK (0xFFU)
11966 #define XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_0_SHIFT (0U)
11967 #define XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_0_SHIFT)) & XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_0_MASK)
11968 #define XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_1_MASK (0xFF00U)
11969 #define XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_1_SHIFT (8U)
11970 #define XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_1_SHIFT)) & XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_1_MASK)
11971 #define XCVR_TX_DIG_DATA_PADDING_DFT_LFSR_OUT_MASK (0x7FFF0000U)
11972 #define XCVR_TX_DIG_DATA_PADDING_DFT_LFSR_OUT_SHIFT (16U)
11973 #define XCVR_TX_DIG_DATA_PADDING_DFT_LFSR_OUT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATA_PADDING_DFT_LFSR_OUT_SHIFT)) & XCVR_TX_DIG_DATA_PADDING_DFT_LFSR_OUT_MASK)
11974 #define XCVR_TX_DIG_DATA_PADDING_LRM_MASK        (0x80000000U)
11975 #define XCVR_TX_DIG_DATA_PADDING_LRM_SHIFT       (31U)
11976 #define XCVR_TX_DIG_DATA_PADDING_LRM(x)          (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATA_PADDING_LRM_SHIFT)) & XCVR_TX_DIG_DATA_PADDING_LRM_MASK)
11977 
11978 /*! @name GFSK_CTRL - TX GFSK Modulator Control */
11979 #define XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL_MASK (0xFFFFU)
11980 #define XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL_SHIFT (0U)
11981 #define XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL_SHIFT)) & XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL_MASK)
11982 #define XCVR_TX_DIG_GFSK_CTRL_GFSK_MI_MASK       (0x30000U)
11983 #define XCVR_TX_DIG_GFSK_CTRL_GFSK_MI_SHIFT      (16U)
11984 #define XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_CTRL_GFSK_MI_SHIFT)) & XCVR_TX_DIG_GFSK_CTRL_GFSK_MI_MASK)
11985 #define XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD_MASK      (0x100000U)
11986 #define XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD_SHIFT     (20U)
11987 #define XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD_SHIFT)) & XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD_MASK)
11988 #define XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD_MASK      (0x200000U)
11989 #define XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD_SHIFT     (21U)
11990 #define XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD_SHIFT)) & XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD_MASK)
11991 #define XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING_MASK (0x7000000U)
11992 #define XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING_SHIFT (24U)
11993 #define XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING_SHIFT)) & XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING_MASK)
11994 #define XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN_MASK (0x10000000U)
11995 #define XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN_SHIFT (28U)
11996 #define XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN_SHIFT)) & XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN_MASK)
11997 #define XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD_MASK (0x20000000U)
11998 #define XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD_SHIFT (29U)
11999 #define XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD_SHIFT)) & XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD_MASK)
12000 #define XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD_MASK (0x40000000U)
12001 #define XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD_SHIFT (30U)
12002 #define XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD_SHIFT)) & XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD_MASK)
12003 #define XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD_MASK (0x80000000U)
12004 #define XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD_SHIFT (31U)
12005 #define XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD_SHIFT)) & XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD_MASK)
12006 
12007 /*! @name GFSK_COEFF2 - TX GFSK Filter Coefficients 2 */
12008 #define XCVR_TX_DIG_GFSK_COEFF2_GFSK_FILTER_COEFF_MANUAL2_MASK (0xFFFFFFFFU)
12009 #define XCVR_TX_DIG_GFSK_COEFF2_GFSK_FILTER_COEFF_MANUAL2_SHIFT (0U)
12010 #define XCVR_TX_DIG_GFSK_COEFF2_GFSK_FILTER_COEFF_MANUAL2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_COEFF2_GFSK_FILTER_COEFF_MANUAL2_SHIFT)) & XCVR_TX_DIG_GFSK_COEFF2_GFSK_FILTER_COEFF_MANUAL2_MASK)
12011 
12012 /*! @name GFSK_COEFF1 - TX GFSK Filter Coefficients 1 */
12013 #define XCVR_TX_DIG_GFSK_COEFF1_GFSK_FILTER_COEFF_MANUAL1_MASK (0xFFFFFFFFU)
12014 #define XCVR_TX_DIG_GFSK_COEFF1_GFSK_FILTER_COEFF_MANUAL1_SHIFT (0U)
12015 #define XCVR_TX_DIG_GFSK_COEFF1_GFSK_FILTER_COEFF_MANUAL1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_COEFF1_GFSK_FILTER_COEFF_MANUAL1_SHIFT)) & XCVR_TX_DIG_GFSK_COEFF1_GFSK_FILTER_COEFF_MANUAL1_MASK)
12016 
12017 /*! @name FSK_SCALE - TX FSK Modulation Levels */
12018 #define XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0_MASK (0x1FFFU)
12019 #define XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0_SHIFT (0U)
12020 #define XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0_SHIFT)) & XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0_MASK)
12021 #define XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1_MASK (0x1FFF0000U)
12022 #define XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1_SHIFT (16U)
12023 #define XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1_SHIFT)) & XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1_MASK)
12024 
12025 /*! @name DFT_PATTERN - TX DFT Modulation Pattern */
12026 #define XCVR_TX_DIG_DFT_PATTERN_DFT_MOD_PATTERN_MASK (0xFFFFFFFFU)
12027 #define XCVR_TX_DIG_DFT_PATTERN_DFT_MOD_PATTERN_SHIFT (0U)
12028 #define XCVR_TX_DIG_DFT_PATTERN_DFT_MOD_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DFT_PATTERN_DFT_MOD_PATTERN_SHIFT)) & XCVR_TX_DIG_DFT_PATTERN_DFT_MOD_PATTERN_MASK)
12029 
12030 /*! @name RF_DFT_BIST_1 - TX DFT Control 1 */
12031 #define XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_GO_MASK (0x1U)
12032 #define XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_GO_SHIFT (0U)
12033 #define XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_GO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_GO_SHIFT)) & XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_GO_MASK)
12034 #define XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_FINISHED_MASK (0x2U)
12035 #define XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_FINISHED_SHIFT (1U)
12036 #define XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_FINISHED_SHIFT)) & XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_FINISHED_MASK)
12037 #define XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_RESULT_MASK (0x4U)
12038 #define XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_RESULT_SHIFT (2U)
12039 #define XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_RESULT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_RESULT_SHIFT)) & XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_RESULT_MASK)
12040 #define XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_THRSHLD_MASK (0xF0U)
12041 #define XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_THRSHLD_SHIFT (4U)
12042 #define XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_THRSHLD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_THRSHLD_SHIFT)) & XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_THRSHLD_MASK)
12043 #define XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_MAX_DIFF_MASK (0xFF00U)
12044 #define XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_MAX_DIFF_SHIFT (8U)
12045 #define XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_MAX_DIFF(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_MAX_DIFF_SHIFT)) & XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_MAX_DIFF_MASK)
12046 #define XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_MAX_DIFF_CH_MASK (0x7F0000U)
12047 #define XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_MAX_DIFF_CH_SHIFT (16U)
12048 #define XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_MAX_DIFF_CH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_MAX_DIFF_CH_SHIFT)) & XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_MAX_DIFF_CH_MASK)
12049 #define XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_FREQ_MASK (0x7000000U)
12050 #define XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_FREQ_SHIFT (24U)
12051 #define XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_FREQ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_FREQ_SHIFT)) & XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_FREQ_MASK)
12052 #define XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_ENTRIES_MASK (0x70000000U)
12053 #define XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_ENTRIES_SHIFT (28U)
12054 #define XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_ENTRIES_SHIFT)) & XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_ENTRIES_MASK)
12055 #define XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_EN_MASK (0x80000000U)
12056 #define XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_EN_SHIFT (31U)
12057 #define XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_EN_SHIFT)) & XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_EN_MASK)
12058 
12059 /*! @name RF_DFT_BIST_2 - TX DFT Control 2 */
12060 #define XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_GO_MASK (0x1U)
12061 #define XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_GO_SHIFT (0U)
12062 #define XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_GO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_GO_SHIFT)) & XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_GO_MASK)
12063 #define XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_FINISHED_MASK (0x2U)
12064 #define XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_FINISHED_SHIFT (1U)
12065 #define XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_FINISHED_SHIFT)) & XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_FINISHED_MASK)
12066 #define XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_RESULT_MASK (0x4U)
12067 #define XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_RESULT_SHIFT (2U)
12068 #define XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_RESULT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_RESULT_SHIFT)) & XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_RESULT_MASK)
12069 #define XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_ALL_CHANNELS_MASK (0x8U)
12070 #define XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_ALL_CHANNELS_SHIFT (3U)
12071 #define XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_ALL_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_ALL_CHANNELS_SHIFT)) & XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_ALL_CHANNELS_MASK)
12072 #define XCVR_TX_DIG_RF_DFT_BIST_2_FREQ_COUNT_THRESHOLD_MASK (0xFF0U)
12073 #define XCVR_TX_DIG_RF_DFT_BIST_2_FREQ_COUNT_THRESHOLD_SHIFT (4U)
12074 #define XCVR_TX_DIG_RF_DFT_BIST_2_FREQ_COUNT_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_BIST_2_FREQ_COUNT_THRESHOLD_SHIFT)) & XCVR_TX_DIG_RF_DFT_BIST_2_FREQ_COUNT_THRESHOLD_MASK)
12075 #define XCVR_TX_DIG_RF_DFT_BIST_2_HPM_INL_BIST_GO_MASK (0x1000U)
12076 #define XCVR_TX_DIG_RF_DFT_BIST_2_HPM_INL_BIST_GO_SHIFT (12U)
12077 #define XCVR_TX_DIG_RF_DFT_BIST_2_HPM_INL_BIST_GO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_BIST_2_HPM_INL_BIST_GO_SHIFT)) & XCVR_TX_DIG_RF_DFT_BIST_2_HPM_INL_BIST_GO_MASK)
12078 #define XCVR_TX_DIG_RF_DFT_BIST_2_HPM_INL_BIST_FINISHED_MASK (0x2000U)
12079 #define XCVR_TX_DIG_RF_DFT_BIST_2_HPM_INL_BIST_FINISHED_SHIFT (13U)
12080 #define XCVR_TX_DIG_RF_DFT_BIST_2_HPM_INL_BIST_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_BIST_2_HPM_INL_BIST_FINISHED_SHIFT)) & XCVR_TX_DIG_RF_DFT_BIST_2_HPM_INL_BIST_FINISHED_MASK)
12081 #define XCVR_TX_DIG_RF_DFT_BIST_2_HPM_INL_BIST_RESULT_MASK (0x4000U)
12082 #define XCVR_TX_DIG_RF_DFT_BIST_2_HPM_INL_BIST_RESULT_SHIFT (14U)
12083 #define XCVR_TX_DIG_RF_DFT_BIST_2_HPM_INL_BIST_RESULT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_BIST_2_HPM_INL_BIST_RESULT_SHIFT)) & XCVR_TX_DIG_RF_DFT_BIST_2_HPM_INL_BIST_RESULT_MASK)
12084 #define XCVR_TX_DIG_RF_DFT_BIST_2_HPM_DNL_BIST_GO_MASK (0x10000U)
12085 #define XCVR_TX_DIG_RF_DFT_BIST_2_HPM_DNL_BIST_GO_SHIFT (16U)
12086 #define XCVR_TX_DIG_RF_DFT_BIST_2_HPM_DNL_BIST_GO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_BIST_2_HPM_DNL_BIST_GO_SHIFT)) & XCVR_TX_DIG_RF_DFT_BIST_2_HPM_DNL_BIST_GO_MASK)
12087 #define XCVR_TX_DIG_RF_DFT_BIST_2_HPM_DNL_BIST_FINISHED_MASK (0x20000U)
12088 #define XCVR_TX_DIG_RF_DFT_BIST_2_HPM_DNL_BIST_FINISHED_SHIFT (17U)
12089 #define XCVR_TX_DIG_RF_DFT_BIST_2_HPM_DNL_BIST_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_BIST_2_HPM_DNL_BIST_FINISHED_SHIFT)) & XCVR_TX_DIG_RF_DFT_BIST_2_HPM_DNL_BIST_FINISHED_MASK)
12090 #define XCVR_TX_DIG_RF_DFT_BIST_2_HPM_DNL_BIST_RESULT_MASK (0x40000U)
12091 #define XCVR_TX_DIG_RF_DFT_BIST_2_HPM_DNL_BIST_RESULT_SHIFT (18U)
12092 #define XCVR_TX_DIG_RF_DFT_BIST_2_HPM_DNL_BIST_RESULT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_BIST_2_HPM_DNL_BIST_RESULT_SHIFT)) & XCVR_TX_DIG_RF_DFT_BIST_2_HPM_DNL_BIST_RESULT_MASK)
12093 #define XCVR_TX_DIG_RF_DFT_BIST_2_DFT_MAX_RAM_SIZE_MASK (0x1FF00000U)
12094 #define XCVR_TX_DIG_RF_DFT_BIST_2_DFT_MAX_RAM_SIZE_SHIFT (20U)
12095 #define XCVR_TX_DIG_RF_DFT_BIST_2_DFT_MAX_RAM_SIZE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_BIST_2_DFT_MAX_RAM_SIZE_SHIFT)) & XCVR_TX_DIG_RF_DFT_BIST_2_DFT_MAX_RAM_SIZE_MASK)
12096 
12097 
12098 /*!
12099  * @}
12100  */ /* end of group XCVR_TX_DIG_Register_Masks */
12101 
12102 
12103 /* XCVR_TX_DIG - Peripheral instance base addresses */
12104 /** Peripheral XCVR_TX_DIG base address */
12105 #define XCVR_TX_DIG_BASE                         (0x4005C200u)
12106 /** Peripheral XCVR_TX_DIG base pointer */
12107 #define XCVR_TX_DIG                              ((XCVR_TX_DIG_Type *)XCVR_TX_DIG_BASE)
12108 /** Array initializer of XCVR_TX_DIG peripheral base addresses */
12109 #define XCVR_TX_DIG_BASE_ADDRS                   { XCVR_TX_DIG_BASE }
12110 /** Array initializer of XCVR_TX_DIG peripheral base pointers */
12111 #define XCVR_TX_DIG_BASE_PTRS                    { XCVR_TX_DIG }
12112 
12113 /*!
12114  * @}
12115  */ /* end of group XCVR_TX_DIG_Peripheral_Access_Layer */
12116 
12117 
12118 /* ----------------------------------------------------------------------------
12119    -- XCVR_ZBDEM Peripheral Access Layer
12120    ---------------------------------------------------------------------------- */
12121 
12122 /*!
12123  * @addtogroup XCVR_ZBDEM_Peripheral_Access_Layer XCVR_ZBDEM Peripheral Access Layer
12124  * @{
12125  */
12126 
12127 /** XCVR_ZBDEM - Register Layout Typedef */
12128 typedef struct {
12129   __IO uint32_t CORR_CTRL;                         /**< 802.15.4 DEMOD CORRELLATOR CONTROL, offset: 0x0 */
12130   __IO uint32_t PN_TYPE;                           /**< 802.15.4 DEMOD PN TYPE, offset: 0x4 */
12131   __IO uint32_t PN_CODE;                           /**< 802.15.4 DEMOD PN CODE, offset: 0x8 */
12132   __IO uint32_t SYNC_CTRL;                         /**< 802.15.4 DEMOD SYMBOL SYNC CONTROL, offset: 0xC */
12133   __IO uint32_t CCA_LQI_SRC;                       /**< 802.15.4 CCA/LQI SOURCE, offset: 0x10 */
12134   __IO uint32_t FAD_THR;                           /**< FAD CORRELATOR THRESHOLD, offset: 0x14 */
12135   __IO uint32_t ZBDEM_AFC;                         /**< 802.15.4 AFC STATUS, offset: 0x18 */
12136 } XCVR_ZBDEM_Type;
12137 
12138 /* ----------------------------------------------------------------------------
12139    -- XCVR_ZBDEM Register Masks
12140    ---------------------------------------------------------------------------- */
12141 
12142 /*!
12143  * @addtogroup XCVR_ZBDEM_Register_Masks XCVR_ZBDEM Register Masks
12144  * @{
12145  */
12146 
12147 /*! @name CORR_CTRL - 802.15.4 DEMOD CORRELLATOR CONTROL */
12148 #define XCVR_ZBDEM_CORR_CTRL_CORR_VT_MASK        (0xFFU)
12149 #define XCVR_ZBDEM_CORR_CTRL_CORR_VT_SHIFT       (0U)
12150 #define XCVR_ZBDEM_CORR_CTRL_CORR_VT(x)          (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CORR_CTRL_CORR_VT_SHIFT)) & XCVR_ZBDEM_CORR_CTRL_CORR_VT_MASK)
12151 #define XCVR_ZBDEM_CORR_CTRL_CORR_NVAL_MASK      (0x700U)
12152 #define XCVR_ZBDEM_CORR_CTRL_CORR_NVAL_SHIFT     (8U)
12153 #define XCVR_ZBDEM_CORR_CTRL_CORR_NVAL(x)        (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CORR_CTRL_CORR_NVAL_SHIFT)) & XCVR_ZBDEM_CORR_CTRL_CORR_NVAL_MASK)
12154 #define XCVR_ZBDEM_CORR_CTRL_MAX_CORR_EN_MASK    (0x800U)
12155 #define XCVR_ZBDEM_CORR_CTRL_MAX_CORR_EN_SHIFT   (11U)
12156 #define XCVR_ZBDEM_CORR_CTRL_MAX_CORR_EN(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CORR_CTRL_MAX_CORR_EN_SHIFT)) & XCVR_ZBDEM_CORR_CTRL_MAX_CORR_EN_MASK)
12157 #define XCVR_ZBDEM_CORR_CTRL_ZBDEM_CLK_ON_MASK   (0x8000U)
12158 #define XCVR_ZBDEM_CORR_CTRL_ZBDEM_CLK_ON_SHIFT  (15U)
12159 #define XCVR_ZBDEM_CORR_CTRL_ZBDEM_CLK_ON(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CORR_CTRL_ZBDEM_CLK_ON_SHIFT)) & XCVR_ZBDEM_CORR_CTRL_ZBDEM_CLK_ON_MASK)
12160 #define XCVR_ZBDEM_CORR_CTRL_RX_MAX_CORR_MASK    (0xFF0000U)
12161 #define XCVR_ZBDEM_CORR_CTRL_RX_MAX_CORR_SHIFT   (16U)
12162 #define XCVR_ZBDEM_CORR_CTRL_RX_MAX_CORR(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CORR_CTRL_RX_MAX_CORR_SHIFT)) & XCVR_ZBDEM_CORR_CTRL_RX_MAX_CORR_MASK)
12163 #define XCVR_ZBDEM_CORR_CTRL_RX_MAX_PREAMBLE_MASK (0xFF000000U)
12164 #define XCVR_ZBDEM_CORR_CTRL_RX_MAX_PREAMBLE_SHIFT (24U)
12165 #define XCVR_ZBDEM_CORR_CTRL_RX_MAX_PREAMBLE(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CORR_CTRL_RX_MAX_PREAMBLE_SHIFT)) & XCVR_ZBDEM_CORR_CTRL_RX_MAX_PREAMBLE_MASK)
12166 
12167 /*! @name PN_TYPE - 802.15.4 DEMOD PN TYPE */
12168 #define XCVR_ZBDEM_PN_TYPE_PN_TYPE_MASK          (0x1U)
12169 #define XCVR_ZBDEM_PN_TYPE_PN_TYPE_SHIFT         (0U)
12170 #define XCVR_ZBDEM_PN_TYPE_PN_TYPE(x)            (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_PN_TYPE_PN_TYPE_SHIFT)) & XCVR_ZBDEM_PN_TYPE_PN_TYPE_MASK)
12171 #define XCVR_ZBDEM_PN_TYPE_TX_INV_MASK           (0x2U)
12172 #define XCVR_ZBDEM_PN_TYPE_TX_INV_SHIFT          (1U)
12173 #define XCVR_ZBDEM_PN_TYPE_TX_INV(x)             (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_PN_TYPE_TX_INV_SHIFT)) & XCVR_ZBDEM_PN_TYPE_TX_INV_MASK)
12174 
12175 /*! @name PN_CODE - 802.15.4 DEMOD PN CODE */
12176 #define XCVR_ZBDEM_PN_CODE_PN_LSB_MASK           (0xFFFFU)
12177 #define XCVR_ZBDEM_PN_CODE_PN_LSB_SHIFT          (0U)
12178 #define XCVR_ZBDEM_PN_CODE_PN_LSB(x)             (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_PN_CODE_PN_LSB_SHIFT)) & XCVR_ZBDEM_PN_CODE_PN_LSB_MASK)
12179 #define XCVR_ZBDEM_PN_CODE_PN_MSB_MASK           (0xFFFF0000U)
12180 #define XCVR_ZBDEM_PN_CODE_PN_MSB_SHIFT          (16U)
12181 #define XCVR_ZBDEM_PN_CODE_PN_MSB(x)             (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_PN_CODE_PN_MSB_SHIFT)) & XCVR_ZBDEM_PN_CODE_PN_MSB_MASK)
12182 
12183 /*! @name SYNC_CTRL - 802.15.4 DEMOD SYMBOL SYNC CONTROL */
12184 #define XCVR_ZBDEM_SYNC_CTRL_SYNC_PER_MASK       (0x7U)
12185 #define XCVR_ZBDEM_SYNC_CTRL_SYNC_PER_SHIFT      (0U)
12186 #define XCVR_ZBDEM_SYNC_CTRL_SYNC_PER(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_SYNC_CTRL_SYNC_PER_SHIFT)) & XCVR_ZBDEM_SYNC_CTRL_SYNC_PER_MASK)
12187 #define XCVR_ZBDEM_SYNC_CTRL_TRACK_ENABLE_MASK   (0x8U)
12188 #define XCVR_ZBDEM_SYNC_CTRL_TRACK_ENABLE_SHIFT  (3U)
12189 #define XCVR_ZBDEM_SYNC_CTRL_TRACK_ENABLE(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_SYNC_CTRL_TRACK_ENABLE_SHIFT)) & XCVR_ZBDEM_SYNC_CTRL_TRACK_ENABLE_MASK)
12190 
12191 /*! @name CCA_LQI_SRC - 802.15.4 CCA/LQI SOURCE */
12192 #define XCVR_ZBDEM_CCA_LQI_SRC_CCA1_FROM_RX_DIG_MASK (0x1U)
12193 #define XCVR_ZBDEM_CCA_LQI_SRC_CCA1_FROM_RX_DIG_SHIFT (0U)
12194 #define XCVR_ZBDEM_CCA_LQI_SRC_CCA1_FROM_RX_DIG(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CCA_LQI_SRC_CCA1_FROM_RX_DIG_SHIFT)) & XCVR_ZBDEM_CCA_LQI_SRC_CCA1_FROM_RX_DIG_MASK)
12195 #define XCVR_ZBDEM_CCA_LQI_SRC_LQI_FROM_RX_DIG_MASK (0x2U)
12196 #define XCVR_ZBDEM_CCA_LQI_SRC_LQI_FROM_RX_DIG_SHIFT (1U)
12197 #define XCVR_ZBDEM_CCA_LQI_SRC_LQI_FROM_RX_DIG(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CCA_LQI_SRC_LQI_FROM_RX_DIG_SHIFT)) & XCVR_ZBDEM_CCA_LQI_SRC_LQI_FROM_RX_DIG_MASK)
12198 #define XCVR_ZBDEM_CCA_LQI_SRC_LQI_START_AT_SFD_MASK (0x4U)
12199 #define XCVR_ZBDEM_CCA_LQI_SRC_LQI_START_AT_SFD_SHIFT (2U)
12200 #define XCVR_ZBDEM_CCA_LQI_SRC_LQI_START_AT_SFD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CCA_LQI_SRC_LQI_START_AT_SFD_SHIFT)) & XCVR_ZBDEM_CCA_LQI_SRC_LQI_START_AT_SFD_MASK)
12201 
12202 /*! @name FAD_THR - FAD CORRELATOR THRESHOLD */
12203 #define XCVR_ZBDEM_FAD_THR_FAD_THR_MASK          (0xFFU)
12204 #define XCVR_ZBDEM_FAD_THR_FAD_THR_SHIFT         (0U)
12205 #define XCVR_ZBDEM_FAD_THR_FAD_THR(x)            (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_FAD_THR_FAD_THR_SHIFT)) & XCVR_ZBDEM_FAD_THR_FAD_THR_MASK)
12206 
12207 /*! @name ZBDEM_AFC - 802.15.4 AFC STATUS */
12208 #define XCVR_ZBDEM_ZBDEM_AFC_AFC_EN_MASK         (0x1U)
12209 #define XCVR_ZBDEM_ZBDEM_AFC_AFC_EN_SHIFT        (0U)
12210 #define XCVR_ZBDEM_ZBDEM_AFC_AFC_EN(x)           (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_ZBDEM_AFC_AFC_EN_SHIFT)) & XCVR_ZBDEM_ZBDEM_AFC_AFC_EN_MASK)
12211 #define XCVR_ZBDEM_ZBDEM_AFC_DCD_EN_MASK         (0x2U)
12212 #define XCVR_ZBDEM_ZBDEM_AFC_DCD_EN_SHIFT        (1U)
12213 #define XCVR_ZBDEM_ZBDEM_AFC_DCD_EN(x)           (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_ZBDEM_AFC_DCD_EN_SHIFT)) & XCVR_ZBDEM_ZBDEM_AFC_DCD_EN_MASK)
12214 #define XCVR_ZBDEM_ZBDEM_AFC_AFC_OUT_MASK        (0x1F00U)
12215 #define XCVR_ZBDEM_ZBDEM_AFC_AFC_OUT_SHIFT       (8U)
12216 #define XCVR_ZBDEM_ZBDEM_AFC_AFC_OUT(x)          (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_ZBDEM_AFC_AFC_OUT_SHIFT)) & XCVR_ZBDEM_ZBDEM_AFC_AFC_OUT_MASK)
12217 
12218 
12219 /*!
12220  * @}
12221  */ /* end of group XCVR_ZBDEM_Register_Masks */
12222 
12223 
12224 /* XCVR_ZBDEM - Peripheral instance base addresses */
12225 /** Peripheral XCVR_ZBDEM base address */
12226 #define XCVR_ZBDEM_BASE                          (0x4005C480u)
12227 /** Peripheral XCVR_ZBDEM base pointer */
12228 #define XCVR_ZBDEM                               ((XCVR_ZBDEM_Type *)XCVR_ZBDEM_BASE)
12229 /** Array initializer of XCVR_ZBDEM peripheral base addresses */
12230 #define XCVR_ZBDEM_BASE_ADDRS                    { XCVR_ZBDEM_BASE }
12231 /** Array initializer of XCVR_ZBDEM peripheral base pointers */
12232 #define XCVR_ZBDEM_BASE_PTRS                     { XCVR_ZBDEM }
12233 
12234 /*!
12235  * @}
12236  */ /* end of group XCVR_ZBDEM_Peripheral_Access_Layer */
12237 
12238 
12239 /* ----------------------------------------------------------------------------
12240    -- ZLL Peripheral Access Layer
12241    ---------------------------------------------------------------------------- */
12242 
12243 /*!
12244  * @addtogroup ZLL_Peripheral_Access_Layer ZLL Peripheral Access Layer
12245  * @{
12246  */
12247 
12248 /** ZLL - Register Layout Typedef */
12249 typedef struct {
12250   __IO uint32_t IRQSTS;                            /**< INTERRUPT REQUEST STATUS, offset: 0x0 */
12251   __IO uint32_t PHY_CTRL;                          /**< PHY CONTROL, offset: 0x4 */
12252   __IO uint32_t EVENT_TMR;                         /**< EVENT TIMER, offset: 0x8 */
12253   __I  uint32_t TIMESTAMP;                         /**< TIMESTAMP, offset: 0xC */
12254   __IO uint32_t T1CMP;                             /**< T1 COMPARE, offset: 0x10 */
12255   __IO uint32_t T2CMP;                             /**< T2 COMPARE, offset: 0x14 */
12256   __IO uint32_t T2PRIMECMP;                        /**< T2 PRIME COMPARE, offset: 0x18 */
12257   __IO uint32_t T3CMP;                             /**< T3 COMPARE, offset: 0x1C */
12258   __IO uint32_t T4CMP;                             /**< T4 COMPARE, offset: 0x20 */
12259   __IO uint32_t PA_PWR;                            /**< PA POWER, offset: 0x24 */
12260   __IO uint32_t CHANNEL_NUM0;                      /**< CHANNEL NUMBER 0, offset: 0x28 */
12261   __I  uint32_t LQI_AND_RSSI;                      /**< LQI AND RSSI, offset: 0x2C */
12262   __IO uint32_t MACSHORTADDRS0;                    /**< MAC SHORT ADDRESS 0, offset: 0x30 */
12263   __IO uint32_t MACLONGADDRS0_LSB;                 /**< MAC LONG ADDRESS 0 LSB, offset: 0x34 */
12264   __IO uint32_t MACLONGADDRS0_MSB;                 /**< MAC LONG ADDRESS 0 MSB, offset: 0x38 */
12265   __IO uint32_t RX_FRAME_FILTER;                   /**< RECEIVE FRAME FILTER, offset: 0x3C */
12266   __IO uint32_t CCA_LQI_CTRL;                      /**< CCA AND LQI CONTROL, offset: 0x40 */
12267   __IO uint32_t CCA2_CTRL;                         /**< CCA2 CONTROL, offset: 0x44 */
12268        uint8_t RESERVED_0[4];
12269   __IO uint32_t DSM_CTRL;                          /**< DSM CONTROL, offset: 0x4C */
12270   __IO uint32_t BSM_CTRL;                          /**< BSM CONTROL, offset: 0x50 */
12271   __IO uint32_t MACSHORTADDRS1;                    /**< MAC SHORT ADDRESS FOR PAN1, offset: 0x54 */
12272   __IO uint32_t MACLONGADDRS1_LSB;                 /**< MAC LONG ADDRESS 1 LSB, offset: 0x58 */
12273   __IO uint32_t MACLONGADDRS1_MSB;                 /**< MAC LONG ADDRESS 1 MSB, offset: 0x5C */
12274   __IO uint32_t DUAL_PAN_CTRL;                     /**< DUAL PAN CONTROL, offset: 0x60 */
12275   __IO uint32_t CHANNEL_NUM1;                      /**< CHANNEL NUMBER 1, offset: 0x64 */
12276   __IO uint32_t SAM_CTRL;                          /**< SAM CONTROL, offset: 0x68 */
12277   __IO uint32_t SAM_TABLE;                         /**< SOURCE ADDRESS MANAGEMENT TABLE, offset: 0x6C */
12278   __I  uint32_t SAM_MATCH;                         /**< SOURCE ADDRESS MANAGEMENT MATCH, offset: 0x70 */
12279   __I  uint32_t SAM_FREE_IDX;                      /**< SAM FREE INDEX, offset: 0x74 */
12280   __IO uint32_t SEQ_CTRL_STS;                      /**< SEQUENCE CONTROL AND STATUS, offset: 0x78 */
12281   __IO uint32_t ACKDELAY;                          /**< ACK DELAY, offset: 0x7C */
12282   __IO uint32_t FILTERFAIL_CODE;                   /**< FILTER FAIL CODE, offset: 0x80 */
12283   __IO uint32_t RX_WTR_MARK;                       /**< RECEIVE WATER MARK, offset: 0x84 */
12284        uint8_t RESERVED_1[4];
12285   __IO uint32_t SLOT_PRELOAD;                      /**< SLOT PRELOAD, offset: 0x8C */
12286   __I  uint32_t SEQ_STATE;                         /**< 802.15.4 SEQUENCE STATE, offset: 0x90 */
12287   __IO uint32_t TMR_PRESCALE;                      /**< TIMER PRESCALER, offset: 0x94 */
12288   __IO uint32_t LENIENCY_LSB;                      /**< LENIENCY LSB, offset: 0x98 */
12289   __IO uint32_t LENIENCY_MSB;                      /**< LENIENCY MSB, offset: 0x9C */
12290   __I  uint32_t PART_ID;                           /**< PART ID, offset: 0xA0 */
12291        uint8_t RESERVED_2[92];
12292   __IO uint16_t PKT_BUFFER_TX[64];                 /**< Packet Buffer TX, array offset: 0x100, array step: 0x2 */
12293   __IO uint16_t PKT_BUFFER_RX[64];                 /**< Packet Buffer RX, array offset: 0x180, array step: 0x2 */
12294 } ZLL_Type;
12295 
12296 /* ----------------------------------------------------------------------------
12297    -- ZLL Register Masks
12298    ---------------------------------------------------------------------------- */
12299 
12300 /*!
12301  * @addtogroup ZLL_Register_Masks ZLL Register Masks
12302  * @{
12303  */
12304 
12305 /*! @name IRQSTS - INTERRUPT REQUEST STATUS */
12306 #define ZLL_IRQSTS_SEQIRQ_MASK                   (0x1U)
12307 #define ZLL_IRQSTS_SEQIRQ_SHIFT                  (0U)
12308 #define ZLL_IRQSTS_SEQIRQ(x)                     (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_SEQIRQ_SHIFT)) & ZLL_IRQSTS_SEQIRQ_MASK)
12309 #define ZLL_IRQSTS_TXIRQ_MASK                    (0x2U)
12310 #define ZLL_IRQSTS_TXIRQ_SHIFT                   (1U)
12311 #define ZLL_IRQSTS_TXIRQ(x)                      (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_TXIRQ_SHIFT)) & ZLL_IRQSTS_TXIRQ_MASK)
12312 #define ZLL_IRQSTS_RXIRQ_MASK                    (0x4U)
12313 #define ZLL_IRQSTS_RXIRQ_SHIFT                   (2U)
12314 #define ZLL_IRQSTS_RXIRQ(x)                      (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_RXIRQ_SHIFT)) & ZLL_IRQSTS_RXIRQ_MASK)
12315 #define ZLL_IRQSTS_CCAIRQ_MASK                   (0x8U)
12316 #define ZLL_IRQSTS_CCAIRQ_SHIFT                  (3U)
12317 #define ZLL_IRQSTS_CCAIRQ(x)                     (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_CCAIRQ_SHIFT)) & ZLL_IRQSTS_CCAIRQ_MASK)
12318 #define ZLL_IRQSTS_RXWTRMRKIRQ_MASK              (0x10U)
12319 #define ZLL_IRQSTS_RXWTRMRKIRQ_SHIFT             (4U)
12320 #define ZLL_IRQSTS_RXWTRMRKIRQ(x)                (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_RXWTRMRKIRQ_SHIFT)) & ZLL_IRQSTS_RXWTRMRKIRQ_MASK)
12321 #define ZLL_IRQSTS_FILTERFAIL_IRQ_MASK           (0x20U)
12322 #define ZLL_IRQSTS_FILTERFAIL_IRQ_SHIFT          (5U)
12323 #define ZLL_IRQSTS_FILTERFAIL_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_FILTERFAIL_IRQ_SHIFT)) & ZLL_IRQSTS_FILTERFAIL_IRQ_MASK)
12324 #define ZLL_IRQSTS_PLL_UNLOCK_IRQ_MASK           (0x40U)
12325 #define ZLL_IRQSTS_PLL_UNLOCK_IRQ_SHIFT          (6U)
12326 #define ZLL_IRQSTS_PLL_UNLOCK_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_PLL_UNLOCK_IRQ_SHIFT)) & ZLL_IRQSTS_PLL_UNLOCK_IRQ_MASK)
12327 #define ZLL_IRQSTS_RX_FRM_PEND_MASK              (0x80U)
12328 #define ZLL_IRQSTS_RX_FRM_PEND_SHIFT             (7U)
12329 #define ZLL_IRQSTS_RX_FRM_PEND(x)                (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_RX_FRM_PEND_SHIFT)) & ZLL_IRQSTS_RX_FRM_PEND_MASK)
12330 #define ZLL_IRQSTS_WAKE_IRQ_MASK                 (0x100U)
12331 #define ZLL_IRQSTS_WAKE_IRQ_SHIFT                (8U)
12332 #define ZLL_IRQSTS_WAKE_IRQ(x)                   (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_WAKE_IRQ_SHIFT)) & ZLL_IRQSTS_WAKE_IRQ_MASK)
12333 #define ZLL_IRQSTS_TSM_IRQ_MASK                  (0x400U)
12334 #define ZLL_IRQSTS_TSM_IRQ_SHIFT                 (10U)
12335 #define ZLL_IRQSTS_TSM_IRQ(x)                    (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_TSM_IRQ_SHIFT)) & ZLL_IRQSTS_TSM_IRQ_MASK)
12336 #define ZLL_IRQSTS_ENH_PKT_STATUS_MASK           (0x800U)
12337 #define ZLL_IRQSTS_ENH_PKT_STATUS_SHIFT          (11U)
12338 #define ZLL_IRQSTS_ENH_PKT_STATUS(x)             (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_ENH_PKT_STATUS_SHIFT)) & ZLL_IRQSTS_ENH_PKT_STATUS_MASK)
12339 #define ZLL_IRQSTS_PI_MASK                       (0x1000U)
12340 #define ZLL_IRQSTS_PI_SHIFT                      (12U)
12341 #define ZLL_IRQSTS_PI(x)                         (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_PI_SHIFT)) & ZLL_IRQSTS_PI_MASK)
12342 #define ZLL_IRQSTS_SRCADDR_MASK                  (0x2000U)
12343 #define ZLL_IRQSTS_SRCADDR_SHIFT                 (13U)
12344 #define ZLL_IRQSTS_SRCADDR(x)                    (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_SRCADDR_SHIFT)) & ZLL_IRQSTS_SRCADDR_MASK)
12345 #define ZLL_IRQSTS_CCA_MASK                      (0x4000U)
12346 #define ZLL_IRQSTS_CCA_SHIFT                     (14U)
12347 #define ZLL_IRQSTS_CCA(x)                        (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_CCA_SHIFT)) & ZLL_IRQSTS_CCA_MASK)
12348 #define ZLL_IRQSTS_CRCVALID_MASK                 (0x8000U)
12349 #define ZLL_IRQSTS_CRCVALID_SHIFT                (15U)
12350 #define ZLL_IRQSTS_CRCVALID(x)                   (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_CRCVALID_SHIFT)) & ZLL_IRQSTS_CRCVALID_MASK)
12351 #define ZLL_IRQSTS_TMR1IRQ_MASK                  (0x10000U)
12352 #define ZLL_IRQSTS_TMR1IRQ_SHIFT                 (16U)
12353 #define ZLL_IRQSTS_TMR1IRQ(x)                    (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_TMR1IRQ_SHIFT)) & ZLL_IRQSTS_TMR1IRQ_MASK)
12354 #define ZLL_IRQSTS_TMR2IRQ_MASK                  (0x20000U)
12355 #define ZLL_IRQSTS_TMR2IRQ_SHIFT                 (17U)
12356 #define ZLL_IRQSTS_TMR2IRQ(x)                    (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_TMR2IRQ_SHIFT)) & ZLL_IRQSTS_TMR2IRQ_MASK)
12357 #define ZLL_IRQSTS_TMR3IRQ_MASK                  (0x40000U)
12358 #define ZLL_IRQSTS_TMR3IRQ_SHIFT                 (18U)
12359 #define ZLL_IRQSTS_TMR3IRQ(x)                    (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_TMR3IRQ_SHIFT)) & ZLL_IRQSTS_TMR3IRQ_MASK)
12360 #define ZLL_IRQSTS_TMR4IRQ_MASK                  (0x80000U)
12361 #define ZLL_IRQSTS_TMR4IRQ_SHIFT                 (19U)
12362 #define ZLL_IRQSTS_TMR4IRQ(x)                    (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_TMR4IRQ_SHIFT)) & ZLL_IRQSTS_TMR4IRQ_MASK)
12363 #define ZLL_IRQSTS_TMR1MSK_MASK                  (0x100000U)
12364 #define ZLL_IRQSTS_TMR1MSK_SHIFT                 (20U)
12365 #define ZLL_IRQSTS_TMR1MSK(x)                    (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_TMR1MSK_SHIFT)) & ZLL_IRQSTS_TMR1MSK_MASK)
12366 #define ZLL_IRQSTS_TMR2MSK_MASK                  (0x200000U)
12367 #define ZLL_IRQSTS_TMR2MSK_SHIFT                 (21U)
12368 #define ZLL_IRQSTS_TMR2MSK(x)                    (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_TMR2MSK_SHIFT)) & ZLL_IRQSTS_TMR2MSK_MASK)
12369 #define ZLL_IRQSTS_TMR3MSK_MASK                  (0x400000U)
12370 #define ZLL_IRQSTS_TMR3MSK_SHIFT                 (22U)
12371 #define ZLL_IRQSTS_TMR3MSK(x)                    (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_TMR3MSK_SHIFT)) & ZLL_IRQSTS_TMR3MSK_MASK)
12372 #define ZLL_IRQSTS_TMR4MSK_MASK                  (0x800000U)
12373 #define ZLL_IRQSTS_TMR4MSK_SHIFT                 (23U)
12374 #define ZLL_IRQSTS_TMR4MSK(x)                    (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_TMR4MSK_SHIFT)) & ZLL_IRQSTS_TMR4MSK_MASK)
12375 #define ZLL_IRQSTS_RX_FRAME_LENGTH_MASK          (0x7F000000U)
12376 #define ZLL_IRQSTS_RX_FRAME_LENGTH_SHIFT         (24U)
12377 #define ZLL_IRQSTS_RX_FRAME_LENGTH(x)            (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_RX_FRAME_LENGTH_SHIFT)) & ZLL_IRQSTS_RX_FRAME_LENGTH_MASK)
12378 
12379 /*! @name PHY_CTRL - PHY CONTROL */
12380 #define ZLL_PHY_CTRL_XCVSEQ_MASK                 (0x7U)
12381 #define ZLL_PHY_CTRL_XCVSEQ_SHIFT                (0U)
12382 #define ZLL_PHY_CTRL_XCVSEQ(x)                   (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_XCVSEQ_SHIFT)) & ZLL_PHY_CTRL_XCVSEQ_MASK)
12383 #define ZLL_PHY_CTRL_AUTOACK_MASK                (0x8U)
12384 #define ZLL_PHY_CTRL_AUTOACK_SHIFT               (3U)
12385 #define ZLL_PHY_CTRL_AUTOACK(x)                  (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_AUTOACK_SHIFT)) & ZLL_PHY_CTRL_AUTOACK_MASK)
12386 #define ZLL_PHY_CTRL_RXACKRQD_MASK               (0x10U)
12387 #define ZLL_PHY_CTRL_RXACKRQD_SHIFT              (4U)
12388 #define ZLL_PHY_CTRL_RXACKRQD(x)                 (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_RXACKRQD_SHIFT)) & ZLL_PHY_CTRL_RXACKRQD_MASK)
12389 #define ZLL_PHY_CTRL_CCABFRTX_MASK               (0x20U)
12390 #define ZLL_PHY_CTRL_CCABFRTX_SHIFT              (5U)
12391 #define ZLL_PHY_CTRL_CCABFRTX(x)                 (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_CCABFRTX_SHIFT)) & ZLL_PHY_CTRL_CCABFRTX_MASK)
12392 #define ZLL_PHY_CTRL_SLOTTED_MASK                (0x40U)
12393 #define ZLL_PHY_CTRL_SLOTTED_SHIFT               (6U)
12394 #define ZLL_PHY_CTRL_SLOTTED(x)                  (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_SLOTTED_SHIFT)) & ZLL_PHY_CTRL_SLOTTED_MASK)
12395 #define ZLL_PHY_CTRL_TMRTRIGEN_MASK              (0x80U)
12396 #define ZLL_PHY_CTRL_TMRTRIGEN_SHIFT             (7U)
12397 #define ZLL_PHY_CTRL_TMRTRIGEN(x)                (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_TMRTRIGEN_SHIFT)) & ZLL_PHY_CTRL_TMRTRIGEN_MASK)
12398 #define ZLL_PHY_CTRL_SEQMSK_MASK                 (0x100U)
12399 #define ZLL_PHY_CTRL_SEQMSK_SHIFT                (8U)
12400 #define ZLL_PHY_CTRL_SEQMSK(x)                   (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_SEQMSK_SHIFT)) & ZLL_PHY_CTRL_SEQMSK_MASK)
12401 #define ZLL_PHY_CTRL_TXMSK_MASK                  (0x200U)
12402 #define ZLL_PHY_CTRL_TXMSK_SHIFT                 (9U)
12403 #define ZLL_PHY_CTRL_TXMSK(x)                    (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_TXMSK_SHIFT)) & ZLL_PHY_CTRL_TXMSK_MASK)
12404 #define ZLL_PHY_CTRL_RXMSK_MASK                  (0x400U)
12405 #define ZLL_PHY_CTRL_RXMSK_SHIFT                 (10U)
12406 #define ZLL_PHY_CTRL_RXMSK(x)                    (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_RXMSK_SHIFT)) & ZLL_PHY_CTRL_RXMSK_MASK)
12407 #define ZLL_PHY_CTRL_CCAMSK_MASK                 (0x800U)
12408 #define ZLL_PHY_CTRL_CCAMSK_SHIFT                (11U)
12409 #define ZLL_PHY_CTRL_CCAMSK(x)                   (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_CCAMSK_SHIFT)) & ZLL_PHY_CTRL_CCAMSK_MASK)
12410 #define ZLL_PHY_CTRL_RX_WMRK_MSK_MASK            (0x1000U)
12411 #define ZLL_PHY_CTRL_RX_WMRK_MSK_SHIFT           (12U)
12412 #define ZLL_PHY_CTRL_RX_WMRK_MSK(x)              (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_RX_WMRK_MSK_SHIFT)) & ZLL_PHY_CTRL_RX_WMRK_MSK_MASK)
12413 #define ZLL_PHY_CTRL_FILTERFAIL_MSK_MASK         (0x2000U)
12414 #define ZLL_PHY_CTRL_FILTERFAIL_MSK_SHIFT        (13U)
12415 #define ZLL_PHY_CTRL_FILTERFAIL_MSK(x)           (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_FILTERFAIL_MSK_SHIFT)) & ZLL_PHY_CTRL_FILTERFAIL_MSK_MASK)
12416 #define ZLL_PHY_CTRL_PLL_UNLOCK_MSK_MASK         (0x4000U)
12417 #define ZLL_PHY_CTRL_PLL_UNLOCK_MSK_SHIFT        (14U)
12418 #define ZLL_PHY_CTRL_PLL_UNLOCK_MSK(x)           (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_PLL_UNLOCK_MSK_SHIFT)) & ZLL_PHY_CTRL_PLL_UNLOCK_MSK_MASK)
12419 #define ZLL_PHY_CTRL_CRC_MSK_MASK                (0x8000U)
12420 #define ZLL_PHY_CTRL_CRC_MSK_SHIFT               (15U)
12421 #define ZLL_PHY_CTRL_CRC_MSK(x)                  (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_CRC_MSK_SHIFT)) & ZLL_PHY_CTRL_CRC_MSK_MASK)
12422 #define ZLL_PHY_CTRL_WAKE_MSK_MASK               (0x10000U)
12423 #define ZLL_PHY_CTRL_WAKE_MSK_SHIFT              (16U)
12424 #define ZLL_PHY_CTRL_WAKE_MSK(x)                 (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_WAKE_MSK_SHIFT)) & ZLL_PHY_CTRL_WAKE_MSK_MASK)
12425 #define ZLL_PHY_CTRL_TSM_MSK_MASK                (0x40000U)
12426 #define ZLL_PHY_CTRL_TSM_MSK_SHIFT               (18U)
12427 #define ZLL_PHY_CTRL_TSM_MSK(x)                  (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_TSM_MSK_SHIFT)) & ZLL_PHY_CTRL_TSM_MSK_MASK)
12428 #define ZLL_PHY_CTRL_TMR1CMP_EN_MASK             (0x100000U)
12429 #define ZLL_PHY_CTRL_TMR1CMP_EN_SHIFT            (20U)
12430 #define ZLL_PHY_CTRL_TMR1CMP_EN(x)               (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_TMR1CMP_EN_SHIFT)) & ZLL_PHY_CTRL_TMR1CMP_EN_MASK)
12431 #define ZLL_PHY_CTRL_TMR2CMP_EN_MASK             (0x200000U)
12432 #define ZLL_PHY_CTRL_TMR2CMP_EN_SHIFT            (21U)
12433 #define ZLL_PHY_CTRL_TMR2CMP_EN(x)               (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_TMR2CMP_EN_SHIFT)) & ZLL_PHY_CTRL_TMR2CMP_EN_MASK)
12434 #define ZLL_PHY_CTRL_TMR3CMP_EN_MASK             (0x400000U)
12435 #define ZLL_PHY_CTRL_TMR3CMP_EN_SHIFT            (22U)
12436 #define ZLL_PHY_CTRL_TMR3CMP_EN(x)               (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_TMR3CMP_EN_SHIFT)) & ZLL_PHY_CTRL_TMR3CMP_EN_MASK)
12437 #define ZLL_PHY_CTRL_TMR4CMP_EN_MASK             (0x800000U)
12438 #define ZLL_PHY_CTRL_TMR4CMP_EN_SHIFT            (23U)
12439 #define ZLL_PHY_CTRL_TMR4CMP_EN(x)               (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_TMR4CMP_EN_SHIFT)) & ZLL_PHY_CTRL_TMR4CMP_EN_MASK)
12440 #define ZLL_PHY_CTRL_TC2PRIME_EN_MASK            (0x1000000U)
12441 #define ZLL_PHY_CTRL_TC2PRIME_EN_SHIFT           (24U)
12442 #define ZLL_PHY_CTRL_TC2PRIME_EN(x)              (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_TC2PRIME_EN_SHIFT)) & ZLL_PHY_CTRL_TC2PRIME_EN_MASK)
12443 #define ZLL_PHY_CTRL_PROMISCUOUS_MASK            (0x2000000U)
12444 #define ZLL_PHY_CTRL_PROMISCUOUS_SHIFT           (25U)
12445 #define ZLL_PHY_CTRL_PROMISCUOUS(x)              (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_PROMISCUOUS_SHIFT)) & ZLL_PHY_CTRL_PROMISCUOUS_MASK)
12446 #define ZLL_PHY_CTRL_CCATYPE_MASK                (0x18000000U)
12447 #define ZLL_PHY_CTRL_CCATYPE_SHIFT               (27U)
12448 #define ZLL_PHY_CTRL_CCATYPE(x)                  (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_CCATYPE_SHIFT)) & ZLL_PHY_CTRL_CCATYPE_MASK)
12449 #define ZLL_PHY_CTRL_PANCORDNTR0_MASK            (0x20000000U)
12450 #define ZLL_PHY_CTRL_PANCORDNTR0_SHIFT           (29U)
12451 #define ZLL_PHY_CTRL_PANCORDNTR0(x)              (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_PANCORDNTR0_SHIFT)) & ZLL_PHY_CTRL_PANCORDNTR0_MASK)
12452 #define ZLL_PHY_CTRL_TC3TMOUT_MASK               (0x40000000U)
12453 #define ZLL_PHY_CTRL_TC3TMOUT_SHIFT              (30U)
12454 #define ZLL_PHY_CTRL_TC3TMOUT(x)                 (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_TC3TMOUT_SHIFT)) & ZLL_PHY_CTRL_TC3TMOUT_MASK)
12455 #define ZLL_PHY_CTRL_TRCV_MSK_MASK               (0x80000000U)
12456 #define ZLL_PHY_CTRL_TRCV_MSK_SHIFT              (31U)
12457 #define ZLL_PHY_CTRL_TRCV_MSK(x)                 (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_TRCV_MSK_SHIFT)) & ZLL_PHY_CTRL_TRCV_MSK_MASK)
12458 
12459 /*! @name EVENT_TMR - EVENT TIMER */
12460 #define ZLL_EVENT_TMR_EVENT_TMR_LD_MASK          (0x1U)
12461 #define ZLL_EVENT_TMR_EVENT_TMR_LD_SHIFT         (0U)
12462 #define ZLL_EVENT_TMR_EVENT_TMR_LD(x)            (((uint32_t)(((uint32_t)(x)) << ZLL_EVENT_TMR_EVENT_TMR_LD_SHIFT)) & ZLL_EVENT_TMR_EVENT_TMR_LD_MASK)
12463 #define ZLL_EVENT_TMR_EVENT_TMR_ADD_MASK         (0x2U)
12464 #define ZLL_EVENT_TMR_EVENT_TMR_ADD_SHIFT        (1U)
12465 #define ZLL_EVENT_TMR_EVENT_TMR_ADD(x)           (((uint32_t)(((uint32_t)(x)) << ZLL_EVENT_TMR_EVENT_TMR_ADD_SHIFT)) & ZLL_EVENT_TMR_EVENT_TMR_ADD_MASK)
12466 #define ZLL_EVENT_TMR_EVENT_TMR_FRAC_MASK        (0xF0U)
12467 #define ZLL_EVENT_TMR_EVENT_TMR_FRAC_SHIFT       (4U)
12468 #define ZLL_EVENT_TMR_EVENT_TMR_FRAC(x)          (((uint32_t)(((uint32_t)(x)) << ZLL_EVENT_TMR_EVENT_TMR_FRAC_SHIFT)) & ZLL_EVENT_TMR_EVENT_TMR_FRAC_MASK)
12469 #define ZLL_EVENT_TMR_EVENT_TMR_MASK             (0xFFFFFF00U)
12470 #define ZLL_EVENT_TMR_EVENT_TMR_SHIFT            (8U)
12471 #define ZLL_EVENT_TMR_EVENT_TMR(x)               (((uint32_t)(((uint32_t)(x)) << ZLL_EVENT_TMR_EVENT_TMR_SHIFT)) & ZLL_EVENT_TMR_EVENT_TMR_MASK)
12472 
12473 /*! @name TIMESTAMP - TIMESTAMP */
12474 #define ZLL_TIMESTAMP_TIMESTAMP_MASK             (0xFFFFFFU)
12475 #define ZLL_TIMESTAMP_TIMESTAMP_SHIFT            (0U)
12476 #define ZLL_TIMESTAMP_TIMESTAMP(x)               (((uint32_t)(((uint32_t)(x)) << ZLL_TIMESTAMP_TIMESTAMP_SHIFT)) & ZLL_TIMESTAMP_TIMESTAMP_MASK)
12477 
12478 /*! @name T1CMP - T1 COMPARE */
12479 #define ZLL_T1CMP_T1CMP_MASK                     (0xFFFFFFU)
12480 #define ZLL_T1CMP_T1CMP_SHIFT                    (0U)
12481 #define ZLL_T1CMP_T1CMP(x)                       (((uint32_t)(((uint32_t)(x)) << ZLL_T1CMP_T1CMP_SHIFT)) & ZLL_T1CMP_T1CMP_MASK)
12482 
12483 /*! @name T2CMP - T2 COMPARE */
12484 #define ZLL_T2CMP_T2CMP_MASK                     (0xFFFFFFU)
12485 #define ZLL_T2CMP_T2CMP_SHIFT                    (0U)
12486 #define ZLL_T2CMP_T2CMP(x)                       (((uint32_t)(((uint32_t)(x)) << ZLL_T2CMP_T2CMP_SHIFT)) & ZLL_T2CMP_T2CMP_MASK)
12487 
12488 /*! @name T2PRIMECMP - T2 PRIME COMPARE */
12489 #define ZLL_T2PRIMECMP_T2PRIMECMP_MASK           (0xFFFFU)
12490 #define ZLL_T2PRIMECMP_T2PRIMECMP_SHIFT          (0U)
12491 #define ZLL_T2PRIMECMP_T2PRIMECMP(x)             (((uint32_t)(((uint32_t)(x)) << ZLL_T2PRIMECMP_T2PRIMECMP_SHIFT)) & ZLL_T2PRIMECMP_T2PRIMECMP_MASK)
12492 
12493 /*! @name T3CMP - T3 COMPARE */
12494 #define ZLL_T3CMP_T3CMP_MASK                     (0xFFFFFFU)
12495 #define ZLL_T3CMP_T3CMP_SHIFT                    (0U)
12496 #define ZLL_T3CMP_T3CMP(x)                       (((uint32_t)(((uint32_t)(x)) << ZLL_T3CMP_T3CMP_SHIFT)) & ZLL_T3CMP_T3CMP_MASK)
12497 
12498 /*! @name T4CMP - T4 COMPARE */
12499 #define ZLL_T4CMP_T4CMP_MASK                     (0xFFFFFFU)
12500 #define ZLL_T4CMP_T4CMP_SHIFT                    (0U)
12501 #define ZLL_T4CMP_T4CMP(x)                       (((uint32_t)(((uint32_t)(x)) << ZLL_T4CMP_T4CMP_SHIFT)) & ZLL_T4CMP_T4CMP_MASK)
12502 
12503 /*! @name PA_PWR - PA POWER */
12504 #define ZLL_PA_PWR_PA_PWR_MASK                   (0x3FU)
12505 #define ZLL_PA_PWR_PA_PWR_SHIFT                  (0U)
12506 #define ZLL_PA_PWR_PA_PWR(x)                     (((uint32_t)(((uint32_t)(x)) << ZLL_PA_PWR_PA_PWR_SHIFT)) & ZLL_PA_PWR_PA_PWR_MASK)
12507 
12508 /*! @name CHANNEL_NUM0 - CHANNEL NUMBER 0 */
12509 #define ZLL_CHANNEL_NUM0_CHANNEL_NUM0_MASK       (0x7FU)
12510 #define ZLL_CHANNEL_NUM0_CHANNEL_NUM0_SHIFT      (0U)
12511 #define ZLL_CHANNEL_NUM0_CHANNEL_NUM0(x)         (((uint32_t)(((uint32_t)(x)) << ZLL_CHANNEL_NUM0_CHANNEL_NUM0_SHIFT)) & ZLL_CHANNEL_NUM0_CHANNEL_NUM0_MASK)
12512 
12513 /*! @name LQI_AND_RSSI - LQI AND RSSI */
12514 #define ZLL_LQI_AND_RSSI_LQI_VALUE_MASK          (0xFFU)
12515 #define ZLL_LQI_AND_RSSI_LQI_VALUE_SHIFT         (0U)
12516 #define ZLL_LQI_AND_RSSI_LQI_VALUE(x)            (((uint32_t)(((uint32_t)(x)) << ZLL_LQI_AND_RSSI_LQI_VALUE_SHIFT)) & ZLL_LQI_AND_RSSI_LQI_VALUE_MASK)
12517 #define ZLL_LQI_AND_RSSI_RSSI_MASK               (0xFF00U)
12518 #define ZLL_LQI_AND_RSSI_RSSI_SHIFT              (8U)
12519 #define ZLL_LQI_AND_RSSI_RSSI(x)                 (((uint32_t)(((uint32_t)(x)) << ZLL_LQI_AND_RSSI_RSSI_SHIFT)) & ZLL_LQI_AND_RSSI_RSSI_MASK)
12520 #define ZLL_LQI_AND_RSSI_CCA1_ED_FNL_MASK        (0xFF0000U)
12521 #define ZLL_LQI_AND_RSSI_CCA1_ED_FNL_SHIFT       (16U)
12522 #define ZLL_LQI_AND_RSSI_CCA1_ED_FNL(x)          (((uint32_t)(((uint32_t)(x)) << ZLL_LQI_AND_RSSI_CCA1_ED_FNL_SHIFT)) & ZLL_LQI_AND_RSSI_CCA1_ED_FNL_MASK)
12523 
12524 /*! @name MACSHORTADDRS0 - MAC SHORT ADDRESS 0 */
12525 #define ZLL_MACSHORTADDRS0_MACPANID0_MASK        (0xFFFFU)
12526 #define ZLL_MACSHORTADDRS0_MACPANID0_SHIFT       (0U)
12527 #define ZLL_MACSHORTADDRS0_MACPANID0(x)          (((uint32_t)(((uint32_t)(x)) << ZLL_MACSHORTADDRS0_MACPANID0_SHIFT)) & ZLL_MACSHORTADDRS0_MACPANID0_MASK)
12528 #define ZLL_MACSHORTADDRS0_MACSHORTADDRS0_MASK   (0xFFFF0000U)
12529 #define ZLL_MACSHORTADDRS0_MACSHORTADDRS0_SHIFT  (16U)
12530 #define ZLL_MACSHORTADDRS0_MACSHORTADDRS0(x)     (((uint32_t)(((uint32_t)(x)) << ZLL_MACSHORTADDRS0_MACSHORTADDRS0_SHIFT)) & ZLL_MACSHORTADDRS0_MACSHORTADDRS0_MASK)
12531 
12532 /*! @name MACLONGADDRS0_LSB - MAC LONG ADDRESS 0 LSB */
12533 #define ZLL_MACLONGADDRS0_LSB_MACLONGADDRS0_LSB_MASK (0xFFFFFFFFU)
12534 #define ZLL_MACLONGADDRS0_LSB_MACLONGADDRS0_LSB_SHIFT (0U)
12535 #define ZLL_MACLONGADDRS0_LSB_MACLONGADDRS0_LSB(x) (((uint32_t)(((uint32_t)(x)) << ZLL_MACLONGADDRS0_LSB_MACLONGADDRS0_LSB_SHIFT)) & ZLL_MACLONGADDRS0_LSB_MACLONGADDRS0_LSB_MASK)
12536 
12537 /*! @name MACLONGADDRS0_MSB - MAC LONG ADDRESS 0 MSB */
12538 #define ZLL_MACLONGADDRS0_MSB_MACLONGADDRS0_MSB_MASK (0xFFFFFFFFU)
12539 #define ZLL_MACLONGADDRS0_MSB_MACLONGADDRS0_MSB_SHIFT (0U)
12540 #define ZLL_MACLONGADDRS0_MSB_MACLONGADDRS0_MSB(x) (((uint32_t)(((uint32_t)(x)) << ZLL_MACLONGADDRS0_MSB_MACLONGADDRS0_MSB_SHIFT)) & ZLL_MACLONGADDRS0_MSB_MACLONGADDRS0_MSB_MASK)
12541 
12542 /*! @name RX_FRAME_FILTER - RECEIVE FRAME FILTER */
12543 #define ZLL_RX_FRAME_FILTER_BEACON_FT_MASK       (0x1U)
12544 #define ZLL_RX_FRAME_FILTER_BEACON_FT_SHIFT      (0U)
12545 #define ZLL_RX_FRAME_FILTER_BEACON_FT(x)         (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_BEACON_FT_SHIFT)) & ZLL_RX_FRAME_FILTER_BEACON_FT_MASK)
12546 #define ZLL_RX_FRAME_FILTER_DATA_FT_MASK         (0x2U)
12547 #define ZLL_RX_FRAME_FILTER_DATA_FT_SHIFT        (1U)
12548 #define ZLL_RX_FRAME_FILTER_DATA_FT(x)           (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_DATA_FT_SHIFT)) & ZLL_RX_FRAME_FILTER_DATA_FT_MASK)
12549 #define ZLL_RX_FRAME_FILTER_ACK_FT_MASK          (0x4U)
12550 #define ZLL_RX_FRAME_FILTER_ACK_FT_SHIFT         (2U)
12551 #define ZLL_RX_FRAME_FILTER_ACK_FT(x)            (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_ACK_FT_SHIFT)) & ZLL_RX_FRAME_FILTER_ACK_FT_MASK)
12552 #define ZLL_RX_FRAME_FILTER_CMD_FT_MASK          (0x8U)
12553 #define ZLL_RX_FRAME_FILTER_CMD_FT_SHIFT         (3U)
12554 #define ZLL_RX_FRAME_FILTER_CMD_FT(x)            (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_CMD_FT_SHIFT)) & ZLL_RX_FRAME_FILTER_CMD_FT_MASK)
12555 #define ZLL_RX_FRAME_FILTER_LLDN_FT_MASK         (0x10U)
12556 #define ZLL_RX_FRAME_FILTER_LLDN_FT_SHIFT        (4U)
12557 #define ZLL_RX_FRAME_FILTER_LLDN_FT(x)           (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_LLDN_FT_SHIFT)) & ZLL_RX_FRAME_FILTER_LLDN_FT_MASK)
12558 #define ZLL_RX_FRAME_FILTER_MULTIPURPOSE_FT_MASK (0x20U)
12559 #define ZLL_RX_FRAME_FILTER_MULTIPURPOSE_FT_SHIFT (5U)
12560 #define ZLL_RX_FRAME_FILTER_MULTIPURPOSE_FT(x)   (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_MULTIPURPOSE_FT_SHIFT)) & ZLL_RX_FRAME_FILTER_MULTIPURPOSE_FT_MASK)
12561 #define ZLL_RX_FRAME_FILTER_NS_FT_MASK           (0x40U)
12562 #define ZLL_RX_FRAME_FILTER_NS_FT_SHIFT          (6U)
12563 #define ZLL_RX_FRAME_FILTER_NS_FT(x)             (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_NS_FT_SHIFT)) & ZLL_RX_FRAME_FILTER_NS_FT_MASK)
12564 #define ZLL_RX_FRAME_FILTER_EXTENDED_FT_MASK     (0x80U)
12565 #define ZLL_RX_FRAME_FILTER_EXTENDED_FT_SHIFT    (7U)
12566 #define ZLL_RX_FRAME_FILTER_EXTENDED_FT(x)       (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_EXTENDED_FT_SHIFT)) & ZLL_RX_FRAME_FILTER_EXTENDED_FT_MASK)
12567 #define ZLL_RX_FRAME_FILTER_FRM_VER_FILTER_MASK  (0xF00U)
12568 #define ZLL_RX_FRAME_FILTER_FRM_VER_FILTER_SHIFT (8U)
12569 #define ZLL_RX_FRAME_FILTER_FRM_VER_FILTER(x)    (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_FRM_VER_FILTER_SHIFT)) & ZLL_RX_FRAME_FILTER_FRM_VER_FILTER_MASK)
12570 #define ZLL_RX_FRAME_FILTER_ACTIVE_PROMISCUOUS_MASK (0x4000U)
12571 #define ZLL_RX_FRAME_FILTER_ACTIVE_PROMISCUOUS_SHIFT (14U)
12572 #define ZLL_RX_FRAME_FILTER_ACTIVE_PROMISCUOUS(x) (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_ACTIVE_PROMISCUOUS_SHIFT)) & ZLL_RX_FRAME_FILTER_ACTIVE_PROMISCUOUS_MASK)
12573 #define ZLL_RX_FRAME_FILTER_EXTENDED_FCS_CHK_MASK (0x8000U)
12574 #define ZLL_RX_FRAME_FILTER_EXTENDED_FCS_CHK_SHIFT (15U)
12575 #define ZLL_RX_FRAME_FILTER_EXTENDED_FCS_CHK(x)  (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_EXTENDED_FCS_CHK_SHIFT)) & ZLL_RX_FRAME_FILTER_EXTENDED_FCS_CHK_MASK)
12576 #define ZLL_RX_FRAME_FILTER_FV2_BEACON_RECD_MASK (0x10000U)
12577 #define ZLL_RX_FRAME_FILTER_FV2_BEACON_RECD_SHIFT (16U)
12578 #define ZLL_RX_FRAME_FILTER_FV2_BEACON_RECD(x)   (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_FV2_BEACON_RECD_SHIFT)) & ZLL_RX_FRAME_FILTER_FV2_BEACON_RECD_MASK)
12579 #define ZLL_RX_FRAME_FILTER_FV2_DATA_RECD_MASK   (0x20000U)
12580 #define ZLL_RX_FRAME_FILTER_FV2_DATA_RECD_SHIFT  (17U)
12581 #define ZLL_RX_FRAME_FILTER_FV2_DATA_RECD(x)     (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_FV2_DATA_RECD_SHIFT)) & ZLL_RX_FRAME_FILTER_FV2_DATA_RECD_MASK)
12582 #define ZLL_RX_FRAME_FILTER_FV2_ACK_RECD_MASK    (0x40000U)
12583 #define ZLL_RX_FRAME_FILTER_FV2_ACK_RECD_SHIFT   (18U)
12584 #define ZLL_RX_FRAME_FILTER_FV2_ACK_RECD(x)      (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_FV2_ACK_RECD_SHIFT)) & ZLL_RX_FRAME_FILTER_FV2_ACK_RECD_MASK)
12585 #define ZLL_RX_FRAME_FILTER_FV2_CMD_RECD_MASK    (0x80000U)
12586 #define ZLL_RX_FRAME_FILTER_FV2_CMD_RECD_SHIFT   (19U)
12587 #define ZLL_RX_FRAME_FILTER_FV2_CMD_RECD(x)      (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_FV2_CMD_RECD_SHIFT)) & ZLL_RX_FRAME_FILTER_FV2_CMD_RECD_MASK)
12588 #define ZLL_RX_FRAME_FILTER_LLDN_RECD_MASK       (0x100000U)
12589 #define ZLL_RX_FRAME_FILTER_LLDN_RECD_SHIFT      (20U)
12590 #define ZLL_RX_FRAME_FILTER_LLDN_RECD(x)         (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_LLDN_RECD_SHIFT)) & ZLL_RX_FRAME_FILTER_LLDN_RECD_MASK)
12591 #define ZLL_RX_FRAME_FILTER_MULTIPURPOSE_RECD_MASK (0x200000U)
12592 #define ZLL_RX_FRAME_FILTER_MULTIPURPOSE_RECD_SHIFT (21U)
12593 #define ZLL_RX_FRAME_FILTER_MULTIPURPOSE_RECD(x) (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_MULTIPURPOSE_RECD_SHIFT)) & ZLL_RX_FRAME_FILTER_MULTIPURPOSE_RECD_MASK)
12594 #define ZLL_RX_FRAME_FILTER_EXTENDED_RECD_MASK   (0x800000U)
12595 #define ZLL_RX_FRAME_FILTER_EXTENDED_RECD_SHIFT  (23U)
12596 #define ZLL_RX_FRAME_FILTER_EXTENDED_RECD(x)     (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_EXTENDED_RECD_SHIFT)) & ZLL_RX_FRAME_FILTER_EXTENDED_RECD_MASK)
12597 
12598 /*! @name CCA_LQI_CTRL - CCA AND LQI CONTROL */
12599 #define ZLL_CCA_LQI_CTRL_CCA1_THRESH_MASK        (0xFFU)
12600 #define ZLL_CCA_LQI_CTRL_CCA1_THRESH_SHIFT       (0U)
12601 #define ZLL_CCA_LQI_CTRL_CCA1_THRESH(x)          (((uint32_t)(((uint32_t)(x)) << ZLL_CCA_LQI_CTRL_CCA1_THRESH_SHIFT)) & ZLL_CCA_LQI_CTRL_CCA1_THRESH_MASK)
12602 #define ZLL_CCA_LQI_CTRL_LQI_OFFSET_COMP_MASK    (0xFF0000U)
12603 #define ZLL_CCA_LQI_CTRL_LQI_OFFSET_COMP_SHIFT   (16U)
12604 #define ZLL_CCA_LQI_CTRL_LQI_OFFSET_COMP(x)      (((uint32_t)(((uint32_t)(x)) << ZLL_CCA_LQI_CTRL_LQI_OFFSET_COMP_SHIFT)) & ZLL_CCA_LQI_CTRL_LQI_OFFSET_COMP_MASK)
12605 #define ZLL_CCA_LQI_CTRL_CCA3_AND_NOT_OR_MASK    (0x8000000U)
12606 #define ZLL_CCA_LQI_CTRL_CCA3_AND_NOT_OR_SHIFT   (27U)
12607 #define ZLL_CCA_LQI_CTRL_CCA3_AND_NOT_OR(x)      (((uint32_t)(((uint32_t)(x)) << ZLL_CCA_LQI_CTRL_CCA3_AND_NOT_OR_SHIFT)) & ZLL_CCA_LQI_CTRL_CCA3_AND_NOT_OR_MASK)
12608 
12609 /*! @name CCA2_CTRL - CCA2 CONTROL */
12610 #define ZLL_CCA2_CTRL_CCA2_NUM_CORR_PEAKS_MASK   (0xFU)
12611 #define ZLL_CCA2_CTRL_CCA2_NUM_CORR_PEAKS_SHIFT  (0U)
12612 #define ZLL_CCA2_CTRL_CCA2_NUM_CORR_PEAKS(x)     (((uint32_t)(((uint32_t)(x)) << ZLL_CCA2_CTRL_CCA2_NUM_CORR_PEAKS_SHIFT)) & ZLL_CCA2_CTRL_CCA2_NUM_CORR_PEAKS_MASK)
12613 #define ZLL_CCA2_CTRL_CCA2_MIN_NUM_CORR_TH_MASK  (0x70U)
12614 #define ZLL_CCA2_CTRL_CCA2_MIN_NUM_CORR_TH_SHIFT (4U)
12615 #define ZLL_CCA2_CTRL_CCA2_MIN_NUM_CORR_TH(x)    (((uint32_t)(((uint32_t)(x)) << ZLL_CCA2_CTRL_CCA2_MIN_NUM_CORR_TH_SHIFT)) & ZLL_CCA2_CTRL_CCA2_MIN_NUM_CORR_TH_MASK)
12616 #define ZLL_CCA2_CTRL_CCA2_CORR_THRESH_MASK      (0xFF00U)
12617 #define ZLL_CCA2_CTRL_CCA2_CORR_THRESH_SHIFT     (8U)
12618 #define ZLL_CCA2_CTRL_CCA2_CORR_THRESH(x)        (((uint32_t)(((uint32_t)(x)) << ZLL_CCA2_CTRL_CCA2_CORR_THRESH_SHIFT)) & ZLL_CCA2_CTRL_CCA2_CORR_THRESH_MASK)
12619 
12620 /*! @name DSM_CTRL - DSM CONTROL */
12621 #define ZLL_DSM_CTRL_ZIGBEE_SLEEP_EN_MASK        (0x1U)
12622 #define ZLL_DSM_CTRL_ZIGBEE_SLEEP_EN_SHIFT       (0U)
12623 #define ZLL_DSM_CTRL_ZIGBEE_SLEEP_EN(x)          (((uint32_t)(((uint32_t)(x)) << ZLL_DSM_CTRL_ZIGBEE_SLEEP_EN_SHIFT)) & ZLL_DSM_CTRL_ZIGBEE_SLEEP_EN_MASK)
12624 
12625 /*! @name BSM_CTRL - BSM CONTROL */
12626 #define ZLL_BSM_CTRL_BSM_EN_MASK                 (0x1U)
12627 #define ZLL_BSM_CTRL_BSM_EN_SHIFT                (0U)
12628 #define ZLL_BSM_CTRL_BSM_EN(x)                   (((uint32_t)(((uint32_t)(x)) << ZLL_BSM_CTRL_BSM_EN_SHIFT)) & ZLL_BSM_CTRL_BSM_EN_MASK)
12629 
12630 /*! @name MACSHORTADDRS1 - MAC SHORT ADDRESS FOR PAN1 */
12631 #define ZLL_MACSHORTADDRS1_MACPANID1_MASK        (0xFFFFU)
12632 #define ZLL_MACSHORTADDRS1_MACPANID1_SHIFT       (0U)
12633 #define ZLL_MACSHORTADDRS1_MACPANID1(x)          (((uint32_t)(((uint32_t)(x)) << ZLL_MACSHORTADDRS1_MACPANID1_SHIFT)) & ZLL_MACSHORTADDRS1_MACPANID1_MASK)
12634 #define ZLL_MACSHORTADDRS1_MACSHORTADDRS1_MASK   (0xFFFF0000U)
12635 #define ZLL_MACSHORTADDRS1_MACSHORTADDRS1_SHIFT  (16U)
12636 #define ZLL_MACSHORTADDRS1_MACSHORTADDRS1(x)     (((uint32_t)(((uint32_t)(x)) << ZLL_MACSHORTADDRS1_MACSHORTADDRS1_SHIFT)) & ZLL_MACSHORTADDRS1_MACSHORTADDRS1_MASK)
12637 
12638 /*! @name MACLONGADDRS1_LSB - MAC LONG ADDRESS 1 LSB */
12639 #define ZLL_MACLONGADDRS1_LSB_MACLONGADDRS1_LSB_MASK (0xFFFFFFFFU)
12640 #define ZLL_MACLONGADDRS1_LSB_MACLONGADDRS1_LSB_SHIFT (0U)
12641 #define ZLL_MACLONGADDRS1_LSB_MACLONGADDRS1_LSB(x) (((uint32_t)(((uint32_t)(x)) << ZLL_MACLONGADDRS1_LSB_MACLONGADDRS1_LSB_SHIFT)) & ZLL_MACLONGADDRS1_LSB_MACLONGADDRS1_LSB_MASK)
12642 
12643 /*! @name MACLONGADDRS1_MSB - MAC LONG ADDRESS 1 MSB */
12644 #define ZLL_MACLONGADDRS1_MSB_MACLONGADDRS1_MSB_MASK (0xFFFFFFFFU)
12645 #define ZLL_MACLONGADDRS1_MSB_MACLONGADDRS1_MSB_SHIFT (0U)
12646 #define ZLL_MACLONGADDRS1_MSB_MACLONGADDRS1_MSB(x) (((uint32_t)(((uint32_t)(x)) << ZLL_MACLONGADDRS1_MSB_MACLONGADDRS1_MSB_SHIFT)) & ZLL_MACLONGADDRS1_MSB_MACLONGADDRS1_MSB_MASK)
12647 
12648 /*! @name DUAL_PAN_CTRL - DUAL PAN CONTROL */
12649 #define ZLL_DUAL_PAN_CTRL_ACTIVE_NETWORK_MASK    (0x1U)
12650 #define ZLL_DUAL_PAN_CTRL_ACTIVE_NETWORK_SHIFT   (0U)
12651 #define ZLL_DUAL_PAN_CTRL_ACTIVE_NETWORK(x)      (((uint32_t)(((uint32_t)(x)) << ZLL_DUAL_PAN_CTRL_ACTIVE_NETWORK_SHIFT)) & ZLL_DUAL_PAN_CTRL_ACTIVE_NETWORK_MASK)
12652 #define ZLL_DUAL_PAN_CTRL_DUAL_PAN_AUTO_MASK     (0x2U)
12653 #define ZLL_DUAL_PAN_CTRL_DUAL_PAN_AUTO_SHIFT    (1U)
12654 #define ZLL_DUAL_PAN_CTRL_DUAL_PAN_AUTO(x)       (((uint32_t)(((uint32_t)(x)) << ZLL_DUAL_PAN_CTRL_DUAL_PAN_AUTO_SHIFT)) & ZLL_DUAL_PAN_CTRL_DUAL_PAN_AUTO_MASK)
12655 #define ZLL_DUAL_PAN_CTRL_PANCORDNTR1_MASK       (0x4U)
12656 #define ZLL_DUAL_PAN_CTRL_PANCORDNTR1_SHIFT      (2U)
12657 #define ZLL_DUAL_PAN_CTRL_PANCORDNTR1(x)         (((uint32_t)(((uint32_t)(x)) << ZLL_DUAL_PAN_CTRL_PANCORDNTR1_SHIFT)) & ZLL_DUAL_PAN_CTRL_PANCORDNTR1_MASK)
12658 #define ZLL_DUAL_PAN_CTRL_CURRENT_NETWORK_MASK   (0x8U)
12659 #define ZLL_DUAL_PAN_CTRL_CURRENT_NETWORK_SHIFT  (3U)
12660 #define ZLL_DUAL_PAN_CTRL_CURRENT_NETWORK(x)     (((uint32_t)(((uint32_t)(x)) << ZLL_DUAL_PAN_CTRL_CURRENT_NETWORK_SHIFT)) & ZLL_DUAL_PAN_CTRL_CURRENT_NETWORK_MASK)
12661 #define ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_EN_MASK (0x10U)
12662 #define ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_EN_SHIFT (4U)
12663 #define ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_EN(x)  (((uint32_t)(((uint32_t)(x)) << ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_EN_SHIFT)) & ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_EN_MASK)
12664 #define ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_SEL_MASK (0x20U)
12665 #define ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_SEL_SHIFT (5U)
12666 #define ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_SEL(x) (((uint32_t)(((uint32_t)(x)) << ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_SEL_SHIFT)) & ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_SEL_MASK)
12667 #define ZLL_DUAL_PAN_CTRL_DUAL_PAN_DWELL_MASK    (0xFF00U)
12668 #define ZLL_DUAL_PAN_CTRL_DUAL_PAN_DWELL_SHIFT   (8U)
12669 #define ZLL_DUAL_PAN_CTRL_DUAL_PAN_DWELL(x)      (((uint32_t)(((uint32_t)(x)) << ZLL_DUAL_PAN_CTRL_DUAL_PAN_DWELL_SHIFT)) & ZLL_DUAL_PAN_CTRL_DUAL_PAN_DWELL_MASK)
12670 #define ZLL_DUAL_PAN_CTRL_DUAL_PAN_REMAIN_MASK   (0x3F0000U)
12671 #define ZLL_DUAL_PAN_CTRL_DUAL_PAN_REMAIN_SHIFT  (16U)
12672 #define ZLL_DUAL_PAN_CTRL_DUAL_PAN_REMAIN(x)     (((uint32_t)(((uint32_t)(x)) << ZLL_DUAL_PAN_CTRL_DUAL_PAN_REMAIN_SHIFT)) & ZLL_DUAL_PAN_CTRL_DUAL_PAN_REMAIN_MASK)
12673 #define ZLL_DUAL_PAN_CTRL_RECD_ON_PAN0_MASK      (0x400000U)
12674 #define ZLL_DUAL_PAN_CTRL_RECD_ON_PAN0_SHIFT     (22U)
12675 #define ZLL_DUAL_PAN_CTRL_RECD_ON_PAN0(x)        (((uint32_t)(((uint32_t)(x)) << ZLL_DUAL_PAN_CTRL_RECD_ON_PAN0_SHIFT)) & ZLL_DUAL_PAN_CTRL_RECD_ON_PAN0_MASK)
12676 #define ZLL_DUAL_PAN_CTRL_RECD_ON_PAN1_MASK      (0x800000U)
12677 #define ZLL_DUAL_PAN_CTRL_RECD_ON_PAN1_SHIFT     (23U)
12678 #define ZLL_DUAL_PAN_CTRL_RECD_ON_PAN1(x)        (((uint32_t)(((uint32_t)(x)) << ZLL_DUAL_PAN_CTRL_RECD_ON_PAN1_SHIFT)) & ZLL_DUAL_PAN_CTRL_RECD_ON_PAN1_MASK)
12679 
12680 /*! @name CHANNEL_NUM1 - CHANNEL NUMBER 1 */
12681 #define ZLL_CHANNEL_NUM1_CHANNEL_NUM1_MASK       (0x7FU)
12682 #define ZLL_CHANNEL_NUM1_CHANNEL_NUM1_SHIFT      (0U)
12683 #define ZLL_CHANNEL_NUM1_CHANNEL_NUM1(x)         (((uint32_t)(((uint32_t)(x)) << ZLL_CHANNEL_NUM1_CHANNEL_NUM1_SHIFT)) & ZLL_CHANNEL_NUM1_CHANNEL_NUM1_MASK)
12684 
12685 /*! @name SAM_CTRL - SAM CONTROL */
12686 #define ZLL_SAM_CTRL_SAP0_EN_MASK                (0x1U)
12687 #define ZLL_SAM_CTRL_SAP0_EN_SHIFT               (0U)
12688 #define ZLL_SAM_CTRL_SAP0_EN(x)                  (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_CTRL_SAP0_EN_SHIFT)) & ZLL_SAM_CTRL_SAP0_EN_MASK)
12689 #define ZLL_SAM_CTRL_SAA0_EN_MASK                (0x2U)
12690 #define ZLL_SAM_CTRL_SAA0_EN_SHIFT               (1U)
12691 #define ZLL_SAM_CTRL_SAA0_EN(x)                  (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_CTRL_SAA0_EN_SHIFT)) & ZLL_SAM_CTRL_SAA0_EN_MASK)
12692 #define ZLL_SAM_CTRL_SAP1_EN_MASK                (0x4U)
12693 #define ZLL_SAM_CTRL_SAP1_EN_SHIFT               (2U)
12694 #define ZLL_SAM_CTRL_SAP1_EN(x)                  (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_CTRL_SAP1_EN_SHIFT)) & ZLL_SAM_CTRL_SAP1_EN_MASK)
12695 #define ZLL_SAM_CTRL_SAA1_EN_MASK                (0x8U)
12696 #define ZLL_SAM_CTRL_SAA1_EN_SHIFT               (3U)
12697 #define ZLL_SAM_CTRL_SAA1_EN(x)                  (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_CTRL_SAA1_EN_SHIFT)) & ZLL_SAM_CTRL_SAA1_EN_MASK)
12698 #define ZLL_SAM_CTRL_SAA0_START_MASK             (0xFF00U)
12699 #define ZLL_SAM_CTRL_SAA0_START_SHIFT            (8U)
12700 #define ZLL_SAM_CTRL_SAA0_START(x)               (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_CTRL_SAA0_START_SHIFT)) & ZLL_SAM_CTRL_SAA0_START_MASK)
12701 #define ZLL_SAM_CTRL_SAP1_START_MASK             (0xFF0000U)
12702 #define ZLL_SAM_CTRL_SAP1_START_SHIFT            (16U)
12703 #define ZLL_SAM_CTRL_SAP1_START(x)               (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_CTRL_SAP1_START_SHIFT)) & ZLL_SAM_CTRL_SAP1_START_MASK)
12704 #define ZLL_SAM_CTRL_SAA1_START_MASK             (0xFF000000U)
12705 #define ZLL_SAM_CTRL_SAA1_START_SHIFT            (24U)
12706 #define ZLL_SAM_CTRL_SAA1_START(x)               (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_CTRL_SAA1_START_SHIFT)) & ZLL_SAM_CTRL_SAA1_START_MASK)
12707 
12708 /*! @name SAM_TABLE - SOURCE ADDRESS MANAGEMENT TABLE */
12709 #define ZLL_SAM_TABLE_SAM_INDEX_MASK             (0x7FU)
12710 #define ZLL_SAM_TABLE_SAM_INDEX_SHIFT            (0U)
12711 #define ZLL_SAM_TABLE_SAM_INDEX(x)               (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_TABLE_SAM_INDEX_SHIFT)) & ZLL_SAM_TABLE_SAM_INDEX_MASK)
12712 #define ZLL_SAM_TABLE_SAM_INDEX_WR_MASK          (0x80U)
12713 #define ZLL_SAM_TABLE_SAM_INDEX_WR_SHIFT         (7U)
12714 #define ZLL_SAM_TABLE_SAM_INDEX_WR(x)            (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_TABLE_SAM_INDEX_WR_SHIFT)) & ZLL_SAM_TABLE_SAM_INDEX_WR_MASK)
12715 #define ZLL_SAM_TABLE_SAM_CHECKSUM_MASK          (0xFFFF00U)
12716 #define ZLL_SAM_TABLE_SAM_CHECKSUM_SHIFT         (8U)
12717 #define ZLL_SAM_TABLE_SAM_CHECKSUM(x)            (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_TABLE_SAM_CHECKSUM_SHIFT)) & ZLL_SAM_TABLE_SAM_CHECKSUM_MASK)
12718 #define ZLL_SAM_TABLE_SAM_INDEX_INV_MASK         (0x1000000U)
12719 #define ZLL_SAM_TABLE_SAM_INDEX_INV_SHIFT        (24U)
12720 #define ZLL_SAM_TABLE_SAM_INDEX_INV(x)           (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_TABLE_SAM_INDEX_INV_SHIFT)) & ZLL_SAM_TABLE_SAM_INDEX_INV_MASK)
12721 #define ZLL_SAM_TABLE_SAM_INDEX_EN_MASK          (0x2000000U)
12722 #define ZLL_SAM_TABLE_SAM_INDEX_EN_SHIFT         (25U)
12723 #define ZLL_SAM_TABLE_SAM_INDEX_EN(x)            (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_TABLE_SAM_INDEX_EN_SHIFT)) & ZLL_SAM_TABLE_SAM_INDEX_EN_MASK)
12724 #define ZLL_SAM_TABLE_ACK_FRM_PND_MASK           (0x4000000U)
12725 #define ZLL_SAM_TABLE_ACK_FRM_PND_SHIFT          (26U)
12726 #define ZLL_SAM_TABLE_ACK_FRM_PND(x)             (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_TABLE_ACK_FRM_PND_SHIFT)) & ZLL_SAM_TABLE_ACK_FRM_PND_MASK)
12727 #define ZLL_SAM_TABLE_ACK_FRM_PND_CTRL_MASK      (0x8000000U)
12728 #define ZLL_SAM_TABLE_ACK_FRM_PND_CTRL_SHIFT     (27U)
12729 #define ZLL_SAM_TABLE_ACK_FRM_PND_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_TABLE_ACK_FRM_PND_CTRL_SHIFT)) & ZLL_SAM_TABLE_ACK_FRM_PND_CTRL_MASK)
12730 #define ZLL_SAM_TABLE_FIND_FREE_IDX_MASK         (0x10000000U)
12731 #define ZLL_SAM_TABLE_FIND_FREE_IDX_SHIFT        (28U)
12732 #define ZLL_SAM_TABLE_FIND_FREE_IDX(x)           (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_TABLE_FIND_FREE_IDX_SHIFT)) & ZLL_SAM_TABLE_FIND_FREE_IDX_MASK)
12733 #define ZLL_SAM_TABLE_INVALIDATE_ALL_MASK        (0x20000000U)
12734 #define ZLL_SAM_TABLE_INVALIDATE_ALL_SHIFT       (29U)
12735 #define ZLL_SAM_TABLE_INVALIDATE_ALL(x)          (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_TABLE_INVALIDATE_ALL_SHIFT)) & ZLL_SAM_TABLE_INVALIDATE_ALL_MASK)
12736 #define ZLL_SAM_TABLE_SAM_BUSY_MASK              (0x80000000U)
12737 #define ZLL_SAM_TABLE_SAM_BUSY_SHIFT             (31U)
12738 #define ZLL_SAM_TABLE_SAM_BUSY(x)                (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_TABLE_SAM_BUSY_SHIFT)) & ZLL_SAM_TABLE_SAM_BUSY_MASK)
12739 
12740 /*! @name SAM_MATCH - SOURCE ADDRESS MANAGEMENT MATCH */
12741 #define ZLL_SAM_MATCH_SAP0_MATCH_MASK            (0x7FU)
12742 #define ZLL_SAM_MATCH_SAP0_MATCH_SHIFT           (0U)
12743 #define ZLL_SAM_MATCH_SAP0_MATCH(x)              (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_MATCH_SAP0_MATCH_SHIFT)) & ZLL_SAM_MATCH_SAP0_MATCH_MASK)
12744 #define ZLL_SAM_MATCH_SAP0_ADDR_PRESENT_MASK     (0x80U)
12745 #define ZLL_SAM_MATCH_SAP0_ADDR_PRESENT_SHIFT    (7U)
12746 #define ZLL_SAM_MATCH_SAP0_ADDR_PRESENT(x)       (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_MATCH_SAP0_ADDR_PRESENT_SHIFT)) & ZLL_SAM_MATCH_SAP0_ADDR_PRESENT_MASK)
12747 #define ZLL_SAM_MATCH_SAA0_MATCH_MASK            (0x7F00U)
12748 #define ZLL_SAM_MATCH_SAA0_MATCH_SHIFT           (8U)
12749 #define ZLL_SAM_MATCH_SAA0_MATCH(x)              (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_MATCH_SAA0_MATCH_SHIFT)) & ZLL_SAM_MATCH_SAA0_MATCH_MASK)
12750 #define ZLL_SAM_MATCH_SAA0_ADDR_ABSENT_MASK      (0x8000U)
12751 #define ZLL_SAM_MATCH_SAA0_ADDR_ABSENT_SHIFT     (15U)
12752 #define ZLL_SAM_MATCH_SAA0_ADDR_ABSENT(x)        (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_MATCH_SAA0_ADDR_ABSENT_SHIFT)) & ZLL_SAM_MATCH_SAA0_ADDR_ABSENT_MASK)
12753 #define ZLL_SAM_MATCH_SAP1_MATCH_MASK            (0x7F0000U)
12754 #define ZLL_SAM_MATCH_SAP1_MATCH_SHIFT           (16U)
12755 #define ZLL_SAM_MATCH_SAP1_MATCH(x)              (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_MATCH_SAP1_MATCH_SHIFT)) & ZLL_SAM_MATCH_SAP1_MATCH_MASK)
12756 #define ZLL_SAM_MATCH_SAP1_ADDR_PRESENT_MASK     (0x800000U)
12757 #define ZLL_SAM_MATCH_SAP1_ADDR_PRESENT_SHIFT    (23U)
12758 #define ZLL_SAM_MATCH_SAP1_ADDR_PRESENT(x)       (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_MATCH_SAP1_ADDR_PRESENT_SHIFT)) & ZLL_SAM_MATCH_SAP1_ADDR_PRESENT_MASK)
12759 #define ZLL_SAM_MATCH_SAA1_MATCH_MASK            (0x7F000000U)
12760 #define ZLL_SAM_MATCH_SAA1_MATCH_SHIFT           (24U)
12761 #define ZLL_SAM_MATCH_SAA1_MATCH(x)              (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_MATCH_SAA1_MATCH_SHIFT)) & ZLL_SAM_MATCH_SAA1_MATCH_MASK)
12762 #define ZLL_SAM_MATCH_SAA1_ADDR_ABSENT_MASK      (0x80000000U)
12763 #define ZLL_SAM_MATCH_SAA1_ADDR_ABSENT_SHIFT     (31U)
12764 #define ZLL_SAM_MATCH_SAA1_ADDR_ABSENT(x)        (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_MATCH_SAA1_ADDR_ABSENT_SHIFT)) & ZLL_SAM_MATCH_SAA1_ADDR_ABSENT_MASK)
12765 
12766 /*! @name SAM_FREE_IDX - SAM FREE INDEX */
12767 #define ZLL_SAM_FREE_IDX_SAP0_1ST_FREE_IDX_MASK  (0xFFU)
12768 #define ZLL_SAM_FREE_IDX_SAP0_1ST_FREE_IDX_SHIFT (0U)
12769 #define ZLL_SAM_FREE_IDX_SAP0_1ST_FREE_IDX(x)    (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_FREE_IDX_SAP0_1ST_FREE_IDX_SHIFT)) & ZLL_SAM_FREE_IDX_SAP0_1ST_FREE_IDX_MASK)
12770 #define ZLL_SAM_FREE_IDX_SAA0_1ST_FREE_IDX_MASK  (0xFF00U)
12771 #define ZLL_SAM_FREE_IDX_SAA0_1ST_FREE_IDX_SHIFT (8U)
12772 #define ZLL_SAM_FREE_IDX_SAA0_1ST_FREE_IDX(x)    (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_FREE_IDX_SAA0_1ST_FREE_IDX_SHIFT)) & ZLL_SAM_FREE_IDX_SAA0_1ST_FREE_IDX_MASK)
12773 #define ZLL_SAM_FREE_IDX_SAP1_1ST_FREE_IDX_MASK  (0xFF0000U)
12774 #define ZLL_SAM_FREE_IDX_SAP1_1ST_FREE_IDX_SHIFT (16U)
12775 #define ZLL_SAM_FREE_IDX_SAP1_1ST_FREE_IDX(x)    (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_FREE_IDX_SAP1_1ST_FREE_IDX_SHIFT)) & ZLL_SAM_FREE_IDX_SAP1_1ST_FREE_IDX_MASK)
12776 #define ZLL_SAM_FREE_IDX_SAA1_1ST_FREE_IDX_MASK  (0xFF000000U)
12777 #define ZLL_SAM_FREE_IDX_SAA1_1ST_FREE_IDX_SHIFT (24U)
12778 #define ZLL_SAM_FREE_IDX_SAA1_1ST_FREE_IDX(x)    (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_FREE_IDX_SAA1_1ST_FREE_IDX_SHIFT)) & ZLL_SAM_FREE_IDX_SAA1_1ST_FREE_IDX_MASK)
12779 
12780 /*! @name SEQ_CTRL_STS - SEQUENCE CONTROL AND STATUS */
12781 #define ZLL_SEQ_CTRL_STS_CLR_NEW_SEQ_INHIBIT_MASK (0x4U)
12782 #define ZLL_SEQ_CTRL_STS_CLR_NEW_SEQ_INHIBIT_SHIFT (2U)
12783 #define ZLL_SEQ_CTRL_STS_CLR_NEW_SEQ_INHIBIT(x)  (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_CLR_NEW_SEQ_INHIBIT_SHIFT)) & ZLL_SEQ_CTRL_STS_CLR_NEW_SEQ_INHIBIT_MASK)
12784 #define ZLL_SEQ_CTRL_STS_EVENT_TMR_DO_NOT_LATCH_MASK (0x8U)
12785 #define ZLL_SEQ_CTRL_STS_EVENT_TMR_DO_NOT_LATCH_SHIFT (3U)
12786 #define ZLL_SEQ_CTRL_STS_EVENT_TMR_DO_NOT_LATCH(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_EVENT_TMR_DO_NOT_LATCH_SHIFT)) & ZLL_SEQ_CTRL_STS_EVENT_TMR_DO_NOT_LATCH_MASK)
12787 #define ZLL_SEQ_CTRL_STS_LATCH_PREAMBLE_MASK     (0x10U)
12788 #define ZLL_SEQ_CTRL_STS_LATCH_PREAMBLE_SHIFT    (4U)
12789 #define ZLL_SEQ_CTRL_STS_LATCH_PREAMBLE(x)       (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_LATCH_PREAMBLE_SHIFT)) & ZLL_SEQ_CTRL_STS_LATCH_PREAMBLE_MASK)
12790 #define ZLL_SEQ_CTRL_STS_NO_RX_RECYCLE_MASK      (0x20U)
12791 #define ZLL_SEQ_CTRL_STS_NO_RX_RECYCLE_SHIFT     (5U)
12792 #define ZLL_SEQ_CTRL_STS_NO_RX_RECYCLE(x)        (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_NO_RX_RECYCLE_SHIFT)) & ZLL_SEQ_CTRL_STS_NO_RX_RECYCLE_MASK)
12793 #define ZLL_SEQ_CTRL_STS_FORCE_CRC_ERROR_MASK    (0x40U)
12794 #define ZLL_SEQ_CTRL_STS_FORCE_CRC_ERROR_SHIFT   (6U)
12795 #define ZLL_SEQ_CTRL_STS_FORCE_CRC_ERROR(x)      (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_FORCE_CRC_ERROR_SHIFT)) & ZLL_SEQ_CTRL_STS_FORCE_CRC_ERROR_MASK)
12796 #define ZLL_SEQ_CTRL_STS_CONTINUOUS_EN_MASK      (0x80U)
12797 #define ZLL_SEQ_CTRL_STS_CONTINUOUS_EN_SHIFT     (7U)
12798 #define ZLL_SEQ_CTRL_STS_CONTINUOUS_EN(x)        (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_CONTINUOUS_EN_SHIFT)) & ZLL_SEQ_CTRL_STS_CONTINUOUS_EN_MASK)
12799 #define ZLL_SEQ_CTRL_STS_XCVSEQ_ACTUAL_MASK      (0x700U)
12800 #define ZLL_SEQ_CTRL_STS_XCVSEQ_ACTUAL_SHIFT     (8U)
12801 #define ZLL_SEQ_CTRL_STS_XCVSEQ_ACTUAL(x)        (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_XCVSEQ_ACTUAL_SHIFT)) & ZLL_SEQ_CTRL_STS_XCVSEQ_ACTUAL_MASK)
12802 #define ZLL_SEQ_CTRL_STS_SEQ_IDLE_MASK           (0x800U)
12803 #define ZLL_SEQ_CTRL_STS_SEQ_IDLE_SHIFT          (11U)
12804 #define ZLL_SEQ_CTRL_STS_SEQ_IDLE(x)             (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_SEQ_IDLE_SHIFT)) & ZLL_SEQ_CTRL_STS_SEQ_IDLE_MASK)
12805 #define ZLL_SEQ_CTRL_STS_NEW_SEQ_INHIBIT_MASK    (0x1000U)
12806 #define ZLL_SEQ_CTRL_STS_NEW_SEQ_INHIBIT_SHIFT   (12U)
12807 #define ZLL_SEQ_CTRL_STS_NEW_SEQ_INHIBIT(x)      (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_NEW_SEQ_INHIBIT_SHIFT)) & ZLL_SEQ_CTRL_STS_NEW_SEQ_INHIBIT_MASK)
12808 #define ZLL_SEQ_CTRL_STS_RX_TIMEOUT_PENDING_MASK (0x2000U)
12809 #define ZLL_SEQ_CTRL_STS_RX_TIMEOUT_PENDING_SHIFT (13U)
12810 #define ZLL_SEQ_CTRL_STS_RX_TIMEOUT_PENDING(x)   (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_RX_TIMEOUT_PENDING_SHIFT)) & ZLL_SEQ_CTRL_STS_RX_TIMEOUT_PENDING_MASK)
12811 #define ZLL_SEQ_CTRL_STS_RX_MODE_MASK            (0x4000U)
12812 #define ZLL_SEQ_CTRL_STS_RX_MODE_SHIFT           (14U)
12813 #define ZLL_SEQ_CTRL_STS_RX_MODE(x)              (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_RX_MODE_SHIFT)) & ZLL_SEQ_CTRL_STS_RX_MODE_MASK)
12814 #define ZLL_SEQ_CTRL_STS_TMR2_SEQ_TRIG_ARMED_MASK (0x8000U)
12815 #define ZLL_SEQ_CTRL_STS_TMR2_SEQ_TRIG_ARMED_SHIFT (15U)
12816 #define ZLL_SEQ_CTRL_STS_TMR2_SEQ_TRIG_ARMED(x)  (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_TMR2_SEQ_TRIG_ARMED_SHIFT)) & ZLL_SEQ_CTRL_STS_TMR2_SEQ_TRIG_ARMED_MASK)
12817 #define ZLL_SEQ_CTRL_STS_SEQ_T_STATUS_MASK       (0x3F0000U)
12818 #define ZLL_SEQ_CTRL_STS_SEQ_T_STATUS_SHIFT      (16U)
12819 #define ZLL_SEQ_CTRL_STS_SEQ_T_STATUS(x)         (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_SEQ_T_STATUS_SHIFT)) & ZLL_SEQ_CTRL_STS_SEQ_T_STATUS_MASK)
12820 #define ZLL_SEQ_CTRL_STS_SW_ABORTED_MASK         (0x1000000U)
12821 #define ZLL_SEQ_CTRL_STS_SW_ABORTED_SHIFT        (24U)
12822 #define ZLL_SEQ_CTRL_STS_SW_ABORTED(x)           (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_SW_ABORTED_SHIFT)) & ZLL_SEQ_CTRL_STS_SW_ABORTED_MASK)
12823 #define ZLL_SEQ_CTRL_STS_TC3_ABORTED_MASK        (0x2000000U)
12824 #define ZLL_SEQ_CTRL_STS_TC3_ABORTED_SHIFT       (25U)
12825 #define ZLL_SEQ_CTRL_STS_TC3_ABORTED(x)          (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_TC3_ABORTED_SHIFT)) & ZLL_SEQ_CTRL_STS_TC3_ABORTED_MASK)
12826 #define ZLL_SEQ_CTRL_STS_PLL_ABORTED_MASK        (0x4000000U)
12827 #define ZLL_SEQ_CTRL_STS_PLL_ABORTED_SHIFT       (26U)
12828 #define ZLL_SEQ_CTRL_STS_PLL_ABORTED(x)          (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_PLL_ABORTED_SHIFT)) & ZLL_SEQ_CTRL_STS_PLL_ABORTED_MASK)
12829 
12830 /*! @name ACKDELAY - ACK DELAY */
12831 #define ZLL_ACKDELAY_ACKDELAY_MASK               (0x3FU)
12832 #define ZLL_ACKDELAY_ACKDELAY_SHIFT              (0U)
12833 #define ZLL_ACKDELAY_ACKDELAY(x)                 (((uint32_t)(((uint32_t)(x)) << ZLL_ACKDELAY_ACKDELAY_SHIFT)) & ZLL_ACKDELAY_ACKDELAY_MASK)
12834 #define ZLL_ACKDELAY_TXDELAY_MASK                (0x3F00U)
12835 #define ZLL_ACKDELAY_TXDELAY_SHIFT               (8U)
12836 #define ZLL_ACKDELAY_TXDELAY(x)                  (((uint32_t)(((uint32_t)(x)) << ZLL_ACKDELAY_TXDELAY_SHIFT)) & ZLL_ACKDELAY_TXDELAY_MASK)
12837 
12838 /*! @name FILTERFAIL_CODE - FILTER FAIL CODE */
12839 #define ZLL_FILTERFAIL_CODE_FILTERFAIL_CODE_MASK (0x3FFU)
12840 #define ZLL_FILTERFAIL_CODE_FILTERFAIL_CODE_SHIFT (0U)
12841 #define ZLL_FILTERFAIL_CODE_FILTERFAIL_CODE(x)   (((uint32_t)(((uint32_t)(x)) << ZLL_FILTERFAIL_CODE_FILTERFAIL_CODE_SHIFT)) & ZLL_FILTERFAIL_CODE_FILTERFAIL_CODE_MASK)
12842 #define ZLL_FILTERFAIL_CODE_FILTERFAIL_PAN_SEL_MASK (0x8000U)
12843 #define ZLL_FILTERFAIL_CODE_FILTERFAIL_PAN_SEL_SHIFT (15U)
12844 #define ZLL_FILTERFAIL_CODE_FILTERFAIL_PAN_SEL(x) (((uint32_t)(((uint32_t)(x)) << ZLL_FILTERFAIL_CODE_FILTERFAIL_PAN_SEL_SHIFT)) & ZLL_FILTERFAIL_CODE_FILTERFAIL_PAN_SEL_MASK)
12845 
12846 /*! @name RX_WTR_MARK - RECEIVE WATER MARK */
12847 #define ZLL_RX_WTR_MARK_RX_WTR_MARK_MASK         (0xFFU)
12848 #define ZLL_RX_WTR_MARK_RX_WTR_MARK_SHIFT        (0U)
12849 #define ZLL_RX_WTR_MARK_RX_WTR_MARK(x)           (((uint32_t)(((uint32_t)(x)) << ZLL_RX_WTR_MARK_RX_WTR_MARK_SHIFT)) & ZLL_RX_WTR_MARK_RX_WTR_MARK_MASK)
12850 
12851 /*! @name SLOT_PRELOAD - SLOT PRELOAD */
12852 #define ZLL_SLOT_PRELOAD_SLOT_PRELOAD_MASK       (0xFFU)
12853 #define ZLL_SLOT_PRELOAD_SLOT_PRELOAD_SHIFT      (0U)
12854 #define ZLL_SLOT_PRELOAD_SLOT_PRELOAD(x)         (((uint32_t)(((uint32_t)(x)) << ZLL_SLOT_PRELOAD_SLOT_PRELOAD_SHIFT)) & ZLL_SLOT_PRELOAD_SLOT_PRELOAD_MASK)
12855 
12856 /*! @name SEQ_STATE - 802.15.4 SEQUENCE STATE */
12857 #define ZLL_SEQ_STATE_SEQ_STATE_MASK             (0x1FU)
12858 #define ZLL_SEQ_STATE_SEQ_STATE_SHIFT            (0U)
12859 #define ZLL_SEQ_STATE_SEQ_STATE(x)               (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_STATE_SEQ_STATE_SHIFT)) & ZLL_SEQ_STATE_SEQ_STATE_MASK)
12860 #define ZLL_SEQ_STATE_PREAMBLE_DET_MASK          (0x100U)
12861 #define ZLL_SEQ_STATE_PREAMBLE_DET_SHIFT         (8U)
12862 #define ZLL_SEQ_STATE_PREAMBLE_DET(x)            (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_STATE_PREAMBLE_DET_SHIFT)) & ZLL_SEQ_STATE_PREAMBLE_DET_MASK)
12863 #define ZLL_SEQ_STATE_SFD_DET_MASK               (0x200U)
12864 #define ZLL_SEQ_STATE_SFD_DET_SHIFT              (9U)
12865 #define ZLL_SEQ_STATE_SFD_DET(x)                 (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_STATE_SFD_DET_SHIFT)) & ZLL_SEQ_STATE_SFD_DET_MASK)
12866 #define ZLL_SEQ_STATE_FILTERFAIL_FLAG_SEL_MASK   (0x400U)
12867 #define ZLL_SEQ_STATE_FILTERFAIL_FLAG_SEL_SHIFT  (10U)
12868 #define ZLL_SEQ_STATE_FILTERFAIL_FLAG_SEL(x)     (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_STATE_FILTERFAIL_FLAG_SEL_SHIFT)) & ZLL_SEQ_STATE_FILTERFAIL_FLAG_SEL_MASK)
12869 #define ZLL_SEQ_STATE_CRCVALID_MASK              (0x800U)
12870 #define ZLL_SEQ_STATE_CRCVALID_SHIFT             (11U)
12871 #define ZLL_SEQ_STATE_CRCVALID(x)                (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_STATE_CRCVALID_SHIFT)) & ZLL_SEQ_STATE_CRCVALID_MASK)
12872 #define ZLL_SEQ_STATE_PLL_ABORT_MASK             (0x1000U)
12873 #define ZLL_SEQ_STATE_PLL_ABORT_SHIFT            (12U)
12874 #define ZLL_SEQ_STATE_PLL_ABORT(x)               (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_STATE_PLL_ABORT_SHIFT)) & ZLL_SEQ_STATE_PLL_ABORT_MASK)
12875 #define ZLL_SEQ_STATE_PLL_ABORTED_MASK           (0x2000U)
12876 #define ZLL_SEQ_STATE_PLL_ABORTED_SHIFT          (13U)
12877 #define ZLL_SEQ_STATE_PLL_ABORTED(x)             (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_STATE_PLL_ABORTED_SHIFT)) & ZLL_SEQ_STATE_PLL_ABORTED_MASK)
12878 #define ZLL_SEQ_STATE_RX_BYTE_COUNT_MASK         (0xFF0000U)
12879 #define ZLL_SEQ_STATE_RX_BYTE_COUNT_SHIFT        (16U)
12880 #define ZLL_SEQ_STATE_RX_BYTE_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_STATE_RX_BYTE_COUNT_SHIFT)) & ZLL_SEQ_STATE_RX_BYTE_COUNT_MASK)
12881 #define ZLL_SEQ_STATE_CCCA_BUSY_CNT_MASK         (0x3F000000U)
12882 #define ZLL_SEQ_STATE_CCCA_BUSY_CNT_SHIFT        (24U)
12883 #define ZLL_SEQ_STATE_CCCA_BUSY_CNT(x)           (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_STATE_CCCA_BUSY_CNT_SHIFT)) & ZLL_SEQ_STATE_CCCA_BUSY_CNT_MASK)
12884 
12885 /*! @name TMR_PRESCALE - TIMER PRESCALER */
12886 #define ZLL_TMR_PRESCALE_TMR_PRESCALE_MASK       (0x7U)
12887 #define ZLL_TMR_PRESCALE_TMR_PRESCALE_SHIFT      (0U)
12888 #define ZLL_TMR_PRESCALE_TMR_PRESCALE(x)         (((uint32_t)(((uint32_t)(x)) << ZLL_TMR_PRESCALE_TMR_PRESCALE_SHIFT)) & ZLL_TMR_PRESCALE_TMR_PRESCALE_MASK)
12889 
12890 /*! @name LENIENCY_LSB - LENIENCY LSB */
12891 #define ZLL_LENIENCY_LSB_LENIENCY_LSB_MASK       (0xFFFFFFFFU)
12892 #define ZLL_LENIENCY_LSB_LENIENCY_LSB_SHIFT      (0U)
12893 #define ZLL_LENIENCY_LSB_LENIENCY_LSB(x)         (((uint32_t)(((uint32_t)(x)) << ZLL_LENIENCY_LSB_LENIENCY_LSB_SHIFT)) & ZLL_LENIENCY_LSB_LENIENCY_LSB_MASK)
12894 
12895 /*! @name LENIENCY_MSB - LENIENCY MSB */
12896 #define ZLL_LENIENCY_MSB_LENIENCY_MSB_MASK       (0xFFU)
12897 #define ZLL_LENIENCY_MSB_LENIENCY_MSB_SHIFT      (0U)
12898 #define ZLL_LENIENCY_MSB_LENIENCY_MSB(x)         (((uint32_t)(((uint32_t)(x)) << ZLL_LENIENCY_MSB_LENIENCY_MSB_SHIFT)) & ZLL_LENIENCY_MSB_LENIENCY_MSB_MASK)
12899 
12900 /*! @name PART_ID - PART ID */
12901 #define ZLL_PART_ID_PART_ID_MASK                 (0xFFU)
12902 #define ZLL_PART_ID_PART_ID_SHIFT                (0U)
12903 #define ZLL_PART_ID_PART_ID(x)                   (((uint32_t)(((uint32_t)(x)) << ZLL_PART_ID_PART_ID_SHIFT)) & ZLL_PART_ID_PART_ID_MASK)
12904 
12905 /*! @name PKT_BUFFER_TX - Packet Buffer TX */
12906 #define ZLL_PKT_BUFFER_TX_PKT_BUFFER_TX_MASK     (0xFFFFU)
12907 #define ZLL_PKT_BUFFER_TX_PKT_BUFFER_TX_SHIFT    (0U)
12908 #define ZLL_PKT_BUFFER_TX_PKT_BUFFER_TX(x)       (((uint16_t)(((uint16_t)(x)) << ZLL_PKT_BUFFER_TX_PKT_BUFFER_TX_SHIFT)) & ZLL_PKT_BUFFER_TX_PKT_BUFFER_TX_MASK)
12909 
12910 /* The count of ZLL_PKT_BUFFER_TX */
12911 #define ZLL_PKT_BUFFER_TX_COUNT                  (64U)
12912 
12913 /*! @name PKT_BUFFER_RX - Packet Buffer RX */
12914 #define ZLL_PKT_BUFFER_RX_PKT_BUFFER_RX_MASK     (0xFFFFU)
12915 #define ZLL_PKT_BUFFER_RX_PKT_BUFFER_RX_SHIFT    (0U)
12916 #define ZLL_PKT_BUFFER_RX_PKT_BUFFER_RX(x)       (((uint16_t)(((uint16_t)(x)) << ZLL_PKT_BUFFER_RX_PKT_BUFFER_RX_SHIFT)) & ZLL_PKT_BUFFER_RX_PKT_BUFFER_RX_MASK)
12917 
12918 /* The count of ZLL_PKT_BUFFER_RX */
12919 #define ZLL_PKT_BUFFER_RX_COUNT                  (64U)
12920 
12921 
12922 /*!
12923  * @}
12924  */ /* end of group ZLL_Register_Masks */
12925 
12926 
12927 /* ZLL - Peripheral instance base addresses */
12928 /** Peripheral ZLL base address */
12929 #define ZLL_BASE                                 (0x4005D000u)
12930 /** Peripheral ZLL base pointer */
12931 #define ZLL                                      ((ZLL_Type *)ZLL_BASE)
12932 /** Array initializer of ZLL peripheral base addresses */
12933 #define ZLL_BASE_ADDRS                           { ZLL_BASE }
12934 /** Array initializer of ZLL peripheral base pointers */
12935 #define ZLL_BASE_PTRS                            { ZLL }
12936 
12937 /*!
12938  * @}
12939  */ /* end of group ZLL_Peripheral_Access_Layer */
12940 
12941 
12942 /*
12943 ** End of section using anonymous unions
12944 */
12945 
12946 #if defined(__ARMCC_VERSION)
12947   #pragma pop
12948 #elif defined(__GNUC__)
12949   /* leave anonymous unions enabled */
12950 #elif defined(__IAR_SYSTEMS_ICC__)
12951   #pragma language=default
12952 #else
12953   #error Not supported compiler type
12954 #endif
12955 
12956 /*!
12957  * @}
12958  */ /* end of group Peripheral_access_layer */
12959 
12960 
12961 /* ----------------------------------------------------------------------------
12962    -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
12963    ---------------------------------------------------------------------------- */
12964 
12965 /*!
12966  * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
12967  * @{
12968  */
12969 
12970 #if defined(__ARMCC_VERSION)
12971   #if (__ARMCC_VERSION >= 6010050)
12972     #pragma clang system_header
12973   #endif
12974 #elif defined(__IAR_SYSTEMS_ICC__)
12975   #pragma system_include
12976 #endif
12977 
12978 /**
12979  * @brief Mask and left-shift a bit field value for use in a register bit range.
12980  * @param field Name of the register bit field.
12981  * @param value Value of the bit field.
12982  * @return Masked and shifted value.
12983  */
12984 #define NXP_VAL2FLD(field, value)    (((value) << (field ## _SHIFT)) & (field ## _MASK))
12985 /**
12986  * @brief Mask and right-shift a register value to extract a bit field value.
12987  * @param field Name of the register bit field.
12988  * @param value Value of the register.
12989  * @return Masked and shifted bit field value.
12990  */
12991 #define NXP_FLD2VAL(field, value)    (((value) & (field ## _MASK)) >> (field ## _SHIFT))
12992 
12993 /*!
12994  * @}
12995  */ /* end of group Bit_Field_Generic_Macros */
12996 
12997 
12998 /* ----------------------------------------------------------------------------
12999    -- SDK Compatibility
13000    ---------------------------------------------------------------------------- */
13001 
13002 /*!
13003  * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
13004  * @{
13005  */
13006 
13007 #define DSPI0                     SPI0
13008 #define DSPI1                     SPI1
13009 
13010 /*!
13011  * @}
13012  */ /* end of group SDK_Compatibility_Symbols */
13013 
13014 
13015 #endif  /* _MKW41Z4_H_ */
13016 
13017