1 /* 2 ** ################################################################### 3 ** Version: rev. 1.2, 2017-06-08 4 ** Build: b220714 5 ** 6 ** Abstract: 7 ** Chip specific module features. 8 ** 9 ** Copyright 2016 Freescale Semiconductor, Inc. 10 ** Copyright 2016-2022 NXP 11 ** All rights reserved. 12 ** 13 ** SPDX-License-Identifier: BSD-3-Clause 14 ** 15 ** http: www.nxp.com 16 ** mail: support@nxp.com 17 ** 18 ** Revisions: 19 ** - rev. 1.0 (2016-08-12) 20 ** Initial version. 21 ** - rev. 1.1 (2016-11-25) 22 ** Update CANFD and Classic CAN register. 23 ** Add MAC TIMERSTAMP registers. 24 ** - rev. 1.2 (2017-06-08) 25 ** Remove RTC_CTRL_RTC_OSC_BYPASS. 26 ** SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV. 27 ** Remove RESET and HALT from SYSCON_AHBCLKDIV. 28 ** 29 ** ################################################################### 30 */ 31 32 #ifndef _LPC844_FEATURES_H_ 33 #define _LPC844_FEATURES_H_ 34 35 /* SOC module features */ 36 37 /* @brief ACOMP availability on the SoC. */ 38 #define FSL_FEATURE_SOC_ACOMP_COUNT (1) 39 /* @brief ADC availability on the SoC. */ 40 #define FSL_FEATURE_SOC_ADC_COUNT (1) 41 /* @brief CRC availability on the SoC. */ 42 #define FSL_FEATURE_SOC_CRC_COUNT (1) 43 /* @brief CTIMER availability on the SoC. */ 44 #define FSL_FEATURE_SOC_CTIMER_COUNT (1) 45 /* @brief DMA availability on the SoC. */ 46 #define FSL_FEATURE_SOC_DMA_COUNT (1) 47 /* @brief GPIO availability on the SoC. */ 48 #define FSL_FEATURE_SOC_GPIO_COUNT (1) 49 /* @brief I2C availability on the SoC. */ 50 #define FSL_FEATURE_SOC_I2C_COUNT (2) 51 /* @brief INPUTMUX availability on the SoC. */ 52 #define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) 53 /* @brief IOCON availability on the SoC. */ 54 #define FSL_FEATURE_SOC_IOCON_COUNT (1) 55 /* @brief MRT availability on the SoC. */ 56 #define FSL_FEATURE_SOC_MRT_COUNT (1) 57 /* @brief MTB availability on the SoC. */ 58 #define FSL_FEATURE_SOC_MTB_COUNT (1) 59 /* @brief PINT availability on the SoC. */ 60 #define FSL_FEATURE_SOC_PINT_COUNT (1) 61 /* @brief PMU availability on the SoC. */ 62 #define FSL_FEATURE_SOC_PMU_COUNT (1) 63 /* @brief SCT availability on the SoC. */ 64 #define FSL_FEATURE_SOC_SCT_COUNT (1) 65 /* @brief SPI availability on the SoC. */ 66 #define FSL_FEATURE_SOC_SPI_COUNT (2) 67 /* @brief SWM availability on the SoC. */ 68 #define FSL_FEATURE_SOC_SWM_COUNT (1) 69 /* @brief SYSCON availability on the SoC. */ 70 #define FSL_FEATURE_SOC_SYSCON_COUNT (1) 71 /* @brief USART availability on the SoC. */ 72 #define FSL_FEATURE_SOC_USART_COUNT (2) 73 /* @brief WWDT availability on the SoC. */ 74 #define FSL_FEATURE_SOC_WWDT_COUNT (1) 75 76 /* ACOMP module features */ 77 78 /* @brief Has INTENA bitfile in CTRL reigster. */ 79 #define FSL_FEATURE_ACOMP_HAS_CTRL_INTENA (1) 80 81 /* ADC module features */ 82 83 /* @brief Do not has input select (register INSEL). */ 84 #define FSL_FEATURE_ADC_HAS_NO_INSEL (1) 85 /* @brief Has ASYNMODE bitfile in CTRL reigster. */ 86 #define FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE (1) 87 /* @brief Has ASYNMODE bitfile in CTRL reigster. */ 88 #define FSL_FEATURE_ADC_HAS_CTRL_RESOL (0) 89 /* @brief Has ASYNMODE bitfile in CTRL reigster. */ 90 #define FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL (0) 91 /* @brief Has ASYNMODE bitfile in CTRL reigster. */ 92 #define FSL_FEATURE_ADC_HAS_CTRL_TSAMP (0) 93 /* @brief Has ASYNMODE bitfile in CTRL reigster. */ 94 #define FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE (1) 95 /* @brief Has ASYNMODE bitfile in CTRL reigster. */ 96 #define FSL_FEATURE_ADC_HAS_CTRL_CALMODE (1) 97 /* @brief Has startup register. */ 98 #define FSL_FEATURE_ADC_HAS_STARTUP_REG (0) 99 /* @brief Has ADC Trim register */ 100 #define FSL_FEATURE_ADC_HAS_TRIM_REG (1) 101 /* @brief Has Calibration register. */ 102 #define FSL_FEATURE_ADC_HAS_CALIB_REG (0) 103 104 /* CLOCK module features */ 105 106 /* @brief GPIOINT clock source. */ 107 #define FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE (1) 108 109 /* CTIMER module features */ 110 111 /* @brief CTIMER has no capture channel. */ 112 #define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0) 113 /* @brief CTIMER has no capture 2 interrupt. */ 114 #define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0) 115 /* @brief CTIMER capture 3 interrupt. */ 116 #define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1) 117 /* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */ 118 #define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0) 119 /* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */ 120 #define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1) 121 /* @brief Writing a zero asserts the CTIMER reset. */ 122 #define FSL_FEATURE_CTIMER_WRITE_ZERO_ASSERT_RESET (1) 123 /* @brief CTIMER Has register MSR */ 124 #define FSL_FEATURE_CTIMER_HAS_MSR (1) 125 126 /* DMA module features */ 127 128 /* @brief Number of channels */ 129 #define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (25) 130 /* @brief Align size of DMA descriptor */ 131 #define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512) 132 /* @brief DMA head link descriptor table align size */ 133 #define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U) 134 135 /* FAIM module features */ 136 137 /* @brief Size of the FAIM */ 138 #define FSL_FEATURE_FAIM_SIZE (32) 139 /* @brief Page count of the FAIM */ 140 #define FSL_FEATURE_FAIM_PAGE_COUNT (8) 141 142 /* INPUTMUX module features */ 143 144 /* @brief Inputmux clock source. */ 145 #define FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE (1) 146 147 /* IOCON module features */ 148 149 /* No feature definitions */ 150 151 /* MRT module features */ 152 153 /* @brief number of channels. */ 154 #define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) 155 /* @brief Has no MULTITASK bitfile in MODCFG reigster. */ 156 #define FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK (1) 157 /* @brief Has no INUSE bitfile in STAT reigster. */ 158 #define FSL_FEATURE_MRT_HAS_NO_CHANNEL_STAT_INUSE (1) 159 /* @brief Writing a zero asserts the MRT reset. */ 160 #define FSL_FEATURE_MRT_WRITE_ZERO_ASSERT_RESET (1) 161 162 /* NVIC module features */ 163 164 /* @brief Number of connected outputs. */ 165 #define FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER (1) 166 167 /* PINT module features */ 168 169 /* @brief Number of connected outputs */ 170 #define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8) 171 172 /* SCT module features */ 173 174 /* @brief Number of events */ 175 #define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (8) 176 /* @brief Number of states */ 177 #define FSL_FEATURE_SCT_NUMBER_OF_STATES (8) 178 /* @brief Number of match capture */ 179 #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (8) 180 /* @brief Number of outputs */ 181 #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (7) 182 /* @brief Writing a zero asserts the SCT reset. */ 183 #define FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET (1) 184 185 /* SPI module features */ 186 187 /* @brief Has SPOL0 bitfile in CFG reigster. */ 188 #define FSL_FEATURE_SPI_HAS_SSEL0 (1) 189 /* @brief Has SPOL1 bitfile in CFG reigster. */ 190 #define FSL_FEATURE_SPI_HAS_SSEL1 (1) 191 /* @brief Has SPOL2 bitfile in CFG reigster. */ 192 #define FSL_FEATURE_SPI_HAS_SSEL2 (1) 193 /* @brief Has SPOL3 bitfile in CFG reigster. */ 194 #define FSL_FEATURE_SPI_HAS_SSEL3 (1) 195 196 /* SWM module features */ 197 198 /* @brief Has SWM PINENABLE0 ACMP I3. */ 199 #define FSL_FEATURE_SWM_HAS_PINENABLE0_ACMP_I3 (1) 200 /* @brief Has SWM PINENABLE0 ACMP I4. */ 201 #define FSL_FEATURE_SWM_HAS_PINENABLE0_ACMP_I4 (1) 202 /* @brief Has SWM PINENABLE0 ACMP I5. */ 203 #define FSL_FEATURE_SWM_HAS_PINENABLE0_ACMP_I5 (1) 204 /* @brief Has SWM PINENABLE1. */ 205 #define FSL_FEATURE_SWM_HAS_PINENABLE1_REGISTER (1) 206 207 /* SYSCON module features */ 208 209 /* @brief Pointer to ROM IAP entry functions */ 210 #define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x0F001FF1) 211 /* @brief IAP Reinvoke ISP command parameter is pointer */ 212 #define FSL_FEATURE_SYSCON_IAP_REINVOKE_ISP_PARAM_POINTER (0) 213 /* @brief Flash page size in bytes */ 214 #define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (64) 215 /* @brief Flash sector size in bytes */ 216 #define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (1024) 217 /* @brief Flash size in bytes */ 218 #define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (65536) 219 /* @brief IAP has Flash read & write function */ 220 #define FSL_FEATURE_IAP_HAS_FLASH_FUNCTION (1) 221 /* @brief IAP has FAIM read & write function */ 222 #define FSL_FEATURE_IAP_HAS_FAIM_FUNCTION (1) 223 /* @brief IAP has read Flash signature function */ 224 #define FSL_FEATURE_IAP_HAS_FLASH_SIGNATURE_READ (0) 225 /* @brief IAP has read extended Flash signature function */ 226 #define FSL_FEATURE_IAP_HAS_FLASH_EXTENDED_SIGNATURE_READ (1) 227 /* @brief Starter register discontinuous. */ 228 #define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1) 229 /* @brief Has PINTSEL register. */ 230 #define FSL_FEATURE_SYSCON_HAS_PINT_SEL_REGISTER (1) 231 232 /* USART module features */ 233 234 /* @brief Has OSR (register OSR). */ 235 #define FSL_FEATURE_USART_HAS_OSR_REGISTER (1) 236 /* @brief Has TXIDLEEN bitfile in INTENSET reigster. */ 237 #define FSL_FEATURE_USART_HAS_INTENSET_TXIDLEEN (1) 238 /* @brief Has ABERREN bitfile in INTENSET reigster. */ 239 #define FSL_FEATURE_USART_HAS_ABERR_CHECK (1) 240 241 /* WKT module features */ 242 243 /* @brief Has SEL_EXTCLK bitfile in CTRL reigster. */ 244 #define FSL_FEATURE_WKT_HAS_CTRL_SEL_EXTCLK (1) 245 246 /* WWDT module features */ 247 248 /* @brief Has no RESET register. */ 249 #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) 250 251 #endif /* _LPC844_FEATURES_H_ */ 252 253
