1 2 /******************************************************************************/ 3 /* Device Specific Peripheral registers structures */ 4 /******************************************************************************/ 5 6 /** @addtogroup REGISTER Control Register 7 8 @{ 9 10 */ 11 12 13 /** 14 @addtogroup RMC RRAM Memory Controller(RMC) 15 Memory Mapped Structure for RMC Controller 16 @{ */ 17 18 typedef struct 19 { 20 21 22 /** 23 * @var RMC_T::ISPCTL 24 * Offset: 0x00 ISP Control Register 25 * --------------------------------------------------------------------------------------------------- 26 * |Bits |Field |Descriptions 27 * | :----: | :----: | :---- | 28 * |[0] |ISPEN |ISP Enable Bit (Write Protect) 29 * | | |ISP function enable bit. Set this bit to enable ISP function. 30 * | | |0 = ISP function Disabled. 31 * | | |1 = ISP function Enabled. 32 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 33 * |[1] |BS |Boot Select (Write Protect) 34 * | | |0 = Boot from APROM. 35 * | | |1 = Boot from LDROM. 36 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 37 * |[3] |APUEN |APROM Update Enable Bit (Write Protect) 38 * | | |0 = APROM cannot be updated when the chip runs in APROM. 39 * | | |1 = APROM can be updated when the chip runs in APROM. 40 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 41 * |[4] |CFGUEN |CONFIG Update Enable Bit (Write Protect) 42 * | | |0 = CONFIG cannot be updated. 43 * | | |1 = CONFIG can be updated. 44 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 45 * |[5] |LDUEN |LDROM Update Enable Bit (Write Protect) 46 * | | |0 = LDROM cannot be updated. 47 * | | |1 = LDROM can be updated. 48 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 49 * |[6] |ISPFF |ISP Fail Flag (Write Protect) 50 * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions: 51 * | | |This bit needs to be cleared by writing 1 to it. 52 * | | |l APROM writes to itself if APUEN is set to 0. 53 * | | |l LDROM writes to itself if LDUEN is set to 0. 54 * | | |l CONFIG is programmed if CFGUEN is set to 0. 55 * | | |l Program command at brown-out detected 56 * | | |l Destination address is illegal, such as over an available range. 57 * | | |l Invalid ISP commands 58 * | | |l The base and size of new XOM regions is wrong, overlap. 59 * | | |l The input setting of XOM page erase function is wrong 60 * | | |l The active XOM region is accessed (except for chip erase, page erase, chksum and read CID/DID) 61 * | | |l The XOM setting page is accessed (except for chip erase, word program and read) 62 * | | |l The XOM setting page is erased when XOM off. 63 * | | |l Violate the load code read protection 64 * | | |l OTP is erased. 65 * | | |l Checksum or Flash All One Verification is not executed in their valid range 66 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 67 * |[24] |INTEN |Secure ISP INT Enable Bit (Write Protect) 68 * | | |0= ISP INT Disabled. 69 * | | |1= ISP INT Enabled. 70 * | | |Note: This bit is write protected 71 * | | |Refer to the SYS_REGLCTL register 72 * | | |Before using INT, user needs to clear the INTFLAG(RMC_ISPSTS[24]) make sure INT happen at correct time. 73 * @var RMC_T::ISPADDR 74 * Offset: 0x04 ISP Address Register 75 * --------------------------------------------------------------------------------------------------- 76 * |Bits |Field |Descriptions 77 * | :----: | :----: | :---- | 78 * |[31:0] |ISPADDR |ISP Address 79 * | | |The M2L31 series is equipped with embedded RRAM. ISPADDR[1:0] must be kept 00 for ISP 32-bit operation. 80 * | | |For CRC32 Checksum Calculation command, this field is the RRAM starting address for checksum calculation, 4 Kbytes alignment is necessary for CRC32 checksum calculation. 81 * | | |For RRAM32-bit Program, ISP address needs word alignment (4-byte). 82 * @var RMC_T::ISPDAT 83 * Offset: 0x08 ISP Data Register 84 * --------------------------------------------------------------------------------------------------- 85 * |Bits |Field |Descriptions 86 * | :----: | :----: | :---- | 87 * |[31:0] |ISPDAT |ISP Data 88 * | | |Write data to this register before ISP program operation. 89 * | | |Read data from this register after ISP read operation. 90 * | | |When ISPFF (RMC_ISPCTL[6]) is 1, ISPDAT = 0xffff_ffff 91 * | | |For Run CRC32 Checksum Calculation command, ISPDAT is the memory size (byte) and 4 Kbytes alignment 92 * | | |For ISP Read CRC32 Checksum command, ISPDAT is the checksum result 93 * | | |If ISPDAT = 0x0000_0000, it means that (1) the checksum calculation is in progress, or (2) the memory range for checksum calculation is incorrect 94 * @var RMC_T::ISPCMD 95 * Offset: 0x0C ISP Command Register 96 * --------------------------------------------------------------------------------------------------- 97 * |Bits |Field |Descriptions 98 * | :----: | :----: | :---- | 99 * |[6:0] |CMD |ISP Command 100 * | | |ISP command table is shown below: 101 * | | |0x00= RRAM Read. 102 * | | |0x04= Read Unique ID. 103 * | | |0x08= Read RRAM All-One Result. 104 * | | |0x0B= Read Company ID. 105 * | | |0x0C= Read Device ID. 106 * | | |0x0D= Read Checksum. 107 * | | |0x21= RRAM 32-bits Program. 108 * | | |0x26= RRAM Mass Erase. Erase all pages in all banks, except for OTP. 109 * | | |0x27= RRAM 32-bits Load Data Buffer. 110 * | | |0x28= Run RRAM All-One Verification. 111 * | | |0x2C=Bank REMAP. 112 * | | |0x2D= Run Checksum Calculation. 113 * | | |0x2E= Vector Remap. 114 * | | |0x2F= RRAM 32-bits Clear Data Buffer. 115 * | | |The other commands are invalid. 116 * @var RMC_T::ISPTRG 117 * Offset: 0x10 ISP Trigger Control Register 118 * --------------------------------------------------------------------------------------------------- 119 * |Bits |Field |Descriptions 120 * | :----: | :----: | :---- | 121 * |[0] |ISPGO |ISP Start Trigger (Write Protect) 122 * | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished. 123 * | | |0 = ISP operation is finished. 124 * | | |1 = ISP is progressed. 125 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 126 * @var RMC_T::DFBA 127 * Offset: 0x14 Data RRAM Base Address 128 * --------------------------------------------------------------------------------------------------- 129 * |Bits |Field |Descriptions 130 * | :----: | :----: | :---- | 131 * |[31:0] |DFBA |Data RRAM Base Address 132 * | | |This register indicates Data RRAM start address. It is a read only register. 133 * | | |The Data RRAM is shared with APROM. the content of this register is loaded from CONFIG1 134 * | | |This register is valid when DFEN (CONFIG0[0]) =0 . 135 * @var RMC_T::FTCTL 136 * Offset: 0x18 RRAM Access Time Control Register 137 * --------------------------------------------------------------------------------------------------- 138 * |Bits |Field |Descriptions 139 * | :----: | :----: | :---- | 140 * |[9] |CACHEINV |RRAM Cache Invalidation (Write Protect) 141 * | | |0 = RRAM Cache Invalidation finished (default). 142 * | | |1 = RRAM Cache Invalidation. 143 * | | |Note 1: Write 1 to start cache invalidation. The value will be changed to 0 once the process finishes. 144 * | | |Note 2: This bit is write-protected. Refer to the SYS_REGLCTL register. 145 * @var RMC_T::ISPSTS 146 * Offset: 0x40 ISP Status Register 147 * --------------------------------------------------------------------------------------------------- 148 * |Bits |Field |Descriptions 149 * | :----: | :----: | :---- | 150 * |[0] |ISPBUSY |ISP Busy Flag (Read Only) 151 * | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished. 152 * | | |This bit is the mirror of ISPGO(RMC_ISPTRG[0]). 153 * | | |0 = ISP operation is finished. 154 * | | |1 = ISP is progressed. 155 * |[2] |CBS |Boot Selection of CONFIG (Read Only) 156 * | | |This bit is initiated with the CBS (CONFIG0[7]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened. 157 * | | |0 = LDROM with IAP mode. 158 * | | |1 = APROM with IAP mode. 159 * |[6] |ISPFF |ISP Fail Flag (Write Protect) 160 * | | |This bit is the mirror of ISPFF (RMC_ISPCTL[6]), it needs to be cleared by writing 1 to RMC_ISPCTL[6] or RMC_ISPSTS[6] 161 * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions: 162 * | | |l APROM writes to itself if APUEN is set to 0. 163 * | | |l LDROM writes to itself if LDUEN is set to 0. 164 * | | |l CONFIG is programmed if CFGUEN is set to 0. 165 * | | |l Program command at brown-out detected 166 * | | |l Destination address is illegal, such as over an available range. 167 * | | |l Invalid ISP commands 168 * | | |l The base and size of new XOM regions is wrong, overlap. 169 * | | |l The input setting of XOM erase function is wrong 170 * | | |l The active XOM region is accessed (except for chip erase, chksum and read CID/DID) 171 * | | |l The XOM setting page is accessed (except for chip erase, word program and read) 172 * | | |l The XOM setting page is erased when XOM off. 173 * | | |l Violate the load code read protection 174 * | | |l OTP is erased. 175 * | | |l Checksum or Flash All One Verification is not executed in their valid range 176 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 177 * |[7] |ALLONE |RRAM All-one Verification Flag 178 * | | |This bit is set by hardware if all of RRAM bits are 1, and clear if RRAM bits are not all 1 after u201CRun RRAM All-One Verificationu201D complete; this bit also can be clear by writing 1 179 * | | |0 = All of RRAM bits are 1 after u201CRun RRAM All-One Verificationu201D complete. 180 * | | |1 = RRAM bits are not all 1 after u201CRun RRAM All-One Verificationu201D complete. 181 * |[23:9] |VECMAP |Vector Page Mapping Address (Read Only) 182 * | | |All access to 0x0000_0000~0x0000_01FF is remapped to the RRAM memory address {VECMAP[14:0], 9'h000} ~ {VECMAP[14:0], 9'h1FF} 183 * | | |Note: If VECMAP[14:11]=0x1, LDROM code is mapped to system memory vector 184 * | | |If VECMAP[14:11]=0x0, APROM code is mapped to system memory vector. 185 * |[24] |INTFLAG |ISP Interrupt Flag 186 * | | |0 = ISP Not Finished. 187 * | | |1 = ISP done or ISPFF set. 188 * | | |Note: This function needs to be enabled by RMC_ISPCTRL[24]. 189 * |[25] |SCFF |Secure Conceal Fail Flag (Write Protect) 190 * | | |This bit is set by hardware if any ISP command accesses secure region when secure conceal function is active. 191 * | | |This bit needs to be cleared by writing 1 to it. 192 * | | |0 = ISP is not accessed secure conceal region 193 * | | |1 = ISP is accessed secure conceal region 194 * |[30] |FBS |Flash Bank Selection 195 * | | |This bit indicate which bank is selected to boot. 196 * | | |0 = Booting from BANK0. 197 * | | |1 = Booting from BANK1. 198 * @var RMC_T::CYCCTL 199 * Offset: 0x4C RRAM Access Cycle Control Register 200 * --------------------------------------------------------------------------------------------------- 201 * |Bits |Field |Descriptions 202 * | :----: | :----: | :---- | 203 * |[3:0] |CYCLE |RRAM Access Cycle Control (Write Protect) 204 * | | |CHIP power level is PL1: 205 * | | |0010 = CPU access with two wait cycles if cache miss. 206 * | | |The HCLK working frequency range is <25 MHz 207 * | | |0011 = CPU access with three wait cycles if cache miss. 208 * | | |The optimized HCLK working frequency range is 25~50 MHz 209 * | | |0100 = CPU access with four wait cycles if cache miss. 210 * | | |The optimized HCLK working frequency range is 50~72 MHz 211 * | | |Others = Reserved 212 * | | |CHIP power level is PL2: TBD 213 * | | |CHIP power level is PL3: 214 * | | |0001 = CPU access with one wait cycle if cache miss. 215 * | | |The HCLK working frequency range is <6 MHz 216 * | | |0010 = CPU access with two wait cycles if cache miss. 217 * | | |The optimized HCLK working frequency range is 6~12 MHz 218 * | | |Others = Reserved 219 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 220 * @var RMC_T::XOMR0STS 221 * Offset: 0xD0 XOM Region 0 Status Register 222 * --------------------------------------------------------------------------------------------------- 223 * |Bits |Field |Descriptions 224 * | :----: | :----: | :---- | 225 * |[7:0] |SIZE |XOM Region 0 Size 226 * | | |SIZE is the page number of XOM Region 0 must be page-aligned.. 227 * |[31:8] |BASE |XOM Region 0 Base Address 228 * | | |BASE is the base address of XOM Region 0 must be page-aligned.. 229 * @var RMC_T::XOMR1STS 230 * Offset: 0xD4 XOM Region 1 Status Register 231 * --------------------------------------------------------------------------------------------------- 232 * |Bits |Field |Descriptions 233 * | :----: | :----: | :---- | 234 * |[7:0] |SIZE |XOM Region 1 Size 235 * | | |SIZE is the page number of XOM Region 1 must be page-aligned.. 236 * |[31:8] |BASE |XOM Region 1 Base Address 237 * | | |BASE is the base address of XOM Region 1 must be page-aligned.. 238 * @var RMC_T::XOMR2STS 239 * Offset: 0xD8 XOM Region 2 Status Register 240 * --------------------------------------------------------------------------------------------------- 241 * |Bits |Field |Descriptions 242 * | :----: | :----: | :---- | 243 * |[7:0] |SIZE |XOM Region 2 Size 244 * | | |SIZE is the page number of XOM Region 2 must be page-aligned.. 245 * |[31:8] |BASE |XOM Region 2 Base Address 246 * | | |BASE is the base address of XOM Region 2 must be page-aligned.. 247 * @var RMC_T::XOMR3STS 248 * Offset: 0xDC XOM Region 3 Status Register 249 * --------------------------------------------------------------------------------------------------- 250 * |Bits |Field |Descriptions 251 * | :----: | :----: | :---- | 252 * |[7:0] |SIZE |XOM Region 3 Size 253 * | | |SIZE is the page number of XOM Region 3 must be page-aligned. 254 * |[31:8] |BASE |XOM Region 3 Base Address 255 * | | |BASE is the base address of XOM Region 3 must be page-aligned. 256 * @var RMC_T::XOMSTS 257 * Offset: 0xE0 XOM Status Register 258 * --------------------------------------------------------------------------------------------------- 259 * |Bits |Field |Descriptions 260 * | :----: | :----: | :---- | 261 * |[0] |XOMR0ON |XOM Region 0 On 262 * | | |XOM Region 0 active status. 263 * | | |0 = No active. 264 * | | |1 = XOM region 0 is active. 265 * |[1] |XOMR1ON |XOM Region 1 On 266 * | | |XOM Region 1 active status. 267 * | | |0 = No active. 268 * | | |1 = XOM region 1 is active. 269 * |[2] |XOMR2ON |XOM Region 2 On 270 * | | |XOM Region 2 active status. 271 * | | |0 = No active. 272 * | | |1 = XOM region 2 is active. 273 * |[3] |XOMR3ON |XOM Region 3 On 274 * | | |XOM Region 3 active status. 275 * | | |0 = No active. 276 * | | |1 = XOM region 3 is active. 277 * |[4] |XOMPEF |XOM Page Erase Function Fail 278 * | | |XOM page erase function status. If XOMPEF is set to 1, user needs to erase XOM region again. 279 * | | |0 = Sucess. 280 * | | |1 = Fail. 281 * @var RMC_T::APWPROT0 282 * Offset: 0x110 APROM Write Protect Register0 283 * --------------------------------------------------------------------------------------------------- 284 * |Bits |Field |Descriptions 285 * | :----: | :----: | :---- | 286 * |[0] |APPROEN0 |APROM Protect enable 287 * | | |This bit indicates which APROM region is protected. 288 * | | |0 = APROM region n is not protected. 289 * | | |1 = APROM region n is protected. 290 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 291 * |[1] |APPROEN1 |APROM Protect enable 292 * | | |This bit indicates which APROM region is protected. 293 * | | |0 = APROM region n is not protected. 294 * | | |1 = APROM region n is protected. 295 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 296 * |[2] |APPROEN2 |APROM Protect enable 297 * | | |This bit indicates which APROM region is protected. 298 * | | |0 = APROM region n is not protected. 299 * | | |1 = APROM region n is protected. 300 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 301 * |[3] |APPROEN3 |APROM Protect enable 302 * | | |This bit indicates which APROM region is protected. 303 * | | |0 = APROM region n is not protected. 304 * | | |1 = APROM region n is protected. 305 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 306 * |[4] |APPROEN4 |APROM Protect enable 307 * | | |This bit indicates which APROM region is protected. 308 * | | |0 = APROM region n is not protected. 309 * | | |1 = APROM region n is protected. 310 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 311 * |[5] |APPROEN5 |APROM Protect enable 312 * | | |This bit indicates which APROM region is protected. 313 * | | |0 = APROM region n is not protected. 314 * | | |1 = APROM region n is protected. 315 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 316 * |[6] |APPROEN6 |APROM Protect enable 317 * | | |This bit indicates which APROM region is protected. 318 * | | |0 = APROM region n is not protected. 319 * | | |1 = APROM region n is protected. 320 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 321 * |[7] |APPROEN7 |APROM Protect enable 322 * | | |This bit indicates which APROM region is protected. 323 * | | |0 = APROM region n is not protected. 324 * | | |1 = APROM region n is protected. 325 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 326 * |[8] |APPROEN8 |APROM Protect enable 327 * | | |This bit indicates which APROM region is protected. 328 * | | |0 = APROM region n is not protected. 329 * | | |1 = APROM region n is protected. 330 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 331 * |[9] |APPROEN9 |APROM Protect enable 332 * | | |This bit indicates which APROM region is protected. 333 * | | |0 = APROM region n is not protected. 334 * | | |1 = APROM region n is protected. 335 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 336 * |[10] |APPROEN10 |APROM Protect enable 337 * | | |This bit indicates which APROM region is protected. 338 * | | |0 = APROM region n is not protected. 339 * | | |1 = APROM region n is protected. 340 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 341 * |[11] |APPROEN11 |APROM Protect enable 342 * | | |This bit indicates which APROM region is protected. 343 * | | |0 = APROM region n is not protected. 344 * | | |1 = APROM region n is protected. 345 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 346 * |[12] |APPROEN12 |APROM Protect enable 347 * | | |This bit indicates which APROM region is protected. 348 * | | |0 = APROM region n is not protected. 349 * | | |1 = APROM region n is protected. 350 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 351 * |[13] |APPROEN13 |APROM Protect enable 352 * | | |This bit indicates which APROM region is protected. 353 * | | |0 = APROM region n is not protected. 354 * | | |1 = APROM region n is protected. 355 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 356 * |[14] |APPROEN14 |APROM Protect enable 357 * | | |This bit indicates which APROM region is protected. 358 * | | |0 = APROM region n is not protected. 359 * | | |1 = APROM region n is protected. 360 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 361 * |[15] |APPROEN15 |APROM Protect enable 362 * | | |This bit indicates which APROM region is protected. 363 * | | |0 = APROM region n is not protected. 364 * | | |1 = APROM region n is protected. 365 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 366 * |[16] |APPROEN16 |APROM Protect enable 367 * | | |This bit indicates which APROM region is protected. 368 * | | |0 = APROM region n is not protected. 369 * | | |1 = APROM region n is protected. 370 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 371 * |[17] |APPROEN17 |APROM Protect enable 372 * | | |This bit indicates which APROM region is protected. 373 * | | |0 = APROM region n is not protected. 374 * | | |1 = APROM region n is protected. 375 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 376 * |[18] |APPROEN18 |APROM Protect enable 377 * | | |This bit indicates which APROM region is protected. 378 * | | |0 = APROM region n is not protected. 379 * | | |1 = APROM region n is protected. 380 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 381 * |[19] |APPROEN19 |APROM Protect enable 382 * | | |This bit indicates which APROM region is protected. 383 * | | |0 = APROM region n is not protected. 384 * | | |1 = APROM region n is protected. 385 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 386 * |[20] |APPROEN20 |APROM Protect enable 387 * | | |This bit indicates which APROM region is protected. 388 * | | |0 = APROM region n is not protected. 389 * | | |1 = APROM region n is protected. 390 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 391 * |[21] |APPROEN21 |APROM Protect enable 392 * | | |This bit indicates which APROM region is protected. 393 * | | |0 = APROM region n is not protected. 394 * | | |1 = APROM region n is protected. 395 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 396 * |[22] |APPROEN22 |APROM Protect enable 397 * | | |This bit indicates which APROM region is protected. 398 * | | |0 = APROM region n is not protected. 399 * | | |1 = APROM region n is protected. 400 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 401 * |[23] |APPROEN23 |APROM Protect enable 402 * | | |This bit indicates which APROM region is protected. 403 * | | |0 = APROM region n is not protected. 404 * | | |1 = APROM region n is protected. 405 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 406 * |[24] |APPROEN24 |APROM Protect enable 407 * | | |This bit indicates which APROM region is protected. 408 * | | |0 = APROM region n is not protected. 409 * | | |1 = APROM region n is protected. 410 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 411 * |[25] |APPROEN25 |APROM Protect enable 412 * | | |This bit indicates which APROM region is protected. 413 * | | |0 = APROM region n is not protected. 414 * | | |1 = APROM region n is protected. 415 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 416 * |[26] |APPROEN26 |APROM Protect enable 417 * | | |This bit indicates which APROM region is protected. 418 * | | |0 = APROM region n is not protected. 419 * | | |1 = APROM region n is protected. 420 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 421 * |[27] |APPROEN27 |APROM Protect enable 422 * | | |This bit indicates which APROM region is protected. 423 * | | |0 = APROM region n is not protected. 424 * | | |1 = APROM region n is protected. 425 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 426 * |[28] |APPROEN28 |APROM Protect enable 427 * | | |This bit indicates which APROM region is protected. 428 * | | |0 = APROM region n is not protected. 429 * | | |1 = APROM region n is protected. 430 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 431 * |[29] |APPROEN29 |APROM Protect enable 432 * | | |This bit indicates which APROM region is protected. 433 * | | |0 = APROM region n is not protected. 434 * | | |1 = APROM region n is protected. 435 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 436 * |[30] |APPROEN30 |APROM Protect enable 437 * | | |This bit indicates which APROM region is protected. 438 * | | |0 = APROM region n is not protected. 439 * | | |1 = APROM region n is protected. 440 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 441 * |[31] |APPROEN31 |APROM Protect enable 442 * | | |This bit indicates which APROM region is protected. 443 * | | |0 = APROM region n is not protected. 444 * | | |1 = APROM region n is protected. 445 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 446 * @var RMC_T::APWPROT1 447 * Offset: 0x114 APROM Write Protect Register1 448 * --------------------------------------------------------------------------------------------------- 449 * |Bits |Field |Descriptions 450 * | :----: | :----: | :---- | 451 * |[0] |APPROEN32 |APROM Protect enable 452 * | | |This bit indicates which APROM region is protected. 453 * | | |0 = APROM region n is not protected. 454 * | | |1 = APROM region n is protected. 455 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 456 * |[1] |APPROEN33 |APROM Protect enable 457 * | | |This bit indicates which APROM region is protected. 458 * | | |0 = APROM region n is not protected. 459 * | | |1 = APROM region n is protected. 460 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 461 * |[2] |APPROEN34 |APROM Protect enable 462 * | | |This bit indicates which APROM region is protected. 463 * | | |0 = APROM region n is not protected. 464 * | | |1 = APROM region n is protected. 465 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 466 * |[3] |APPROEN35 |APROM Protect enable 467 * | | |This bit indicates which APROM region is protected. 468 * | | |0 = APROM region n is not protected. 469 * | | |1 = APROM region n is protected. 470 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 471 * |[4] |APPROEN36 |APROM Protect enable 472 * | | |This bit indicates which APROM region is protected. 473 * | | |0 = APROM region n is not protected. 474 * | | |1 = APROM region n is protected. 475 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 476 * |[5] |APPROEN37 |APROM Protect enable 477 * | | |This bit indicates which APROM region is protected. 478 * | | |0 = APROM region n is not protected. 479 * | | |1 = APROM region n is protected. 480 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 481 * |[6] |APPROEN38 |APROM Protect enable 482 * | | |This bit indicates which APROM region is protected. 483 * | | |0 = APROM region n is not protected. 484 * | | |1 = APROM region n is protected. 485 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 486 * |[7] |APPROEN39 |APROM Protect enable 487 * | | |This bit indicates which APROM region is protected. 488 * | | |0 = APROM region n is not protected. 489 * | | |1 = APROM region n is protected. 490 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 491 * |[8] |APPROEN40 |APROM Protect enable 492 * | | |This bit indicates which APROM region is protected. 493 * | | |0 = APROM region n is not protected. 494 * | | |1 = APROM region n is protected. 495 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 496 * |[9] |APPROEN41 |APROM Protect enable 497 * | | |This bit indicates which APROM region is protected. 498 * | | |0 = APROM region n is not protected. 499 * | | |1 = APROM region n is protected. 500 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 501 * |[10] |APPROEN42 |APROM Protect enable 502 * | | |This bit indicates which APROM region is protected. 503 * | | |0 = APROM region n is not protected. 504 * | | |1 = APROM region n is protected. 505 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 506 * |[11] |APPROEN43 |APROM Protect enable 507 * | | |This bit indicates which APROM region is protected. 508 * | | |0 = APROM region n is not protected. 509 * | | |1 = APROM region n is protected. 510 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 511 * |[12] |APPROEN44 |APROM Protect enable 512 * | | |This bit indicates which APROM region is protected. 513 * | | |0 = APROM region n is not protected. 514 * | | |1 = APROM region n is protected. 515 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 516 * |[13] |APPROEN45 |APROM Protect enable 517 * | | |This bit indicates which APROM region is protected. 518 * | | |0 = APROM region n is not protected. 519 * | | |1 = APROM region n is protected. 520 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 521 * |[14] |APPROEN46 |APROM Protect enable 522 * | | |This bit indicates which APROM region is protected. 523 * | | |0 = APROM region n is not protected. 524 * | | |1 = APROM region n is protected. 525 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 526 * |[15] |APPROEN47 |APROM Protect enable 527 * | | |This bit indicates which APROM region is protected. 528 * | | |0 = APROM region n is not protected. 529 * | | |1 = APROM region n is protected. 530 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 531 * |[16] |APPROEN48 |APROM Protect enable 532 * | | |This bit indicates which APROM region is protected. 533 * | | |0 = APROM region n is not protected. 534 * | | |1 = APROM region n is protected. 535 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 536 * |[17] |APPROEN49 |APROM Protect enable 537 * | | |This bit indicates which APROM region is protected. 538 * | | |0 = APROM region n is not protected. 539 * | | |1 = APROM region n is protected. 540 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 541 * |[18] |APPROEN50 |APROM Protect enable 542 * | | |This bit indicates which APROM region is protected. 543 * | | |0 = APROM region n is not protected. 544 * | | |1 = APROM region n is protected. 545 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 546 * |[19] |APPROEN51 |APROM Protect enable 547 * | | |This bit indicates which APROM region is protected. 548 * | | |0 = APROM region n is not protected. 549 * | | |1 = APROM region n is protected. 550 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 551 * |[20] |APPROEN52 |APROM Protect enable 552 * | | |This bit indicates which APROM region is protected. 553 * | | |0 = APROM region n is not protected. 554 * | | |1 = APROM region n is protected. 555 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 556 * |[21] |APPROEN53 |APROM Protect enable 557 * | | |This bit indicates which APROM region is protected. 558 * | | |0 = APROM region n is not protected. 559 * | | |1 = APROM region n is protected. 560 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 561 * |[22] |APPROEN54 |APROM Protect enable 562 * | | |This bit indicates which APROM region is protected. 563 * | | |0 = APROM region n is not protected. 564 * | | |1 = APROM region n is protected. 565 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 566 * |[23] |APPROEN55 |APROM Protect enable 567 * | | |This bit indicates which APROM region is protected. 568 * | | |0 = APROM region n is not protected. 569 * | | |1 = APROM region n is protected. 570 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 571 * |[24] |APPROEN56 |APROM Protect enable 572 * | | |This bit indicates which APROM region is protected. 573 * | | |0 = APROM region n is not protected. 574 * | | |1 = APROM region n is protected. 575 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 576 * |[25] |APPROEN57 |APROM Protect enable 577 * | | |This bit indicates which APROM region is protected. 578 * | | |0 = APROM region n is not protected. 579 * | | |1 = APROM region n is protected. 580 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 581 * |[26] |APPROEN58 |APROM Protect enable 582 * | | |This bit indicates which APROM region is protected. 583 * | | |0 = APROM region n is not protected. 584 * | | |1 = APROM region n is protected. 585 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 586 * |[27] |APPROEN59 |APROM Protect enable 587 * | | |This bit indicates which APROM region is protected. 588 * | | |0 = APROM region n is not protected. 589 * | | |1 = APROM region n is protected. 590 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 591 * |[28] |APPROEN60 |APROM Protect enable 592 * | | |This bit indicates which APROM region is protected. 593 * | | |0 = APROM region n is not protected. 594 * | | |1 = APROM region n is protected. 595 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 596 * |[29] |APPROEN61 |APROM Protect enable 597 * | | |This bit indicates which APROM region is protected. 598 * | | |0 = APROM region n is not protected. 599 * | | |1 = APROM region n is protected. 600 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 601 * |[30] |APPROEN62 |APROM Protect enable 602 * | | |This bit indicates which APROM region is protected. 603 * | | |0 = APROM region n is not protected. 604 * | | |1 = APROM region n is protected. 605 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 606 * |[31] |APPROEN63 |APROM Protect enable 607 * | | |This bit indicates which APROM region is protected. 608 * | | |0 = APROM region n is not protected. 609 * | | |1 = APROM region n is protected. 610 * | | |Note: APROM protect region is 0x0 + n*(0x2000) to 0x1fff + n*(0x2000) 611 * @var RMC_T::APWPKEEP 612 * Offset: 0x118 APROM Write Protect Keep Register 613 * --------------------------------------------------------------------------------------------------- 614 * |Bits |Field |Descriptions 615 * | :----: | :----: | :---- | 616 * |[15:0] |APWPKEEP0 |APROM Write Protect Keep 0 617 * | | |0x55AA = APWPROT0 register is be locked. 618 * | | |others = APWPROT0 register is free. 619 * |[31:16] |APWPKEEP1 |APROM Write Protect Keep 1 620 * | | |0x55AA = APWPROT1 register is be locked. 621 * | | |others = APWPROT1 register is free. 622 * @var RMC_T::SCACT 623 * Offset: 0x11C APROM Secure Conceal Active Register 624 * --------------------------------------------------------------------------------------------------- 625 * |Bits |Field |Descriptions 626 * | :----: | :----: | :---- | 627 * |[0] |SCACT |Secure Conceal Function Active 628 * | | |0 = secure conceal function inactive. 629 * | | |1 = secure conceal function active. 630 * | | |Note: secure conceal function active will base on this bit and setting of CONFIG6 is all 0. 631 * | | |Note: After SCACT is set to 1, the secure conceal function is active and cannot be disable by software 632 * | | |So read SCACT will always get 1 after set this bit. 633 */ 634 __IO uint32_t ISPCTL; /*!< [0x0000] ISP Control Register */ 635 __IO uint32_t ISPADDR; /*!< [0x0004] ISP Address Register */ 636 __IO uint32_t ISPDAT; /*!< [0x0008] ISP Data Register */ 637 __IO uint32_t ISPCMD; /*!< [0x000c] ISP Command Register */ 638 __IO uint32_t ISPTRG; /*!< [0x0010] ISP Trigger Control Register */ 639 __I uint32_t DFBA; /*!< [0x0014] Data RRAM Base Address */ 640 __IO uint32_t FTCTL; /*!< [0x0018] RRAM Access Time Control Register */ 641 __I uint32_t RESERVE0[9]; 642 __IO uint32_t ISPSTS; /*!< [0x0040] ISP Status Register */ 643 __I uint32_t RESERVE1[2]; 644 __IO uint32_t CYCCTL; /*!< [0x004c] RRAM Access Cycle Control Register */ 645 __I uint32_t RESERVE2[32]; 646 __I uint32_t XOMR0STS; /*!< [0x00d0] XOM Region 0 Status Register */ 647 __I uint32_t XOMR1STS; /*!< [0x00d4] XOM Region 1 Status Register */ 648 __I uint32_t XOMR2STS; /*!< [0x00d8] XOM Region 2 Status Register */ 649 __I uint32_t XOMR3STS; /*!< [0x00dc] XOM Region 3 Status Register */ 650 __I uint32_t XOMSTS; /*!< [0x00e0] XOM Status Register */ 651 __I uint32_t RESERVE3[11]; 652 __IO uint32_t APWPROT0; /*!< [0x0110] APROM Write Protect Register0 */ 653 __IO uint32_t APWPROT1; /*!< [0x0114] APROM Write Protect Register1 */ 654 __IO uint32_t APWPKEEP; /*!< [0x0118] APROM Write Protect Keep Register */ 655 __IO uint32_t SCACT; /*!< [0x011c] APROM Secure Conceal Active Register */ 656 657 } RMC_T; 658 659 /** 660 @addtogroup RMC_CONST RMC Bit Field Definition 661 Constant Definitions for RMC Controller 662 @{ */ 663 664 #define RMC_ISPCTL_ISPEN_Pos (0) /*!< RMC_T::ISPCTL: ISPEN Position */ 665 #define RMC_ISPCTL_ISPEN_Msk (0x1ul << RMC_ISPCTL_ISPEN_Pos) /*!< RMC_T::ISPCTL: ISPEN Mask */ 666 667 #define RMC_ISPCTL_BS_Pos (1) /*!< RMC_T::ISPCTL: BS Position */ 668 #define RMC_ISPCTL_BS_Msk (0x1ul << RMC_ISPCTL_BS_Pos) /*!< RMC_T::ISPCTL: BS Mask */ 669 670 #define RMC_ISPCTL_APUEN_Pos (3) /*!< RMC_T::ISPCTL: APUEN Position */ 671 #define RMC_ISPCTL_APUEN_Msk (0x1ul << RMC_ISPCTL_APUEN_Pos) /*!< RMC_T::ISPCTL: APUEN Mask */ 672 673 #define RMC_ISPCTL_CFGUEN_Pos (4) /*!< RMC_T::ISPCTL: CFGUEN Position */ 674 #define RMC_ISPCTL_CFGUEN_Msk (0x1ul << RMC_ISPCTL_CFGUEN_Pos) /*!< RMC_T::ISPCTL: CFGUEN Mask */ 675 676 #define RMC_ISPCTL_LDUEN_Pos (5) /*!< RMC_T::ISPCTL: LDUEN Position */ 677 #define RMC_ISPCTL_LDUEN_Msk (0x1ul << RMC_ISPCTL_LDUEN_Pos) /*!< RMC_T::ISPCTL: LDUEN Mask */ 678 679 #define RMC_ISPCTL_ISPFF_Pos (6) /*!< RMC_T::ISPCTL: ISPFF Position */ 680 #define RMC_ISPCTL_ISPFF_Msk (0x1ul << RMC_ISPCTL_ISPFF_Pos) /*!< RMC_T::ISPCTL: ISPFF Mask */ 681 682 #define RMC_ISPCTL_INTEN_Pos (24) /*!< RMC_T::ISPCTL: INTEN Position */ 683 #define RMC_ISPCTL_INTEN_Msk (0x1ul << RMC_ISPCTL_INTEN_Pos) /*!< RMC_T::ISPCTL: INTEN Mask */ 684 685 #define RMC_ISPADDR_ISPADDR_Pos (0) /*!< RMC_T::ISPADDR: ISPADDR Position */ 686 #define RMC_ISPADDR_ISPADDR_Msk (0xfffffffful << RMC_ISPADDR_ISPADDR_Pos) /*!< RMC_T::ISPADDR: ISPADDR Mask */ 687 688 #define RMC_ISPDAT_ISPDAT_Pos (0) /*!< RMC_T::ISPDAT: ISPDAT Position */ 689 #define RMC_ISPDAT_ISPDAT_Msk (0xfffffffful << RMC_ISPDAT_ISPDAT_Pos) /*!< RMC_T::ISPDAT: ISPDAT Mask */ 690 691 #define RMC_ISPCMD_CMD_Pos (0) /*!< RMC_T::ISPCMD: CMD Position */ 692 #define RMC_ISPCMD_CMD_Msk (0x7ful << RMC_ISPCMD_CMD_Pos) /*!< RMC_T::ISPCMD: CMD Mask */ 693 694 #define RMC_ISPTRG_ISPGO_Pos (0) /*!< RMC_T::ISPTRG: ISPGO Position */ 695 #define RMC_ISPTRG_ISPGO_Msk (0x1ul << RMC_ISPTRG_ISPGO_Pos) /*!< RMC_T::ISPTRG: ISPGO Mask */ 696 697 #define RMC_DFBA_DFBA_Pos (0) /*!< RMC_T::DFBA: DFBA Position */ 698 #define RMC_DFBA_DFBA_Msk (0xfffffffful << RMC_DFBA_DFBA_Pos) /*!< RMC_T::DFBA: DFBA Mask */ 699 700 #define RMC_FTCTL_CACHEINV_Pos (9) /*!< RMC_T::FTCTL: CACHEINV Position */ 701 #define RMC_FTCTL_CACHEINV_Msk (0x1ul << RMC_FTCTL_CACHEINV_Pos) /*!< RMC_T::FTCTL: CACHEINV Mask */ 702 703 #define RMC_ISPSTS_ISPBUSY_Pos (0) /*!< RMC_T::ISPSTS: ISPBUSY Position */ 704 #define RMC_ISPSTS_ISPBUSY_Msk (0x1ul << RMC_ISPSTS_ISPBUSY_Pos) /*!< RMC_T::ISPSTS: ISPBUSY Mask */ 705 706 #define RMC_ISPSTS_CBS_Pos (2) /*!< RMC_T::ISPSTS: CBS Position */ 707 #define RMC_ISPSTS_CBS_Msk (0x1ul << RMC_ISPSTS_CBS_Pos) /*!< RMC_T::ISPSTS: CBS Mask */ 708 709 #define RMC_ISPSTS_ISPFF_Pos (6) /*!< RMC_T::ISPSTS: ISPFF Position */ 710 #define RMC_ISPSTS_ISPFF_Msk (0x1ul << RMC_ISPSTS_ISPFF_Pos) /*!< RMC_T::ISPSTS: ISPFF Mask */ 711 712 #define RMC_ISPSTS_ALLONE_Pos (7) /*!< RMC_T::ISPSTS: ALLONE Position */ 713 #define RMC_ISPSTS_ALLONE_Msk (0x1ul << RMC_ISPSTS_ALLONE_Pos) /*!< RMC_T::ISPSTS: ALLONE Mask */ 714 715 #define RMC_ISPSTS_VECMAP_Pos (9) /*!< RMC_T::ISPSTS: VECMAP Position */ 716 #define RMC_ISPSTS_VECMAP_Msk (0x7ffful << RMC_ISPSTS_VECMAP_Pos) /*!< RMC_T::ISPSTS: VECMAP Mask */ 717 718 #define RMC_ISPSTS_INTFLAG_Pos (24) /*!< RMC_T::ISPSTS: INTFLAG Position */ 719 #define RMC_ISPSTS_INTFLAG_Msk (0x1ul << RMC_ISPSTS_INTFLAG_Pos) /*!< RMC_T::ISPSTS: INTFLAG Mask */ 720 721 #define RMC_ISPSTS_SCFF_Pos (25) /*!< RMC_T::ISPSTS: SCFF Position */ 722 #define RMC_ISPSTS_SCFF_Msk (0x1ul << RMC_ISPSTS_SCFF_Pos) /*!< RMC_T::ISPSTS: SCFF Mask */ 723 724 #define RMC_ISPSTS_FBS_Pos (30) /*!< RMC_T::ISPSTS: FBS Position */ 725 #define RMC_ISPSTS_FBS_Msk (0x1ul << RMC_ISPSTS_FBS_Pos) /*!< RMC_T::ISPSTS: FBS Mask */ 726 727 #define RMC_CYCCTL_CYCLE_Pos (0) /*!< RMC_T::CYCCTL: CYCLE Position */ 728 #define RMC_CYCCTL_CYCLE_Msk (0xful << RMC_CYCCTL_CYCLE_Pos) /*!< RMC_T::CYCCTL: CYCLE Mask */ 729 730 #define RMC_XOMR0STS_SIZE_Pos (0) /*!< RMC_T::XOMR0STS: SIZE Position */ 731 #define RMC_XOMR0STS_SIZE_Msk (0xfful << RMC_XOMR0STS_SIZE_Pos) /*!< RMC_T::XOMR0STS: SIZE Mask */ 732 733 #define RMC_XOMR0STS_BASE_Pos (8) /*!< RMC_T::XOMR0STS: BASE Position */ 734 #define RMC_XOMR0STS_BASE_Msk (0xfffffful << RMC_XOMR0STS_BASE_Pos) /*!< RMC_T::XOMR0STS: BASE Mask */ 735 736 #define RMC_XOMR1STS_SIZE_Pos (0) /*!< RMC_T::XOMR1STS: SIZE Position */ 737 #define RMC_XOMR1STS_SIZE_Msk (0xfful << RMC_XOMR1STS_SIZE_Pos) /*!< RMC_T::XOMR1STS: SIZE Mask */ 738 739 #define RMC_XOMR1STS_BASE_Pos (8) /*!< RMC_T::XOMR1STS: BASE Position */ 740 #define RMC_XOMR1STS_BASE_Msk (0xfffffful << RMC_XOMR1STS_BASE_Pos) /*!< RMC_T::XOMR1STS: BASE Mask */ 741 742 #define RMC_XOMR2STS_SIZE_Pos (0) /*!< RMC_T::XOMR2STS: SIZE Position */ 743 #define RMC_XOMR2STS_SIZE_Msk (0xfful << RMC_XOMR2STS_SIZE_Pos) /*!< RMC_T::XOMR2STS: SIZE Mask */ 744 745 #define RMC_XOMR2STS_BASE_Pos (8) /*!< RMC_T::XOMR2STS: BASE Position */ 746 #define RMC_XOMR2STS_BASE_Msk (0xfffffful << RMC_XOMR2STS_BASE_Pos) /*!< RMC_T::XOMR2STS: BASE Mask */ 747 748 #define RMC_XOMR3STS_SIZE_Pos (0) /*!< RMC_T::XOMR3STS: SIZE Position */ 749 #define RMC_XOMR3STS_SIZE_Msk (0xfful << RMC_XOMR3STS_SIZE_Pos) /*!< RMC_T::XOMR3STS: SIZE Mask */ 750 751 #define RMC_XOMR3STS_BASE_Pos (8) /*!< RMC_T::XOMR3STS: BASE Position */ 752 #define RMC_XOMR3STS_BASE_Msk (0xfffffful << RMC_XOMR3STS_BASE_Pos) /*!< RMC_T::XOMR3STS: BASE Mask */ 753 754 #define RMC_XOMSTS_XOMR0ON_Pos (0) /*!< RMC_T::XOMSTS: XOMR0ON Position */ 755 #define RMC_XOMSTS_XOMR0ON_Msk (0x1ul << RMC_XOMSTS_XOMR0ON_Pos) /*!< RMC_T::XOMSTS: XOMR0ON Mask */ 756 757 #define RMC_XOMSTS_XOMR1ON_Pos (1) /*!< RMC_T::XOMSTS: XOMR1ON Position */ 758 #define RMC_XOMSTS_XOMR1ON_Msk (0x1ul << RMC_XOMSTS_XOMR1ON_Pos) /*!< RMC_T::XOMSTS: XOMR1ON Mask */ 759 760 #define RMC_XOMSTS_XOMR2ON_Pos (2) /*!< RMC_T::XOMSTS: XOMR2ON Position */ 761 #define RMC_XOMSTS_XOMR2ON_Msk (0x1ul << RMC_XOMSTS_XOMR2ON_Pos) /*!< RMC_T::XOMSTS: XOMR2ON Mask */ 762 763 #define RMC_XOMSTS_XOMR3ON_Pos (3) /*!< RMC_T::XOMSTS: XOMR3ON Position */ 764 #define RMC_XOMSTS_XOMR3ON_Msk (0x1ul << RMC_XOMSTS_XOMR3ON_Pos) /*!< RMC_T::XOMSTS: XOMR3ON Mask */ 765 766 #define RMC_XOMSTS_XOMPEF_Pos (4) /*!< RMC_T::XOMSTS: XOMPEF Position */ 767 #define RMC_XOMSTS_XOMPEF_Msk (0x1ul << RMC_XOMSTS_XOMPEF_Pos) /*!< RMC_T::XOMSTS: XOMPEF Mask */ 768 769 #define RMC_APWPROT0_APPROEN0_Pos (0) /*!< RMC_T::APWPROT0: APPROEN0 Position */ 770 #define RMC_APWPROT0_APPROEN0_Msk (0x1ul << RMC_APWPROT0_APPROEN0_Pos) /*!< RMC_T::APWPROT0: APPROEN0 Mask */ 771 772 #define RMC_APWPROT0_APPROEN1_Pos (1) /*!< RMC_T::APWPROT0: APPROEN1 Position */ 773 #define RMC_APWPROT0_APPROEN1_Msk (0x1ul << RMC_APWPROT0_APPROEN1_Pos) /*!< RMC_T::APWPROT0: APPROEN1 Mask */ 774 775 #define RMC_APWPROT0_APPROEN2_Pos (2) /*!< RMC_T::APWPROT0: APPROEN2 Position */ 776 #define RMC_APWPROT0_APPROEN2_Msk (0x1ul << RMC_APWPROT0_APPROEN2_Pos) /*!< RMC_T::APWPROT0: APPROEN2 Mask */ 777 778 #define RMC_APWPROT0_APPROEN3_Pos (3) /*!< RMC_T::APWPROT0: APPROEN3 Position */ 779 #define RMC_APWPROT0_APPROEN3_Msk (0x1ul << RMC_APWPROT0_APPROEN3_Pos) /*!< RMC_T::APWPROT0: APPROEN3 Mask */ 780 781 #define RMC_APWPROT0_APPROEN4_Pos (4) /*!< RMC_T::APWPROT0: APPROEN4 Position */ 782 #define RMC_APWPROT0_APPROEN4_Msk (0x1ul << RMC_APWPROT0_APPROEN4_Pos) /*!< RMC_T::APWPROT0: APPROEN4 Mask */ 783 784 #define RMC_APWPROT0_APPROEN5_Pos (5) /*!< RMC_T::APWPROT0: APPROEN5 Position */ 785 #define RMC_APWPROT0_APPROEN5_Msk (0x1ul << RMC_APWPROT0_APPROEN5_Pos) /*!< RMC_T::APWPROT0: APPROEN5 Mask */ 786 787 #define RMC_APWPROT0_APPROEN6_Pos (6) /*!< RMC_T::APWPROT0: APPROEN6 Position */ 788 #define RMC_APWPROT0_APPROEN6_Msk (0x1ul << RMC_APWPROT0_APPROEN6_Pos) /*!< RMC_T::APWPROT0: APPROEN6 Mask */ 789 790 #define RMC_APWPROT0_APPROEN7_Pos (7) /*!< RMC_T::APWPROT0: APPROEN7 Position */ 791 #define RMC_APWPROT0_APPROEN7_Msk (0x1ul << RMC_APWPROT0_APPROEN7_Pos) /*!< RMC_T::APWPROT0: APPROEN7 Mask */ 792 793 #define RMC_APWPROT0_APPROEN8_Pos (8) /*!< RMC_T::APWPROT0: APPROEN8 Position */ 794 #define RMC_APWPROT0_APPROEN8_Msk (0x1ul << RMC_APWPROT0_APPROEN8_Pos) /*!< RMC_T::APWPROT0: APPROEN8 Mask */ 795 796 #define RMC_APWPROT0_APPROEN9_Pos (9) /*!< RMC_T::APWPROT0: APPROEN9 Position */ 797 #define RMC_APWPROT0_APPROEN9_Msk (0x1ul << RMC_APWPROT0_APPROEN9_Pos) /*!< RMC_T::APWPROT0: APPROEN9 Mask */ 798 799 #define RMC_APWPROT0_APPROEN10_Pos (10) /*!< RMC_T::APWPROT0: APPROEN10 Position */ 800 #define RMC_APWPROT0_APPROEN10_Msk (0x1ul << RMC_APWPROT0_APPROEN10_Pos) /*!< RMC_T::APWPROT0: APPROEN10 Mask */ 801 802 #define RMC_APWPROT0_APPROEN11_Pos (11) /*!< RMC_T::APWPROT0: APPROEN11 Position */ 803 #define RMC_APWPROT0_APPROEN11_Msk (0x1ul << RMC_APWPROT0_APPROEN11_Pos) /*!< RMC_T::APWPROT0: APPROEN11 Mask */ 804 805 #define RMC_APWPROT0_APPROEN12_Pos (12) /*!< RMC_T::APWPROT0: APPROEN12 Position */ 806 #define RMC_APWPROT0_APPROEN12_Msk (0x1ul << RMC_APWPROT0_APPROEN12_Pos) /*!< RMC_T::APWPROT0: APPROEN12 Mask */ 807 808 #define RMC_APWPROT0_APPROEN13_Pos (13) /*!< RMC_T::APWPROT0: APPROEN13 Position */ 809 #define RMC_APWPROT0_APPROEN13_Msk (0x1ul << RMC_APWPROT0_APPROEN13_Pos) /*!< RMC_T::APWPROT0: APPROEN13 Mask */ 810 811 #define RMC_APWPROT0_APPROEN14_Pos (14) /*!< RMC_T::APWPROT0: APPROEN14 Position */ 812 #define RMC_APWPROT0_APPROEN14_Msk (0x1ul << RMC_APWPROT0_APPROEN14_Pos) /*!< RMC_T::APWPROT0: APPROEN14 Mask */ 813 814 #define RMC_APWPROT0_APPROEN15_Pos (15) /*!< RMC_T::APWPROT0: APPROEN15 Position */ 815 #define RMC_APWPROT0_APPROEN15_Msk (0x1ul << RMC_APWPROT0_APPROEN15_Pos) /*!< RMC_T::APWPROT0: APPROEN15 Mask */ 816 817 #define RMC_APWPROT0_APPROEN16_Pos (16) /*!< RMC_T::APWPROT0: APPROEN16 Position */ 818 #define RMC_APWPROT0_APPROEN16_Msk (0x1ul << RMC_APWPROT0_APPROEN16_Pos) /*!< RMC_T::APWPROT0: APPROEN16 Mask */ 819 820 #define RMC_APWPROT0_APPROEN17_Pos (17) /*!< RMC_T::APWPROT0: APPROEN17 Position */ 821 #define RMC_APWPROT0_APPROEN17_Msk (0x1ul << RMC_APWPROT0_APPROEN17_Pos) /*!< RMC_T::APWPROT0: APPROEN17 Mask */ 822 823 #define RMC_APWPROT0_APPROEN18_Pos (18) /*!< RMC_T::APWPROT0: APPROEN18 Position */ 824 #define RMC_APWPROT0_APPROEN18_Msk (0x1ul << RMC_APWPROT0_APPROEN18_Pos) /*!< RMC_T::APWPROT0: APPROEN18 Mask */ 825 826 #define RMC_APWPROT0_APPROEN19_Pos (19) /*!< RMC_T::APWPROT0: APPROEN19 Position */ 827 #define RMC_APWPROT0_APPROEN19_Msk (0x1ul << RMC_APWPROT0_APPROEN19_Pos) /*!< RMC_T::APWPROT0: APPROEN19 Mask */ 828 829 #define RMC_APWPROT0_APPROEN20_Pos (20) /*!< RMC_T::APWPROT0: APPROEN20 Position */ 830 #define RMC_APWPROT0_APPROEN20_Msk (0x1ul << RMC_APWPROT0_APPROEN20_Pos) /*!< RMC_T::APWPROT0: APPROEN20 Mask */ 831 832 #define RMC_APWPROT0_APPROEN21_Pos (21) /*!< RMC_T::APWPROT0: APPROEN21 Position */ 833 #define RMC_APWPROT0_APPROEN21_Msk (0x1ul << RMC_APWPROT0_APPROEN21_Pos) /*!< RMC_T::APWPROT0: APPROEN21 Mask */ 834 835 #define RMC_APWPROT0_APPROEN22_Pos (22) /*!< RMC_T::APWPROT0: APPROEN22 Position */ 836 #define RMC_APWPROT0_APPROEN22_Msk (0x1ul << RMC_APWPROT0_APPROEN22_Pos) /*!< RMC_T::APWPROT0: APPROEN22 Mask */ 837 838 #define RMC_APWPROT0_APPROEN23_Pos (23) /*!< RMC_T::APWPROT0: APPROEN23 Position */ 839 #define RMC_APWPROT0_APPROEN23_Msk (0x1ul << RMC_APWPROT0_APPROEN23_Pos) /*!< RMC_T::APWPROT0: APPROEN23 Mask */ 840 841 #define RMC_APWPROT0_APPROEN24_Pos (24) /*!< RMC_T::APWPROT0: APPROEN24 Position */ 842 #define RMC_APWPROT0_APPROEN24_Msk (0x1ul << RMC_APWPROT0_APPROEN24_Pos) /*!< RMC_T::APWPROT0: APPROEN24 Mask */ 843 844 #define RMC_APWPROT0_APPROEN25_Pos (25) /*!< RMC_T::APWPROT0: APPROEN25 Position */ 845 #define RMC_APWPROT0_APPROEN25_Msk (0x1ul << RMC_APWPROT0_APPROEN25_Pos) /*!< RMC_T::APWPROT0: APPROEN25 Mask */ 846 847 #define RMC_APWPROT0_APPROEN26_Pos (26) /*!< RMC_T::APWPROT0: APPROEN26 Position */ 848 #define RMC_APWPROT0_APPROEN26_Msk (0x1ul << RMC_APWPROT0_APPROEN26_Pos) /*!< RMC_T::APWPROT0: APPROEN26 Mask */ 849 850 #define RMC_APWPROT0_APPROEN27_Pos (27) /*!< RMC_T::APWPROT0: APPROEN27 Position */ 851 #define RMC_APWPROT0_APPROEN27_Msk (0x1ul << RMC_APWPROT0_APPROEN27_Pos) /*!< RMC_T::APWPROT0: APPROEN27 Mask */ 852 853 #define RMC_APWPROT0_APPROEN28_Pos (28) /*!< RMC_T::APWPROT0: APPROEN28 Position */ 854 #define RMC_APWPROT0_APPROEN28_Msk (0x1ul << RMC_APWPROT0_APPROEN28_Pos) /*!< RMC_T::APWPROT0: APPROEN28 Mask */ 855 856 #define RMC_APWPROT0_APPROEN29_Pos (29) /*!< RMC_T::APWPROT0: APPROEN29 Position */ 857 #define RMC_APWPROT0_APPROEN29_Msk (0x1ul << RMC_APWPROT0_APPROEN29_Pos) /*!< RMC_T::APWPROT0: APPROEN29 Mask */ 858 859 #define RMC_APWPROT0_APPROEN30_Pos (30) /*!< RMC_T::APWPROT0: APPROEN30 Position */ 860 #define RMC_APWPROT0_APPROEN30_Msk (0x1ul << RMC_APWPROT0_APPROEN30_Pos) /*!< RMC_T::APWPROT0: APPROEN30 Mask */ 861 862 #define RMC_APWPROT0_APPROEN31_Pos (31) /*!< RMC_T::APWPROT0: APPROEN31 Position */ 863 #define RMC_APWPROT0_APPROEN31_Msk (0x1ul << RMC_APWPROT0_APPROEN31_Pos) /*!< RMC_T::APWPROT0: APPROEN31 Mask */ 864 865 #define RMC_APWPROT1_APPROEN32_Pos (0) /*!< RMC_T::APWPROT1: APPROEN32 Position */ 866 #define RMC_APWPROT1_APPROEN32_Msk (0x1ul << RMC_APWPROT1_APPROEN32_Pos) /*!< RMC_T::APWPROT1: APPROEN32 Mask */ 867 868 #define RMC_APWPROT1_APPROEN33_Pos (1) /*!< RMC_T::APWPROT1: APPROEN33 Position */ 869 #define RMC_APWPROT1_APPROEN33_Msk (0x1ul << RMC_APWPROT1_APPROEN33_Pos) /*!< RMC_T::APWPROT1: APPROEN33 Mask */ 870 871 #define RMC_APWPROT1_APPROEN34_Pos (2) /*!< RMC_T::APWPROT1: APPROEN34 Position */ 872 #define RMC_APWPROT1_APPROEN34_Msk (0x1ul << RMC_APWPROT1_APPROEN34_Pos) /*!< RMC_T::APWPROT1: APPROEN34 Mask */ 873 874 #define RMC_APWPROT1_APPROEN35_Pos (3) /*!< RMC_T::APWPROT1: APPROEN35 Position */ 875 #define RMC_APWPROT1_APPROEN35_Msk (0x1ul << RMC_APWPROT1_APPROEN35_Pos) /*!< RMC_T::APWPROT1: APPROEN35 Mask */ 876 877 #define RMC_APWPROT1_APPROEN36_Pos (4) /*!< RMC_T::APWPROT1: APPROEN36 Position */ 878 #define RMC_APWPROT1_APPROEN36_Msk (0x1ul << RMC_APWPROT1_APPROEN36_Pos) /*!< RMC_T::APWPROT1: APPROEN36 Mask */ 879 880 #define RMC_APWPROT1_APPROEN37_Pos (5) /*!< RMC_T::APWPROT1: APPROEN37 Position */ 881 #define RMC_APWPROT1_APPROEN37_Msk (0x1ul << RMC_APWPROT1_APPROEN37_Pos) /*!< RMC_T::APWPROT1: APPROEN37 Mask */ 882 883 #define RMC_APWPROT1_APPROEN38_Pos (6) /*!< RMC_T::APWPROT1: APPROEN38 Position */ 884 #define RMC_APWPROT1_APPROEN38_Msk (0x1ul << RMC_APWPROT1_APPROEN38_Pos) /*!< RMC_T::APWPROT1: APPROEN38 Mask */ 885 886 #define RMC_APWPROT1_APPROEN39_Pos (7) /*!< RMC_T::APWPROT1: APPROEN39 Position */ 887 #define RMC_APWPROT1_APPROEN39_Msk (0x1ul << RMC_APWPROT1_APPROEN39_Pos) /*!< RMC_T::APWPROT1: APPROEN39 Mask */ 888 889 #define RMC_APWPROT1_APPROEN40_Pos (8) /*!< RMC_T::APWPROT1: APPROEN40 Position */ 890 #define RMC_APWPROT1_APPROEN40_Msk (0x1ul << RMC_APWPROT1_APPROEN40_Pos) /*!< RMC_T::APWPROT1: APPROEN40 Mask */ 891 892 #define RMC_APWPROT1_APPROEN41_Pos (9) /*!< RMC_T::APWPROT1: APPROEN41 Position */ 893 #define RMC_APWPROT1_APPROEN41_Msk (0x1ul << RMC_APWPROT1_APPROEN41_Pos) /*!< RMC_T::APWPROT1: APPROEN41 Mask */ 894 895 #define RMC_APWPROT1_APPROEN42_Pos (10) /*!< RMC_T::APWPROT1: APPROEN42 Position */ 896 #define RMC_APWPROT1_APPROEN42_Msk (0x1ul << RMC_APWPROT1_APPROEN42_Pos) /*!< RMC_T::APWPROT1: APPROEN42 Mask */ 897 898 #define RMC_APWPROT1_APPROEN43_Pos (11) /*!< RMC_T::APWPROT1: APPROEN43 Position */ 899 #define RMC_APWPROT1_APPROEN43_Msk (0x1ul << RMC_APWPROT1_APPROEN43_Pos) /*!< RMC_T::APWPROT1: APPROEN43 Mask */ 900 901 #define RMC_APWPROT1_APPROEN44_Pos (12) /*!< RMC_T::APWPROT1: APPROEN44 Position */ 902 #define RMC_APWPROT1_APPROEN44_Msk (0x1ul << RMC_APWPROT1_APPROEN44_Pos) /*!< RMC_T::APWPROT1: APPROEN44 Mask */ 903 904 #define RMC_APWPROT1_APPROEN45_Pos (13) /*!< RMC_T::APWPROT1: APPROEN45 Position */ 905 #define RMC_APWPROT1_APPROEN45_Msk (0x1ul << RMC_APWPROT1_APPROEN45_Pos) /*!< RMC_T::APWPROT1: APPROEN45 Mask */ 906 907 #define RMC_APWPROT1_APPROEN46_Pos (14) /*!< RMC_T::APWPROT1: APPROEN46 Position */ 908 #define RMC_APWPROT1_APPROEN46_Msk (0x1ul << RMC_APWPROT1_APPROEN46_Pos) /*!< RMC_T::APWPROT1: APPROEN46 Mask */ 909 910 #define RMC_APWPROT1_APPROEN47_Pos (15) /*!< RMC_T::APWPROT1: APPROEN47 Position */ 911 #define RMC_APWPROT1_APPROEN47_Msk (0x1ul << RMC_APWPROT1_APPROEN47_Pos) /*!< RMC_T::APWPROT1: APPROEN47 Mask */ 912 913 #define RMC_APWPROT1_APPROEN48_Pos (16) /*!< RMC_T::APWPROT1: APPROEN48 Position */ 914 #define RMC_APWPROT1_APPROEN48_Msk (0x1ul << RMC_APWPROT1_APPROEN48_Pos) /*!< RMC_T::APWPROT1: APPROEN48 Mask */ 915 916 #define RMC_APWPROT1_APPROEN49_Pos (17) /*!< RMC_T::APWPROT1: APPROEN49 Position */ 917 #define RMC_APWPROT1_APPROEN49_Msk (0x1ul << RMC_APWPROT1_APPROEN49_Pos) /*!< RMC_T::APWPROT1: APPROEN49 Mask */ 918 919 #define RMC_APWPROT1_APPROEN50_Pos (18) /*!< RMC_T::APWPROT1: APPROEN50 Position */ 920 #define RMC_APWPROT1_APPROEN50_Msk (0x1ul << RMC_APWPROT1_APPROEN50_Pos) /*!< RMC_T::APWPROT1: APPROEN50 Mask */ 921 922 #define RMC_APWPROT1_APPROEN51_Pos (19) /*!< RMC_T::APWPROT1: APPROEN51 Position */ 923 #define RMC_APWPROT1_APPROEN51_Msk (0x1ul << RMC_APWPROT1_APPROEN51_Pos) /*!< RMC_T::APWPROT1: APPROEN51 Mask */ 924 925 #define RMC_APWPROT1_APPROEN52_Pos (20) /*!< RMC_T::APWPROT1: APPROEN52 Position */ 926 #define RMC_APWPROT1_APPROEN52_Msk (0x1ul << RMC_APWPROT1_APPROEN52_Pos) /*!< RMC_T::APWPROT1: APPROEN52 Mask */ 927 928 #define RMC_APWPROT1_APPROEN53_Pos (21) /*!< RMC_T::APWPROT1: APPROEN53 Position */ 929 #define RMC_APWPROT1_APPROEN53_Msk (0x1ul << RMC_APWPROT1_APPROEN53_Pos) /*!< RMC_T::APWPROT1: APPROEN53 Mask */ 930 931 #define RMC_APWPROT1_APPROEN54_Pos (22) /*!< RMC_T::APWPROT1: APPROEN54 Position */ 932 #define RMC_APWPROT1_APPROEN54_Msk (0x1ul << RMC_APWPROT1_APPROEN54_Pos) /*!< RMC_T::APWPROT1: APPROEN54 Mask */ 933 934 #define RMC_APWPROT1_APPROEN55_Pos (23) /*!< RMC_T::APWPROT1: APPROEN55 Position */ 935 #define RMC_APWPROT1_APPROEN55_Msk (0x1ul << RMC_APWPROT1_APPROEN55_Pos) /*!< RMC_T::APWPROT1: APPROEN55 Mask */ 936 937 #define RMC_APWPROT1_APPROEN56_Pos (24) /*!< RMC_T::APWPROT1: APPROEN56 Position */ 938 #define RMC_APWPROT1_APPROEN56_Msk (0x1ul << RMC_APWPROT1_APPROEN56_Pos) /*!< RMC_T::APWPROT1: APPROEN56 Mask */ 939 940 #define RMC_APWPROT1_APPROEN57_Pos (25) /*!< RMC_T::APWPROT1: APPROEN57 Position */ 941 #define RMC_APWPROT1_APPROEN57_Msk (0x1ul << RMC_APWPROT1_APPROEN57_Pos) /*!< RMC_T::APWPROT1: APPROEN57 Mask */ 942 943 #define RMC_APWPROT1_APPROEN58_Pos (26) /*!< RMC_T::APWPROT1: APPROEN58 Position */ 944 #define RMC_APWPROT1_APPROEN58_Msk (0x1ul << RMC_APWPROT1_APPROEN58_Pos) /*!< RMC_T::APWPROT1: APPROEN58 Mask */ 945 946 #define RMC_APWPROT1_APPROEN59_Pos (27) /*!< RMC_T::APWPROT1: APPROEN59 Position */ 947 #define RMC_APWPROT1_APPROEN59_Msk (0x1ul << RMC_APWPROT1_APPROEN59_Pos) /*!< RMC_T::APWPROT1: APPROEN59 Mask */ 948 949 #define RMC_APWPROT1_APPROEN60_Pos (28) /*!< RMC_T::APWPROT1: APPROEN60 Position */ 950 #define RMC_APWPROT1_APPROEN60_Msk (0x1ul << RMC_APWPROT1_APPROEN60_Pos) /*!< RMC_T::APWPROT1: APPROEN60 Mask */ 951 952 #define RMC_APWPROT1_APPROEN61_Pos (29) /*!< RMC_T::APWPROT1: APPROEN61 Position */ 953 #define RMC_APWPROT1_APPROEN61_Msk (0x1ul << RMC_APWPROT1_APPROEN61_Pos) /*!< RMC_T::APWPROT1: APPROEN61 Mask */ 954 955 #define RMC_APWPROT1_APPROEN62_Pos (30) /*!< RMC_T::APWPROT1: APPROEN62 Position */ 956 #define RMC_APWPROT1_APPROEN62_Msk (0x1ul << RMC_APWPROT1_APPROEN62_Pos) /*!< RMC_T::APWPROT1: APPROEN62 Mask */ 957 958 #define RMC_APWPROT1_APPROEN63_Pos (31) /*!< RMC_T::APWPROT1: APPROEN63 Position */ 959 #define RMC_APWPROT1_APPROEN63_Msk (0x1ul << RMC_APWPROT1_APPROEN63_Pos) /*!< RMC_T::APWPROT1: APPROEN63 Mask */ 960 961 #define RMC_APWPKEEP_APWPKEEP0_Pos (0) /*!< RMC_T::APWPKEEP: APWPKEEP0 Position */ 962 #define RMC_APWPKEEP_APWPKEEP0_Msk (0xfffful << RMC_APWPKEEP_APWPKEEP0_Pos) /*!< RMC_T::APWPKEEP: APWPKEEP0 Mask */ 963 964 #define RMC_APWPKEEP_APWPKEEP1_Pos (16) /*!< RMC_T::APWPKEEP: APWPKEEP1 Position */ 965 #define RMC_APWPKEEP_APWPKEEP1_Msk (0xfffful << RMC_APWPKEEP_APWPKEEP1_Pos) /*!< RMC_T::APWPKEEP: APWPKEEP1 Mask */ 966 967 #define RMC_SCACT_SCACT_Pos (0) /*!< RMC_T::SCACT: SCACT Position */ 968 #define RMC_SCACT_SCACT_Msk (0x1ul << RMC_SCACT_SCACT_Pos) /*!< RMC_T::SCACT: SCACT Mask */ 969 970 /**@}*/ /* RMC_CONST */ 971 /**@}*/ /* end of RMC register group */ 972 973 974 /**@}*/ /* end of REGISTER group */ 975
