1 /**************************************************************************//**
2 * @file SYS.h
3 * @version V3.0
4 * @brief M480 Series SYS Driver Header File
5 *
6 * SPDX-License-Identifier: Apache-2.0
7 * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
8 ******************************************************************************/
9
10 #ifndef __SYS_H__
11 #define __SYS_H__
12
13 #ifdef __cplusplus
14 extern "C"
15 {
16 #endif
17
18
19 /** @addtogroup Standard_Driver Standard Driver
20 @{
21 */
22
23 /** @addtogroup SYS_Driver SYS Driver
24 @{
25 */
26
27 /** @addtogroup SYS_EXPORTED_CONSTANTS SYS Exported Constants
28 @{
29 */
30
31
32 /*---------------------------------------------------------------------------------------------------------*/
33 /* Module Reset Control Resister constant definitions. */
34 /*---------------------------------------------------------------------------------------------------------*/
35 #define PDMA_RST ((0UL<<24) | SYS_IPRST0_PDMARST_Pos) /*!< Reset PDMA \hideinitializer*/
36 #define EBI_RST ((0UL<<24) | SYS_IPRST0_EBIRST_Pos) /*!< Reset EBI \hideinitializer*/
37 #define EMAC_RST ((0UL<<24) | SYS_IPRST0_EMACRST_Pos) /*!< Reset EMAC \hideinitializer */
38 #define SDH0_RST ((0UL<<24) | SYS_IPRST0_SDH0RST_Pos) /*!< Reset SDH0 \hideinitializer */
39 #define CRC_RST ((0UL<<24) | SYS_IPRST0_CRCRST_Pos) /*!< Reset CRC \hideinitializer */
40 #define CCAP_RST ((0UL<<24) | SYS_IPRST0_CCAPRST_Pos) /*!< Reset ICAP \hideinitializer */
41 #define HSUSBD_RST ((0UL<<24) | SYS_IPRST0_HSUSBDRST_Pos) /*!< Reset HSUSBD \hideinitializer */
42 #define CRPT_RST ((0UL<<24) | SYS_IPRST0_CRPTRST_Pos) /*!< Reset CRPT \hideinitializer */
43 #define SPIM_RST ((0UL<<24) | SYS_IPRST0_SPIMRST_Pos) /*!< Reset SPIM \hideinitializer */
44 #define USBH_RST ((0UL<<24) | SYS_IPRST0_USBHRST_Pos) /*!< Reset USBH \hideinitializer */
45 #define SDH1_RST ((0UL<<24) | SYS_IPRST0_SDH1RST_Pos) /*!< Reset SDH1 \hideinitializer */
46
47 #define GPIO_RST ((4UL<<24) | SYS_IPRST1_GPIORST_Pos) /*!< Reset GPIO \hideinitializer */
48 #define TMR0_RST ((4UL<<24) | SYS_IPRST1_TMR0RST_Pos) /*!< Reset TMR0 \hideinitializer */
49 #define TMR1_RST ((4UL<<24) | SYS_IPRST1_TMR1RST_Pos) /*!< Reset TMR1 \hideinitializer */
50 #define TMR2_RST ((4UL<<24) | SYS_IPRST1_TMR2RST_Pos) /*!< Reset TMR2 \hideinitializer */
51 #define TMR3_RST ((4UL<<24) | SYS_IPRST1_TMR3RST_Pos) /*!< Reset TMR3 \hideinitializer */
52 #define ACMP01_RST ((4UL<<24) | SYS_IPRST1_ACMP01RST_Pos) /*!< Reset ACMP01 \hideinitializer */
53 #define I2C0_RST ((4UL<<24) | SYS_IPRST1_I2C0RST_Pos) /*!< Reset I2C0 \hideinitializer */
54 #define I2C1_RST ((4UL<<24) | SYS_IPRST1_I2C1RST_Pos) /*!< Reset I2C1 \hideinitializer */
55 #define I2C2_RST ((4UL<<24) | SYS_IPRST1_I2C2RST_Pos) /*!< Reset I2C2 \hideinitializer */
56 #define QSPI0_RST ((4UL<<24) | SYS_IPRST1_QSPI0RST_Pos) /*!< Reset QSPI0 \hideinitializer */
57 #define SPI0_RST ((4UL<<24) | SYS_IPRST1_SPI0RST_Pos) /*!< Reset SPI0 \hideinitializer */
58 #define SPI1_RST ((4UL<<24) | SYS_IPRST1_SPI1RST_Pos) /*!< Reset SPI1 \hideinitializer */
59 #define SPI2_RST ((4UL<<24) | SYS_IPRST1_SPI2RST_Pos) /*!< Reset SPI2 \hideinitializer */
60 #define UART0_RST ((4UL<<24) | SYS_IPRST1_UART0RST_Pos) /*!< Reset UART0 \hideinitializer */
61 #define UART1_RST ((4UL<<24) | SYS_IPRST1_UART1RST_Pos) /*!< Reset UART1 \hideinitializer */
62 #define UART2_RST ((4UL<<24) | SYS_IPRST1_UART2RST_Pos) /*!< Reset UART2 \hideinitializer */
63 #define UART3_RST ((4UL<<24) | SYS_IPRST1_UART3RST_Pos) /*!< Reset UART3 \hideinitializer */
64 #define UART4_RST ((4UL<<24) | SYS_IPRST1_UART4RST_Pos) /*!< Reset UART4 \hideinitializer */
65 #define UART5_RST ((4UL<<24) | SYS_IPRST1_UART5RST_Pos) /*!< Reset UART5 \hideinitializer */
66 #define UART6_RST ((4UL<<24) | SYS_IPRST1_UART6RST_Pos) /*!< Reset UART6 \hideinitializer */
67 #define UART7_RST ((4UL<<24) | SYS_IPRST1_UART7RST_Pos) /*!< Reset UART7 \hideinitializer */
68 #define CAN0_RST ((4UL<<24) | SYS_IPRST1_CAN0RST_Pos) /*!< Reset CAN0 \hideinitializer */
69 #define CAN1_RST ((4UL<<24) | SYS_IPRST1_CAN1RST_Pos) /*!< Reset CAN1 \hideinitializer */
70 #define OTG_RST ((4UL<<24) | SYS_IPRST1_OTGRST_Pos) /*!< Reset OTG \hideinitializer */
71 #define USBD_RST ((4UL<<24) | SYS_IPRST1_USBDRST_Pos) /*!< Reset USBD \hideinitializer */
72 #define EADC_RST ((4UL<<24) | SYS_IPRST1_EADCRST_Pos) /*!< Reset EADC \hideinitializer */
73 #define I2S0_RST ((4UL<<24) | SYS_IPRST1_I2S0RST_Pos) /*!< Reset I2S0 \hideinitializer */
74 #define HSOTG_RST ((4UL<<24) | SYS_IPRST1_HSOTGRST_Pos) /*!< Reset HSOTG \hideinitializer */
75 #define TRNG_RST ((4UL<<24) | SYS_IPRST1_TRNGRST_Pos) /*!< Reset TRNG \hideinitializer */
76
77 #define SC0_RST ((8UL<<24) | SYS_IPRST2_SC0RST_Pos) /*!< Reset SC0 \hideinitializer */
78 #define SC1_RST ((8UL<<24) | SYS_IPRST2_SC1RST_Pos) /*!< Reset SC1 \hideinitializer */
79 #define SC2_RST ((8UL<<24) | SYS_IPRST2_SC2RST_Pos) /*!< Reset SC2 \hideinitializer */
80 #define QSPI1_RST ((8UL<<24) | SYS_IPRST2_QSPI1RST_Pos) /*!< Reset QSPI1 \hideinitializer */
81 #define SPI3_RST ((8UL<<24) | SYS_IPRST2_SPI3RST_Pos) /*!< Reset SPI3 \hideinitializer */
82 #define USCI0_RST ((8UL<<24) | SYS_IPRST2_USCI0RST_Pos) /*!< Reset USCI0 \hideinitializer */
83 #define USCI1_RST ((8UL<<24) | SYS_IPRST2_USCI1RST_Pos) /*!< Reset USCI1 \hideinitializer */
84 #define DAC_RST ((8UL<<24) | SYS_IPRST2_DACRST_Pos) /*!< Reset DAC \hideinitializer */
85 #define EPWM0_RST ((8UL<<24) | SYS_IPRST2_EPWM0RST_Pos) /*!< Reset EPWM0 \hideinitializer */
86 #define EPWM1_RST ((8UL<<24) | SYS_IPRST2_EPWM1RST_Pos) /*!< Reset EPWM1 \hideinitializer */
87 #define BPWM0_RST ((8UL<<24) | SYS_IPRST2_BPWM0RST_Pos) /*!< Reset BPWM0 \hideinitializer */
88 #define BPWM1_RST ((8UL<<24) | SYS_IPRST2_BPWM1RST_Pos) /*!< Reset BPWM1 \hideinitializer */
89 #define QEI0_RST ((8UL<<24) | SYS_IPRST2_QEI0RST_Pos) /*!< Reset QEI0 \hideinitializer */
90 #define QEI1_RST ((8UL<<24) | SYS_IPRST2_QEI1RST_Pos) /*!< Reset QEI1 \hideinitializer */
91 #define ECAP0_RST ((8UL<<24) | SYS_IPRST2_ECAP0RST_Pos) /*!< Reset ECAP0 \hideinitializer */
92 #define ECAP1_RST ((8UL<<24) | SYS_IPRST2_ECAP1RST_Pos) /*!< Reset ECAP1 \hideinitializer */
93 #define CAN2_RST ((8UL<<24) | SYS_IPRST2_CAN2RST_Pos) /*!< Reset CAN2 \hideinitializer */
94 #define OPA_RST ((8UL<<24) | SYS_IPRST2_OPARST_Pos) /*!< Reset OPA \hideinitializer */
95 #define EADC1_RST ((8UL<<24) | SYS_IPRST2_EADC1RST_Pos) /*!< Reset EADC1 \hideinitializer */
96
97 /*---------------------------------------------------------------------------------------------------------*/
98 /* Brown Out Detector Threshold Voltage Selection constant definitions. */
99 /*---------------------------------------------------------------------------------------------------------*/
100 #define SYS_BODCTL_BOD_RST_EN (1UL << SYS_BODCTL_BODRSTEN_Pos) /*!< Brown-out Reset Enable \hideinitializer */
101 #define SYS_BODCTL_BOD_INTERRUPT_EN (0UL << SYS_BODCTL_BODRSTEN_Pos) /*!< Brown-out Interrupt Enable \hideinitializer */
102 #define SYS_BODCTL_BODVL_3_0V (7UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 3.0V \hideinitializer */
103 #define SYS_BODCTL_BODVL_2_8V (6UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.8V \hideinitializer */
104 #define SYS_BODCTL_BODVL_2_6V (5UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.6V \hideinitializer */
105 #define SYS_BODCTL_BODVL_2_4V (4UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.4V \hideinitializer */
106 #define SYS_BODCTL_BODVL_2_2V (3UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.2V \hideinitializer */
107 #define SYS_BODCTL_BODVL_2_0V (2UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.0V \hideinitializer */
108 #define SYS_BODCTL_BODVL_1_8V (1UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 1.8V \hideinitializer */
109 #define SYS_BODCTL_BODVL_1_6V (0UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 1.6V \hideinitializer */
110
111
112 /*---------------------------------------------------------------------------------------------------------*/
113 /* VREFCTL constant definitions. (Write-Protection Register) */
114 /*---------------------------------------------------------------------------------------------------------*/
115 #define SYS_VREFCTL_VREF_PIN (0x0UL << SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = Vref pin \hideinitializer */
116 #define SYS_VREFCTL_VREF_1_6V (0x3UL << SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = 1.6V \hideinitializer */
117 #define SYS_VREFCTL_VREF_2_0V (0x7UL << SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = 2.0V \hideinitializer */
118 #define SYS_VREFCTL_VREF_2_5V (0xBUL << SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = 2.5V \hideinitializer */
119 #define SYS_VREFCTL_VREF_3_0V (0xFUL << SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = 3.0V \hideinitializer */
120 #define SYS_VREFCTL_VREF_AVDD (0x10UL << SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = AVDD \hideinitializer */
121
122
123 /*---------------------------------------------------------------------------------------------------------*/
124 /* USBPHY constant definitions. (Write-Protection Register) */
125 /*---------------------------------------------------------------------------------------------------------*/
126 #define SYS_USBPHY_USBROLE_STD_USBD (0x0UL << SYS_USBPHY_USBROLE_Pos) /*!< Standard USB device \hideinitializer */
127 #define SYS_USBPHY_USBROLE_STD_USBH (0x1UL << SYS_USBPHY_USBROLE_Pos) /*!< Standard USB host \hideinitializer */
128 #define SYS_USBPHY_USBROLE_ID_DEPH (0x2UL << SYS_USBPHY_USBROLE_Pos) /*!< ID dependent device \hideinitializer */
129 #define SYS_USBPHY_USBROLE_ON_THE_GO (0x3UL << SYS_USBPHY_USBROLE_Pos) /*!< On-The-Go device \hideinitializer */
130 #define SYS_USBPHY_HSUSBROLE_STD_USBD (0x0UL << SYS_USBPHY_HSUSBROLE_Pos) /*!< Standard HSUSB device \hideinitializer */
131 #define SYS_USBPHY_HSUSBROLE_STD_USBH (0x1UL << SYS_USBPHY_HSUSBROLE_Pos) /*!< Standard HSUSB host \hideinitializer */
132 #define SYS_USBPHY_HSUSBROLE_ID_DEPH (0x2UL << SYS_USBPHY_HSUSBROLE_Pos) /*!< ID dependent device \hideinitializer */
133
134 /*---------------------------------------------------------------------------------------------------------*/
135 /* PLCTL constant definitions. (Write-Protection Register) */
136 /*---------------------------------------------------------------------------------------------------------*/
137 #define SYS_PLCTL_PLSEL_PL0 (0x0UL<<SYS_PLCTL_PLSEL_Pos) /*!< Set power level to power level 0 */
138 #define SYS_PLCTL_PLSEL_PL1 (0x1UL<<SYS_PLCTL_PLSEL_Pos) /*!< Set power level to power level 1 */
139
140
141 /*---------------------------------------------------------------------------------------------------------*/
142 /* Multi-Function constant definitions. */
143 /*---------------------------------------------------------------------------------------------------------*/
144 /* How to use below #define?
145 Example 1: If user want to set PA.0 as SC0_CLK in initial function,
146 user can issue following command to achieve it.
147
148 SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SYS_GPA_MFPL_PA0MFP_Msk) ) | SYS_GPA_MFPL_PA0_MFP_SC0_CLK ;
149
150 */
151 /********************* Bit definition of GPA_MFPL register **********************/
152 #define SYS_GPA_MFPL_PA0MFP_GPIO (0x00UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
153 #define SYS_GPA_MFPL_PA0MFP_SPIM_MOSI (0x02UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< 1st SPIM MOSI (Master Out, Slave In) pin. \hideinitializer */
154 #define SYS_GPA_MFPL_PA0MFP_QSPI0_MOSI0 (0x03UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< 1st QSPI0 MOSI (Master Out, Slave In) pin. \hideinitializer */
155 #define SYS_GPA_MFPL_PA0MFP_SPI0_MOSI (0x04UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< 1st SPI0 MOSI (Master Out, Slave In) pin. \hideinitializer */
156 #define SYS_GPA_MFPL_PA0MFP_SD1_DAT0 (0x05UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< SD/SDIO 1 data line bit 0. \hideinitializer */
157 #define SYS_GPA_MFPL_PA0MFP_SC0_CLK (0x06UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< SmartCard0 clock pin. \hideinitializer */
158 #define SYS_GPA_MFPL_PA0MFP_UART0_RXD (0x07UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< Data receiver input pin for UART0. \hideinitializer */
159 #define SYS_GPA_MFPL_PA0MFP_UART1_nRTS (0x08UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< Request to Send output pin for UART1. \hideinitializer */
160 #define SYS_GPA_MFPL_PA0MFP_I2C2_SDA (0x09UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< I2C2 data input/output pin. \hideinitializer */
161 #define SYS_GPA_MFPL_PA0MFP_CCAP_DATA6 (0x0AUL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< Sensor pixel data6 input pin. \hideinitializer */
162 #define SYS_GPA_MFPL_PA0MFP_BPWM0_CH0 (0x0CUL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< BPWM0 channel0 output/capture input. \hideinitializer */
163 #define SYS_GPA_MFPL_PA0MFP_EPWM0_CH5 (0x0DUL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< EPWM0 channel5 output/capture input. \hideinitializer */
164 #define SYS_GPA_MFPL_PA0MFP_DAC0_ST (0x0FUL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< DAC0 external trigger input. \hideinitializer */
165 #define SYS_GPA_MFPL_PA1MFP_GPIO (0x00UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
166 #define SYS_GPA_MFPL_PA1MFP_SPIM_MISO (0x02UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< 1st SPIM MISO (Master In, Slave Out) pin. \hideinitializer */
167 #define SYS_GPA_MFPL_PA1MFP_QSPI0_MISO0 (0x03UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< 1st QSPI0 MISO (Master In, Slave Out) pin. \hideinitializer */
168 #define SYS_GPA_MFPL_PA1MFP_SPI0_MISO (0x04UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< 1st SPI0 MISO (Master In, Slave Out) pin. \hideinitializer */
169 #define SYS_GPA_MFPL_PA1MFP_SD1_DAT1 (0x05UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< SD/SDIO 1 data line bit 1. \hideinitializer */
170 #define SYS_GPA_MFPL_PA1MFP_SC0_DAT (0x06UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< SmartCard0 data pin. \hideinitializer */
171 #define SYS_GPA_MFPL_PA1MFP_UART0_TXD (0x07UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< Data transmitter output pin for UART0. \hideinitializer */
172 #define SYS_GPA_MFPL_PA1MFP_UART1_nCTS (0x08UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< Clear to Send input pin for UART1. \hideinitializer */
173 #define SYS_GPA_MFPL_PA1MFP_I2C2_SCL (0x09UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< I2C2 clock pin. \hideinitializer */
174 #define SYS_GPA_MFPL_PA1MFP_CCAP_DATA7 (0x0AUL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< Sensor pixel data7 input pin. \hideinitializer */
175 #define SYS_GPA_MFPL_PA1MFP_BPWM0_CH1 (0x0CUL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< BPWM0 channel1 output/capture input. \hideinitializer */
176 #define SYS_GPA_MFPL_PA1MFP_EPWM0_CH4 (0x0DUL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< EPWM0 channel4 output/capture input. \hideinitializer */
177 #define SYS_GPA_MFPL_PA1MFP_DAC1_ST (0x0FUL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< DAC1 external trigger input. \hideinitializer */
178 #define SYS_GPA_MFPL_PA2MFP_GPIO (0x00UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
179 #define SYS_GPA_MFPL_PA2MFP_SPIM_CLK (0x02UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< SPIM serial clock pin. \hideinitializer */
180 #define SYS_GPA_MFPL_PA2MFP_QSPI0_CLK (0x03UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< QSPI0 serial clock pin. \hideinitializer */
181 #define SYS_GPA_MFPL_PA2MFP_SPI0_CLK (0x04UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< SPI0 serial clock pin. \hideinitializer */
182 #define SYS_GPA_MFPL_PA2MFP_SD1_DAT2 (0x05UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< SD/SDIO 1 data line bit 2. \hideinitializer */
183 #define SYS_GPA_MFPL_PA2MFP_SC0_RST (0x06UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< SmartCard0 reset pin. \hideinitializer */
184 #define SYS_GPA_MFPL_PA2MFP_UART4_RXD (0x07UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< Data receiver input pin for UART4. \hideinitializer */
185 #define SYS_GPA_MFPL_PA2MFP_UART1_RXD (0x08UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< Data receiver input pin for UART1. \hideinitializer */
186 #define SYS_GPA_MFPL_PA2MFP_I2C1_SDA (0x09UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< I2C1 data input/output pin. \hideinitializer */
187 #define SYS_GPA_MFPL_PA2MFP_I2C0_SMBSUS (0x0AUL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< I2C0 SMBus SMBSUS# pin (PMBus CONTROL pin) \hideinitializer */
188 #define SYS_GPA_MFPL_PA2MFP_BPWM0_CH2 (0x0CUL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< BPWM0 channel2 output/capture input. \hideinitializer */
189 #define SYS_GPA_MFPL_PA2MFP_EPWM0_CH3 (0x0DUL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< EPWM0 channel3 output/capture input. \hideinitializer */
190 #define SYS_GPA_MFPL_PA3MFP_GPIO (0x00UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
191 #define SYS_GPA_MFPL_PA3MFP_SPIM_SS (0x02UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< 1st SPIM slave select pin. \hideinitializer */
192 #define SYS_GPA_MFPL_PA3MFP_QSPI0_SS (0x03UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< 1st QSPI0 slave select pin. \hideinitializer */
193 #define SYS_GPA_MFPL_PA3MFP_SPI0_SS (0x04UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< 1st SPI0 slave select pin. \hideinitializer */
194 #define SYS_GPA_MFPL_PA3MFP_SD1_DAT3 (0x05UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< SD/SDIO 1 data line bit 3. \hideinitializer */
195 #define SYS_GPA_MFPL_PA3MFP_SC0_PWR (0x06UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< SmartCard0 power pin. \hideinitializer */
196 #define SYS_GPA_MFPL_PA3MFP_UART4_TXD (0x07UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< Data transmitter output pin for UART4. \hideinitializer */
197 #define SYS_GPA_MFPL_PA3MFP_UART1_TXD (0x08UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< Data transmitter output pin for UART1. \hideinitializer */
198 #define SYS_GPA_MFPL_PA3MFP_I2C1_SCL (0x09UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< I2C1 clock pin. \hideinitializer */
199 #define SYS_GPA_MFPL_PA3MFP_I2C0_SMBAL (0x0AUL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< I2C0 SMBus SMBALTER# pin. \hideinitializer */
200 #define SYS_GPA_MFPL_PA3MFP_BPWM0_CH3 (0x0CUL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< BPWM0 channel3 output/capture input. \hideinitializer */
201 #define SYS_GPA_MFPL_PA3MFP_EPWM0_CH2 (0x0DUL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< EPWM0 channel2 output/capture input. \hideinitializer */
202 #define SYS_GPA_MFPL_PA3MFP_QEI0_B (0x0EUL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< Quadrature encoder phase B input of QEI Unit 0. \hideinitializer */
203 #define SYS_GPA_MFPL_PA3MFP_EPWM1_BRAKE1 (0x0FUL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< Brake input pin 1 of EPWM1. \hideinitializer */
204 #define SYS_GPA_MFPL_PA4MFP_GPIO (0x00UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
205 #define SYS_GPA_MFPL_PA4MFP_SPIM_D3 (0x02UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< SPIM data 3 pin for Quad Mode I/O. \hideinitializer */
206 #define SYS_GPA_MFPL_PA4MFP_QSPI0_MOSI1 (0x03UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< 2nd QSPI0 MOSI (Master Out, Slave In) pin. \hideinitializer */
207 #define SYS_GPA_MFPL_PA4MFP_SPI0_I2SMCLK (0x04UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< SPI0 I2S master clock output pin. \hideinitializer */
208 #define SYS_GPA_MFPL_PA4MFP_SD1_CLK (0x05UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< SD/SDIO 1 clock. \hideinitializer */
209 #define SYS_GPA_MFPL_PA4MFP_SC0_nCD (0x06UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< SmartCard0 card detect pin. \hideinitializer */
210 #define SYS_GPA_MFPL_PA4MFP_UART0_nRTS (0x07UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< Request to Send output pin for UART0. \hideinitializer */
211 #define SYS_GPA_MFPL_PA4MFP_UART5_RXD (0x08UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< Data receiver input pin for UART5. \hideinitializer */
212 #define SYS_GPA_MFPL_PA4MFP_I2C0_SDA (0x09UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< I2C0 data input/output pin. \hideinitializer */
213 #define SYS_GPA_MFPL_PA4MFP_CAN0_RXD (0x0AUL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< CAN0 bus receiver input. \hideinitializer */
214 #define SYS_GPA_MFPL_PA4MFP_UART0_RXD (0x0BUL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< Data receiver input pin for UART0. \hideinitializer */
215 #define SYS_GPA_MFPL_PA4MFP_BPWM0_CH4 (0x0CUL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< BPWM0 channel4 output/capture input. \hideinitializer */
216 #define SYS_GPA_MFPL_PA4MFP_EPWM0_CH1 (0x0DUL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< EPWM0 channel1 output/capture input. \hideinitializer */
217 #define SYS_GPA_MFPL_PA4MFP_QEI0_A (0x0EUL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< Quadrature encoder phase A input of QEI Unit 0. \hideinitializer */
218 #define SYS_GPA_MFPL_PA5MFP_GPIO (0x00UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
219 #define SYS_GPA_MFPL_PA5MFP_SPIM_D2 (0x02UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< SPIM data 2 pin for Quad Mode I/O. \hideinitializer */
220 #define SYS_GPA_MFPL_PA5MFP_QSPI0_MISO1 (0x03UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< 2nd QSPI0 MISO (Master In, Slave Out) pin. \hideinitializer */
221 #define SYS_GPA_MFPL_PA5MFP_SPI1_I2SMCLK (0x04UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< SPI1 I2S master clock output pin. \hideinitializer */
222 #define SYS_GPA_MFPL_PA5MFP_SD1_CMD (0x05UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< SD/SDIO 1 command/response. \hideinitializer */
223 #define SYS_GPA_MFPL_PA5MFP_SC2_nCD (0x06UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< SmartCard2 card detect pin. \hideinitializer */
224 #define SYS_GPA_MFPL_PA5MFP_UART0_nCTS (0x07UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< Clear to Send input pin for UART0. \hideinitializer */
225 #define SYS_GPA_MFPL_PA5MFP_UART5_TXD (0x08UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< Data transmitter output pin for UART5. \hideinitializer */
226 #define SYS_GPA_MFPL_PA5MFP_I2C0_SCL (0x09UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< I2C0 clock pin. \hideinitializer */
227 #define SYS_GPA_MFPL_PA5MFP_CAN0_TXD (0x0AUL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< CAN0 bus transmitter output. \hideinitializer */
228 #define SYS_GPA_MFPL_PA5MFP_UART0_TXD (0x0BUL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< Data transmitter output pin for UART0. \hideinitializer */
229 #define SYS_GPA_MFPL_PA5MFP_BPWM0_CH5 (0x0CUL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< BPWM0 channel5 output/capture input. \hideinitializer */
230 #define SYS_GPA_MFPL_PA5MFP_EPWM0_CH0 (0x0DUL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< EPWM0 channel0 output/capture input. \hideinitializer */
231 #define SYS_GPA_MFPL_PA5MFP_QEI0_INDEX (0x0EUL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< Quadrature encoder index input of QEI Unit 0. \hideinitializer */
232 #define SYS_GPA_MFPL_PA6MFP_GPIO (0x00UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
233 #define SYS_GPA_MFPL_PA6MFP_EBI_AD6 (0x02UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< EBI address/data bus bit6. \hideinitializer */
234 #define SYS_GPA_MFPL_PA6MFP_EMAC_RMII_RXERR (0x03UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< RMII Receive Data error. \hideinitializer */
235 #define SYS_GPA_MFPL_PA6MFP_SPI1_SS (0x04UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< 1st SPI1 slave select pin. \hideinitializer */
236 #define SYS_GPA_MFPL_PA6MFP_SD1_nCD (0x05UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< SD/SDIO 1 card detect \hideinitializer */
237 #define SYS_GPA_MFPL_PA6MFP_SC2_CLK (0x06UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< SmartCard2 clock pin. \hideinitializer */
238 #define SYS_GPA_MFPL_PA6MFP_UART0_RXD (0x07UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< Data receiver input pin for UART0. \hideinitializer */
239 #define SYS_GPA_MFPL_PA6MFP_I2C1_SDA (0x08UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< I2C1 data input/output pin. \hideinitializer */
240 #define SYS_GPA_MFPL_PA6MFP_QSPI1_MOSI1 (0x09UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< 2nd QSPI1 MOSI (Master Out, Slave In) pin. \hideinitializer */
241 #define SYS_GPA_MFPL_PA6MFP_EPWM1_CH5 (0x0BUL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< EPWM1 channel5 output/capture input. \hideinitializer */
242 #define SYS_GPA_MFPL_PA6MFP_BPWM1_CH3 (0x0CUL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< BPWM1 channel3 output/capture input. \hideinitializer */
243 #define SYS_GPA_MFPL_PA6MFP_ACMP1_WLAT (0x0DUL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< Analog comparator1 window latch input pin. \hideinitializer */
244 #define SYS_GPA_MFPL_PA6MFP_TM3 (0x0EUL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< Timer3 event counter input / toggle output \hideinitializer */
245 #define SYS_GPA_MFPL_PA6MFP_INT0 (0x0FUL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< External interrupt0 input pin. \hideinitializer */
246 #define SYS_GPA_MFPL_PA7MFP_GPIO (0x00UL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
247 #define SYS_GPA_MFPL_PA7MFP_EBI_AD7 (0x02UL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< EBI address/data bus bit7. \hideinitializer */
248 #define SYS_GPA_MFPL_PA7MFP_EMAC_RMII_CRSDV (0x03UL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< MII Receive Data Valid / RMII CRS_DV input. \hideinitializer */
249 #define SYS_GPA_MFPL_PA7MFP_SPI1_CLK (0x04UL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< SPI1 serial clock pin. \hideinitializer */
250 #define SYS_GPA_MFPL_PA7MFP_SC2_DAT (0x06UL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< SmartCard2 data pin. \hideinitializer */
251 #define SYS_GPA_MFPL_PA7MFP_UART0_TXD (0x07UL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< Data transmitter output pin for UART0. \hideinitializer */
252 #define SYS_GPA_MFPL_PA7MFP_I2C1_SCL (0x08UL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< I2C1 clock pin. \hideinitializer */
253 #define SYS_GPA_MFPL_PA7MFP_QSPI1_MISO1 (0x09UL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< 2nd QSPI1 MISO (Master In, Slave Out) pin. \hideinitializer */
254 #define SYS_GPA_MFPL_PA7MFP_EPWM1_CH4 (0x0BUL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< EPWM1 channel4 output/capture input. \hideinitializer */
255 #define SYS_GPA_MFPL_PA7MFP_BPWM1_CH2 (0x0CUL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< BPWM1 channel2 output/capture input. \hideinitializer */
256 #define SYS_GPA_MFPL_PA7MFP_ACMP0_WLAT (0x0DUL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< Analog comparator0 window latch input pin. \hideinitializer */
257 #define SYS_GPA_MFPL_PA7MFP_TM2 (0x0EUL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< Timer2 event counter input / toggle output \hideinitializer */
258 #define SYS_GPA_MFPL_PA7MFP_INT1 (0x0FUL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< External interrupt1 input pin. \hideinitializer */
259 /********************* Bit definition of GPA_MFPH register **********************/
260 #define SYS_GPA_MFPH_PA8MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
261 #define SYS_GPA_MFPH_PA8MFP_OPA1_P (0x01UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< Operational amplifier positive input pin. \hideinitializer */
262 #define SYS_GPA_MFPH_PA8MFP_EADC1_CH4 (0x01UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< EADC1 channel4 analog input. \hideinitializer */
263 #define SYS_GPA_MFPH_PA8MFP_EBI_ALE (0x02UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< EBI address latch enable output pin. \hideinitializer */
264 #define SYS_GPA_MFPH_PA8MFP_SC2_CLK (0x03UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< SmartCard2 clock pin. \hideinitializer */
265 #define SYS_GPA_MFPH_PA8MFP_SPI2_MOSI (0x04UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< 1st SPI2 MOSI (Master Out, Slave In) pin. \hideinitializer */
266 #define SYS_GPA_MFPH_PA8MFP_SD1_DAT0 (0x05UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< SD/SDIO 1 data line bit 0. \hideinitializer */
267 #define SYS_GPA_MFPH_PA8MFP_USCI0_CTL1 (0x06UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< USCI0 control1 pin. \hideinitializer */
268 #define SYS_GPA_MFPH_PA8MFP_UART1_RXD (0x07UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< Data receiver input pin for UART1. \hideinitializer */
269 #define SYS_GPA_MFPH_PA8MFP_UART7_RXD (0x08UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< Data receiver input pin for UART7. \hideinitializer */
270 #define SYS_GPA_MFPH_PA8MFP_BPWM0_CH3 (0x09UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< BPWM0 channel3 output/capture input. \hideinitializer */
271 #define SYS_GPA_MFPH_PA8MFP_QEI1_B (0x0AUL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< Quadrature encoder phase B input of QEI Unit 1. \hideinitializer */
272 #define SYS_GPA_MFPH_PA8MFP_ECAP0_IC2 (0x0BUL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< Input 0 of enhanced capture unit 2. \hideinitializer */
273 #define SYS_GPA_MFPH_PA8MFP_TM3_EXT (0x0DUL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< Timer3 event counter input / toggle output \hideinitializer */
274 #define SYS_GPA_MFPH_PA8MFP_INT4 (0x0FUL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< External interrupt4 input pin. \hideinitializer */
275 #define SYS_GPA_MFPH_PA9MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
276 #define SYS_GPA_MFPH_PA9MFP_OPA1_N (0x01UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< Operational amplifier negative input pin. \hideinitializer */
277 #define SYS_GPA_MFPH_PA9MFP_EADC1_CH5 (0x01UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< EADC1 channel5 analog input. \hideinitializer */
278 #define SYS_GPA_MFPH_PA9MFP_EBI_MCLK (0x02UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< EBI external clock output pin. \hideinitializer */
279 #define SYS_GPA_MFPH_PA9MFP_SC2_DAT (0x03UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< SmartCard2 data pin. \hideinitializer */
280 #define SYS_GPA_MFPH_PA9MFP_SPI2_MISO (0x04UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< 1st SPI2 MISO (Master In, Slave Out) pin. \hideinitializer */
281 #define SYS_GPA_MFPH_PA9MFP_SD1_DAT1 (0x05UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< SD/SDIO 1 data line bit 1. \hideinitializer */
282 #define SYS_GPA_MFPH_PA9MFP_USCI0_DAT1 (0x06UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< USCI0 data1 pin. \hideinitializer */
283 #define SYS_GPA_MFPH_PA9MFP_UART1_TXD (0x07UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< Data transmitter output pin for UART1. \hideinitializer */
284 #define SYS_GPA_MFPH_PA9MFP_UART7_TXD (0x08UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< Data transmitter output pin for UART7. \hideinitializer */
285 #define SYS_GPA_MFPH_PA9MFP_BPWM0_CH2 (0x09UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< BPWM0 channel2 output/capture input. \hideinitializer */
286 #define SYS_GPA_MFPH_PA9MFP_QEI1_A (0x0AUL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< Quadrature encoder phase A input of QEI Unit 1. \hideinitializer */
287 #define SYS_GPA_MFPH_PA9MFP_ECAP0_IC1 (0x0BUL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< Input 1 of enhanced capture unit 0. \hideinitializer */
288 #define SYS_GPA_MFPH_PA9MFP_TM2_EXT (0x0DUL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< Timer2 event counter input / toggle output \hideinitializer */
289 #define SYS_GPA_MFPH_PA9MFP_SWDH_DAT (0x0FUL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< SWD Host interface input/output bus bit. \hideinitializer */
290 #define SYS_GPA_MFPH_PA10MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
291 #define SYS_GPA_MFPH_PA10MFP_ACMP1_P0 (0x01UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< Analog comparator1 positive input pin. \hideinitializer */
292 #define SYS_GPA_MFPH_PA10MFP_OPA1_O (0x01UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< Operational amplifier output pin. \hideinitializer */
293 #define SYS_GPA_MFPH_PA10MFP_EADC1_CH6 (0x01UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< EADC1 channel6 analog input. \hideinitializer */
294 #define SYS_GPA_MFPH_PA10MFP_EBI_nWR (0x02UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< EBI write enable output pin. \hideinitializer */
295 #define SYS_GPA_MFPH_PA10MFP_SC2_RST (0x03UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< SmartCard2 reset pin. \hideinitializer */
296 #define SYS_GPA_MFPH_PA10MFP_SPI2_CLK (0x04UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< SPI2 serial clock pin. \hideinitializer */
297 #define SYS_GPA_MFPH_PA10MFP_SD1_DAT2 (0x05UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< SD/SDIO 1 data line bit 2. \hideinitializer */
298 #define SYS_GPA_MFPH_PA10MFP_USCI0_DAT0 (0x06UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< USCI0 data0 pin. \hideinitializer */
299 #define SYS_GPA_MFPH_PA10MFP_I2C2_SDA (0x07UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< I2C2 data input/output pin. \hideinitializer */
300 #define SYS_GPA_MFPH_PA10MFP_UART6_RXD (0x08UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< Data receiver input pin for UART6. \hideinitializer */
301 #define SYS_GPA_MFPH_PA10MFP_BPWM0_CH1 (0x09UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< BPWM0 channel1 output/capture input. \hideinitializer */
302 #define SYS_GPA_MFPH_PA10MFP_QEI1_INDEX (0x0AUL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< Quadrature encoder index input of QEI Unit 1. \hideinitializer */
303 #define SYS_GPA_MFPH_PA10MFP_ECAP0_IC0 (0x0BUL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< Input 0 of enhanced capture unit 0. \hideinitializer */
304 #define SYS_GPA_MFPH_PA10MFP_TM1_EXT (0x0DUL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< Timer1 event counter input / toggle output \hideinitializer */
305 #define SYS_GPA_MFPH_PA10MFP_DAC0_ST (0x0EUL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< DAC0 external trigger input. \hideinitializer */
306 #define SYS_GPA_MFPH_PA10MFP_SWDH_CLK (0x0FUL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< SWD Host interface clock output pin. \hideinitializer */
307 #define SYS_GPA_MFPH_PA11MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
308 #define SYS_GPA_MFPH_PA11MFP_ACMP0_P0 (0x01UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< Analog comparator0 positive input pin. \hideinitializer */
309 #define SYS_GPA_MFPH_PA11MFP_EADC1_CH7 (0x01UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< EADC1 channel7 analog input. \hideinitializer */
310 #define SYS_GPA_MFPH_PA11MFP_EBI_nRD (0x02UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< EBI read enable output pin. \hideinitializer */
311 #define SYS_GPA_MFPH_PA11MFP_SC2_PWR (0x03UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< SmartCard2 power pin. \hideinitializer */
312 #define SYS_GPA_MFPH_PA11MFP_SPI2_SS (0x04UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< 1st SPI2 slave select pin. \hideinitializer */
313 #define SYS_GPA_MFPH_PA11MFP_SD1_DAT3 (0x05UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< SD/SDIO 1 data line bit 3. \hideinitializer */
314 #define SYS_GPA_MFPH_PA11MFP_USCI0_CLK (0x06UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< USCI0 clock pin. \hideinitializer */
315 #define SYS_GPA_MFPH_PA11MFP_I2C2_SCL (0x07UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< I2C2 clock pin. \hideinitializer */
316 #define SYS_GPA_MFPH_PA11MFP_UART6_TXD (0x08UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< Data transmitter output pin for UART6. \hideinitializer */
317 #define SYS_GPA_MFPH_PA11MFP_BPWM0_CH0 (0x09UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< BPWM0 channel0 output/capture input. \hideinitializer */
318 #define SYS_GPA_MFPH_PA11MFP_EPWM0_SYNC_OUT (0x0AUL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< EPWM0 counter synchronous trigger output pin. \hideinitializer */
319 #define SYS_GPA_MFPH_PA11MFP_TM0_EXT (0x0DUL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< Timer0 event counter input / toggle output \hideinitializer */
320 #define SYS_GPA_MFPH_PA11MFP_DAC1_ST (0x0EUL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< DAC1 external trigger input. \hideinitializer */
321 #define SYS_GPA_MFPH_PA12MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
322 #define SYS_GPA_MFPH_PA12MFP_I2S0_BCLK (0x02UL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< I2S0 bit clock pin. \hideinitializer */
323 #define SYS_GPA_MFPH_PA12MFP_UART4_TXD (0x03UL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< Data transmitter output pin for UART4. \hideinitializer */
324 #define SYS_GPA_MFPH_PA12MFP_I2C1_SCL (0x04UL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< I2C1 clock pin. \hideinitializer */
325 #define SYS_GPA_MFPH_PA12MFP_SPI2_SS (0x05UL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< 1st SPI2 slave select pin. \hideinitializer */
326 #define SYS_GPA_MFPH_PA12MFP_CAN0_TXD (0x06UL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< CAN0 bus transmitter output. \hideinitializer */
327 #define SYS_GPA_MFPH_PA12MFP_SC2_PWR (0x07UL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< SmartCard2 power pin. \hideinitializer */
328 #define SYS_GPA_MFPH_PA12MFP_BPWM1_CH2 (0x0BUL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< BPWM1 channel2 output/capture input. \hideinitializer */
329 #define SYS_GPA_MFPH_PA12MFP_QEI1_INDEX (0x0CUL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< Quadrature encoder index input of QEI Unit 1. \hideinitializer */
330 #define SYS_GPA_MFPH_PA12MFP_USB_VBUS (0x0EUL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< Power supply from USB Full speed host or HUB. \hideinitializer */
331 #define SYS_GPA_MFPH_PA13MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
332 #define SYS_GPA_MFPH_PA13MFP_I2S0_MCLK (0x02UL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< I2S0 master clock output pin. \hideinitializer */
333 #define SYS_GPA_MFPH_PA13MFP_UART4_RXD (0x03UL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< Data receiver input pin for UART4. \hideinitializer */
334 #define SYS_GPA_MFPH_PA13MFP_I2C1_SDA (0x04UL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< I2C1 data input/output pin. \hideinitializer */
335 #define SYS_GPA_MFPH_PA13MFP_SPI2_CLK (0x05UL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< SPI2 serial clock pin. \hideinitializer */
336 #define SYS_GPA_MFPH_PA13MFP_CAN0_RXD (0x06UL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< CAN0 bus receiver input. \hideinitializer */
337 #define SYS_GPA_MFPH_PA13MFP_SC2_RST (0x07UL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< SmartCard2 reset pin. \hideinitializer */
338 #define SYS_GPA_MFPH_PA13MFP_BPWM1_CH3 (0x0BUL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< BPWM1 channel3 output/capture input. \hideinitializer */
339 #define SYS_GPA_MFPH_PA13MFP_QEI1_A (0x0CUL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< Quadrature encoder phase A input of QEI Unit 1. \hideinitializer */
340 #define SYS_GPA_MFPH_PA13MFP_USB_D_N (0x0EUL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< USB Full speed differential signal D-. \hideinitializer */
341 #define SYS_GPA_MFPH_PA14MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
342 #define SYS_GPA_MFPH_PA14MFP_I2S0_DI (0x02UL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< I2S0 data input. \hideinitializer */
343 #define SYS_GPA_MFPH_PA14MFP_UART0_TXD (0x03UL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< Data transmitter output pin for UART0. \hideinitializer */
344 #define SYS_GPA_MFPH_PA14MFP_SPI2_MISO (0x05UL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< 1st SPI2 MISO (Master In, Slave Out) pin. \hideinitializer */
345 #define SYS_GPA_MFPH_PA14MFP_I2C2_SCL (0x06UL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< I2C2 clock pin. \hideinitializer */
346 #define SYS_GPA_MFPH_PA14MFP_SC2_DAT (0x07UL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< SmartCard2 data pin. \hideinitializer */
347 #define SYS_GPA_MFPH_PA14MFP_BPWM1_CH4 (0x0BUL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< BPWM1 channel4 output/capture input. \hideinitializer */
348 #define SYS_GPA_MFPH_PA14MFP_QEI1_B (0x0CUL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< Quadrature encoder phase B input of QEI Unit 1. \hideinitializer */
349 #define SYS_GPA_MFPH_PA14MFP_USB_D_P (0x0EUL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< USB Full speed differential signal D+. \hideinitializer */
350 #define SYS_GPA_MFPH_PA15MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
351 #define SYS_GPA_MFPH_PA15MFP_I2S0_DO (0x02UL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< I2S0 data output. \hideinitializer */
352 #define SYS_GPA_MFPH_PA15MFP_UART0_RXD (0x03UL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< Data receiver input pin for UART0. \hideinitializer */
353 #define SYS_GPA_MFPH_PA15MFP_SPI2_MOSI (0x05UL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< 1st SPI2 MOSI (Master Out, Slave In) pin. \hideinitializer */
354 #define SYS_GPA_MFPH_PA15MFP_I2C2_SDA (0x06UL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< I2C2 data input/output pin. \hideinitializer */
355 #define SYS_GPA_MFPH_PA15MFP_SC2_CLK (0x07UL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< SmartCard2 clock pin. \hideinitializer */
356 #define SYS_GPA_MFPH_PA15MFP_BPWM1_CH5 (0x0BUL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< BPWM1 channel5 output/capture input. \hideinitializer */
357 #define SYS_GPA_MFPH_PA15MFP_EPWM0_SYNC_IN (0x0CUL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< EPWM0 counter synchronous trigger input pin. \hideinitializer */
358 #define SYS_GPA_MFPH_PA15MFP_USB_OTG_ID (0x0EUL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< USB Full speed identification. \hideinitializer */
359 /********************* Bit definition of GPB_MFPL register **********************/
360 #define SYS_GPB_MFPL_PB0MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
361 #define SYS_GPB_MFPL_PB0MFP_EADC0_CH0 (0x01UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< EADC0 channel0 analog input. \hideinitializer */
362 #define SYS_GPB_MFPL_PB0MFP_EADC1_CH8 (0x01UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< EADC1 channel8 analog input. \hideinitializer */
363 #define SYS_GPB_MFPL_PB0MFP_OPA0_P (0x01UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< Operational amplifier positive input pin. \hideinitializer */
364 #define SYS_GPB_MFPL_PB0MFP_EBI_ADR9 (0x02UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
365 #define SYS_GPB_MFPL_PB0MFP_SD0_CMD (0x03UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< SD/SDIO 0 command/response. \hideinitializer */
366 #define SYS_GPB_MFPL_PB0MFP_SPI2_I2SMCLK (0x04UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< SPI2 I2S master clock output pin. \hideinitializer */
367 #define SYS_GPB_MFPL_PB0MFP_UART2_RXD (0x07UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< Data receiver input pin for UART2. \hideinitializer */
368 #define SYS_GPB_MFPL_PB0MFP_SPI0_I2SMCLK (0x08UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< SPI0 I2S master clock output pin. \hideinitializer */
369 #define SYS_GPB_MFPL_PB0MFP_I2C1_SDA (0x09UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< I2C1 data input/output pin. \hideinitializer */
370 #define SYS_GPB_MFPL_PB0MFP_EPWM0_CH5 (0x0BUL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< EPWM0 channel5 output/capture input. \hideinitializer */
371 #define SYS_GPB_MFPL_PB0MFP_EPWM1_CH5 (0x0CUL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< EPWM1 channel5 output/capture input. \hideinitializer */
372 #define SYS_GPB_MFPL_PB0MFP_EPWM0_BRAKE1 (0x0DUL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< Brake input pin 1 of EPWM0. \hideinitializer */
373 #define SYS_GPB_MFPL_PB1MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
374 #define SYS_GPB_MFPL_PB1MFP_EADC0_CH1 (0x01UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< EADC0 channel1 analog input. \hideinitializer */
375 #define SYS_GPB_MFPL_PB1MFP_OPA0_N (0x01UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< Operational amplifier negative input pin. \hideinitializer */
376 #define SYS_GPB_MFPL_PB1MFP_EADC1_CH9 (0x01UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< EADC1 channel9 analog input. \hideinitializer */
377 #define SYS_GPB_MFPL_PB1MFP_EBI_ADR8 (0x02UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
378 #define SYS_GPB_MFPL_PB1MFP_SD0_CLK (0x03UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< SD/SDIO 0 clock. \hideinitializer */
379 #define SYS_GPB_MFPL_PB1MFP_EMAC_RMII_RXERR (0x04UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< RMII Receive Data error. \hideinitializer */
380 #define SYS_GPB_MFPL_PB1MFP_SPI1_I2SMCLK (0x05UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< SPI1 I2S master clock output pin. \hideinitializer */
381 #define SYS_GPB_MFPL_PB1MFP_SPI3_I2SMCLK (0x06UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< SPI3 I2S master clock output pin. \hideinitializer */
382 #define SYS_GPB_MFPL_PB1MFP_UART2_TXD (0x07UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< Data transmitter output pin for UART2. \hideinitializer */
383 #define SYS_GPB_MFPL_PB1MFP_USCI1_CLK (0x08UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< USCI1 clock pin. \hideinitializer */
384 #define SYS_GPB_MFPL_PB1MFP_I2C1_SCL (0x09UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< I2C1 clock pin. \hideinitializer */
385 #define SYS_GPB_MFPL_PB1MFP_I2S0_LRCK (0x0AUL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< I2S0 left right channel clock. \hideinitializer */
386 #define SYS_GPB_MFPL_PB1MFP_EPWM0_CH4 (0x0BUL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< EPWM0 channel4 output/capture input. \hideinitializer */
387 #define SYS_GPB_MFPL_PB1MFP_EPWM1_CH4 (0x0CUL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< EPWM1 channel4 output/capture input. \hideinitializer */
388 #define SYS_GPB_MFPL_PB1MFP_EPWM0_BRAKE0 (0x0DUL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< Brake input pin 0 of EPWM0. \hideinitializer */
389 #define SYS_GPB_MFPL_PB2MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
390 #define SYS_GPB_MFPL_PB2MFP_ACMP0_P1 (0x01UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< Analog comparator0 positive input pin. \hideinitializer */
391 #define SYS_GPB_MFPL_PB2MFP_EADC0_CH2 (0x01UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< EADC0 channel2 analog input. \hideinitializer */
392 #define SYS_GPB_MFPL_PB2MFP_OPA0_O (0x01UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< Operational amplifier output pin. \hideinitializer */
393 #define SYS_GPB_MFPL_PB2MFP_EADC1_CH10 (0x01UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< EADC1 channel1 analog input. \hideinitializer */
394 #define SYS_GPB_MFPL_PB2MFP_EBI_ADR3 (0x02UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
395 #define SYS_GPB_MFPL_PB2MFP_SD0_DAT0 (0x03UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< SD/SDIO 0 data line bit 0. \hideinitializer */
396 #define SYS_GPB_MFPL_PB2MFP_EMAC_RMII_CRSDV (0x04UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< MII Receive Data Valid / RMII CRS_DV input. \hideinitializer */
397 #define SYS_GPB_MFPL_PB2MFP_SPI1_SS (0x05UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< 1st SPI1 slave select pin. \hideinitializer */
398 #define SYS_GPB_MFPL_PB2MFP_UART1_RXD (0x06UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< Data receiver input pin for UART1. \hideinitializer */
399 #define SYS_GPB_MFPL_PB2MFP_UART5_nCTS (0x07UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< Clear to Send input pin for UART5. \hideinitializer */
400 #define SYS_GPB_MFPL_PB2MFP_USCI1_DAT0 (0x08UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< USCI1 data0 pin. \hideinitializer */
401 #define SYS_GPB_MFPL_PB2MFP_SC0_PWR (0x09UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< SmartCard0 power pin. \hideinitializer */
402 #define SYS_GPB_MFPL_PB2MFP_I2S0_DO (0x0AUL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< I2S0 data output. \hideinitializer */
403 #define SYS_GPB_MFPL_PB2MFP_EPWM0_CH3 (0x0BUL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< EPWM0 channel3 output/capture input. \hideinitializer */
404 #define SYS_GPB_MFPL_PB2MFP_I2C1_SDA (0x0CUL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< I2C1 data input/output pin. */
405 #define SYS_GPB_MFPL_PB2MFP_TM3 (0x0EUL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< Timer3 event counter input / toggle output \hideinitializer */
406 #define SYS_GPB_MFPL_PB2MFP_INT3 (0x0FUL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< External interrupt3 input pin. \hideinitializer */
407 #define SYS_GPB_MFPL_PB3MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
408 #define SYS_GPB_MFPL_PB3MFP_ACMP0_N (0x01UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< Analog comparator0 negative input pin. \hideinitializer */
409 #define SYS_GPB_MFPL_PB3MFP_EADC0_CH3 (0x01UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< EADC0 channel3 analog input. \hideinitializer */
410 #define SYS_GPB_MFPL_PB3MFP_EADC1_CH11 (0x01UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< EADC1 channel1 analog input. \hideinitializer */
411 #define SYS_GPB_MFPL_PB3MFP_EBI_ADR2 (0x02UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
412 #define SYS_GPB_MFPL_PB3MFP_SD0_DAT1 (0x03UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< SD/SDIO 0 data line bit 1. \hideinitializer */
413 #define SYS_GPB_MFPL_PB3MFP_EMAC_RMII_RXD1 (0x04UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< RMII Receive Data bus bit 1. \hideinitializer */
414 #define SYS_GPB_MFPL_PB3MFP_SPI1_CLK (0x05UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< SPI1 serial clock pin. \hideinitializer */
415 #define SYS_GPB_MFPL_PB3MFP_UART1_TXD (0x06UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< Data transmitter output pin for UART1. \hideinitializer */
416 #define SYS_GPB_MFPL_PB3MFP_UART5_nRTS (0x07UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< Request to Send output pin for UART5. \hideinitializer */
417 #define SYS_GPB_MFPL_PB3MFP_USCI1_DAT1 (0x08UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< USCI1 data1 pin. \hideinitializer */
418 #define SYS_GPB_MFPL_PB3MFP_SC0_RST (0x09UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< SmartCard0 reset pin. \hideinitializer */
419 #define SYS_GPB_MFPL_PB3MFP_I2S0_DI (0x0AUL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< I2S0 data input. \hideinitializer */
420 #define SYS_GPB_MFPL_PB3MFP_EPWM0_CH2 (0x0BUL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< EPWM0 channel2 output/capture input. \hideinitializer */
421 #define SYS_GPB_MFPL_PB3MFP_I2C1_SCL (0x0CUL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< I2C1 clock pin. */
422 #define SYS_GPB_MFPL_PB3MFP_TM2 (0x0EUL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< Timer2 event counter input / toggle output \hideinitializer */
423 #define SYS_GPB_MFPL_PB3MFP_INT2 (0x0FUL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< External interrupt2 input pin. \hideinitializer */
424 #define SYS_GPB_MFPL_PB4MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
425 #define SYS_GPB_MFPL_PB4MFP_ACMP1_P1 (0x01UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< Analog comparator1 positive input pin. \hideinitializer */
426 #define SYS_GPB_MFPL_PB4MFP_EADC0_CH4 (0x01UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< EADC0 channel4 analog input. \hideinitializer */
427 #define SYS_GPB_MFPL_PB4MFP_EBI_ADR1 (0x02UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
428 #define SYS_GPB_MFPL_PB4MFP_SD0_DAT2 (0x03UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< SD/SDIO 0 data line bit 2. \hideinitializer */
429 #define SYS_GPB_MFPL_PB4MFP_EMAC_RMII_RXD0 (0x04UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< RMII Receive Data bus bit 0. \hideinitializer */
430 #define SYS_GPB_MFPL_PB4MFP_SPI1_MOSI (0x05UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< 1st SPI1 MOSI (Master Out, Slave In) pin. \hideinitializer */
431 #define SYS_GPB_MFPL_PB4MFP_I2C0_SDA (0x06UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< I2C0 data input/output pin. \hideinitializer */
432 #define SYS_GPB_MFPL_PB4MFP_UART5_RXD (0x07UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< Data receiver input pin for UART5. \hideinitializer */
433 #define SYS_GPB_MFPL_PB4MFP_USCI1_CTL1 (0x08UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< USCI1 control1 pin. \hideinitializer */
434 #define SYS_GPB_MFPL_PB4MFP_SC0_DAT (0x09UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< SmartCard0 data pin. \hideinitializer */
435 #define SYS_GPB_MFPL_PB4MFP_I2S0_MCLK (0x0AUL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< I2S0 master clock output pin. \hideinitializer */
436 #define SYS_GPB_MFPL_PB4MFP_EPWM0_CH1 (0x0BUL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< EPWM0 channel1 output/capture input. \hideinitializer */
437 #define SYS_GPB_MFPL_PB4MFP_UART2_RXD (0x0CUL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< Data receiver input pin for UART2. \hideinitializer */
438 #define SYS_GPB_MFPL_PB4MFP_TM1 (0x0EUL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< Timer1 event counter input / toggle output \hideinitializer */
439 #define SYS_GPB_MFPL_PB4MFP_INT1 (0x0FUL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< External interrupt1 input pin. \hideinitializer */
440 #define SYS_GPB_MFPL_PB5MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
441 #define SYS_GPB_MFPL_PB5MFP_ACMP1_N (0x01UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< Analog comparator1 negative input pin. \hideinitializer */
442 #define SYS_GPB_MFPL_PB5MFP_EADC0_CH5 (0x01UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< EADC0 channel5 analog input. \hideinitializer */
443 #define SYS_GPB_MFPL_PB5MFP_EBI_ADR0 (0x02UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
444 #define SYS_GPB_MFPL_PB5MFP_SD0_DAT3 (0x03UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< SD/SDIO 0 data line bit 3. \hideinitializer */
445 #define SYS_GPB_MFPL_PB5MFP_EMAC_RMII_REFCLK (0x04UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< EMAC mode clock input. \hideinitializer */
446 #define SYS_GPB_MFPL_PB5MFP_SPI1_MISO (0x05UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< 1st SPI1 MISO (Master In, Slave Out) pin. \hideinitializer */
447 #define SYS_GPB_MFPL_PB5MFP_I2C0_SCL (0x06UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< I2C0 clock pin. \hideinitializer */
448 #define SYS_GPB_MFPL_PB5MFP_UART5_TXD (0x07UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< Data transmitter output pin for UART5. \hideinitializer */
449 #define SYS_GPB_MFPL_PB5MFP_USCI1_CTL0 (0x08UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< USCI1 control0 pin. \hideinitializer */
450 #define SYS_GPB_MFPL_PB5MFP_SC0_CLK (0x09UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< SmartCard0 clock pin. \hideinitializer */
451 #define SYS_GPB_MFPL_PB5MFP_I2S0_BCLK (0x0AUL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< I2S0 bit clock pin. \hideinitializer */
452 #define SYS_GPB_MFPL_PB5MFP_EPWM0_CH0 (0x0BUL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< EPWM0 channel0 output/capture input. \hideinitializer */
453 #define SYS_GPB_MFPL_PB5MFP_UART2_TXD (0x0CUL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< Data transmitter output pin for UART2. \hideinitializer */
454 #define SYS_GPB_MFPL_PB5MFP_TM0 (0x0EUL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< Timer0 event counter input / toggle output \hideinitializer */
455 #define SYS_GPB_MFPL_PB5MFP_INT0 (0x0FUL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< External interrupt0 input pin. \hideinitializer */
456 #define SYS_GPB_MFPL_PB6MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
457 #define SYS_GPB_MFPL_PB6MFP_EADC0_CH6 (0x01UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< EADC0 channel6 analog input. \hideinitializer */
458 #define SYS_GPB_MFPL_PB6MFP_EBI_nWRH (0x02UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< EBI write enable output pin. \hideinitializer */
459 #define SYS_GPB_MFPL_PB6MFP_EMAC_PPS (0x03UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< EMAC Pulse Per Second output \hideinitializer */
460 #define SYS_GPB_MFPL_PB6MFP_USCI1_DAT1 (0x04UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< USCI1 data1 pin. \hideinitializer */
461 #define SYS_GPB_MFPL_PB6MFP_CAN1_RXD (0x05UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< CAN1 bus receiver input. \hideinitializer */
462 #define SYS_GPB_MFPL_PB6MFP_UART1_RXD (0x06UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< Data receiver input pin for UART1. \hideinitializer */
463 #define SYS_GPB_MFPL_PB6MFP_SD1_CLK (0x07UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< SD/SDIO 1 clock. \hideinitializer */
464 #define SYS_GPB_MFPL_PB6MFP_EBI_nCS1 (0x08UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< EBI chip select enable output pin. \hideinitializer */
465 #define SYS_GPB_MFPL_PB6MFP_BPWM1_CH5 (0x0AUL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< BPWM1 channel5 output/capture input. \hideinitializer */
466 #define SYS_GPB_MFPL_PB6MFP_EPWM1_BRAKE1 (0x0BUL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< Brake input pin 1 of EPWM1. \hideinitializer */
467 #define SYS_GPB_MFPL_PB6MFP_EPWM1_CH5 (0x0CUL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< EPWM1 channel5 output/capture input. \hideinitializer */
468 #define SYS_GPB_MFPL_PB6MFP_INT4 (0x0DUL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< External interrupt4 input pin. \hideinitializer */
469 #define SYS_GPB_MFPL_PB6MFP_USB_VBUS_EN (0x0EUL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< Power supply from USB Full speed host or HUB. \hideinitializer */
470 #define SYS_GPB_MFPL_PB6MFP_ACMP1_O (0x0FUL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< Analog comparator1 output. \hideinitializer */
471 #define SYS_GPB_MFPL_PB7MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
472 #define SYS_GPB_MFPL_PB7MFP_EADC0_CH7 (0x01UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< EADC0 channel7 analog input. \hideinitializer */
473 #define SYS_GPB_MFPL_PB7MFP_EBI_nWRL (0x02UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< EBI write enable output pin. \hideinitializer */
474 #define SYS_GPB_MFPL_PB7MFP_EMAC_RMII_TXEN (0x03UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< RMII Transmit Enable. \hideinitializer */
475 #define SYS_GPB_MFPL_PB7MFP_USCI1_DAT0 (0x04UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< USCI1 data0 pin. \hideinitializer */
476 #define SYS_GPB_MFPL_PB7MFP_CAN1_TXD (0x05UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< CAN1 bus transmitter output. \hideinitializer */
477 #define SYS_GPB_MFPL_PB7MFP_UART1_TXD (0x06UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< Data transmitter output pin for UART1. \hideinitializer */
478 #define SYS_GPB_MFPL_PB7MFP_SD1_CMD (0x07UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< SD/SDIO 1 command/response. \hideinitializer */
479 #define SYS_GPB_MFPL_PB7MFP_EBI_nCS0 (0x08UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< EBI chip select enable output pin. \hideinitializer */
480 #define SYS_GPB_MFPL_PB7MFP_BPWM1_CH4 (0x0AUL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< BPWM1 channel4 output/capture input. \hideinitializer */
481 #define SYS_GPB_MFPL_PB7MFP_EPWM1_BRAKE0 (0x0BUL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< Brake input pin 0 of EPWM1. \hideinitializer */
482 #define SYS_GPB_MFPL_PB7MFP_EPWM1_CH4 (0x0CUL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< EPWM1 channel4 output/capture input. \hideinitializer */
483 #define SYS_GPB_MFPL_PB7MFP_INT5 (0x0DUL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< External interrupt5 input pin. \hideinitializer */
484 #define SYS_GPB_MFPL_PB7MFP_USB_VBUS_ST (0x0EUL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< Power supply from USB Full speed host or HUB. \hideinitializer */
485 #define SYS_GPB_MFPL_PB7MFP_ACMP0_O (0x0FUL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< Analog comparator0 output. \hideinitializer */
486 /********************* Bit definition of GPB_MFPH register **********************/
487 #define SYS_GPB_MFPH_PB8MFP_GPIO (0x00UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
488 #define SYS_GPB_MFPH_PB8MFP_EADC0_CH8 (0x01UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< EADC0 channel8 analog input. \hideinitializer */
489 #define SYS_GPB_MFPH_PB8MFP_EBI_ADR19 (0x02UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
490 #define SYS_GPB_MFPH_PB8MFP_EMAC_RMII_TXD1 (0x03UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< RMII Transmit Data bus bit 1. \hideinitializer */
491 #define SYS_GPB_MFPH_PB8MFP_USCI1_CLK (0x04UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< USCI1 clock pin. \hideinitializer */
492 #define SYS_GPB_MFPH_PB8MFP_UART0_RXD (0x05UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< Data receiver input pin for UART0. \hideinitializer */
493 #define SYS_GPB_MFPH_PB8MFP_UART1_nRTS (0x06UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< Request to Send output pin for UART1. \hideinitializer */
494 #define SYS_GPB_MFPH_PB8MFP_I2C1_SMBSUS (0x07UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< I2C1 SMBus SMBSUS# pin (PMBus CONTROL pin) \hideinitializer */
495 #define SYS_GPB_MFPH_PB8MFP_UART7_RXD (0x08UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< Data receiver input pin for UART7. \hideinitializer */
496 #define SYS_GPB_MFPH_PB8MFP_I2C0_SDA (0x09UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< I2C0 data input/output pin. \hideinitializer */
497 #define SYS_GPB_MFPH_PB8MFP_BPWM1_CH3 (0x0AUL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< BPWM1 channel3 output/capture input. \hideinitializer */
498 #define SYS_GPB_MFPH_PB8MFP_SPI3_MOSI (0x0BUL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< 1st SPI3 MOSI (Master Out, Slave In) pin. \hideinitializer */
499 #define SYS_GPB_MFPH_PB8MFP_CAN2_RXD (0x0CUL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< CAN2 bus receiver input. \hideinitializer */
500 #define SYS_GPB_MFPH_PB8MFP_INT6 (0x0DUL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< External interrupt6 input pin. \hideinitializer */
501 #define SYS_GPB_MFPH_PB9MFP_GPIO (0x00UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
502 #define SYS_GPB_MFPH_PB9MFP_EADC0_CH9 (0x01UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< EADC0 channel9 analog input. \hideinitializer */
503 #define SYS_GPB_MFPH_PB9MFP_EBI_ADR18 (0x02UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
504 #define SYS_GPB_MFPH_PB9MFP_EMAC_RMII_TXD0 (0x03UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< RMII Transmit Data bus bit 0. \hideinitializer */
505 #define SYS_GPB_MFPH_PB9MFP_USCI1_CTL1 (0x04UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< USCI1 control1 pin. \hideinitializer */
506 #define SYS_GPB_MFPH_PB9MFP_UART0_TXD (0x05UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< Data transmitter output pin for UART0. \hideinitializer */
507 #define SYS_GPB_MFPH_PB9MFP_UART1_nCTS (0x06UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< Clear to Send input pin for UART1. \hideinitializer */
508 #define SYS_GPB_MFPH_PB9MFP_I2C1_SMBAL (0x07UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< I2C1 SMBus SMBALTER# pin \hideinitializer */
509 #define SYS_GPB_MFPH_PB9MFP_UART7_TXD (0x08UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< Data transmitter output pin for UART7. \hideinitializer */
510 #define SYS_GPB_MFPH_PB9MFP_I2C0_SCL (0x09UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< I2C0 clock pin. \hideinitializer */
511 #define SYS_GPB_MFPH_PB9MFP_BPWM1_CH2 (0x0AUL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< BPWM1 channel2 output/capture input. \hideinitializer */
512 #define SYS_GPB_MFPH_PB9MFP_SPI3_MISO (0x0BUL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< 1st SPI3 MISO (Master In, Slave Out) pin. \hideinitializer */
513 #define SYS_GPB_MFPH_PB9MFP_CAN2_TXD (0x0CUL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< CAN2 bus transmitter output. \hideinitializer */
514 #define SYS_GPB_MFPH_PB9MFP_INT7 (0x0DUL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< External interrupt7 input pin. \hideinitializer */
515 #define SYS_GPB_MFPH_PB9MFP_CCAP_HSYNC (0x0EUL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< Sensor horizontal synchronization input pin. \hideinitializer */
516 #define SYS_GPB_MFPH_PB10MFP_GPIO (0x00UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
517 #define SYS_GPB_MFPH_PB10MFP_EADC0_CH10 (0x01UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< EADC0 channel1 analog input. \hideinitializer */
518 #define SYS_GPB_MFPH_PB10MFP_EBI_ADR17 (0x02UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
519 #define SYS_GPB_MFPH_PB10MFP_EMAC_RMII_MDIO (0x03UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< RMII Management Data I/O. \hideinitializer */
520 #define SYS_GPB_MFPH_PB10MFP_USCI1_CTL0 (0x04UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< USCI1 control0 pin. \hideinitializer */
521 #define SYS_GPB_MFPH_PB10MFP_UART0_nRTS (0x05UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< Request to Send output pin for UART0. \hideinitializer */
522 #define SYS_GPB_MFPH_PB10MFP_UART4_RXD (0x06UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< Data receiver input pin for UART4. \hideinitializer */
523 #define SYS_GPB_MFPH_PB10MFP_I2C1_SDA (0x07UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< I2C1 data input/output pin. \hideinitializer */
524 #define SYS_GPB_MFPH_PB10MFP_CAN0_RXD (0x08UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< CAN0 bus receiver input. \hideinitializer */
525 #define SYS_GPB_MFPH_PB10MFP_BPWM1_CH1 (0x0AUL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< BPWM1 channel1 output/capture input. \hideinitializer */
526 #define SYS_GPB_MFPH_PB10MFP_SPI3_SS (0x0BUL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< 1st SPI3 slave select pin. \hideinitializer */
527 #define SYS_GPB_MFPH_PB10MFP_CCAP_VSYNC (0x0CUL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< Sensor vertical synchronization input pin. \hideinitializer */
528 #define SYS_GPB_MFPH_PB10MFP_HSUSB_VBUS_EN (0x0EUL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< Power supply from USB High speed host or HUB. \hideinitializer */
529 #define SYS_GPB_MFPH_PB11MFP_GPIO (0x00UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
530 #define SYS_GPB_MFPH_PB11MFP_EADC0_CH11 (0x01UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< EADC0 channel1 analog input. \hideinitializer */
531 #define SYS_GPB_MFPH_PB11MFP_EBI_ADR16 (0x02UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
532 #define SYS_GPB_MFPH_PB11MFP_EMAC_RMII_MDC (0x03UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< RMII Management Data Clock. \hideinitializer */
533 #define SYS_GPB_MFPH_PB11MFP_UART0_nCTS (0x05UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< Clear to Send input pin for UART0. \hideinitializer */
534 #define SYS_GPB_MFPH_PB11MFP_UART4_TXD (0x06UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< Data transmitter output pin for UART4. \hideinitializer */
535 #define SYS_GPB_MFPH_PB11MFP_I2C1_SCL (0x07UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< I2C1 clock pin. \hideinitializer */
536 #define SYS_GPB_MFPH_PB11MFP_CAN0_TXD (0x08UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< CAN0 bus transmitter output. \hideinitializer */
537 #define SYS_GPB_MFPH_PB11MFP_SPI0_I2SMCLK (0x09UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< SPI0 I2S master clock output pin. \hideinitializer */
538 #define SYS_GPB_MFPH_PB11MFP_BPWM1_CH0 (0x0AUL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< BPWM1 channel0 output/capture input. \hideinitializer */
539 #define SYS_GPB_MFPH_PB11MFP_SPI3_CLK (0x0BUL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< SPI3 serial clock pin. \hideinitializer */
540 #define SYS_GPB_MFPH_PB11MFP_CCAP_SFIELD (0x0CUL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< Even/Odd Field Flag input pin. \hideinitializer */
541 #define SYS_GPB_MFPH_PB11MFP_HSUSB_VBUS_ST (0x0EUL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< Power supply from USB High speed host or HUB. \hideinitializer */
542 #define SYS_GPB_MFPH_PB12MFP_GPIO (0x00UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
543 #define SYS_GPB_MFPH_PB12MFP_ACMP0_P2 (0x01UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< Analog comparator0 positive input pin. \hideinitializer */
544 #define SYS_GPB_MFPH_PB12MFP_ACMP1_P2 (0x01UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< Analog comparator1 positive input pin. \hideinitializer */
545 #define SYS_GPB_MFPH_PB12MFP_DAC0_OUT (0x01UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< DAC0 channel analog output. \hideinitializer */
546 #define SYS_GPB_MFPH_PB12MFP_EADC0_CH12 (0x01UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< EADC0 channel1 analog input. \hideinitializer */
547 #define SYS_GPB_MFPH_PB12MFP_EADC1_CH12 (0x01UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< EADC1 channel1 analog input. \hideinitializer */
548 #define SYS_GPB_MFPH_PB12MFP_EBI_AD15 (0x02UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */
549 #define SYS_GPB_MFPH_PB12MFP_SC1_CLK (0x03UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< SmartCard1 clock pin. \hideinitializer */
550 #define SYS_GPB_MFPH_PB12MFP_SPI0_MOSI (0x04UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< 1st SPI0 MOSI (Master Out, Slave In) pin. \hideinitializer */
551 #define SYS_GPB_MFPH_PB12MFP_USCI0_CLK (0x05UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< USCI0 clock pin. \hideinitializer */
552 #define SYS_GPB_MFPH_PB12MFP_UART0_RXD (0x06UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< Data receiver input pin for UART0. \hideinitializer */
553 #define SYS_GPB_MFPH_PB12MFP_UART3_nCTS (0x07UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< Clear to Send input pin for UART3. \hideinitializer */
554 #define SYS_GPB_MFPH_PB12MFP_I2C2_SDA (0x08UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< I2C2 data input/output pin. \hideinitializer */
555 #define SYS_GPB_MFPH_PB12MFP_SD0_nCD (0x09UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< SD/SDIO 0 card detect. \hideinitializer */
556 #define SYS_GPB_MFPH_PB12MFP_CCAP_SCLK (0x0AUL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< Sensor pixel clock(to sensor) output pin. \hideinitializer */
557 #define SYS_GPB_MFPH_PB12MFP_EPWM1_CH3 (0x0BUL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< EPWM1 channel3 output/capture input. \hideinitializer */
558 #define SYS_GPB_MFPH_PB12MFP_ETM_TRACE_DATA3 (0x0CUL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< ETM Rx input bus bit3. \hideinitializer */
559 #define SYS_GPB_MFPH_PB12MFP_TM3_EXT (0x0DUL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< Timer3 event counter input / toggle output \hideinitializer */
560 #define SYS_GPB_MFPH_PB13MFP_GPIO (0x00UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
561 #define SYS_GPB_MFPH_PB13MFP_ACMP0_P3 (0x01UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< Analog comparator0 positive input pin. \hideinitializer */
562 #define SYS_GPB_MFPH_PB13MFP_ACMP1_P3 (0x01UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< Analog comparator1 positive input pin. \hideinitializer */
563 #define SYS_GPB_MFPH_PB13MFP_DAC1_OUT (0x01UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< DAC1 channel analog output. \hideinitializer */
564 #define SYS_GPB_MFPH_PB13MFP_EADC0_CH13 (0x01UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< EADC0 channel1 analog input. \hideinitializer */
565 #define SYS_GPB_MFPH_PB13MFP_EADC1_CH13 (0x01UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< EADC1 channel1 analog input. \hideinitializer */
566 #define SYS_GPB_MFPH_PB13MFP_EBI_AD14 (0x02UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */
567 #define SYS_GPB_MFPH_PB13MFP_SC1_DAT (0x03UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< SmartCard1 data pin. \hideinitializer */
568 #define SYS_GPB_MFPH_PB13MFP_SPI0_MISO (0x04UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< 1st SPI0 MISO (Master In, Slave Out) pin. \hideinitializer */
569 #define SYS_GPB_MFPH_PB13MFP_USCI0_DAT0 (0x05UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< USCI0 data0 pin. \hideinitializer */
570 #define SYS_GPB_MFPH_PB13MFP_UART0_TXD (0x06UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< Data transmitter output pin for UART0. \hideinitializer */
571 #define SYS_GPB_MFPH_PB13MFP_UART3_nRTS (0x07UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< Request to Send output pin for UART3. \hideinitializer */
572 #define SYS_GPB_MFPH_PB13MFP_I2C2_SCL (0x08UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< I2C2 clock pin. \hideinitializer */
573 #define SYS_GPB_MFPH_PB13MFP_CCAP_PIXCLK (0x0AUL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< Sensor pixel clock(from sensor) input pin. \hideinitializer */
574 #define SYS_GPB_MFPH_PB13MFP_EPWM1_CH2 (0x0BUL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< EPWM1 channel2 output/capture input. \hideinitializer */
575 #define SYS_GPB_MFPH_PB13MFP_ETM_TRACE_DATA2 (0x0CUL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< ETM Rx input bus bit2. \hideinitializer */
576 #define SYS_GPB_MFPH_PB13MFP_TM2_EXT (0x0DUL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< Timer2 event counter input / toggle output \hideinitializer */
577 #define SYS_GPB_MFPH_PB14MFP_GPIO (0x00UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
578 #define SYS_GPB_MFPH_PB14MFP_EADC0_CH14 (0x01UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< EADC0 channel1 analog input. \hideinitializer */
579 #define SYS_GPB_MFPH_PB14MFP_EADC1_CH14 (0x01UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< EADC1 channel1 analog input. \hideinitializer */
580 #define SYS_GPB_MFPH_PB14MFP_EBI_AD13 (0x02UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */
581 #define SYS_GPB_MFPH_PB14MFP_SC1_RST (0x03UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< SmartCard1 reset pin. \hideinitializer */
582 #define SYS_GPB_MFPH_PB14MFP_SPI0_CLK (0x04UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< SPI0 serial clock pin. \hideinitializer */
583 #define SYS_GPB_MFPH_PB14MFP_USCI0_DAT1 (0x05UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< USCI0 data1 pin. \hideinitializer */
584 #define SYS_GPB_MFPH_PB14MFP_UART0_nRTS (0x06UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< Request to Send output pin for UART0. \hideinitializer */
585 #define SYS_GPB_MFPH_PB14MFP_UART3_RXD (0x07UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< Data receiver input pin for UART3. \hideinitializer */
586 #define SYS_GPB_MFPH_PB14MFP_I2C2_SMBSUS (0x08UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< I2C2 SMBus SMBSUS# pin (PMBus CONTROL pin) \hideinitializer */
587 #define SYS_GPB_MFPH_PB14MFP_EPWM1_CH1 (0x0BUL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< EPWM1 channel1 output/capture input. \hideinitializer */
588 #define SYS_GPB_MFPH_PB14MFP_ETM_TRACE_DATA1 (0x0CUL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< ETM Rx input bus bit1. \hideinitializer */
589 #define SYS_GPB_MFPH_PB14MFP_TM1_EXT (0x0DUL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< Timer1 event counter input / toggle output \hideinitializer */
590 #define SYS_GPB_MFPH_PB14MFP_CLKO (0x0EUL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< Clock Output pin. \hideinitializer */
591 #define SYS_GPB_MFPH_PB14MFP_USB_VBUS_ST (0x0FUL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< Power supply from USB Full speed host or HUB. */
592 #define SYS_GPB_MFPH_PB15MFP_GPIO (0x00UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
593 #define SYS_GPB_MFPH_PB15MFP_EADC0_CH15 (0x01UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< EADC0 channel1 analog input. \hideinitializer */
594 #define SYS_GPB_MFPH_PB15MFP_EADC1_CH15 (0x01UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< EADC1 channel1 analog input. \hideinitializer */
595 #define SYS_GPB_MFPH_PB15MFP_EBI_AD12 (0x02UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */
596 #define SYS_GPB_MFPH_PB15MFP_SC1_PWR (0x03UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< SmartCard1 power pin. \hideinitializer */
597 #define SYS_GPB_MFPH_PB15MFP_SPI0_SS (0x04UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< 1st SPI0 slave select pin. \hideinitializer */
598 #define SYS_GPB_MFPH_PB15MFP_USCI0_CTL1 (0x05UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< USCI0 control1 pin. \hideinitializer */
599 #define SYS_GPB_MFPH_PB15MFP_UART0_nCTS (0x06UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< Clear to Send input pin for UART0. \hideinitializer */
600 #define SYS_GPB_MFPH_PB15MFP_UART3_TXD (0x07UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< Data transmitter output pin for UART3. \hideinitializer */
601 #define SYS_GPB_MFPH_PB15MFP_I2C2_SMBAL (0x08UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< I2C2 SMBus SMBALTER# pin. \hideinitializer */
602 #define SYS_GPB_MFPH_PB15MFP_EPWM0_BRAKE1 (0x0AUL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< Brake input pin 1 of EPWM0. \hideinitializer */
603 #define SYS_GPB_MFPH_PB15MFP_EPWM1_CH0 (0x0BUL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< EPWM1 channel0 output/capture input. \hideinitializer */
604 #define SYS_GPB_MFPH_PB15MFP_ETM_TRACE_DATA0 (0x0CUL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< ETM Rx input bus bit0. \hideinitializer */
605 #define SYS_GPB_MFPH_PB15MFP_TM0_EXT (0x0DUL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< Timer0 event counter input / toggle output \hideinitializer */
606 #define SYS_GPB_MFPH_PB15MFP_USB_VBUS_EN (0x0EUL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< Power supply from USB Full speed host or HUB. \hideinitializer */
607 #define SYS_GPB_MFPH_PB15MFP_HSUSB_VBUS_EN (0x0FUL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< Power supply from USB High speed host or HUB. \hideinitializer */
608 /********************* Bit definition of GPC_MFPL register **********************/
609 #define SYS_GPC_MFPL_PC0MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
610 #define SYS_GPC_MFPL_PC0MFP_EBI_AD0 (0x02UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< EBI address/data bus bit0. \hideinitializer */
611 #define SYS_GPC_MFPL_PC0MFP_SPIM_MOSI (0x03UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< 1st SPIM MOSI (Master Out, Slave In) pin. \hideinitializer */
612 #define SYS_GPC_MFPL_PC0MFP_QSPI0_MOSI0 (0x04UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< 1st QSPI0 MOSI (Master Out, Slave In) pin. \hideinitializer */
613 #define SYS_GPC_MFPL_PC0MFP_SC1_CLK (0x05UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< SmartCard1 clock pin. \hideinitializer */
614 #define SYS_GPC_MFPL_PC0MFP_I2S0_LRCK (0x06UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< I2S0 left right channel clock. \hideinitializer */
615 #define SYS_GPC_MFPL_PC0MFP_SPI1_SS (0x07UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< 1st SPI1 slave select pin. \hideinitializer */
616 #define SYS_GPC_MFPL_PC0MFP_UART2_RXD (0x08UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< Data receiver input pin for UART2. \hideinitializer */
617 #define SYS_GPC_MFPL_PC0MFP_I2C0_SDA (0x09UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< I2C0 data input/output pin. \hideinitializer */
618 #define SYS_GPC_MFPL_PC0MFP_CAN2_RXD (0x0AUL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< CAN2 bus receiver input. \hideinitializer */
619 #define SYS_GPC_MFPL_PC0MFP_EPWM1_CH5 (0x0CUL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< EPWM1 channel5 output/capture input. \hideinitializer */
620 #define SYS_GPC_MFPL_PC0MFP_CCAP_DATA0 (0x0DUL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< Sensor pixel data0 input pin. \hideinitializer */
621 #define SYS_GPC_MFPL_PC0MFP_ACMP1_O (0x0EUL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< Analog comparator1 output. \hideinitializer */
622 #define SYS_GPC_MFPL_PC0MFP_EADC1_ST (0x0FUL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< EADC external trigger input. \hideinitializer */
623 #define SYS_GPC_MFPL_PC1MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
624 #define SYS_GPC_MFPL_PC1MFP_EBI_AD1 (0x02UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */
625 #define SYS_GPC_MFPL_PC1MFP_SPIM_MISO (0x03UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< 1st SPIM MISO (Master In, Slave Out) pin. \hideinitializer */
626 #define SYS_GPC_MFPL_PC1MFP_QSPI0_MISO0 (0x04UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< 1st QSPI0 MISO (Master In, Slave Out) pin. \hideinitializer */
627 #define SYS_GPC_MFPL_PC1MFP_SC1_DAT (0x05UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< SmartCard1 data pin. \hideinitializer */
628 #define SYS_GPC_MFPL_PC1MFP_I2S0_DO (0x06UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< I2S0 data output. \hideinitializer */
629 #define SYS_GPC_MFPL_PC1MFP_SPI1_CLK (0x07UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< SPI1 serial clock pin. \hideinitializer */
630 #define SYS_GPC_MFPL_PC1MFP_UART2_TXD (0x08UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< Data transmitter output pin for UART2. \hideinitializer */
631 #define SYS_GPC_MFPL_PC1MFP_I2C0_SCL (0x09UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< I2C0 clock pin. \hideinitializer */
632 #define SYS_GPC_MFPL_PC1MFP_CAN2_TXD (0x0AUL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< CAN2 bus transmitter output. \hideinitializer */
633 #define SYS_GPC_MFPL_PC1MFP_EPWM1_CH4 (0x0CUL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< EPWM1 channel4 output/capture input. \hideinitializer */
634 #define SYS_GPC_MFPL_PC1MFP_CCAP_DATA1 (0x0DUL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< Sensor pixel data1 input pin. \hideinitializer */
635 #define SYS_GPC_MFPL_PC1MFP_ACMP0_O (0x0EUL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< Analog comparator0 output. \hideinitializer */
636 #define SYS_GPC_MFPL_PC1MFP_EADC0_ST (0x0FUL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< EADC external trigger input. \hideinitializer */
637 #define SYS_GPC_MFPL_PC2MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
638 #define SYS_GPC_MFPL_PC2MFP_EBI_AD2 (0x02UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< EBI address/data bus bit2. \hideinitializer */
639 #define SYS_GPC_MFPL_PC2MFP_SPIM_CLK (0x03UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< SPIM serial clock pin. \hideinitializer */
640 #define SYS_GPC_MFPL_PC2MFP_QSPI0_CLK (0x04UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< QSPI0 serial clock pin. \hideinitializer */
641 #define SYS_GPC_MFPL_PC2MFP_SC1_RST (0x05UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< SmartCard1 reset pin. \hideinitializer */
642 #define SYS_GPC_MFPL_PC2MFP_I2S0_DI (0x06UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< I2S0 data input. \hideinitializer */
643 #define SYS_GPC_MFPL_PC2MFP_SPI1_MOSI (0x07UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< 1st SPI1 MOSI (Master Out, Slave In) pin. \hideinitializer */
644 #define SYS_GPC_MFPL_PC2MFP_UART2_nCTS (0x08UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< Clear to Send input pin for UART2. \hideinitializer */
645 #define SYS_GPC_MFPL_PC2MFP_I2C0_SMBSUS (0x09UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< I2C0 SMBus SMBSUS# pin (PMBus CONTROL pin) \hideinitializer */
646 #define SYS_GPC_MFPL_PC2MFP_CAN1_RXD (0x0AUL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< CAN1 bus receiver input. \hideinitializer */
647 #define SYS_GPC_MFPL_PC2MFP_UART3_RXD (0x0BUL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< Data receiver input pin for UART3. \hideinitializer */
648 #define SYS_GPC_MFPL_PC2MFP_EPWM1_CH3 (0x0CUL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< EPWM1 channel3 output/capture input. \hideinitializer */
649 #define SYS_GPC_MFPL_PC2MFP_CCAP_DATA2 (0x0DUL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< Sensor pixel data2 input pin. \hideinitializer */
650 #define SYS_GPC_MFPL_PC2MFP_QSPI1_MOSI0 (0x0EUL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< 1st QSPI1 MOSI (Master Out, Slave In) pin. \hideinitializer */
651 #define SYS_GPC_MFPL_PC3MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
652 #define SYS_GPC_MFPL_PC3MFP_EBI_AD3 (0x02UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< EBI address/data bus bit3. \hideinitializer */
653 #define SYS_GPC_MFPL_PC3MFP_SPIM_SS (0x03UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< 1st SPIM slave select pin. \hideinitializer */
654 #define SYS_GPC_MFPL_PC3MFP_QSPI0_SS (0x04UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< 1st QSPI0 slave select pin. \hideinitializer */
655 #define SYS_GPC_MFPL_PC3MFP_SC1_PWR (0x05UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< SmartCard1 power pin. \hideinitializer */
656 #define SYS_GPC_MFPL_PC3MFP_I2S0_MCLK (0x06UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< I2S0 master clock output pin. \hideinitializer */
657 #define SYS_GPC_MFPL_PC3MFP_SPI1_MISO (0x07UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< 1st SPI1 MISO (Master In, Slave Out) pin. \hideinitializer */
658 #define SYS_GPC_MFPL_PC3MFP_UART2_nRTS (0x08UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< Request to Send output pin for UART2. \hideinitializer */
659 #define SYS_GPC_MFPL_PC3MFP_I2C0_SMBAL (0x09UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< I2C0 SMBus SMBALTER# pin \hideinitializer */
660 #define SYS_GPC_MFPL_PC3MFP_CAN1_TXD (0x0AUL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< CAN1 bus transmitter output. \hideinitializer */
661 #define SYS_GPC_MFPL_PC3MFP_UART3_TXD (0x0BUL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< Data transmitter output pin for UART3. \hideinitializer */
662 #define SYS_GPC_MFPL_PC3MFP_EPWM1_CH2 (0x0CUL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< EPWM1 channel2 output/capture input. \hideinitializer */
663 #define SYS_GPC_MFPL_PC3MFP_CCAP_DATA3 (0x0DUL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< Sensor pixel data3 input pin. \hideinitializer */
664 #define SYS_GPC_MFPL_PC3MFP_QSPI1_MISO0 (0x0EUL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< 1st QSPI1 MISO (Master In, Slave Out) pin. \hideinitializer */
665 #define SYS_GPC_MFPL_PC4MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
666 #define SYS_GPC_MFPL_PC4MFP_EBI_AD4 (0x02UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< EBI address/data bus bit4. \hideinitializer */
667 #define SYS_GPC_MFPL_PC4MFP_SPIM_D3 (0x03UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< SPIM data 3 pin for Quad Mode I/O. \hideinitializer */
668 #define SYS_GPC_MFPL_PC4MFP_QSPI0_MOSI1 (0x04UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< 2nd QSPI0 MOSI (Master Out, Slave In) pin. \hideinitializer */
669 #define SYS_GPC_MFPL_PC4MFP_SC1_nCD (0x05UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< SmartCard1 card detect pin. \hideinitializer */
670 #define SYS_GPC_MFPL_PC4MFP_I2S0_BCLK (0x06UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< I2S0 bit clock pin. \hideinitializer */
671 #define SYS_GPC_MFPL_PC4MFP_SPI1_I2SMCLK (0x07UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< SPI1 I2S master clock output pin. \hideinitializer */
672 #define SYS_GPC_MFPL_PC4MFP_UART2_RXD (0x08UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< Data receiver input pin for UART2. \hideinitializer */
673 #define SYS_GPC_MFPL_PC4MFP_I2C1_SDA (0x09UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< I2C1 data input/output pin. \hideinitializer */
674 #define SYS_GPC_MFPL_PC4MFP_CAN0_RXD (0x0AUL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< CAN0 bus receiver input. \hideinitializer */
675 #define SYS_GPC_MFPL_PC4MFP_UART4_RXD (0x0BUL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< Data receiver input pin for UART4. \hideinitializer */
676 #define SYS_GPC_MFPL_PC4MFP_EPWM1_CH1 (0x0CUL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< EPWM1 channel1 output/capture input. \hideinitializer */
677 #define SYS_GPC_MFPL_PC4MFP_CCAP_DATA4 (0x0DUL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< Sensor pixel data4 input pin. \hideinitializer */
678 #define SYS_GPC_MFPL_PC4MFP_QSPI1_CLK (0x0EUL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< QSPI1 serial clock pin. \hideinitializer */
679 #define SYS_GPC_MFPL_PC5MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
680 #define SYS_GPC_MFPL_PC5MFP_EBI_AD5 (0x02UL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< EBI address/data bus bit5. \hideinitializer */
681 #define SYS_GPC_MFPL_PC5MFP_SPIM_D2 (0x03UL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< SPIM data 2 pin for Quad Mode I/O. \hideinitializer */
682 #define SYS_GPC_MFPL_PC5MFP_QSPI0_MISO1 (0x04UL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< 2nd QSPI0 MISO (Master In, Slave Out) pin. \hideinitializer */
683 #define SYS_GPC_MFPL_PC5MFP_UART2_TXD (0x08UL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< Data transmitter output pin for UART2. \hideinitializer */
684 #define SYS_GPC_MFPL_PC5MFP_I2C1_SCL (0x09UL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< I2C1 clock pin. \hideinitializer */
685 #define SYS_GPC_MFPL_PC5MFP_CAN0_TXD (0x0AUL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< CAN0 bus transmitter output. \hideinitializer */
686 #define SYS_GPC_MFPL_PC5MFP_UART4_TXD (0x0BUL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< Data transmitter output pin for UART4. \hideinitializer */
687 #define SYS_GPC_MFPL_PC5MFP_EPWM1_CH0 (0x0CUL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< EPWM1 channel0 output/capture input. \hideinitializer */
688 #define SYS_GPC_MFPL_PC5MFP_CCAP_DATA5 (0x0DUL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< Sensor pixel data5 input pin. \hideinitializer */
689 #define SYS_GPC_MFPL_PC5MFP_QSPI1_SS (0x0EUL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< 1st QSPI1 slave select pin. \hideinitializer */
690 #define SYS_GPC_MFPL_PC6MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
691 #define SYS_GPC_MFPL_PC6MFP_EBI_AD8 (0x02UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< EBI address/data bus bit8. \hideinitializer */
692 #define SYS_GPC_MFPL_PC6MFP_EMAC_RMII_RXD1 (0x03UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< RMII Receive Data bus bit 1. \hideinitializer */
693 #define SYS_GPC_MFPL_PC6MFP_SPI1_MOSI (0x04UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< 1st SPI1 MOSI (Master Out, Slave In) pin. \hideinitializer */
694 #define SYS_GPC_MFPL_PC6MFP_UART4_RXD (0x05UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< Data receiver input pin for UART4. \hideinitializer */
695 #define SYS_GPC_MFPL_PC6MFP_SC2_RST (0x06UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< SmartCard2 reset pin. \hideinitializer */
696 #define SYS_GPC_MFPL_PC6MFP_UART0_nRTS (0x07UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< Request to Send output pin for UART0. \hideinitializer */
697 #define SYS_GPC_MFPL_PC6MFP_I2C1_SMBSUS (0x08UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< I2C1 SMBus SMBSUS# pin (PMBus CONTROL pin) \hideinitializer */
698 #define SYS_GPC_MFPL_PC6MFP_UART6_RXD (0x09UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< Data receiver input pin for UART6. \hideinitializer */
699 #define SYS_GPC_MFPL_PC6MFP_EPWM1_CH3 (0x0BUL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< EPWM1 channel3 output/capture input. \hideinitializer */
700 #define SYS_GPC_MFPL_PC6MFP_BPWM1_CH1 (0x0CUL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< BPWM1 channel1 output/capture input. \hideinitializer */
701 #define SYS_GPC_MFPL_PC6MFP_TM1 (0x0EUL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< Timer1 event counter input / toggle output \hideinitializer */
702 #define SYS_GPC_MFPL_PC6MFP_INT2 (0x0FUL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< External interrupt2 input pin. \hideinitializer */
703 #define SYS_GPC_MFPL_PC7MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
704 #define SYS_GPC_MFPL_PC7MFP_EBI_AD9 (0x02UL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< EBI address/data bus bit9. \hideinitializer */
705 #define SYS_GPC_MFPL_PC7MFP_EMAC_RMII_RXD0 (0x03UL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< RMII Receive Data bus bit 0. \hideinitializer */
706 #define SYS_GPC_MFPL_PC7MFP_SPI1_MISO (0x04UL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< 1st SPI1 MISO (Master In, Slave Out) pin. \hideinitializer */
707 #define SYS_GPC_MFPL_PC7MFP_UART4_TXD (0x05UL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< Data transmitter output pin for UART4. \hideinitializer */
708 #define SYS_GPC_MFPL_PC7MFP_SC2_PWR (0x06UL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< SmartCard2 power pin. \hideinitializer */
709 #define SYS_GPC_MFPL_PC7MFP_UART0_nCTS (0x07UL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< Clear to Send input pin for UART0. \hideinitializer */
710 #define SYS_GPC_MFPL_PC7MFP_I2C1_SMBAL (0x08UL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< I2C1 SMBus SMBALTER# pin \hideinitializer */
711 #define SYS_GPC_MFPL_PC7MFP_UART6_TXD (0x09UL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< Data transmitter output pin for UART6. \hideinitializer */
712 #define SYS_GPC_MFPL_PC7MFP_EPWM1_CH2 (0x0BUL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< EPWM1 channel2 output/capture input. \hideinitializer */
713 #define SYS_GPC_MFPL_PC7MFP_BPWM1_CH0 (0x0CUL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< BPWM1 channel0 output/capture input. \hideinitializer */
714 #define SYS_GPC_MFPL_PC7MFP_TM0 (0x0EUL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< Timer0 event counter input / toggle output \hideinitializer */
715 #define SYS_GPC_MFPL_PC7MFP_INT3 (0x0FUL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< External interrupt3 input pin. \hideinitializer */
716 /********************* Bit definition of GPC_MFPH register **********************/
717 #define SYS_GPC_MFPH_PC8MFP_GPIO (0x00UL<<SYS_GPC_MFPH_PC8MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
718 #define SYS_GPC_MFPH_PC8MFP_EBI_ADR16 (0x02UL<<SYS_GPC_MFPH_PC8MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
719 #define SYS_GPC_MFPH_PC8MFP_EMAC_RMII_REFCLK (0x03UL<<SYS_GPC_MFPH_PC8MFP_Pos) /*!< EMAC mode clock input. \hideinitializer */
720 #define SYS_GPC_MFPH_PC8MFP_I2C0_SDA (0x04UL<<SYS_GPC_MFPH_PC8MFP_Pos) /*!< I2C0 data input/output pin. \hideinitializer */
721 #define SYS_GPC_MFPH_PC8MFP_UART4_nCTS (0x05UL<<SYS_GPC_MFPH_PC8MFP_Pos) /*!< Clear to Send input pin for UART4. \hideinitializer */
722 #define SYS_GPC_MFPH_PC8MFP_UART1_RXD (0x08UL<<SYS_GPC_MFPH_PC8MFP_Pos) /*!< Data receiver input pin for UART1. \hideinitializer */
723 #define SYS_GPC_MFPH_PC8MFP_EPWM1_CH1 (0x0BUL<<SYS_GPC_MFPH_PC8MFP_Pos) /*!< EPWM1 channel1 output/capture input. \hideinitializer */
724 #define SYS_GPC_MFPH_PC8MFP_BPWM1_CH4 (0x0CUL<<SYS_GPC_MFPH_PC8MFP_Pos) /*!< BPWM1 channel4 output/capture input. \hideinitializer */
725 #define SYS_GPC_MFPH_PC9MFP_GPIO (0x00UL<<SYS_GPC_MFPH_PC9MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
726 #define SYS_GPC_MFPH_PC9MFP_EBI_ADR7 (0x02UL<<SYS_GPC_MFPH_PC9MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
727 #define SYS_GPC_MFPH_PC9MFP_UART6_nCTS (0x05UL<<SYS_GPC_MFPH_PC9MFP_Pos) /*!< Clear to Send input pin for UART6. \hideinitializer */
728 #define SYS_GPC_MFPH_PC9MFP_SPI3_SS (0x06UL<<SYS_GPC_MFPH_PC9MFP_Pos) /*!< 1st SPI3 slave select pin. \hideinitializer */
729 #define SYS_GPC_MFPH_PC9MFP_UART3_RXD (0x07UL<<SYS_GPC_MFPH_PC9MFP_Pos) /*!< Data receiver input pin for UART3. \hideinitializer */
730 #define SYS_GPC_MFPH_PC9MFP_CAN1_RXD (0x09UL<<SYS_GPC_MFPH_PC9MFP_Pos) /*!< CAN1 bus receiver input. \hideinitializer */
731 #define SYS_GPC_MFPH_PC9MFP_EPWM1_CH3 (0x0CUL<<SYS_GPC_MFPH_PC9MFP_Pos) /*!< EPWM1 channel3 output/capture input. \hideinitializer */
732 #define SYS_GPC_MFPH_PC9MFP_EADC1_ST (0x0EUL<<SYS_GPC_MFPH_PC9MFP_Pos) /*!< EADC external trigger input. \hideinitializer */
733 #define SYS_GPC_MFPH_PC10MFP_GPIO (0x00UL<<SYS_GPC_MFPH_PC10MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
734 #define SYS_GPC_MFPH_PC10MFP_EBI_ADR6 (0x02UL<<SYS_GPC_MFPH_PC10MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
735 #define SYS_GPC_MFPH_PC10MFP_UART6_nRTS (0x05UL<<SYS_GPC_MFPH_PC10MFP_Pos) /*!< Request to Send output pin for UART6. \hideinitializer */
736 #define SYS_GPC_MFPH_PC10MFP_SPI3_CLK (0x06UL<<SYS_GPC_MFPH_PC10MFP_Pos) /*!< SPI3 serial clock pin. \hideinitializer */
737 #define SYS_GPC_MFPH_PC10MFP_UART3_TXD (0x07UL<<SYS_GPC_MFPH_PC10MFP_Pos) /*!< Data transmitter output pin for UART3. \hideinitializer */
738 #define SYS_GPC_MFPH_PC10MFP_CAN1_TXD (0x09UL<<SYS_GPC_MFPH_PC10MFP_Pos) /*!< CAN1 bus transmitter output. \hideinitializer */
739 #define SYS_GPC_MFPH_PC10MFP_ECAP1_IC0 (0x0BUL<<SYS_GPC_MFPH_PC10MFP_Pos) /*!< Input 0 of enhanced capture unit 1. \hideinitializer */
740 #define SYS_GPC_MFPH_PC10MFP_EPWM1_CH2 (0x0CUL<<SYS_GPC_MFPH_PC10MFP_Pos) /*!< EPWM1 channel2 output/capture input. \hideinitializer */
741 #define SYS_GPC_MFPH_PC10MFP_EADC1_ST (0x0EUL<<SYS_GPC_MFPH_PC10MFP_Pos) /*!< EADC external trigger input. \hideinitializer */
742 #define SYS_GPC_MFPH_PC11MFP_GPIO (0x00UL<<SYS_GPC_MFPH_PC11MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
743 #define SYS_GPC_MFPH_PC11MFP_EBI_ADR5 (0x02UL<<SYS_GPC_MFPH_PC11MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
744 #define SYS_GPC_MFPH_PC11MFP_UART0_RXD (0x03UL<<SYS_GPC_MFPH_PC11MFP_Pos) /*!< Data receiver input pin for UART0. \hideinitializer */
745 #define SYS_GPC_MFPH_PC11MFP_I2C0_SDA (0x04UL<<SYS_GPC_MFPH_PC11MFP_Pos) /*!< I2C0 data input/output pin. \hideinitializer */
746 #define SYS_GPC_MFPH_PC11MFP_UART6_RXD (0x05UL<<SYS_GPC_MFPH_PC11MFP_Pos) /*!< Data receiver input pin for UART6. \hideinitializer */
747 #define SYS_GPC_MFPH_PC11MFP_SPI3_MOSI (0x06UL<<SYS_GPC_MFPH_PC11MFP_Pos) /*!< 1st SPI3 MOSI (Master Out, Slave In) pin. \hideinitializer */
748 #define SYS_GPC_MFPH_PC11MFP_ECAP1_IC1 (0x0BUL<<SYS_GPC_MFPH_PC11MFP_Pos) /*!< Input 1 of enhanced capture unit 1. \hideinitializer */
749 #define SYS_GPC_MFPH_PC11MFP_EPWM1_CH1 (0x0CUL<<SYS_GPC_MFPH_PC11MFP_Pos) /*!< EPWM1 channel1 output/capture input. \hideinitializer */
750 #define SYS_GPC_MFPH_PC11MFP_ACMP1_O (0x0EUL<<SYS_GPC_MFPH_PC11MFP_Pos) /*!< Analog comparator1 output. \hideinitializer */
751 #define SYS_GPC_MFPH_PC12MFP_GPIO (0x00UL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
752 #define SYS_GPC_MFPH_PC12MFP_EBI_ADR4 (0x02UL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
753 #define SYS_GPC_MFPH_PC12MFP_UART0_TXD (0x03UL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< Data transmitter output pin for UART0. \hideinitializer */
754 #define SYS_GPC_MFPH_PC12MFP_I2C0_SCL (0x04UL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< I2C0 clock pin. \hideinitializer */
755 #define SYS_GPC_MFPH_PC12MFP_UART6_TXD (0x05UL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< Data transmitter output pin for UART6. \hideinitializer */
756 #define SYS_GPC_MFPH_PC12MFP_SPI3_MISO (0x06UL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< 1st SPI3 MISO (Master In, Slave Out) pin. \hideinitializer */
757 #define SYS_GPC_MFPH_PC12MFP_SC0_nCD (0x09UL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< SmartCard0 card detect pin. \hideinitializer */
758 #define SYS_GPC_MFPH_PC12MFP_ECAP1_IC2 (0x0BUL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< Input 1 of enhanced capture unit 2. \hideinitializer */
759 #define SYS_GPC_MFPH_PC12MFP_EPWM1_CH0 (0x0CUL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< EPWM1 channel0 output/capture input. \hideinitializer */
760 #define SYS_GPC_MFPH_PC12MFP_ACMP0_O (0x0EUL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< Analog comparator0 output. \hideinitializer */
761 #define SYS_GPC_MFPH_PC13MFP_GPIO (0x00UL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
762 #define SYS_GPC_MFPH_PC13MFP_EADC1_CH3 (0x01UL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< EADC1 channel3 analog input. \hideinitializer */
763 #define SYS_GPC_MFPH_PC13MFP_EBI_ADR10 (0x02UL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
764 #define SYS_GPC_MFPH_PC13MFP_SC2_nCD (0x03UL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< SmartCard2 card detect pin. \hideinitializer */
765 #define SYS_GPC_MFPH_PC13MFP_SPI2_I2SMCLK (0x04UL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< SPI2 I2S master clock output pin. \hideinitializer */
766 #define SYS_GPC_MFPH_PC13MFP_CAN1_TXD (0x05UL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< CAN1 bus transmitter output. \hideinitializer */
767 #define SYS_GPC_MFPH_PC13MFP_USCI0_CTL0 (0x06UL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< USCI0 control0 pin. \hideinitializer */
768 #define SYS_GPC_MFPH_PC13MFP_UART2_TXD (0x07UL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< Data transmitter output pin for UART2. \hideinitializer */
769 #define SYS_GPC_MFPH_PC13MFP_BPWM0_CH4 (0x09UL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< BPWM0 channel4 output/capture input. \hideinitializer */
770 #define SYS_GPC_MFPH_PC13MFP_CLKO (0x0DUL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< Clock Output pin. \hideinitializer */
771 #define SYS_GPC_MFPH_PC13MFP_EADC0_ST (0x0EUL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< EADC external trigger input. \hideinitializer */
772 #define SYS_GPC_MFPH_PC14MFP_GPIO (0x00UL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
773 #define SYS_GPC_MFPH_PC14MFP_EBI_AD11 (0x02UL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */
774 #define SYS_GPC_MFPH_PC14MFP_SC1_nCD (0x03UL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< SmartCard1 card detect pin. \hideinitializer */
775 #define SYS_GPC_MFPH_PC14MFP_SPI0_I2SMCLK (0x04UL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< SPI0 I2S master clock output pin. \hideinitializer */
776 #define SYS_GPC_MFPH_PC14MFP_USCI0_CTL0 (0x05UL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< USCI0 control0 pin. \hideinitializer */
777 #define SYS_GPC_MFPH_PC14MFP_QSPI0_CLK (0x06UL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< QSPI0 serial clock pin. \hideinitializer */
778 #define SYS_GPC_MFPH_PC14MFP_EPWM0_SYNC_IN (0x0BUL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< EPWM0 counter synchronous trigger input pin. \hideinitializer */
779 #define SYS_GPC_MFPH_PC14MFP_ETM_TRACE_CLK (0x0CUL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< ETM Rx clock input pin. \hideinitializer */
780 #define SYS_GPC_MFPH_PC14MFP_TM1 (0x0DUL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< Timer1 event counter input / toggle output \hideinitializer */
781 #define SYS_GPC_MFPH_PC14MFP_USB_VBUS_ST (0x0EUL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< Power supply from USB Full speed host or HUB. \hideinitializer */
782 #define SYS_GPC_MFPH_PC14MFP_HSUSB_VBUS_ST (0x0FUL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< Power supply from USB High speed host or HUB. \hideinitializer */
783 /********************* Bit definition of GPD_MFPL register **********************/
784 #define SYS_GPD_MFPL_PD0MFP_GPIO (0x00UL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
785 #define SYS_GPD_MFPL_PD0MFP_EBI_AD13 (0x02UL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */
786 #define SYS_GPD_MFPL_PD0MFP_USCI0_CLK (0x03UL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< USCI0 clock pin. \hideinitializer */
787 #define SYS_GPD_MFPL_PD0MFP_SPI0_MOSI (0x04UL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< 1st SPI0 MOSI (Master Out, Slave In) pin. \hideinitializer */
788 #define SYS_GPD_MFPL_PD0MFP_UART3_RXD (0x05UL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< Data receiver input pin for UART3. \hideinitializer */
789 #define SYS_GPD_MFPL_PD0MFP_I2C2_SDA (0x06UL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< I2C2 data input/output pin. \hideinitializer */
790 #define SYS_GPD_MFPL_PD0MFP_SC2_CLK (0x07UL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< SmartCard2 clock pin. \hideinitializer */
791 #define SYS_GPD_MFPL_PD0MFP_TM2 (0x0EUL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< Timer2 event counter input / toggle output \hideinitializer */
792 #define SYS_GPD_MFPL_PD1MFP_GPIO (0x00UL<<SYS_GPD_MFPL_PD1MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
793 #define SYS_GPD_MFPL_PD1MFP_EBI_AD12 (0x02UL<<SYS_GPD_MFPL_PD1MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */
794 #define SYS_GPD_MFPL_PD1MFP_USCI0_DAT0 (0x03UL<<SYS_GPD_MFPL_PD1MFP_Pos) /*!< USCI0 data0 pin. \hideinitializer */
795 #define SYS_GPD_MFPL_PD1MFP_SPI0_MISO (0x04UL<<SYS_GPD_MFPL_PD1MFP_Pos) /*!< 1st SPI0 MISO (Master In, Slave Out) pin. \hideinitializer */
796 #define SYS_GPD_MFPL_PD1MFP_UART3_TXD (0x05UL<<SYS_GPD_MFPL_PD1MFP_Pos) /*!< Data transmitter output pin for UART3. \hideinitializer */
797 #define SYS_GPD_MFPL_PD1MFP_I2C2_SCL (0x06UL<<SYS_GPD_MFPL_PD1MFP_Pos) /*!< I2C2 clock pin. \hideinitializer */
798 #define SYS_GPD_MFPL_PD1MFP_SC2_DAT (0x07UL<<SYS_GPD_MFPL_PD1MFP_Pos) /*!< SmartCard2 data pin. \hideinitializer */
799 #define SYS_GPD_MFPL_PD2MFP_GPIO (0x00UL<<SYS_GPD_MFPL_PD2MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
800 #define SYS_GPD_MFPL_PD2MFP_EBI_AD11 (0x02UL<<SYS_GPD_MFPL_PD2MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */
801 #define SYS_GPD_MFPL_PD2MFP_USCI0_DAT1 (0x03UL<<SYS_GPD_MFPL_PD2MFP_Pos) /*!< USCI0 data1 pin. \hideinitializer */
802 #define SYS_GPD_MFPL_PD2MFP_SPI0_CLK (0x04UL<<SYS_GPD_MFPL_PD2MFP_Pos) /*!< SPI0 serial clock pin. \hideinitializer */
803 #define SYS_GPD_MFPL_PD2MFP_UART3_nCTS (0x05UL<<SYS_GPD_MFPL_PD2MFP_Pos) /*!< Clear to Send input pin for UART3. \hideinitializer */
804 #define SYS_GPD_MFPL_PD2MFP_SC2_RST (0x07UL<<SYS_GPD_MFPL_PD2MFP_Pos) /*!< SmartCard2 reset pin. \hideinitializer */
805 #define SYS_GPD_MFPL_PD2MFP_UART0_RXD (0x09UL<<SYS_GPD_MFPL_PD2MFP_Pos) /*!< Data receiver input pin for UART0. \hideinitializer */
806 #define SYS_GPD_MFPL_PD3MFP_GPIO (0x00UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
807 #define SYS_GPD_MFPL_PD3MFP_EBI_AD10 (0x02UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */
808 #define SYS_GPD_MFPL_PD3MFP_USCI0_CTL1 (0x03UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< USCI0 control1 pin. \hideinitializer */
809 #define SYS_GPD_MFPL_PD3MFP_SPI0_SS (0x04UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< 1st SPI0 slave select pin. \hideinitializer */
810 #define SYS_GPD_MFPL_PD3MFP_UART3_nRTS (0x05UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< Request to Send output pin for UART3. \hideinitializer */
811 #define SYS_GPD_MFPL_PD3MFP_USCI1_CTL0 (0x06UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< USCI1 control0 pin. \hideinitializer */
812 #define SYS_GPD_MFPL_PD3MFP_SC2_PWR (0x07UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< SmartCard2 power pin. \hideinitializer */
813 #define SYS_GPD_MFPL_PD3MFP_SC1_nCD (0x08UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< SmartCard1 card detect pin. \hideinitializer */
814 #define SYS_GPD_MFPL_PD3MFP_UART0_TXD (0x09UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< Data transmitter output pin for UART0. \hideinitializer */
815 #define SYS_GPD_MFPL_PD4MFP_GPIO (0x00UL<<SYS_GPD_MFPL_PD4MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
816 #define SYS_GPD_MFPL_PD4MFP_USCI0_CTL0 (0x03UL<<SYS_GPD_MFPL_PD4MFP_Pos) /*!< USCI0 control0 pin. \hideinitializer */
817 #define SYS_GPD_MFPL_PD4MFP_I2C1_SDA (0x04UL<<SYS_GPD_MFPL_PD4MFP_Pos) /*!< I2C1 data input/output pin. \hideinitializer */
818 #define SYS_GPD_MFPL_PD4MFP_SPI1_SS (0x05UL<<SYS_GPD_MFPL_PD4MFP_Pos) /*!< 1st SPI1 slave select pin. \hideinitializer */
819 #define SYS_GPD_MFPL_PD4MFP_USCI1_CTL1 (0x06UL<<SYS_GPD_MFPL_PD4MFP_Pos) /*!< USCI1 control1 pin. \hideinitializer */
820 #define SYS_GPD_MFPL_PD4MFP_SC1_CLK (0x08UL<<SYS_GPD_MFPL_PD4MFP_Pos) /*!< SmartCard1 clock pin. \hideinitializer */
821 #define SYS_GPD_MFPL_PD4MFP_USB_VBUS_ST (0x0EUL<<SYS_GPD_MFPL_PD4MFP_Pos) /*!< Power supply from USB Full speed host or HUB. \hideinitializer */
822 #define SYS_GPD_MFPL_PD5MFP_GPIO (0x00UL<<SYS_GPD_MFPL_PD5MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
823 #define SYS_GPD_MFPL_PD5MFP_I2C1_SCL (0x04UL<<SYS_GPD_MFPL_PD5MFP_Pos) /*!< I2C1 clock pin. \hideinitializer */
824 #define SYS_GPD_MFPL_PD5MFP_SPI1_CLK (0x05UL<<SYS_GPD_MFPL_PD5MFP_Pos) /*!< SPI1 serial clock pin. \hideinitializer */
825 #define SYS_GPD_MFPL_PD5MFP_USCI1_DAT0 (0x06UL<<SYS_GPD_MFPL_PD5MFP_Pos) /*!< USCI1 data0 pin. \hideinitializer */
826 #define SYS_GPD_MFPL_PD5MFP_SC1_DAT (0x08UL<<SYS_GPD_MFPL_PD5MFP_Pos) /*!< SmartCard1 data pin. \hideinitializer */
827 #define SYS_GPD_MFPL_PD6MFP_GPIO (0x00UL<<SYS_GPD_MFPL_PD6MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
828 #define SYS_GPD_MFPL_PD6MFP_UART1_RXD (0x03UL<<SYS_GPD_MFPL_PD6MFP_Pos) /*!< Data receiver input pin for UART1. \hideinitializer */
829 #define SYS_GPD_MFPL_PD6MFP_I2C0_SDA (0x04UL<<SYS_GPD_MFPL_PD6MFP_Pos) /*!< I2C0 data input/output pin. \hideinitializer */
830 #define SYS_GPD_MFPL_PD6MFP_SPI1_MOSI (0x05UL<<SYS_GPD_MFPL_PD6MFP_Pos) /*!< 1st SPI1 MOSI (Master Out, Slave In) pin. \hideinitializer */
831 #define SYS_GPD_MFPL_PD6MFP_USCI1_DAT1 (0x06UL<<SYS_GPD_MFPL_PD6MFP_Pos) /*!< USCI1 data1 pin. \hideinitializer */
832 #define SYS_GPD_MFPL_PD6MFP_SC1_RST (0x08UL<<SYS_GPD_MFPL_PD6MFP_Pos) /*!< SmartCard1 reset pin. \hideinitializer */
833 #define SYS_GPD_MFPL_PD7MFP_GPIO (0x00UL<<SYS_GPD_MFPL_PD7MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
834 #define SYS_GPD_MFPL_PD7MFP_UART1_TXD (0x03UL<<SYS_GPD_MFPL_PD7MFP_Pos) /*!< Data transmitter output pin for UART1. \hideinitializer */
835 #define SYS_GPD_MFPL_PD7MFP_I2C0_SCL (0x04UL<<SYS_GPD_MFPL_PD7MFP_Pos) /*!< I2C0 clock pin. \hideinitializer */
836 #define SYS_GPD_MFPL_PD7MFP_SPI1_MISO (0x05UL<<SYS_GPD_MFPL_PD7MFP_Pos) /*!< 1st SPI1 MISO (Master In, Slave Out) pin. \hideinitializer */
837 #define SYS_GPD_MFPL_PD7MFP_USCI1_CLK (0x06UL<<SYS_GPD_MFPL_PD7MFP_Pos) /*!< USCI1 clock pin. \hideinitializer */
838 #define SYS_GPD_MFPL_PD7MFP_SC1_PWR (0x08UL<<SYS_GPD_MFPL_PD7MFP_Pos) /*!< SmartCard1 power pin. \hideinitializer */
839 /********************* Bit definition of GPD_MFPH register **********************/
840 #define SYS_GPD_MFPH_PD8MFP_GPIO (0x00UL<<SYS_GPD_MFPH_PD8MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
841 #define SYS_GPD_MFPH_PD8MFP_EBI_AD6 (0x02UL<<SYS_GPD_MFPH_PD8MFP_Pos) /*!< EBI address/data bus bit6. \hideinitializer */
842 #define SYS_GPD_MFPH_PD8MFP_I2C2_SDA (0x03UL<<SYS_GPD_MFPH_PD8MFP_Pos) /*!< I2C2 data input/output pin. \hideinitializer */
843 #define SYS_GPD_MFPH_PD8MFP_UART2_nRTS (0x04UL<<SYS_GPD_MFPH_PD8MFP_Pos) /*!< Request to Send output pin for UART2. \hideinitializer */
844 #define SYS_GPD_MFPH_PD8MFP_UART7_RXD (0x05UL<<SYS_GPD_MFPH_PD8MFP_Pos) /*!< Data receiver input pin for UART7. \hideinitializer */
845 #define SYS_GPD_MFPH_PD8MFP_CAN2_RXD (0x06UL<<SYS_GPD_MFPH_PD8MFP_Pos) /*!< CAN2 bus receiver input. \hideinitializer */
846 #define SYS_GPD_MFPH_PD9MFP_GPIO (0x00UL<<SYS_GPD_MFPH_PD9MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
847 #define SYS_GPD_MFPH_PD9MFP_EBI_AD7 (0x02UL<<SYS_GPD_MFPH_PD9MFP_Pos) /*!< EBI address/data bus bit7. \hideinitializer */
848 #define SYS_GPD_MFPH_PD9MFP_I2C2_SCL (0x03UL<<SYS_GPD_MFPH_PD9MFP_Pos) /*!< I2C2 clock pin. \hideinitializer */
849 #define SYS_GPD_MFPH_PD9MFP_UART2_nCTS (0x04UL<<SYS_GPD_MFPH_PD9MFP_Pos) /*!< Clear to Send input pin for UART2. \hideinitializer */
850 #define SYS_GPD_MFPH_PD9MFP_UART7_TXD (0x05UL<<SYS_GPD_MFPH_PD9MFP_Pos) /*!< Data transmitter output pin for UART7. \hideinitializer */
851 #define SYS_GPD_MFPH_PD9MFP_CAN2_TXD (0x06UL<<SYS_GPD_MFPH_PD9MFP_Pos) /*!< CAN2 bus transmitter output. \hideinitializer */
852 #define SYS_GPD_MFPH_PD10MFP_GPIO (0x00UL<<SYS_GPD_MFPH_PD10MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
853 #define SYS_GPD_MFPH_PD10MFP_OPA2_P (0x01UL<<SYS_GPD_MFPH_PD10MFP_Pos) /*!< Operational amplifier positive input pin. \hideinitializer */
854 #define SYS_GPD_MFPH_PD10MFP_EADC1_CH0 (0x01UL<<SYS_GPD_MFPH_PD10MFP_Pos) /*!< EADC1 channel0 analog input. \hideinitializer */
855 #define SYS_GPD_MFPH_PD10MFP_EBI_nCS2 (0x02UL<<SYS_GPD_MFPH_PD10MFP_Pos) /*!< EBI chip select enable output pin. \hideinitializer */
856 #define SYS_GPD_MFPH_PD10MFP_UART1_RXD (0x03UL<<SYS_GPD_MFPH_PD10MFP_Pos) /*!< Data receiver input pin for UART1. \hideinitializer */
857 #define SYS_GPD_MFPH_PD10MFP_CAN0_RXD (0x04UL<<SYS_GPD_MFPH_PD10MFP_Pos) /*!< CAN0 bus receiver input. \hideinitializer */
858 #define SYS_GPD_MFPH_PD10MFP_QEI0_B (0x0AUL<<SYS_GPD_MFPH_PD10MFP_Pos) /*!< Quadrature encoder phase B input of QEI Unit 0. \hideinitializer */
859 #define SYS_GPD_MFPH_PD10MFP_INT7 (0x0FUL<<SYS_GPD_MFPH_PD10MFP_Pos) /*!< External interrupt7 input pin. \hideinitializer */
860 #define SYS_GPD_MFPH_PD11MFP_GPIO (0x00UL<<SYS_GPD_MFPH_PD11MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
861 #define SYS_GPD_MFPH_PD11MFP_EADC1_CH1 (0x01UL<<SYS_GPD_MFPH_PD11MFP_Pos) /*!< EADC1 channel1 analog input. \hideinitializer */
862 #define SYS_GPD_MFPH_PD11MFP_OPA2_N (0x01UL<<SYS_GPD_MFPH_PD11MFP_Pos) /*!< Operational amplifier negative input pin. \hideinitializer */
863 #define SYS_GPD_MFPH_PD11MFP_EBI_nCS1 (0x02UL<<SYS_GPD_MFPH_PD11MFP_Pos) /*!< EBI chip select enable output pin. \hideinitializer */
864 #define SYS_GPD_MFPH_PD11MFP_UART1_TXD (0x03UL<<SYS_GPD_MFPH_PD11MFP_Pos) /*!< Data transmitter output pin for UART1. \hideinitializer */
865 #define SYS_GPD_MFPH_PD11MFP_CAN0_TXD (0x04UL<<SYS_GPD_MFPH_PD11MFP_Pos) /*!< CAN0 bus transmitter output. \hideinitializer */
866 #define SYS_GPD_MFPH_PD11MFP_QEI0_A (0x0AUL<<SYS_GPD_MFPH_PD11MFP_Pos) /*!< Quadrature encoder phase A input of QEI Unit 0. \hideinitializer */
867 #define SYS_GPD_MFPH_PD11MFP_INT6 (0x0FUL<<SYS_GPD_MFPH_PD11MFP_Pos) /*!< External interrupt6 input pin. \hideinitializer */
868 #define SYS_GPD_MFPH_PD12MFP_GPIO (0x00UL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
869 #define SYS_GPD_MFPH_PD12MFP_OPA2_O (0x01UL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< Operational amplifier output pin. \hideinitializer */
870 #define SYS_GPD_MFPH_PD12MFP_EADC1_CH2 (0x01UL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< EADC1 channel2 analog input. \hideinitializer */
871 #define SYS_GPD_MFPH_PD12MFP_EBI_nCS0 (0x02UL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< EBI chip select enable output pin. \hideinitializer */
872 #define SYS_GPD_MFPH_PD12MFP_CAN1_RXD (0x05UL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< CAN1 bus receiver input. \hideinitializer */
873 #define SYS_GPD_MFPH_PD12MFP_UART2_RXD (0x07UL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< Data receiver input pin for UART2. \hideinitializer */
874 #define SYS_GPD_MFPH_PD12MFP_BPWM0_CH5 (0x09UL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< BPWM0 channel5 output/capture input. \hideinitializer */
875 #define SYS_GPD_MFPH_PD12MFP_QEI0_INDEX (0x0AUL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< Quadrature encoder index input of QEI Unit 0. \hideinitializer */
876 #define SYS_GPD_MFPH_PD12MFP_CLKO (0x0DUL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< Clock Output pin. \hideinitializer */
877 #define SYS_GPD_MFPH_PD12MFP_EADC0_ST (0x0EUL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< EADC external trigger input. \hideinitializer */
878 #define SYS_GPD_MFPH_PD12MFP_INT5 (0x0FUL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< External interrupt5 input pin. \hideinitializer */
879 #define SYS_GPD_MFPH_PD13MFP_GPIO (0x00UL<<SYS_GPD_MFPH_PD13MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
880 #define SYS_GPD_MFPH_PD13MFP_EBI_AD10 (0x02UL<<SYS_GPD_MFPH_PD13MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */
881 #define SYS_GPD_MFPH_PD13MFP_SD0_nCD (0x03UL<<SYS_GPD_MFPH_PD13MFP_Pos) /*!< SD/SDIO 0 card detect \hideinitializer */
882 #define SYS_GPD_MFPH_PD13MFP_SPI0_I2SMCLK (0x04UL<<SYS_GPD_MFPH_PD13MFP_Pos) /*!< SPI0 I2S master clock output pin. \hideinitializer */
883 #define SYS_GPD_MFPH_PD13MFP_SPI1_I2SMCLK (0x05UL<<SYS_GPD_MFPH_PD13MFP_Pos) /*!< SPI1 I2S master clock output pin. \hideinitializer */
884 #define SYS_GPD_MFPH_PD13MFP_SC2_nCD (0x07UL<<SYS_GPD_MFPH_PD13MFP_Pos) /*!< SmartCard2 card detect pin. \hideinitializer */
885 #define SYS_GPD_MFPH_PD14MFP_GPIO (0x00UL<<SYS_GPD_MFPH_PD14MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
886 #define SYS_GPD_MFPH_PD14MFP_EBI_nCS0 (0x02UL<<SYS_GPD_MFPH_PD14MFP_Pos) /*!< EBI chip select enable output pin. \hideinitializer */
887 #define SYS_GPD_MFPH_PD14MFP_SPI3_I2SMCLK (0x03UL<<SYS_GPD_MFPH_PD14MFP_Pos) /*!< SPI3 I2S master clock output pin. \hideinitializer */
888 #define SYS_GPD_MFPH_PD14MFP_SC1_nCD (0x04UL<<SYS_GPD_MFPH_PD14MFP_Pos) /*!< SmartCard1 card detect pin. \hideinitializer */
889 #define SYS_GPD_MFPH_PD14MFP_SPI0_I2SMCLK (0x05UL<<SYS_GPD_MFPH_PD14MFP_Pos) /*!< SPI0 I2S master clock output pin. \hideinitializer */
890 #define SYS_GPD_MFPH_PD14MFP_EPWM0_CH4 (0x0BUL<<SYS_GPD_MFPH_PD14MFP_Pos) /*!< EPWM0 channel4 output/capture input. \hideinitializer */
891 /********************* Bit definition of GPE_MFPL register **********************/
892 #define SYS_GPE_MFPL_PE0MFP_GPIO (0x00UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
893 #define SYS_GPE_MFPL_PE0MFP_EBI_AD11 (0x02UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */
894 #define SYS_GPE_MFPL_PE0MFP_QSPI0_MOSI0 (0x03UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< 1st QSPI0 MOSI (Master Out, Slave In) pin. \hideinitializer */
895 #define SYS_GPE_MFPL_PE0MFP_SC2_CLK (0x04UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< SmartCard2 clock pin. \hideinitializer */
896 #define SYS_GPE_MFPL_PE0MFP_I2S0_MCLK (0x05UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< I2S0 master clock output pin. \hideinitializer */
897 #define SYS_GPE_MFPL_PE0MFP_SPI1_MOSI (0x06UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< 1st SPI1 MOSI (Master Out, Slave In) pin. \hideinitializer */
898 #define SYS_GPE_MFPL_PE0MFP_UART3_RXD (0x07UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< Data receiver input pin for UART3. \hideinitializer */
899 #define SYS_GPE_MFPL_PE0MFP_I2C1_SDA (0x08UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< I2C1 data input/output pin. \hideinitializer */
900 #define SYS_GPE_MFPL_PE0MFP_UART4_nRTS (0x09UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< Request to Send output pin for UART4. \hideinitializer */
901 #define SYS_GPE_MFPL_PE1MFP_GPIO (0x00UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
902 #define SYS_GPE_MFPL_PE1MFP_EBI_AD10 (0x02UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */
903 #define SYS_GPE_MFPL_PE1MFP_QSPI0_MISO0 (0x03UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< 1st QSPI0 MISO (Master In, Slave Out) pin. \hideinitializer */
904 #define SYS_GPE_MFPL_PE1MFP_SC2_DAT (0x04UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< SmartCard2 data pin. \hideinitializer */
905 #define SYS_GPE_MFPL_PE1MFP_I2S0_BCLK (0x05UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< I2S0 bit clock pin. \hideinitializer */
906 #define SYS_GPE_MFPL_PE1MFP_SPI1_MISO (0x06UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< 1st SPI1 MISO (Master In, Slave Out) pin. \hideinitializer */
907 #define SYS_GPE_MFPL_PE1MFP_UART3_TXD (0x07UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< Data transmitter output pin for UART3. \hideinitializer */
908 #define SYS_GPE_MFPL_PE1MFP_I2C1_SCL (0x08UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< I2C1 clock pin. \hideinitializer */
909 #define SYS_GPE_MFPL_PE1MFP_UART4_nCTS (0x09UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< Clear to Send input pin for UART4. \hideinitializer */
910 #define SYS_GPE_MFPL_PE2MFP_GPIO (0x00UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
911 #define SYS_GPE_MFPL_PE2MFP_EBI_ALE (0x02UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< EBI address latch enable output pin. \hideinitializer */
912 #define SYS_GPE_MFPL_PE2MFP_SD0_DAT0 (0x03UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< SD/SDIO 0 data line bit 0. \hideinitializer */
913 #define SYS_GPE_MFPL_PE2MFP_SPIM_MOSI (0x04UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< 1st SPIM MOSI (Master Out, Slave In) pin. \hideinitializer */
914 #define SYS_GPE_MFPL_PE2MFP_SPI3_MOSI (0x05UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< 1st SPI3 MOSI (Master Out, Slave In) pin. \hideinitializer */
915 #define SYS_GPE_MFPL_PE2MFP_SC0_CLK (0x06UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< SmartCard0 clock pin. \hideinitializer */
916 #define SYS_GPE_MFPL_PE2MFP_USCI0_CLK (0x07UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< USCI0 clock pin. \hideinitializer */
917 #define SYS_GPE_MFPL_PE2MFP_UART6_nCTS (0x08UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< Clear to Send input pin for UART6. \hideinitializer */
918 #define SYS_GPE_MFPL_PE2MFP_UART7_RXD (0x09UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< Data receiver input pin for UART7. \hideinitializer */
919 #define SYS_GPE_MFPL_PE2MFP_QEI0_B (0x0BUL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< Quadrature encoder phase B input of QEI Unit 0. \hideinitializer */
920 #define SYS_GPE_MFPL_PE2MFP_EPWM0_CH5 (0x0CUL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< EPWM0 channel5 output/capture input. \hideinitializer */
921 #define SYS_GPE_MFPL_PE2MFP_BPWM0_CH0 (0x0DUL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< BPWM0 channel0 output/capture input. \hideinitializer */
922 #define SYS_GPE_MFPL_PE3MFP_GPIO (0x00UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
923 #define SYS_GPE_MFPL_PE3MFP_EBI_MCLK (0x02UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< EBI external clock output pin. \hideinitializer */
924 #define SYS_GPE_MFPL_PE3MFP_SD0_DAT1 (0x03UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< SD/SDIO 0 data line bit 1. \hideinitializer */
925 #define SYS_GPE_MFPL_PE3MFP_SPIM_MISO (0x04UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< 1st SPIM MISO (Master In, Slave Out) pin. \hideinitializer */
926 #define SYS_GPE_MFPL_PE3MFP_SPI3_MISO (0x05UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< 1st SPI3 MISO (Master In, Slave Out) pin. \hideinitializer */
927 #define SYS_GPE_MFPL_PE3MFP_SC0_DAT (0x06UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< SmartCard0 data pin. \hideinitializer */
928 #define SYS_GPE_MFPL_PE3MFP_USCI0_DAT0 (0x07UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< USCI0 data0 pin. \hideinitializer */
929 #define SYS_GPE_MFPL_PE3MFP_UART6_nRTS (0x08UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< Request to Send output pin for UART6. \hideinitializer */
930 #define SYS_GPE_MFPL_PE3MFP_UART7_TXD (0x09UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< Data transmitter output pin for UART7. \hideinitializer */
931 #define SYS_GPE_MFPL_PE3MFP_QEI0_A (0x0BUL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< Quadrature encoder phase A input of QEI Unit 0. \hideinitializer */
932 #define SYS_GPE_MFPL_PE3MFP_EPWM0_CH4 (0x0CUL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< EPWM0 channel4 output/capture input. \hideinitializer */
933 #define SYS_GPE_MFPL_PE3MFP_BPWM0_CH1 (0x0DUL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< BPWM0 channel1 output/capture input. \hideinitializer */
934 #define SYS_GPE_MFPL_PE4MFP_GPIO (0x00UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
935 #define SYS_GPE_MFPL_PE4MFP_EBI_nWR (0x02UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< EBI write enable output pin. \hideinitializer */
936 #define SYS_GPE_MFPL_PE4MFP_SD0_DAT2 (0x03UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< SD/SDIO 0 data line bit 2. \hideinitializer */
937 #define SYS_GPE_MFPL_PE4MFP_SPIM_CLK (0x04UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< SPIM serial clock pin. \hideinitializer */
938 #define SYS_GPE_MFPL_PE4MFP_SPI3_CLK (0x05UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< SPI3 serial clock pin. \hideinitializer */
939 #define SYS_GPE_MFPL_PE4MFP_SC0_RST (0x06UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< SmartCard0 reset pin. \hideinitializer */
940 #define SYS_GPE_MFPL_PE4MFP_USCI0_DAT1 (0x07UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< USCI0 data1 pin. \hideinitializer */
941 #define SYS_GPE_MFPL_PE4MFP_UART6_RXD (0x08UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< Data receiver input pin for UART6. \hideinitializer */
942 #define SYS_GPE_MFPL_PE4MFP_UART7_nCTS (0x09UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< Clear to Send input pin for UART7. \hideinitializer */
943 #define SYS_GPE_MFPL_PE4MFP_QEI0_INDEX (0x0BUL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< Quadrature encoder index input of QEI Unit 0. \hideinitializer */
944 #define SYS_GPE_MFPL_PE4MFP_EPWM0_CH3 (0x0CUL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< EPWM0 channel3 output/capture input. \hideinitializer */
945 #define SYS_GPE_MFPL_PE4MFP_BPWM0_CH2 (0x0DUL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< BPWM0 channel2 output/capture input. \hideinitializer */
946 #define SYS_GPE_MFPL_PE5MFP_GPIO (0x00UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
947 #define SYS_GPE_MFPL_PE5MFP_EBI_nRD (0x02UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< EBI read enable output pin. \hideinitializer */
948 #define SYS_GPE_MFPL_PE5MFP_SD0_DAT3 (0x03UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< SD/SDIO 0 data line bit 3. \hideinitializer */
949 #define SYS_GPE_MFPL_PE5MFP_SPIM_SS (0x04UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< 1st SPIM slave select pin. \hideinitializer */
950 #define SYS_GPE_MFPL_PE5MFP_SPI3_SS (0x05UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< 1st SPI3 slave select pin. \hideinitializer */
951 #define SYS_GPE_MFPL_PE5MFP_SC0_PWR (0x06UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< SmartCard0 power pin. \hideinitializer */
952 #define SYS_GPE_MFPL_PE5MFP_USCI0_CTL1 (0x07UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< USCI0 control1 pin. \hideinitializer */
953 #define SYS_GPE_MFPL_PE5MFP_UART6_TXD (0x08UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< Data transmitter output pin for UART6. \hideinitializer */
954 #define SYS_GPE_MFPL_PE5MFP_UART7_nRTS (0x09UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< Request to Send output pin for UART7. \hideinitializer */
955 #define SYS_GPE_MFPL_PE5MFP_QEI1_B (0x0BUL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< Quadrature encoder phase B input of QEI Unit 1. \hideinitializer */
956 #define SYS_GPE_MFPL_PE5MFP_EPWM0_CH2 (0x0CUL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< EPWM0 channel2 output/capture input. \hideinitializer */
957 #define SYS_GPE_MFPL_PE5MFP_BPWM0_CH3 (0x0DUL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< BPWM0 channel3 output/capture input. \hideinitializer */
958 #define SYS_GPE_MFPL_PE6MFP_GPIO (0x00UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
959 #define SYS_GPE_MFPL_PE6MFP_SD0_CLK (0x03UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< SD/SDIO 0 clock. \hideinitializer */
960 #define SYS_GPE_MFPL_PE6MFP_SPIM_D3 (0x04UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< SPIM data 3 pin for Quad Mode I/O. \hideinitializer */
961 #define SYS_GPE_MFPL_PE6MFP_SPI3_I2SMCLK (0x05UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< SPI3 I2S master clock output pin. \hideinitializer */
962 #define SYS_GPE_MFPL_PE6MFP_SC0_nCD (0x06UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< SmartCard0 card detect pin. \hideinitializer */
963 #define SYS_GPE_MFPL_PE6MFP_USCI0_CTL0 (0x07UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< USCI0 control0 pin. \hideinitializer */
964 #define SYS_GPE_MFPL_PE6MFP_UART5_RXD (0x08UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< Data receiver input pin for UART5. \hideinitializer */
965 #define SYS_GPE_MFPL_PE6MFP_CAN1_RXD (0x09UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< CAN1 bus receiver input. \hideinitializer */
966 #define SYS_GPE_MFPL_PE6MFP_QEI1_A (0x0BUL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< Quadrature encoder phase A input of QEI Unit 1. \hideinitializer */
967 #define SYS_GPE_MFPL_PE6MFP_EPWM0_CH1 (0x0CUL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< EPWM0 channel1 output/capture input. \hideinitializer */
968 #define SYS_GPE_MFPL_PE6MFP_BPWM0_CH4 (0x0DUL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< BPWM0 channel4 output/capture input. \hideinitializer */
969 #define SYS_GPE_MFPL_PE7MFP_GPIO (0x00UL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
970 #define SYS_GPE_MFPL_PE7MFP_SD0_CMD (0x03UL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< SD/SDIO 0 command/response. \hideinitializer */
971 #define SYS_GPE_MFPL_PE7MFP_SPIM_D2 (0x04UL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< SPIM data 2 pin for Quad Mode I/O. \hideinitializer */
972 #define SYS_GPE_MFPL_PE7MFP_UART5_TXD (0x08UL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< Data transmitter output pin for UART5. \hideinitializer */
973 #define SYS_GPE_MFPL_PE7MFP_CAN1_TXD (0x09UL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< CAN1 bus transmitter output. \hideinitializer */
974 #define SYS_GPE_MFPL_PE7MFP_QEI1_INDEX (0x0BUL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< Quadrature encoder index input of QEI Unit 1. \hideinitializer */
975 #define SYS_GPE_MFPL_PE7MFP_EPWM0_CH0 (0x0CUL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< EPWM0 channel0 output/capture input. \hideinitializer */
976 #define SYS_GPE_MFPL_PE7MFP_BPWM0_CH5 (0x0DUL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< BPWM0 channel5 output/capture input. \hideinitializer */
977 /********************* Bit definition of GPE_MFPH register **********************/
978 #define SYS_GPE_MFPH_PE8MFP_GPIO (0x00UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
979 #define SYS_GPE_MFPH_PE8MFP_EBI_ADR10 (0x02UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
980 #define SYS_GPE_MFPH_PE8MFP_EMAC_RMII_MDC (0x03UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< RMII Management Data Clock. \hideinitializer */
981 #define SYS_GPE_MFPH_PE8MFP_I2S0_BCLK (0x04UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< I2S0 bit clock pin. \hideinitializer */
982 #define SYS_GPE_MFPH_PE8MFP_SPI2_CLK (0x05UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< SPI2 serial clock pin. \hideinitializer */
983 #define SYS_GPE_MFPH_PE8MFP_USCI1_CTL1 (0x06UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< USCI1 control1 pin. \hideinitializer */
984 #define SYS_GPE_MFPH_PE8MFP_UART2_TXD (0x07UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< Data transmitter output pin for UART2. \hideinitializer */
985 #define SYS_GPE_MFPH_PE8MFP_EPWM0_CH0 (0x0AUL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< EPWM0 channel0 output/capture input. \hideinitializer */
986 #define SYS_GPE_MFPH_PE8MFP_EPWM0_BRAKE0 (0x0BUL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< Brake input pin 0 of EPWM0. \hideinitializer */
987 #define SYS_GPE_MFPH_PE8MFP_ECAP0_IC0 (0x0CUL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< Input 0 of enhanced capture unit 0. \hideinitializer */
988 #define SYS_GPE_MFPH_PE8MFP_TRACE_DATA3 (0x0EUL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< ETM Rx input bus bit3. \hideinitializer */
989 #define SYS_GPE_MFPH_PE9MFP_GPIO (0x00UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
990 #define SYS_GPE_MFPH_PE9MFP_EBI_ADR11 (0x02UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
991 #define SYS_GPE_MFPH_PE9MFP_EMAC_RMII_MDIO (0x03UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< RMII Management Data I/O. \hideinitializer */
992 #define SYS_GPE_MFPH_PE9MFP_I2S0_MCLK (0x04UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< I2S0 master clock output pin. \hideinitializer */
993 #define SYS_GPE_MFPH_PE9MFP_SPI2_MISO (0x05UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< 1st SPI2 MISO (Master In, Slave Out) pin. \hideinitializer */
994 #define SYS_GPE_MFPH_PE9MFP_USCI1_CTL0 (0x06UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< USCI1 control0 pin. \hideinitializer */
995 #define SYS_GPE_MFPH_PE9MFP_UART2_RXD (0x07UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< Data receiver input pin for UART2. \hideinitializer */
996 #define SYS_GPE_MFPH_PE9MFP_EPWM0_CH1 (0x0AUL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< EPWM0 channel1 output/capture input. \hideinitializer */
997 #define SYS_GPE_MFPH_PE9MFP_EPWM0_BRAKE1 (0x0BUL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< Brake input pin 1 of EPWM0. \hideinitializer */
998 #define SYS_GPE_MFPH_PE9MFP_ECAP0_IC1 (0x0CUL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< Input 1 of enhanced capture unit 0. \hideinitializer */
999 #define SYS_GPE_MFPH_PE9MFP_TRACE_DATA2 (0x0EUL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< ETM Rx input bus bit2. \hideinitializer */
1000 #define SYS_GPE_MFPH_PE10MFP_GPIO (0x00UL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
1001 #define SYS_GPE_MFPH_PE10MFP_EBI_ADR12 (0x02UL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
1002 #define SYS_GPE_MFPH_PE10MFP_EMAC_RMII_TXD0 (0x03UL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< RMII Transmit Data bus bit 0. \hideinitializer */
1003 #define SYS_GPE_MFPH_PE10MFP_I2S0_DI (0x04UL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< I2S0 data input. \hideinitializer */
1004 #define SYS_GPE_MFPH_PE10MFP_SPI2_MOSI (0x05UL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< 1st SPI2 MOSI (Master Out, Slave In) pin. \hideinitializer */
1005 #define SYS_GPE_MFPH_PE10MFP_USCI1_DAT0 (0x06UL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< USCI1 data0 pin. \hideinitializer */
1006 #define SYS_GPE_MFPH_PE10MFP_UART3_TXD (0x07UL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< Data transmitter output pin for UART3. \hideinitializer */
1007 #define SYS_GPE_MFPH_PE10MFP_EPWM0_CH2 (0x0AUL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< EPWM0 channel2 output/capture input. \hideinitializer */
1008 #define SYS_GPE_MFPH_PE10MFP_EPWM1_BRAKE0 (0x0BUL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< Brake input pin 0 of EPWM1. \hideinitializer */
1009 #define SYS_GPE_MFPH_PE10MFP_ECAP0_IC2 (0x0CUL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< Input 0 of enhanced capture unit 2. \hideinitializer */
1010 #define SYS_GPE_MFPH_PE10MFP_TRACE_DATA1 (0x0EUL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< ETM Rx input bus bit1. \hideinitializer */
1011 #define SYS_GPE_MFPH_PE11MFP_GPIO (0x00UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
1012 #define SYS_GPE_MFPH_PE11MFP_EBI_ADR13 (0x02UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
1013 #define SYS_GPE_MFPH_PE11MFP_EMAC_RMII_TXD1 (0x03UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< RMII Transmit Data bus bit 1. \hideinitializer */
1014 #define SYS_GPE_MFPH_PE11MFP_I2S0_DO (0x04UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< I2S0 data output. \hideinitializer */
1015 #define SYS_GPE_MFPH_PE11MFP_SPI2_SS (0x05UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< 1st SPI2 slave select pin. \hideinitializer */
1016 #define SYS_GPE_MFPH_PE11MFP_USCI1_DAT1 (0x06UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< USCI1 data1 pin. \hideinitializer */
1017 #define SYS_GPE_MFPH_PE11MFP_UART3_RXD (0x07UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< Data receiver input pin for UART3. \hideinitializer */
1018 #define SYS_GPE_MFPH_PE11MFP_UART1_nCTS (0x08UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< Clear to Send input pin for UART1. \hideinitializer */
1019 #define SYS_GPE_MFPH_PE11MFP_EPWM0_CH3 (0x0AUL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< EPWM0 channel3 output/capture input. \hideinitializer */
1020 #define SYS_GPE_MFPH_PE11MFP_EPWM1_BRAKE1 (0x0BUL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< Brake input pin 1 of EPWM1. \hideinitializer */
1021 #define SYS_GPE_MFPH_PE11MFP_ECAP1_IC2 (0x0DUL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< Input 1 of enhanced capture unit 2. \hideinitializer */
1022 #define SYS_GPE_MFPH_PE11MFP_TRACE_DATA0 (0x0EUL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< ETM Rx input bus bit0. \hideinitializer */
1023 #define SYS_GPE_MFPH_PE12MFP_GPIO (0x00UL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
1024 #define SYS_GPE_MFPH_PE12MFP_EBI_ADR14 (0x02UL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
1025 #define SYS_GPE_MFPH_PE12MFP_EMAC_RMII_TXEN (0x03UL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< RMII? Transmit Enable. \hideinitializer */
1026 #define SYS_GPE_MFPH_PE12MFP_I2S0_LRCK (0x04UL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< I2S0 left right channel clock. \hideinitializer */
1027 #define SYS_GPE_MFPH_PE12MFP_SPI2_I2SMCLK (0x05UL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< SPI2 I2S master clock output pin. \hideinitializer */
1028 #define SYS_GPE_MFPH_PE12MFP_USCI1_CLK (0x06UL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< USCI1 clock pin. \hideinitializer */
1029 #define SYS_GPE_MFPH_PE12MFP_UART1_nRTS (0x08UL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< Request to Send output pin for UART1. \hideinitializer */
1030 #define SYS_GPE_MFPH_PE12MFP_EPWM0_CH4 (0x0AUL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< EPWM0 channel4 output/capture input. \hideinitializer */
1031 #define SYS_GPE_MFPH_PE12MFP_ECAP1_IC1 (0x0DUL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< Input 1 of enhanced capture unit 1. \hideinitializer */
1032 #define SYS_GPE_MFPH_PE12MFP_TRACE_CLK (0x0EUL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< ETM Rx clock input pin. \hideinitializer */
1033 #define SYS_GPE_MFPH_PE13MFP_GPIO (0x00UL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
1034 #define SYS_GPE_MFPH_PE13MFP_EBI_ADR15 (0x02UL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
1035 #define SYS_GPE_MFPH_PE13MFP_EMAC_PPS (0x03UL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< EMAC Pulse Per Second output \hideinitializer */
1036 #define SYS_GPE_MFPH_PE13MFP_I2C0_SCL (0x04UL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< I2C0 clock pin. \hideinitializer */
1037 #define SYS_GPE_MFPH_PE13MFP_UART4_nRTS (0x05UL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< Request to Send output pin for UART4. \hideinitializer */
1038 #define SYS_GPE_MFPH_PE13MFP_UART1_TXD (0x08UL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< Data transmitter output pin for UART1. \hideinitializer */
1039 #define SYS_GPE_MFPH_PE13MFP_EPWM0_CH5 (0x0AUL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< EPWM0 channel5 output/capture input. \hideinitializer */
1040 #define SYS_GPE_MFPH_PE13MFP_EPWM1_CH0 (0x0BUL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< EPWM1 channel0 output/capture input. \hideinitializer */
1041 #define SYS_GPE_MFPH_PE13MFP_BPWM1_CH5 (0x0CUL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< BPWM1 channel5 output/capture input. \hideinitializer */
1042 #define SYS_GPE_MFPH_PE13MFP_ECAP1_IC0 (0x0DUL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< Input 0 of enhanced capture unit 1. \hideinitializer */
1043 #define SYS_GPE_MFPH_PE14MFP_GPIO (0x00UL<<SYS_GPE_MFPH_PE14MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
1044 #define SYS_GPE_MFPH_PE14MFP_EBI_AD8 (0x02UL<<SYS_GPE_MFPH_PE14MFP_Pos) /*!< EBI address/data bus bit8. \hideinitializer */
1045 #define SYS_GPE_MFPH_PE14MFP_UART2_TXD (0x03UL<<SYS_GPE_MFPH_PE14MFP_Pos) /*!< Data transmitter output pin for UART2. \hideinitializer */
1046 #define SYS_GPE_MFPH_PE14MFP_CAN0_TXD (0x04UL<<SYS_GPE_MFPH_PE14MFP_Pos) /*!< CAN0 bus transmitter output. \hideinitializer */
1047 #define SYS_GPE_MFPH_PE14MFP_SD1_nCD (0x05UL<<SYS_GPE_MFPH_PE14MFP_Pos) /*!< SD/SDIO 1 card detect \hideinitializer */
1048 #define SYS_GPE_MFPH_PE14MFP_UART6_TXD (0x06UL<<SYS_GPE_MFPH_PE14MFP_Pos) /*!< Data transmitter output pin for UART6. */
1049 #define SYS_GPE_MFPH_PE15MFP_GPIO (0x00UL<<SYS_GPE_MFPH_PE15MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
1050 #define SYS_GPE_MFPH_PE15MFP_EBI_AD9 (0x02UL<<SYS_GPE_MFPH_PE15MFP_Pos) /*!< EBI address/data bus bit9. \hideinitializer */
1051 #define SYS_GPE_MFPH_PE15MFP_UART2_RXD (0x03UL<<SYS_GPE_MFPH_PE15MFP_Pos) /*!< Data receiver input pin for UART2. \hideinitializer */
1052 #define SYS_GPE_MFPH_PE15MFP_CAN0_RXD (0x04UL<<SYS_GPE_MFPH_PE15MFP_Pos) /*!< CAN0 bus receiver input. \hideinitializer */
1053 #define SYS_GPE_MFPH_PE15MFP_UART6_RXD (0x06UL<<SYS_GPE_MFPH_PE15MFP_Pos) /*!< Data receiver input pin for UART6. \hideinitializer */
1054 /********************* Bit definition of GPF_MFPL register **********************/
1055 #define SYS_GPF_MFPL_PF0MFP_GPIO (0x00UL<<SYS_GPF_MFPL_PF0MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
1056 #define SYS_GPF_MFPL_PF0MFP_UART1_TXD (0x02UL<<SYS_GPF_MFPL_PF0MFP_Pos) /*!< Data transmitter output pin for UART1. \hideinitializer */
1057 #define SYS_GPF_MFPL_PF0MFP_I2C1_SCL (0x03UL<<SYS_GPF_MFPL_PF0MFP_Pos) /*!< I2C1 clock pin. \hideinitializer */
1058 #define SYS_GPF_MFPL_PF0MFP_UART0_TXD (0x04UL<<SYS_GPF_MFPL_PF0MFP_Pos) /*!< Data transmitter output pin for UART0. \hideinitializer */
1059 #define SYS_GPF_MFPL_PF0MFP_BPWM1_CH0 (0x0CUL<<SYS_GPF_MFPL_PF0MFP_Pos) /*!< BPWM1 channel0 output/capture input. \hideinitializer */
1060 #define SYS_GPF_MFPL_PF0MFP_ICE_DAT (0x0EUL<<SYS_GPF_MFPL_PF0MFP_Pos) /*!< Serial wired debugger data pin. \hideinitializer */
1061 #define SYS_GPF_MFPL_PF1MFP_GPIO (0x00UL<<SYS_GPF_MFPL_PF1MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
1062 #define SYS_GPF_MFPL_PF1MFP_UART1_RXD (0x02UL<<SYS_GPF_MFPL_PF1MFP_Pos) /*!< Data receiver input pin for UART1. \hideinitializer */
1063 #define SYS_GPF_MFPL_PF1MFP_I2C1_SDA (0x03UL<<SYS_GPF_MFPL_PF1MFP_Pos) /*!< I2C1 data input/output pin. \hideinitializer */
1064 #define SYS_GPF_MFPL_PF1MFP_UART0_RXD (0x04UL<<SYS_GPF_MFPL_PF1MFP_Pos) /*!< Data receiver input pin for UART0. \hideinitializer */
1065 #define SYS_GPF_MFPL_PF1MFP_BPWM1_CH1 (0x0CUL<<SYS_GPF_MFPL_PF1MFP_Pos) /*!< BPWM1 channel1 output/capture input. \hideinitializer */
1066 #define SYS_GPF_MFPL_PF1MFP_ICE_CLK (0x0EUL<<SYS_GPF_MFPL_PF1MFP_Pos) /*!< Serial wired debugger clock pin. \hideinitializer */
1067 #define SYS_GPF_MFPL_PF2MFP_GPIO (0x00UL<<SYS_GPF_MFPL_PF2MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
1068 #define SYS_GPF_MFPL_PF2MFP_EBI_nCS1 (0x02UL<<SYS_GPF_MFPL_PF2MFP_Pos) /*!< EBI chip select enable output pin. \hideinitializer */
1069 #define SYS_GPF_MFPL_PF2MFP_UART0_RXD (0x03UL<<SYS_GPF_MFPL_PF2MFP_Pos) /*!< Data receiver input pin for UART0. \hideinitializer */
1070 #define SYS_GPF_MFPL_PF2MFP_I2C0_SDA (0x04UL<<SYS_GPF_MFPL_PF2MFP_Pos) /*!< I2C0 data input/output pin. \hideinitializer */
1071 #define SYS_GPF_MFPL_PF2MFP_QSPI0_CLK (0x05UL<<SYS_GPF_MFPL_PF2MFP_Pos) /*!< QSPI0 serial clock pin. \hideinitializer */
1072 #define SYS_GPF_MFPL_PF2MFP_XT1_OUT (0x0AUL<<SYS_GPF_MFPL_PF2MFP_Pos) /*!< External 4~24 MHz (high speed) crystal output pin. \hideinitializer */
1073 #define SYS_GPF_MFPL_PF2MFP_BPWM1_CH1 (0x0BUL<<SYS_GPF_MFPL_PF2MFP_Pos) /*!< BPWM1 channel1 output/capture input. \hideinitializer */
1074 #define SYS_GPF_MFPL_PF3MFP_GPIO (0x00UL<<SYS_GPF_MFPL_PF3MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
1075 #define SYS_GPF_MFPL_PF3MFP_EBI_nCS0 (0x02UL<<SYS_GPF_MFPL_PF3MFP_Pos) /*!< EBI chip select enable output pin. \hideinitializer */
1076 #define SYS_GPF_MFPL_PF3MFP_UART0_TXD (0x03UL<<SYS_GPF_MFPL_PF3MFP_Pos) /*!< Data transmitter output pin for UART0. \hideinitializer */
1077 #define SYS_GPF_MFPL_PF3MFP_I2C0_SCL (0x04UL<<SYS_GPF_MFPL_PF3MFP_Pos) /*!< I2C0 clock pin. \hideinitializer */
1078 #define SYS_GPF_MFPL_PF3MFP_XT1_IN (0x0AUL<<SYS_GPF_MFPL_PF3MFP_Pos) /*!< External 4~24 MHz (high speed) crystal input pin. \hideinitializer */
1079 #define SYS_GPF_MFPL_PF3MFP_BPWM1_CH0 (0x0BUL<<SYS_GPF_MFPL_PF3MFP_Pos) /*!< BPWM1 channel0 output/capture input. \hideinitializer */
1080 #define SYS_GPF_MFPL_PF4MFP_GPIO (0x00UL<<SYS_GPF_MFPL_PF4MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
1081 #define SYS_GPF_MFPL_PF4MFP_UART2_TXD (0x02UL<<SYS_GPF_MFPL_PF4MFP_Pos) /*!< Data transmitter output pin for UART2. \hideinitializer */
1082 #define SYS_GPF_MFPL_PF4MFP_UART2_nRTS (0x04UL<<SYS_GPF_MFPL_PF4MFP_Pos) /*!< Request to Send output pin for UART2. \hideinitializer */
1083 #define SYS_GPF_MFPL_PF4MFP_EPWM0_CH1 (0x07UL<<SYS_GPF_MFPL_PF4MFP_Pos) /*!< EPWM0 channel1 output/capture input. \hideinitializer */
1084 #define SYS_GPF_MFPL_PF4MFP_BPWM0_CH5 (0x08UL<<SYS_GPF_MFPL_PF4MFP_Pos) /*!< BPWM0 channel5 output/capture input. \hideinitializer */
1085 #define SYS_GPF_MFPL_PF4MFP_X32_OUT (0x0AUL<<SYS_GPF_MFPL_PF4MFP_Pos) /*!< External 32.768 kHz (low speed) crystal output pin. \hideinitializer */
1086 #define SYS_GPF_MFPL_PF4MFP_EADC1_ST (0x0BUL<<SYS_GPF_MFPL_PF4MFP_Pos) /*!< EADC external trigger input. \hideinitializer */
1087 #define SYS_GPF_MFPL_PF5MFP_GPIO (0x00UL<<SYS_GPF_MFPL_PF5MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
1088 #define SYS_GPF_MFPL_PF5MFP_UART2_RXD (0x02UL<<SYS_GPF_MFPL_PF5MFP_Pos) /*!< Data receiver input pin for UART2. \hideinitializer */
1089 #define SYS_GPF_MFPL_PF5MFP_UART2_nCTS (0x04UL<<SYS_GPF_MFPL_PF5MFP_Pos) /*!< Clear to Send input pin for UART2. \hideinitializer */
1090 #define SYS_GPF_MFPL_PF5MFP_EPWM0_CH0 (0x07UL<<SYS_GPF_MFPL_PF5MFP_Pos) /*!< EPWM0 channel0 output/capture input. \hideinitializer */
1091 #define SYS_GPF_MFPL_PF5MFP_BPWM0_CH4 (0x08UL<<SYS_GPF_MFPL_PF5MFP_Pos) /*!< BPWM0 channel4 output/capture input. \hideinitializer */
1092 #define SYS_GPF_MFPL_PF5MFP_EPWM0_SYNC_OUT (0x09UL<<SYS_GPF_MFPL_PF5MFP_Pos) /*!< EPWM0 counter synchronous trigger output pin. \hideinitializer */
1093 #define SYS_GPF_MFPL_PF5MFP_X32_IN (0x0AUL<<SYS_GPF_MFPL_PF5MFP_Pos) /*!< External 32.768 kHz (low speed) crystal input pin. \hideinitializer */
1094 #define SYS_GPF_MFPL_PF5MFP_EADC0_ST (0x0BUL<<SYS_GPF_MFPL_PF5MFP_Pos) /*!< EADC external trigger input. \hideinitializer */
1095 #define SYS_GPF_MFPL_PF6MFP_GPIO (0x00UL<<SYS_GPF_MFPL_PF6MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
1096 #define SYS_GPF_MFPL_PF6MFP_EBI_ADR19 (0x02UL<<SYS_GPF_MFPL_PF6MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
1097 #define SYS_GPF_MFPL_PF6MFP_SC0_CLK (0x03UL<<SYS_GPF_MFPL_PF6MFP_Pos) /*!< SmartCard0 clock pin. \hideinitializer */
1098 #define SYS_GPF_MFPL_PF6MFP_I2S0_LRCK (0x04UL<<SYS_GPF_MFPL_PF6MFP_Pos) /*!< I2S0 left right channel clock. \hideinitializer */
1099 #define SYS_GPF_MFPL_PF6MFP_SPI0_MOSI (0x05UL<<SYS_GPF_MFPL_PF6MFP_Pos) /*!< 1st SPI0 MOSI (Master Out, Slave In) pin. \hideinitializer */
1100 #define SYS_GPF_MFPL_PF6MFP_UART4_RXD (0x06UL<<SYS_GPF_MFPL_PF6MFP_Pos) /*!< Data receiver input pin for UART4. \hideinitializer */
1101 #define SYS_GPF_MFPL_PF6MFP_EBI_nCS0 (0x07UL<<SYS_GPF_MFPL_PF6MFP_Pos) /*!< EBI chip select enable output pin. \hideinitializer */
1102 #define SYS_GPF_MFPL_PF6MFP_CAN2_RXD (0x08UL<<SYS_GPF_MFPL_PF6MFP_Pos) /*!< CAN2 bus receiver input. \hideinitializer */
1103 #define SYS_GPF_MFPL_PF6MFP_TAMPER0 (0x0AUL<<SYS_GPF_MFPL_PF6MFP_Pos) /*!< TAMPER detector loop pin0. \hideinitializer */
1104 #define SYS_GPF_MFPL_PF7MFP_GPIO (0x00UL<<SYS_GPF_MFPL_PF7MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
1105 #define SYS_GPF_MFPL_PF7MFP_EBI_ADR18 (0x02UL<<SYS_GPF_MFPL_PF7MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
1106 #define SYS_GPF_MFPL_PF7MFP_SC0_DAT (0x03UL<<SYS_GPF_MFPL_PF7MFP_Pos) /*!< SmartCard0 data pin. \hideinitializer */
1107 #define SYS_GPF_MFPL_PF7MFP_I2S0_DO (0x04UL<<SYS_GPF_MFPL_PF7MFP_Pos) /*!< I2S0 data output. \hideinitializer */
1108 #define SYS_GPF_MFPL_PF7MFP_SPI0_MISO (0x05UL<<SYS_GPF_MFPL_PF7MFP_Pos) /*!< 1st SPI0 MISO (Master In, Slave Out) pin. \hideinitializer */
1109 #define SYS_GPF_MFPL_PF7MFP_UART4_TXD (0x06UL<<SYS_GPF_MFPL_PF7MFP_Pos) /*!< Data transmitter output pin for UART4. \hideinitializer */
1110 #define SYS_GPF_MFPL_PF7MFP_CCAP_DATA0 (0x07UL<<SYS_GPF_MFPL_PF7MFP_Pos) /*!< Sensor pixel data0 input pin. */
1111 #define SYS_GPF_MFPL_PF7MFP_CAN2_TXD (0x08UL<<SYS_GPF_MFPL_PF7MFP_Pos) /*!< CAN2 bus transmitter output. */
1112 #define SYS_GPF_MFPL_PF7MFP_TAMPER1 (0x0AUL<<SYS_GPF_MFPL_PF7MFP_Pos) /*!< TAMPER detector loop pin1. \hideinitializer */
1113 /********************* Bit definition of GPF_MFPH register **********************/
1114 #define SYS_GPF_MFPH_PF8MFP_GPIO (0x00UL<<SYS_GPF_MFPH_PF8MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
1115 #define SYS_GPF_MFPH_PF8MFP_EBI_ADR17 (0x02UL<<SYS_GPF_MFPH_PF8MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
1116 #define SYS_GPF_MFPH_PF8MFP_SC0_RST (0x03UL<<SYS_GPF_MFPH_PF8MFP_Pos) /*!< SmartCard0 reset pin. \hideinitializer */
1117 #define SYS_GPF_MFPH_PF8MFP_I2S0_DI (0x04UL<<SYS_GPF_MFPH_PF8MFP_Pos) /*!< I2S0 data input. \hideinitializer */
1118 #define SYS_GPF_MFPH_PF8MFP_SPI0_CLK (0x05UL<<SYS_GPF_MFPH_PF8MFP_Pos) /*!< SPI0 serial clock pin. \hideinitializer */
1119 #define SYS_GPF_MFPH_PF8MFP_UART5_nCTS (0x06UL<<SYS_GPF_MFPH_PF8MFP_Pos) /*!< Clear to Send input pin for UART5. \hideinitializer */
1120 #define SYS_GPF_MFPH_PF8MFP_CCAP_DATA1 (0x07UL<<SYS_GPF_MFPH_PF8MFP_Pos) /*!< Sensor pixel data1 input pin. \hideinitializer */
1121 #define SYS_GPF_MFPH_PF8MFP_CAN1_RXD (0x08UL<<SYS_GPF_MFPH_PF8MFP_Pos) /*!< CAN1 bus receiver input. */
1122 #define SYS_GPF_MFPH_PF8MFP_TAMPER2 (0x0AUL<<SYS_GPF_MFPH_PF8MFP_Pos) /*!< TAMPER detector loop pin2. \hideinitializer */
1123 #define SYS_GPF_MFPH_PF9MFP_GPIO (0x00UL<<SYS_GPF_MFPH_PF9MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
1124 #define SYS_GPF_MFPH_PF9MFP_EBI_ADR16 (0x02UL<<SYS_GPF_MFPH_PF9MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
1125 #define SYS_GPF_MFPH_PF9MFP_SC0_PWR (0x03UL<<SYS_GPF_MFPH_PF9MFP_Pos) /*!< SmartCard0 power pin. \hideinitializer */
1126 #define SYS_GPF_MFPH_PF9MFP_I2S0_MCLK (0x04UL<<SYS_GPF_MFPH_PF9MFP_Pos) /*!< I2S0 master clock output pin. \hideinitializer */
1127 #define SYS_GPF_MFPH_PF9MFP_SPI0_SS (0x05UL<<SYS_GPF_MFPH_PF9MFP_Pos) /*!< 1st SPI0 slave select pin. \hideinitializer */
1128 #define SYS_GPF_MFPH_PF9MFP_UART5_nRTS (0x06UL<<SYS_GPF_MFPH_PF9MFP_Pos) /*!< Request to Send output pin for UART5. \hideinitializer */
1129 #define SYS_GPF_MFPH_PF9MFP_CCAP_DATA2 (0x07UL<<SYS_GPF_MFPH_PF9MFP_Pos) /*!< Sensor pixel data2 input pin. \hideinitializer */
1130 #define SYS_GPF_MFPH_PF9MFP_CAN1_TXD (0x08UL<<SYS_GPF_MFPH_PF9MFP_Pos) /*!< CAN1 bus transmitter output. \hideinitializer */
1131 #define SYS_GPF_MFPH_PF9MFP_TAMPER3 (0x0AUL<<SYS_GPF_MFPH_PF9MFP_Pos) /*!< TAMPER detector loop pin3. \hideinitializer */
1132 #define SYS_GPF_MFPH_PF10MFP_GPIO (0x00UL<<SYS_GPF_MFPH_PF10MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
1133 #define SYS_GPF_MFPH_PF10MFP_EBI_ADR15 (0x02UL<<SYS_GPF_MFPH_PF10MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
1134 #define SYS_GPF_MFPH_PF10MFP_SC0_nCD (0x03UL<<SYS_GPF_MFPH_PF10MFP_Pos) /*!< SmartCard0 card detect pin. \hideinitializer */
1135 #define SYS_GPF_MFPH_PF10MFP_I2S0_BCLK (0x04UL<<SYS_GPF_MFPH_PF10MFP_Pos) /*!< I2S0 bit clock pin. \hideinitializer */
1136 #define SYS_GPF_MFPH_PF10MFP_SPI0_I2SMCLK (0x05UL<<SYS_GPF_MFPH_PF10MFP_Pos) /*!< SPI0 I2S master clock output pin. \hideinitializer */
1137 #define SYS_GPF_MFPH_PF10MFP_UART5_RXD (0x06UL<<SYS_GPF_MFPH_PF10MFP_Pos) /*!< Data receiver input pin for UART5. \hideinitializer */
1138 #define SYS_GPF_MFPH_PF10MFP_CCAP_DATA3 (0x07UL<<SYS_GPF_MFPH_PF10MFP_Pos) /*!< Sensor pixel data3 input pin. \hideinitializer */
1139 #define SYS_GPF_MFPH_PF10MFP_TAMPER4 (0x0AUL<<SYS_GPF_MFPH_PF10MFP_Pos) /*!< TAMPER detector loop pin4. \hideinitializer */
1140 #define SYS_GPF_MFPH_PF11MFP_GPIO (0x00UL<<SYS_GPF_MFPH_PF11MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
1141 #define SYS_GPF_MFPH_PF11MFP_EBI_ADR14 (0x02UL<<SYS_GPF_MFPH_PF11MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
1142 #define SYS_GPF_MFPH_PF11MFP_SPI2_MOSI (0x03UL<<SYS_GPF_MFPH_PF11MFP_Pos) /*!< 1st SPI2 MOSI (Master Out, Slave In) pin. \hideinitializer */
1143 #define SYS_GPF_MFPH_PF11MFP_UART5_TXD (0x06UL<<SYS_GPF_MFPH_PF11MFP_Pos) /*!< Data transmitter output pin for UART5. \hideinitializer */
1144 #define SYS_GPF_MFPH_PF11MFP_CCAP_DATA4 (0x07UL<<SYS_GPF_MFPH_PF11MFP_Pos) /*!< Sensor pixel data4 input pin. \hideinitializer */
1145 #define SYS_GPF_MFPH_PF11MFP_TAMPER5 (0x0AUL<<SYS_GPF_MFPH_PF11MFP_Pos) /*!< TAMPER detector loop pin5. \hideinitializer */
1146 #define SYS_GPF_MFPH_PF11MFP_TM3 (0x0DUL<<SYS_GPF_MFPH_PF11MFP_Pos) /*!< Timer3 event counter input / toggle output \hideinitializer */
1147 /********************* Bit definition of GPG_MFPL register **********************/
1148 #define SYS_GPG_MFPL_PG0MFP_GPIO (0x00UL<<SYS_GPG_MFPL_PG0MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
1149 #define SYS_GPG_MFPL_PG0MFP_EBI_ADR8 (0x02UL<<SYS_GPG_MFPL_PG0MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
1150 #define SYS_GPG_MFPL_PG0MFP_I2C0_SCL (0x04UL<<SYS_GPG_MFPL_PG0MFP_Pos) /*!< I2C0 clock pin. \hideinitializer */
1151 #define SYS_GPG_MFPL_PG0MFP_I2C1_SMBAL (0x05UL<<SYS_GPG_MFPL_PG0MFP_Pos) /*!< I2C1 SMBus SMBALTER# pin \hideinitializer */
1152 #define SYS_GPG_MFPL_PG0MFP_UART2_RXD (0x06UL<<SYS_GPG_MFPL_PG0MFP_Pos) /*!< Data receiver input pin for UART2. \hideinitializer */
1153 #define SYS_GPG_MFPL_PG0MFP_CAN1_TXD (0x07UL<<SYS_GPG_MFPL_PG0MFP_Pos) /*!< CAN1 bus transmitter output. \hideinitializer */
1154 #define SYS_GPG_MFPL_PG0MFP_UART1_TXD (0x08UL<<SYS_GPG_MFPL_PG0MFP_Pos) /*!< Data transmitter output pin for UART1. \hideinitializer */
1155 #define SYS_GPG_MFPL_PG1MFP_GPIO (0x00UL<<SYS_GPG_MFPL_PG1MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
1156 #define SYS_GPG_MFPL_PG1MFP_EBI_ADR9 (0x02UL<<SYS_GPG_MFPL_PG1MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
1157 #define SYS_GPG_MFPL_PG1MFP_SPI2_I2SMCLK (0x03UL<<SYS_GPG_MFPL_PG1MFP_Pos) /*!< SPI2 I2S master clock output pin. \hideinitializer */
1158 #define SYS_GPG_MFPL_PG1MFP_I2C0_SDA (0x04UL<<SYS_GPG_MFPL_PG1MFP_Pos) /*!< I2C0 data input/output pin. \hideinitializer */
1159 #define SYS_GPG_MFPL_PG1MFP_I2C1_SMBSUS (0x05UL<<SYS_GPG_MFPL_PG1MFP_Pos) /*!< I2C1 SMBus SMBSUS# pin (PMBus CONTROL pin) \hideinitializer */
1160 #define SYS_GPG_MFPL_PG1MFP_UART2_TXD (0x06UL<<SYS_GPG_MFPL_PG1MFP_Pos) /*!< Data transmitter output pin for UART2. \hideinitializer */
1161 #define SYS_GPG_MFPL_PG1MFP_CAN1_RXD (0x07UL<<SYS_GPG_MFPL_PG1MFP_Pos) /*!< CAN1 bus receiver input. \hideinitializer */
1162 #define SYS_GPG_MFPL_PG1MFP_UART1_RXD (0x08UL<<SYS_GPG_MFPL_PG1MFP_Pos) /*!< Data receiver input pin for UART1. \hideinitializer */
1163 #define SYS_GPG_MFPL_PG2MFP_GPIO (0x00UL<<SYS_GPG_MFPL_PG2MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
1164 #define SYS_GPG_MFPL_PG2MFP_EBI_ADR11 (0x02UL<<SYS_GPG_MFPL_PG2MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
1165 #define SYS_GPG_MFPL_PG2MFP_SPI2_SS (0x03UL<<SYS_GPG_MFPL_PG2MFP_Pos) /*!< 1st SPI2 slave select pin. \hideinitializer */
1166 #define SYS_GPG_MFPL_PG2MFP_I2C0_SMBAL (0x04UL<<SYS_GPG_MFPL_PG2MFP_Pos) /*!< I2C0 SMBus SMBALTER# pin \hideinitializer */
1167 #define SYS_GPG_MFPL_PG2MFP_I2C1_SCL (0x05UL<<SYS_GPG_MFPL_PG2MFP_Pos) /*!< I2C1 clock pin. \hideinitializer */
1168 #define SYS_GPG_MFPL_PG2MFP_CCAP_DATA7 (0x07UL<<SYS_GPG_MFPL_PG2MFP_Pos) /*!< Sensor pixel data7 input pin. \hideinitializer */
1169 #define SYS_GPG_MFPL_PG2MFP_TM0 (0x0DUL<<SYS_GPG_MFPL_PG2MFP_Pos) /*!< Timer0 event counter input / toggle output \hideinitializer */
1170 #define SYS_GPG_MFPL_PG3MFP_GPIO (0x00UL<<SYS_GPG_MFPL_PG3MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
1171 #define SYS_GPG_MFPL_PG3MFP_EBI_ADR12 (0x02UL<<SYS_GPG_MFPL_PG3MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
1172 #define SYS_GPG_MFPL_PG3MFP_SPI2_CLK (0x03UL<<SYS_GPG_MFPL_PG3MFP_Pos) /*!< SPI2 serial clock pin. \hideinitializer */
1173 #define SYS_GPG_MFPL_PG3MFP_I2C0_SMBSUS (0x04UL<<SYS_GPG_MFPL_PG3MFP_Pos) /*!< I2C0 SMBus SMBSUS# pin (PMBus CONTROL pin) \hideinitializer */
1174 #define SYS_GPG_MFPL_PG3MFP_I2C1_SDA (0x05UL<<SYS_GPG_MFPL_PG3MFP_Pos) /*!< I2C1 data input/output pin. \hideinitializer */
1175 #define SYS_GPG_MFPL_PG3MFP_CCAP_DATA6 (0x07UL<<SYS_GPG_MFPL_PG3MFP_Pos) /*!< Sensor pixel data6 input pin. \hideinitializer */
1176 #define SYS_GPG_MFPL_PG3MFP_TM1 (0x0DUL<<SYS_GPG_MFPL_PG3MFP_Pos) /*!< Timer1 event counter input / toggle output \hideinitializer */
1177 #define SYS_GPG_MFPL_PG4MFP_GPIO (0x00UL<<SYS_GPG_MFPL_PG4MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
1178 #define SYS_GPG_MFPL_PG4MFP_EBI_ADR13 (0x02UL<<SYS_GPG_MFPL_PG4MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
1179 #define SYS_GPG_MFPL_PG4MFP_SPI2_MISO (0x03UL<<SYS_GPG_MFPL_PG4MFP_Pos) /*!< 1st SPI2 MISO (Master In, Slave Out) pin. \hideinitializer */
1180 #define SYS_GPG_MFPL_PG4MFP_CCAP_DATA5 (0x07UL<<SYS_GPG_MFPL_PG4MFP_Pos) /*!< Sensor pixel data5 input pin. \hideinitializer */
1181 #define SYS_GPG_MFPL_PG4MFP_TM2 (0x0DUL<<SYS_GPG_MFPL_PG4MFP_Pos) /*!< Timer2 event counter input / toggle output \hideinitializer */
1182 #define SYS_GPG_MFPL_PG5MFP_GPIO (0x00UL<<SYS_GPG_MFPL_PG5MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
1183 #define SYS_GPG_MFPL_PG5MFP_EBI_nCS1 (0x02UL<<SYS_GPG_MFPL_PG5MFP_Pos) /*!< EBI chip select enable output pin. \hideinitializer */
1184 #define SYS_GPG_MFPL_PG5MFP_SPI3_SS (0x03UL<<SYS_GPG_MFPL_PG5MFP_Pos) /*!< 1st SPI3 slave select pin. \hideinitializer */
1185 #define SYS_GPG_MFPL_PG5MFP_SC1_PWR (0x04UL<<SYS_GPG_MFPL_PG5MFP_Pos) /*!< SmartCard1 power pin. \hideinitializer */
1186 #define SYS_GPG_MFPL_PG5MFP_EPWM0_CH3 (0x0BUL<<SYS_GPG_MFPL_PG5MFP_Pos) /*!< EPWM0 channel3 output/capture input. \hideinitializer */
1187 #define SYS_GPG_MFPL_PG6MFP_GPIO (0x00UL<<SYS_GPG_MFPL_PG6MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
1188 #define SYS_GPG_MFPL_PG6MFP_EBI_nCS2 (0x02UL<<SYS_GPG_MFPL_PG6MFP_Pos) /*!< EBI chip select enable output pin. \hideinitializer */
1189 #define SYS_GPG_MFPL_PG6MFP_SPI3_CLK (0x03UL<<SYS_GPG_MFPL_PG6MFP_Pos) /*!< SPI3 serial clock pin. \hideinitializer */
1190 #define SYS_GPG_MFPL_PG6MFP_SC1_RST (0x04UL<<SYS_GPG_MFPL_PG6MFP_Pos) /*!< SmartCard1 reset pin. \hideinitializer */
1191 #define SYS_GPG_MFPL_PG6MFP_EPWM0_CH2 (0x0BUL<<SYS_GPG_MFPL_PG6MFP_Pos) /*!< EPWM0 channel2 output/capture input. \hideinitializer */
1192 #define SYS_GPG_MFPL_PG7MFP_GPIO (0x00UL<<SYS_GPG_MFPL_PG7MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
1193 #define SYS_GPG_MFPL_PG7MFP_EBI_nWRL (0x02UL<<SYS_GPG_MFPL_PG7MFP_Pos) /*!< EBI write enable output pin. \hideinitializer */
1194 #define SYS_GPG_MFPL_PG7MFP_SPI3_MISO (0x03UL<<SYS_GPG_MFPL_PG7MFP_Pos) /*!< 1st SPI3 MISO (Master In, Slave Out) pin. \hideinitializer */
1195 #define SYS_GPG_MFPL_PG7MFP_SC1_DAT (0x04UL<<SYS_GPG_MFPL_PG7MFP_Pos) /*!< SmartCard1 data pin. \hideinitializer */
1196 #define SYS_GPG_MFPL_PG7MFP_EPWM0_CH1 (0x0BUL<<SYS_GPG_MFPL_PG7MFP_Pos) /*!< EPWM0 channel1 output/capture input. \hideinitializer */
1197 /********************* Bit definition of GPG_MFPH register **********************/
1198 #define SYS_GPG_MFPH_PG8MFP_GPIO (0x00UL<<SYS_GPG_MFPH_PG8MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
1199 #define SYS_GPG_MFPH_PG8MFP_EBI_nWRH (0x02UL<<SYS_GPG_MFPH_PG8MFP_Pos) /*!< EBI write enable output pin. \hideinitializer */
1200 #define SYS_GPG_MFPH_PG8MFP_SPI3_MOSI (0x03UL<<SYS_GPG_MFPH_PG8MFP_Pos) /*!< 1st SPI3 MOSI (Master Out, Slave In) pin. \hideinitializer */
1201 #define SYS_GPG_MFPH_PG8MFP_SC1_CLK (0x04UL<<SYS_GPG_MFPH_PG8MFP_Pos) /*!< SmartCard1 clock pin. \hideinitializer */
1202 #define SYS_GPG_MFPH_PG8MFP_EPWM0_CH0 (0x0BUL<<SYS_GPG_MFPH_PG8MFP_Pos) /*!< EPWM0 channel0 output/capture input. \hideinitializer */
1203 #define SYS_GPG_MFPH_PG9MFP_GPIO (0x00UL<<SYS_GPG_MFPH_PG9MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
1204 #define SYS_GPG_MFPH_PG9MFP_EBI_AD0 (0x02UL<<SYS_GPG_MFPH_PG9MFP_Pos) /*!< EBI address/data bus bit0. \hideinitializer */
1205 #define SYS_GPG_MFPH_PG9MFP_SD1_DAT3 (0x03UL<<SYS_GPG_MFPH_PG9MFP_Pos) /*!< SD/SDIO 1 data line bit 3. \hideinitializer */
1206 #define SYS_GPG_MFPH_PG9MFP_SPIM_D2 (0x04UL<<SYS_GPG_MFPH_PG9MFP_Pos) /*!< SPIM data 2 pin for Quad Mode I/O. \hideinitializer */
1207 #define SYS_GPG_MFPH_PG9MFP_QSPI1_MISO1 (0x05UL<<SYS_GPG_MFPH_PG9MFP_Pos) /*!< 2nd QSPI1 MISO (Master In, Slave Out) pin. \hideinitializer */
1208 #define SYS_GPG_MFPH_PG9MFP_CCAP_PIXCLK (0x07UL<<SYS_GPG_MFPH_PG9MFP_Pos) /*!< Sensor pixel clock(from sensor) input pin. \hideinitializer */
1209 #define SYS_GPG_MFPH_PG9MFP_BPWM0_CH5 (0x0CUL<<SYS_GPG_MFPH_PG9MFP_Pos) /*!< BPWM0 channel5 output/capture input. \hideinitializer */
1210 #define SYS_GPG_MFPH_PG10MFP_GPIO (0x00UL<<SYS_GPG_MFPH_PG10MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
1211 #define SYS_GPG_MFPH_PG10MFP_EBI_AD1 (0x02UL<<SYS_GPG_MFPH_PG10MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */
1212 #define SYS_GPG_MFPH_PG10MFP_SD1_DAT2 (0x03UL<<SYS_GPG_MFPH_PG10MFP_Pos) /*!< SD/SDIO 1 data line bit 2. \hideinitializer */
1213 #define SYS_GPG_MFPH_PG10MFP_SPIM_D3 (0x04UL<<SYS_GPG_MFPH_PG10MFP_Pos) /*!< SPIM data 3 pin for Quad Mode I/O. \hideinitializer */
1214 #define SYS_GPG_MFPH_PG10MFP_QSPI1_MOSI1 (0x05UL<<SYS_GPG_MFPH_PG10MFP_Pos) /*!< 2nd QSPI1 MOSI (Master Out, Slave In) pin. \hideinitializer */
1215 #define SYS_GPG_MFPH_PG10MFP_CCAP_SCLK (0x07UL<<SYS_GPG_MFPH_PG10MFP_Pos) /*!< Sensor pixel clock(to sensor) output pin. \hideinitializer */
1216 #define SYS_GPG_MFPH_PG10MFP_BPWM0_CH4 (0x0CUL<<SYS_GPG_MFPH_PG10MFP_Pos) /*!< BPWM0 channel4 output/capture input. \hideinitializer */
1217 #define SYS_GPG_MFPH_PG11MFP_GPIO (0x00UL<<SYS_GPG_MFPH_PG11MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
1218 #define SYS_GPG_MFPH_PG11MFP_EBI_AD2 (0x02UL<<SYS_GPG_MFPH_PG11MFP_Pos) /*!< EBI address/data bus bit2. \hideinitializer */
1219 #define SYS_GPG_MFPH_PG11MFP_SD1_DAT1 (0x03UL<<SYS_GPG_MFPH_PG11MFP_Pos) /*!< SD/SDIO 1 data line bit 1. \hideinitializer */
1220 #define SYS_GPG_MFPH_PG11MFP_SPIM_SS (0x04UL<<SYS_GPG_MFPH_PG11MFP_Pos) /*!< 1st SPIM slave select pin. \hideinitializer */
1221 #define SYS_GPG_MFPH_PG11MFP_QSPI1_SS (0x05UL<<SYS_GPG_MFPH_PG11MFP_Pos) /*!< 1st QSPI1 slave select pin. \hideinitializer */
1222 #define SYS_GPG_MFPH_PG11MFP_UART7_TXD (0x06UL<<SYS_GPG_MFPH_PG11MFP_Pos) /*!< Data transmitter output pin for UART7. \hideinitializer */
1223 #define SYS_GPG_MFPH_PG11MFP_CCAP_SFIELD (0x07UL<<SYS_GPG_MFPH_PG11MFP_Pos) /*!< Even/Odd Field Flag input pin. \hideinitializer */
1224 #define SYS_GPG_MFPH_PG11MFP_BPWM0_CH3 (0x0CUL<<SYS_GPG_MFPH_PG11MFP_Pos) /*!< BPWM0 channel3 output/capture input. \hideinitializer */
1225 #define SYS_GPG_MFPH_PG12MFP_GPIO (0x00UL<<SYS_GPG_MFPH_PG12MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
1226 #define SYS_GPG_MFPH_PG12MFP_EBI_AD3 (0x02UL<<SYS_GPG_MFPH_PG12MFP_Pos) /*!< EBI address/data bus bit3. \hideinitializer */
1227 #define SYS_GPG_MFPH_PG12MFP_SD1_DAT0 (0x03UL<<SYS_GPG_MFPH_PG12MFP_Pos) /*!< SD/SDIO 1 data line bit 0. \hideinitializer */
1228 #define SYS_GPG_MFPH_PG12MFP_SPIM_CLK (0x04UL<<SYS_GPG_MFPH_PG12MFP_Pos) /*!< SPIM serial clock pin. \hideinitializer */
1229 #define SYS_GPG_MFPH_PG12MFP_QSPI1_CLK (0x05UL<<SYS_GPG_MFPH_PG12MFP_Pos) /*!< QSPI1 serial clock pin. \hideinitializer */
1230 #define SYS_GPG_MFPH_PG12MFP_UART7_RXD (0x06UL<<SYS_GPG_MFPH_PG12MFP_Pos) /*!< Data receiver input pin for UART7. \hideinitializer */
1231 #define SYS_GPG_MFPH_PG12MFP_CCAP_VSYNC (0x07UL<<SYS_GPG_MFPH_PG12MFP_Pos) /*!< Sensor vertical synchronization input pin. \hideinitializer */
1232 #define SYS_GPG_MFPH_PG12MFP_BPWM0_CH2 (0x0CUL<<SYS_GPG_MFPH_PG12MFP_Pos) /*!< BPWM0 channel2 output/capture input. \hideinitializer */
1233 #define SYS_GPG_MFPH_PG13MFP_GPIO (0x00UL<<SYS_GPG_MFPH_PG13MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
1234 #define SYS_GPG_MFPH_PG13MFP_EBI_AD4 (0x02UL<<SYS_GPG_MFPH_PG13MFP_Pos) /*!< EBI address/data bus bit4. \hideinitializer */
1235 #define SYS_GPG_MFPH_PG13MFP_SD1_CMD (0x03UL<<SYS_GPG_MFPH_PG13MFP_Pos) /*!< SD/SDIO 1 command/response. \hideinitializer */
1236 #define SYS_GPG_MFPH_PG13MFP_SPIM_MISO (0x04UL<<SYS_GPG_MFPH_PG13MFP_Pos) /*!< 1st SPIM MISO (Master In, Slave Out) pin. \hideinitializer */
1237 #define SYS_GPG_MFPH_PG13MFP_QSPI1_MISO0 (0x05UL<<SYS_GPG_MFPH_PG13MFP_Pos) /*!< 1st QSPI1 MISO (Master In, Slave Out) pin. \hideinitializer */
1238 #define SYS_GPG_MFPH_PG13MFP_UART6_TXD (0x06UL<<SYS_GPG_MFPH_PG13MFP_Pos) /*!< Data transmitter output pin for UART6. \hideinitializer */
1239 #define SYS_GPG_MFPH_PG13MFP_CCAP_HSYNC (0x07UL<<SYS_GPG_MFPH_PG13MFP_Pos) /*!< Sensor horizontal synchronization input pin. \hideinitializer */
1240 #define SYS_GPG_MFPH_PG13MFP_BPWM0_CH1 (0x0CUL<<SYS_GPG_MFPH_PG13MFP_Pos) /*!< BPWM0 channel1 output/capture input. \hideinitializer */
1241 #define SYS_GPG_MFPH_PG14MFP_GPIO (0x00UL<<SYS_GPG_MFPH_PG14MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
1242 #define SYS_GPG_MFPH_PG14MFP_EBI_AD5 (0x02UL<<SYS_GPG_MFPH_PG14MFP_Pos) /*!< EBI address/data bus bit5. \hideinitializer */
1243 #define SYS_GPG_MFPH_PG14MFP_SD1_CLK (0x03UL<<SYS_GPG_MFPH_PG14MFP_Pos) /*!< SD/SDIO 1 clock. \hideinitializer */
1244 #define SYS_GPG_MFPH_PG14MFP_SPIM_MOSI (0x04UL<<SYS_GPG_MFPH_PG14MFP_Pos) /*!< 1st SPIM MOSI (Master Out, Slave In) pin. \hideinitializer */
1245 #define SYS_GPG_MFPH_PG14MFP_QSPI1_MOSI0 (0x05UL<<SYS_GPG_MFPH_PG14MFP_Pos) /*!< 1st QSPI1 MOSI (Master Out, Slave In) pin. \hideinitializer */
1246 #define SYS_GPG_MFPH_PG14MFP_UART6_RXD (0x06UL<<SYS_GPG_MFPH_PG14MFP_Pos) /*!< Data receiver input pin for UART6. \hideinitializer */
1247 #define SYS_GPG_MFPH_PG14MFP_BPWM0_CH0 (0x0CUL<<SYS_GPG_MFPH_PG14MFP_Pos) /*!< BPWM0 channel0 output/capture input. \hideinitializer */
1248 #define SYS_GPG_MFPH_PG15MFP_GPIO (0x00UL<<SYS_GPG_MFPH_PG15MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
1249 #define SYS_GPG_MFPH_PG15MFP_SD1_nCD (0x03UL<<SYS_GPG_MFPH_PG15MFP_Pos) /*!< SD/SDIO 1 card detect \hideinitializer */
1250 #define SYS_GPG_MFPH_PG15MFP_CLKO (0x0EUL<<SYS_GPG_MFPH_PG15MFP_Pos) /*!< Clock Output pin. \hideinitializer */
1251 #define SYS_GPG_MFPH_PG15MFP_EADC0_ST (0x0FUL<<SYS_GPG_MFPH_PG15MFP_Pos) /*!< EADC external trigger input. \hideinitializer */
1252 /********************* Bit definition of GPH_MFPL register **********************/
1253 #define SYS_GPH_MFPL_PH0MFP_GPIO (0x00UL<<SYS_GPH_MFPL_PH0MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
1254 #define SYS_GPH_MFPL_PH0MFP_EBI_ADR7 (0x02UL<<SYS_GPH_MFPL_PH0MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
1255 #define SYS_GPH_MFPL_PH0MFP_UART5_TXD (0x04UL<<SYS_GPH_MFPL_PH0MFP_Pos) /*!< Data transmitter output pin for UART5. \hideinitializer */
1256 #define SYS_GPH_MFPL_PH0MFP_TM0_EXT (0x0DUL<<SYS_GPH_MFPL_PH0MFP_Pos) /*!< Timer0 event counter input / toggle output \hideinitializer */
1257 #define SYS_GPH_MFPL_PH1MFP_GPIO (0x00UL<<SYS_GPH_MFPL_PH1MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
1258 #define SYS_GPH_MFPL_PH1MFP_EBI_ADR6 (0x02UL<<SYS_GPH_MFPL_PH1MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
1259 #define SYS_GPH_MFPL_PH1MFP_UART5_RXD (0x04UL<<SYS_GPH_MFPL_PH1MFP_Pos) /*!< Data receiver input pin for UART5. \hideinitializer */
1260 #define SYS_GPH_MFPL_PH1MFP_TM1_EXT (0x0DUL<<SYS_GPH_MFPL_PH1MFP_Pos) /*!< Timer1 event counter input / toggle output \hideinitializer */
1261 #define SYS_GPH_MFPL_PH2MFP_GPIO (0x00UL<<SYS_GPH_MFPL_PH2MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
1262 #define SYS_GPH_MFPL_PH2MFP_EBI_ADR5 (0x02UL<<SYS_GPH_MFPL_PH2MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
1263 #define SYS_GPH_MFPL_PH2MFP_UART5_nRTS (0x04UL<<SYS_GPH_MFPL_PH2MFP_Pos) /*!< Request to Send output pin for UART5. \hideinitializer */
1264 #define SYS_GPH_MFPL_PH2MFP_UART4_TXD (0x05UL<<SYS_GPH_MFPL_PH2MFP_Pos) /*!< Data transmitter output pin for UART4. \hideinitializer */
1265 #define SYS_GPH_MFPL_PH2MFP_I2C0_SCL (0x06UL<<SYS_GPH_MFPL_PH2MFP_Pos) /*!< I2C0 clock pin. \hideinitializer */
1266 #define SYS_GPH_MFPL_PH2MFP_TM2_EXT (0x0DUL<<SYS_GPH_MFPL_PH2MFP_Pos) /*!< Timer2 event counter input / toggle output \hideinitializer */
1267 #define SYS_GPH_MFPL_PH3MFP_GPIO (0x00UL<<SYS_GPH_MFPL_PH3MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
1268 #define SYS_GPH_MFPL_PH3MFP_EBI_ADR4 (0x02UL<<SYS_GPH_MFPL_PH3MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
1269 #define SYS_GPH_MFPL_PH3MFP_SPI1_I2SMCLK (0x03UL<<SYS_GPH_MFPL_PH3MFP_Pos) /*!< SPI1 I2S master clock output pin. \hideinitializer */
1270 #define SYS_GPH_MFPL_PH3MFP_UART5_nCTS (0x04UL<<SYS_GPH_MFPL_PH3MFP_Pos) /*!< Clear to Send input pin for UART5. \hideinitializer */
1271 #define SYS_GPH_MFPL_PH3MFP_UART4_RXD (0x05UL<<SYS_GPH_MFPL_PH3MFP_Pos) /*!< Data receiver input pin for UART4. \hideinitializer */
1272 #define SYS_GPH_MFPL_PH3MFP_I2C0_SDA (0x06UL<<SYS_GPH_MFPL_PH3MFP_Pos) /*!< I2C0 data input/output pin. \hideinitializer */
1273 #define SYS_GPH_MFPL_PH3MFP_TM3_EXT (0x0DUL<<SYS_GPH_MFPL_PH3MFP_Pos) /*!< Timer3 event counter input / toggle output \hideinitializer */
1274 #define SYS_GPH_MFPL_PH4MFP_GPIO (0x00UL<<SYS_GPH_MFPL_PH4MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
1275 #define SYS_GPH_MFPL_PH4MFP_EBI_ADR3 (0x02UL<<SYS_GPH_MFPL_PH4MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
1276 #define SYS_GPH_MFPL_PH4MFP_SPI1_MISO (0x03UL<<SYS_GPH_MFPL_PH4MFP_Pos) /*!< 1st SPI1 MISO (Master In, Slave Out) pin. \hideinitializer */
1277 #define SYS_GPH_MFPL_PH4MFP_UART7_nRTS (0x04UL<<SYS_GPH_MFPL_PH4MFP_Pos) /*!< Request to Send output pin for UART7. \hideinitializer */
1278 #define SYS_GPH_MFPL_PH4MFP_UART6_TXD (0x05UL<<SYS_GPH_MFPL_PH4MFP_Pos) /*!< Data transmitter output pin for UART6. \hideinitializer */
1279 #define SYS_GPH_MFPL_PH5MFP_GPIO (0x00UL<<SYS_GPH_MFPL_PH5MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
1280 #define SYS_GPH_MFPL_PH5MFP_EBI_ADR2 (0x02UL<<SYS_GPH_MFPL_PH5MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
1281 #define SYS_GPH_MFPL_PH5MFP_SPI1_MOSI (0x03UL<<SYS_GPH_MFPL_PH5MFP_Pos) /*!< 1st SPI1 MOSI (Master Out, Slave In) pin. \hideinitializer */
1282 #define SYS_GPH_MFPL_PH5MFP_UART7_nCTS (0x04UL<<SYS_GPH_MFPL_PH5MFP_Pos) /*!< Clear to Send input pin for UART7. \hideinitializer */
1283 #define SYS_GPH_MFPL_PH5MFP_UART6_RXD (0x05UL<<SYS_GPH_MFPL_PH5MFP_Pos) /*!< Data receiver input pin for UART6. \hideinitializer */
1284 #define SYS_GPH_MFPL_PH6MFP_GPIO (0x00UL<<SYS_GPH_MFPL_PH6MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
1285 #define SYS_GPH_MFPL_PH6MFP_EBI_ADR1 (0x02UL<<SYS_GPH_MFPL_PH6MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
1286 #define SYS_GPH_MFPL_PH6MFP_SPI1_CLK (0x03UL<<SYS_GPH_MFPL_PH6MFP_Pos) /*!< SPI1 serial clock pin. \hideinitializer */
1287 #define SYS_GPH_MFPL_PH6MFP_UART7_TXD (0x04UL<<SYS_GPH_MFPL_PH6MFP_Pos) /*!< Data transmitter output pin for UART7. \hideinitializer */
1288 #define SYS_GPH_MFPL_PH7MFP_GPIO (0x00UL<<SYS_GPH_MFPL_PH7MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
1289 #define SYS_GPH_MFPL_PH7MFP_EBI_ADR0 (0x02UL<<SYS_GPH_MFPL_PH7MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
1290 #define SYS_GPH_MFPL_PH7MFP_SPI1_SS (0x03UL<<SYS_GPH_MFPL_PH7MFP_Pos) /*!< 1st SPI1 slave select pin. \hideinitializer */
1291 #define SYS_GPH_MFPL_PH7MFP_UART7_RXD (0x04UL<<SYS_GPH_MFPL_PH7MFP_Pos) /*!< Data receiver input pin for UART7. \hideinitializer */
1292 /********************* Bit definition of GPH_MFPH register **********************/
1293 #define SYS_GPH_MFPH_PH8MFP_GPIO (0x00UL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
1294 #define SYS_GPH_MFPH_PH8MFP_EBI_AD12 (0x02UL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */
1295 #define SYS_GPH_MFPH_PH8MFP_QSPI0_CLK (0x03UL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< QSPI0 serial clock pin. \hideinitializer */
1296 #define SYS_GPH_MFPH_PH8MFP_SC2_PWR (0x04UL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< SmartCard2 power pin. \hideinitializer */
1297 #define SYS_GPH_MFPH_PH8MFP_I2S0_DI (0x05UL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< I2S0 data input. \hideinitializer */
1298 #define SYS_GPH_MFPH_PH8MFP_SPI1_CLK (0x06UL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< SPI1 serial clock pin. \hideinitializer */
1299 #define SYS_GPH_MFPH_PH8MFP_UART3_nRTS (0x07UL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< Request to Send output pin for UART3. \hideinitializer */
1300 #define SYS_GPH_MFPH_PH8MFP_I2C1_SMBAL (0x08UL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< I2C1 SMBus SMBALTER# pin \hideinitializer */
1301 #define SYS_GPH_MFPH_PH8MFP_I2C2_SCL (0x09UL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< I2C2 clock pin. \hideinitializer */
1302 #define SYS_GPH_MFPH_PH8MFP_UART1_TXD (0x0AUL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< Data transmitter output pin for UART1. \hideinitializer */
1303 #define SYS_GPH_MFPH_PH9MFP_GPIO (0x00UL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
1304 #define SYS_GPH_MFPH_PH9MFP_EBI_AD13 (0x02UL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */
1305 #define SYS_GPH_MFPH_PH9MFP_QSPI0_SS (0x03UL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< 1st QSPI0 slave select pin. \hideinitializer */
1306 #define SYS_GPH_MFPH_PH9MFP_SC2_RST (0x04UL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< SmartCard2 reset pin. \hideinitializer */
1307 #define SYS_GPH_MFPH_PH9MFP_I2S0_DO (0x05UL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< I2S0 data output. \hideinitializer */
1308 #define SYS_GPH_MFPH_PH9MFP_SPI1_SS (0x06UL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< 1st SPI1 slave select pin. \hideinitializer */
1309 #define SYS_GPH_MFPH_PH9MFP_UART3_nCTS (0x07UL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< Clear to Send input pin for UART3. \hideinitializer */
1310 #define SYS_GPH_MFPH_PH9MFP_I2C1_SMBSUS (0x08UL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< I2C1 SMBus SMBSUS# pin (PMBus CONTROL pin) \hideinitializer */
1311 #define SYS_GPH_MFPH_PH9MFP_I2C2_SDA (0x09UL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< I2C2 data input/output pin. \hideinitializer */
1312 #define SYS_GPH_MFPH_PH9MFP_UART1_RXD (0x0AUL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< Data receiver input pin for UART1. \hideinitializer */
1313 #define SYS_GPH_MFPH_PH10MFP_GPIO (0x00UL<<SYS_GPH_MFPH_PH10MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
1314 #define SYS_GPH_MFPH_PH10MFP_EBI_AD14 (0x02UL<<SYS_GPH_MFPH_PH10MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */
1315 #define SYS_GPH_MFPH_PH10MFP_QSPI0_MISO1 (0x03UL<<SYS_GPH_MFPH_PH10MFP_Pos) /*!< 2nd QSPI0 MISO (Master In, Slave Out) pin. \hideinitializer */
1316 #define SYS_GPH_MFPH_PH10MFP_SC2_nCD (0x04UL<<SYS_GPH_MFPH_PH10MFP_Pos) /*!< SmartCard2 card detect pin. \hideinitializer */
1317 #define SYS_GPH_MFPH_PH10MFP_I2S0_LRCK (0x05UL<<SYS_GPH_MFPH_PH10MFP_Pos) /*!< I2S0 left right channel clock. \hideinitializer */
1318 #define SYS_GPH_MFPH_PH10MFP_SPI1_I2SMCLK (0x06UL<<SYS_GPH_MFPH_PH10MFP_Pos) /*!< SPI1 I2S master clock output pin. \hideinitializer */
1319 #define SYS_GPH_MFPH_PH10MFP_UART4_TXD (0x07UL<<SYS_GPH_MFPH_PH10MFP_Pos) /*!< Data transmitter output pin for UART4. \hideinitializer */
1320 #define SYS_GPH_MFPH_PH10MFP_UART0_TXD (0x08UL<<SYS_GPH_MFPH_PH10MFP_Pos) /*!< Data transmitter output pin for UART0. \hideinitializer */
1321 #define SYS_GPH_MFPH_PH11MFP_GPIO (0x00UL<<SYS_GPH_MFPH_PH11MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
1322 #define SYS_GPH_MFPH_PH11MFP_EBI_AD15 (0x02UL<<SYS_GPH_MFPH_PH11MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */
1323 #define SYS_GPH_MFPH_PH11MFP_QSPI0_MOSI1 (0x03UL<<SYS_GPH_MFPH_PH11MFP_Pos) /*!< 2nd QSPI0 MOSI (Master Out, Slave In) pin. \hideinitializer */
1324 #define SYS_GPH_MFPH_PH11MFP_UART4_RXD (0x07UL<<SYS_GPH_MFPH_PH11MFP_Pos) /*!< Data receiver input pin for UART4. \hideinitializer */
1325 #define SYS_GPH_MFPH_PH11MFP_UART0_RXD (0x08UL<<SYS_GPH_MFPH_PH11MFP_Pos) /*!< Data receiver input pin for UART0. \hideinitializer */
1326 #define SYS_GPH_MFPH_PH11MFP_EPWM0_CH5 (0x0BUL<<SYS_GPH_MFPH_PH11MFP_Pos) /*!< EPWM0 channel5 output/capture input. \hideinitializer */
1327
1328 /*@}*/ /* end of group SYS_EXPORTED_CONSTANTS */
1329
1330
1331 /** @addtogroup SYS_EXPORTED_FUNCTIONS SYS Exported Functions
1332 @{
1333 */
1334
1335
1336 /**
1337 * @brief Clear Brown-out detector interrupt flag
1338 * @param None
1339 * @return None
1340 * @details This macro clear Brown-out detector interrupt flag.
1341 * \hideinitializer
1342 */
1343 #define SYS_CLEAR_BOD_INT_FLAG() (SYS->BODCTL |= SYS_BODCTL_BODIF_Msk)
1344
1345 /**
1346 * @brief Set Brown-out detector function to normal mode
1347 * @param None
1348 * @return None
1349 * @details This macro set Brown-out detector to normal mode.
1350 * The register write-protection function should be disabled before using this macro.
1351 * \hideinitializer
1352 */
1353 #define SYS_CLEAR_BOD_LPM() (SYS->BODCTL &= ~SYS_BODCTL_BODLPM_Msk)
1354
1355 /**
1356 * @brief Disable Brown-out detector function
1357 * @param None
1358 * @return None
1359 * @details This macro disable Brown-out detector function.
1360 * The register write-protection function should be disabled before using this macro.
1361 * \hideinitializer
1362 */
1363 #define SYS_DISABLE_BOD() (SYS->BODCTL &= ~SYS_BODCTL_BODEN_Msk)
1364
1365 /**
1366 * @brief Enable Brown-out detector function
1367 * @param None
1368 * @return None
1369 * @details This macro enable Brown-out detector function.
1370 * The register write-protection function should be disabled before using this macro.
1371 * \hideinitializer
1372 */
1373 #define SYS_ENABLE_BOD() (SYS->BODCTL |= SYS_BODCTL_BODEN_Msk)
1374
1375 /**
1376 * @brief Get Brown-out detector interrupt flag
1377 * @param None
1378 * @retval 0 Brown-out detect interrupt flag is not set.
1379 * @retval >=1 Brown-out detect interrupt flag is set.
1380 * @details This macro get Brown-out detector interrupt flag.
1381 * \hideinitializer
1382 */
1383 #define SYS_GET_BOD_INT_FLAG() (SYS->BODCTL & SYS_BODCTL_BODIF_Msk)
1384
1385 /**
1386 * @brief Get Brown-out detector status
1387 * @param None
1388 * @retval 0 System voltage is higher than BOD threshold voltage setting or BOD function is disabled.
1389 * @retval >=1 System voltage is lower than BOD threshold voltage setting.
1390 * @details This macro get Brown-out detector output status.
1391 * If the BOD function is disabled, this function always return 0.
1392 * \hideinitializer
1393 */
1394 #define SYS_GET_BOD_OUTPUT() (SYS->BODCTL & SYS_BODCTL_BODOUT_Msk)
1395
1396 /**
1397 * @brief Enable Brown-out detector interrupt function
1398 * @param None
1399 * @return None
1400 * @details This macro enable Brown-out detector interrupt function.
1401 * The register write-protection function should be disabled before using this macro.
1402 * \hideinitializer
1403 */
1404 #define SYS_DISABLE_BOD_RST() (SYS->BODCTL &= ~SYS_BODCTL_BODRSTEN_Msk)
1405
1406 /**
1407 * @brief Enable Brown-out detector reset function
1408 * @param None
1409 * @return None
1410 * @details This macro enable Brown-out detect reset function.
1411 * The register write-protection function should be disabled before using this macro.
1412 * \hideinitializer
1413 */
1414 #define SYS_ENABLE_BOD_RST() (SYS->BODCTL |= SYS_BODCTL_BODRSTEN_Msk)
1415
1416 /**
1417 * @brief Set Brown-out detector function low power mode
1418 * @param None
1419 * @return None
1420 * @details This macro set Brown-out detector to low power mode.
1421 * The register write-protection function should be disabled before using this macro.
1422 * \hideinitializer
1423 */
1424 #define SYS_SET_BOD_LPM() (SYS->BODCTL |= SYS_BODCTL_BODLPM_Msk)
1425
1426 /**
1427 * @brief Set Brown-out detector voltage level
1428 * @param[in] u32Level is Brown-out voltage level. Including :
1429 * - \ref SYS_BODCTL_BODVL_3_0V
1430 * - \ref SYS_BODCTL_BODVL_2_8V
1431 * - \ref SYS_BODCTL_BODVL_2_6V
1432 * - \ref SYS_BODCTL_BODVL_2_4V
1433 * - \ref SYS_BODCTL_BODVL_2_2V
1434 * - \ref SYS_BODCTL_BODVL_2_0V
1435 * - \ref SYS_BODCTL_BODVL_1_8V
1436 * - \ref SYS_BODCTL_BODVL_1_6V
1437 * @return None
1438 * @details This macro set Brown-out detector voltage level.
1439 * The write-protection function should be disabled before using this macro.
1440 * \hideinitializer
1441 */
1442 #define SYS_SET_BOD_LEVEL(u32Level) (SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODVL_Msk) | (u32Level))
1443
1444 /**
1445 * @brief Get reset source is from Brown-out detector reset
1446 * @param None
1447 * @retval 0 Previous reset source is not from Brown-out detector reset
1448 * @retval >=1 Previous reset source is from Brown-out detector reset
1449 * @details This macro get previous reset source is from Brown-out detect reset or not.
1450 * \hideinitializer
1451 */
1452 #define SYS_IS_BOD_RST() (SYS->RSTSTS & SYS_RSTSTS_BODRF_Msk)
1453
1454 /**
1455 * @brief Get reset source is from CPU reset
1456 * @param None
1457 * @retval 0 Previous reset source is not from CPU reset
1458 * @retval >=1 Previous reset source is from CPU reset
1459 * @details This macro get previous reset source is from CPU reset.
1460 * \hideinitializer
1461 */
1462 #define SYS_IS_CPU_RST() (SYS->RSTSTS & SYS_RSTSTS_CPURF_Msk)
1463
1464 /**
1465 * @brief Get reset source is from LVR Reset
1466 * @param None
1467 * @retval 0 Previous reset source is not from Low-Voltage-Reset
1468 * @retval >=1 Previous reset source is from Low-Voltage-Reset
1469 * @details This macro get previous reset source is from Low-Voltage-Reset.
1470 * \hideinitializer
1471 */
1472 #define SYS_IS_LVR_RST() (SYS->RSTSTS & SYS_RSTSTS_LVRF_Msk)
1473
1474 /**
1475 * @brief Get reset source is from Power-on Reset
1476 * @param None
1477 * @retval 0 Previous reset source is not from Power-on Reset
1478 * @retval >=1 Previous reset source is from Power-on Reset
1479 * @details This macro get previous reset source is from Power-on Reset.
1480 * \hideinitializer
1481 */
1482 #define SYS_IS_POR_RST() (SYS->RSTSTS & SYS_RSTSTS_PORF_Msk)
1483
1484 /**
1485 * @brief Get reset source is from reset pin reset
1486 * @param None
1487 * @retval 0 Previous reset source is not from reset pin reset
1488 * @retval >=1 Previous reset source is from reset pin reset
1489 * @details This macro get previous reset source is from reset pin reset.
1490 * \hideinitializer
1491 */
1492 #define SYS_IS_RSTPIN_RST() (SYS->RSTSTS & SYS_RSTSTS_PINRF_Msk)
1493
1494 /**
1495 * @brief Get reset source is from system reset
1496 * @param None
1497 * @retval 0 Previous reset source is not from system reset
1498 * @retval >=1 Previous reset source is from system reset
1499 * @details This macro get previous reset source is from system reset.
1500 * \hideinitializer
1501 */
1502 #define SYS_IS_SYSTEM_RST() (SYS->RSTSTS & SYS_RSTSTS_SYSRF_Msk)
1503
1504 /**
1505 * @brief Get reset source is from window watch dog reset
1506 * @param None
1507 * @retval 0 Previous reset source is not from window watch dog reset
1508 * @retval >=1 Previous reset source is from window watch dog reset
1509 * @details This macro get previous reset source is from window watch dog reset.
1510 * \hideinitializer
1511 */
1512 #define SYS_IS_WDT_RST() (SYS->RSTSTS & SYS_RSTSTS_WDTRF_Msk)
1513
1514 /**
1515 * @brief Disable Low-Voltage-Reset function
1516 * @param None
1517 * @return None
1518 * @details This macro disable Low-Voltage-Reset function.
1519 * The register write-protection function should be disabled before using this macro.
1520 * \hideinitializer
1521 */
1522 #define SYS_DISABLE_LVR() (SYS->BODCTL &= ~SYS_BODCTL_LVREN_Msk)
1523
1524 /**
1525 * @brief Enable Low-Voltage-Reset function
1526 * @param None
1527 * @return None
1528 * @details This macro enable Low-Voltage-Reset function.
1529 * The register write-protection function should be disabled before using this macro.
1530 * \hideinitializer
1531 */
1532 #define SYS_ENABLE_LVR() (SYS->BODCTL |= SYS_BODCTL_LVREN_Msk)
1533
1534 /**
1535 * @brief Disable Power-on Reset function
1536 * @param None
1537 * @return None
1538 * @details This macro disable Power-on Reset function.
1539 * The register write-protection function should be disabled before using this macro.
1540 * \hideinitializer
1541 */
1542 #define SYS_DISABLE_POR() (((SYS->CSERVER & SYS_CSERVER_VERSION_Msk) == 0) ? (SYS->PORCTL = 0x5AA5):(SYS->PORDISAN = 0x5AA5))
1543
1544 /**
1545 * @brief Enable Power-on Reset function
1546 * @param None
1547 * @return None
1548 * @details This macro enable Power-on Reset function.
1549 * The register write-protection function should be disabled before using this macro.
1550 * \hideinitializer
1551 */
1552 #define SYS_ENABLE_POR() (((SYS->CSERVER & SYS_CSERVER_VERSION_Msk) == 0) ? (SYS->PORCTL = 0):(SYS->PORDISAN = 0))
1553
1554 /**
1555 * @brief Clear reset source flag
1556 * @param[in] u32RstSrc is reset source. Including :
1557 * - \ref SYS_RSTSTS_PORF_Msk
1558 * - \ref SYS_RSTSTS_PINRF_Msk
1559 * - \ref SYS_RSTSTS_WDTRF_Msk
1560 * - \ref SYS_RSTSTS_LVRF_Msk
1561 * - \ref SYS_RSTSTS_BODRF_Msk
1562 * - \ref SYS_RSTSTS_SYSRF_Msk
1563 * - \ref SYS_RSTSTS_CPURF_Msk
1564 * - \ref SYS_RSTSTS_CPULKRF_Msk
1565 * @return None
1566 * @details This macro clear reset source flag.
1567 * \hideinitializer
1568 */
1569 #define SYS_CLEAR_RST_SOURCE(u32RstSrc) ((SYS->RSTSTS) = (u32RstSrc) )
1570
1571
1572 /*---------------------------------------------------------------------------------------------------------*/
1573 /* static inline functions */
1574 /*---------------------------------------------------------------------------------------------------------*/
1575 /* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
1576 __STATIC_INLINE void SYS_UnlockReg(void);
1577 __STATIC_INLINE void SYS_LockReg(void);
1578
1579 /**
1580 * @brief Disable register write-protection function
1581 * @param None
1582 * @return None
1583 * @details This function disable register write-protection function.
1584 * To unlock the protected register to allow write access.
1585 */
SYS_UnlockReg(void)1586 __STATIC_INLINE void SYS_UnlockReg(void)
1587 {
1588 do
1589 {
1590 SYS->REGLCTL = 0x59UL;
1591 SYS->REGLCTL = 0x16UL;
1592 SYS->REGLCTL = 0x88UL;
1593 }
1594 while(SYS->REGLCTL == 0UL);
1595 }
1596
1597 /**
1598 * @brief Enable register write-protection function
1599 * @param None
1600 * @return None
1601 * @details This function is used to enable register write-protection function.
1602 * To lock the protected register to forbid write access.
1603 */
SYS_LockReg(void)1604 __STATIC_INLINE void SYS_LockReg(void)
1605 {
1606 SYS->REGLCTL = 0UL;
1607 }
1608
1609
1610 void SYS_ClearResetSrc(uint32_t u32Src);
1611 uint32_t SYS_GetBODStatus(void);
1612 uint32_t SYS_GetResetSrc(void);
1613 uint32_t SYS_IsRegLocked(void);
1614 uint32_t SYS_ReadPDID(void);
1615 void SYS_ResetChip(void);
1616 void SYS_ResetCPU(void);
1617 void SYS_ResetModule(uint32_t u32ModuleIndex);
1618 void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel);
1619 void SYS_DisableBOD(void);
1620 void SYS_SetPowerLevel(uint32_t u32PowerLevel);
1621 void SYS_SetVRef(uint32_t u32VRefCTL);
1622
1623 /*@}*/ /* end of group SYS_EXPORTED_FUNCTIONS */
1624
1625 /*@}*/ /* end of group SYS_Driver */
1626
1627 /*@}*/ /* end of group Standard_Driver */
1628
1629
1630 #ifdef __cplusplus
1631 }
1632 #endif
1633
1634 #endif /* __SYS_H__ */
1635
1636 /*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
1637
