1 /**************************************************************************//**
2 * @file CLK.h
3 * @version V1.0
4 * @brief M480 Series CLK Driver Header File
5 *
6 * SPDX-License-Identifier: Apache-2.0
7 * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
8 ******************************************************************************/
9 #ifndef __CLK_H__
10 #define __CLK_H__
11
12 #ifdef __cplusplus
13 extern "C"
14 {
15 #endif
16
17
18 /** @addtogroup Standard_Driver Standard Driver
19 @{
20 */
21
22 /** @addtogroup CLK_Driver CLK Driver
23 @{
24 */
25
26 /** @addtogroup CLK_EXPORTED_CONSTANTS CLK Exported Constants
27 @{
28 */
29
30
31 #define FREQ_25MHZ 25000000UL /*!< 25 MHz \hideinitializer */
32 #define FREQ_50MHZ 50000000UL /*!< 50 MHz \hideinitializer */
33 #define FREQ_72MHZ 72000000UL /*!< 72 MHz \hideinitializer */
34 #define FREQ_80MHZ 80000000UL /*!< 80 MHz \hideinitializer */
35 #define FREQ_100MHZ 100000000UL /*!< 100 MHz \hideinitializer */
36 #define FREQ_125MHZ 125000000UL /*!< 125 MHz \hideinitializer */
37 #define FREQ_160MHZ 160000000UL /*!< 160 MHz \hideinitializer */
38 #define FREQ_192MHZ 192000000UL /*!< 192 MHz \hideinitializer */
39 #define FREQ_200MHZ 200000000UL /*!< 200 MHz \hideinitializer */
40 #define FREQ_250MHZ 250000000UL /*!< 250 MHz \hideinitializer */
41 #define FREQ_500MHZ 500000000UL /*!< 500 MHz \hideinitializer */
42
43 /*---------------------------------------------------------------------------------------------------------*/
44 /* CLKSEL0 constant definitions. (Write-protection) */
45 /*---------------------------------------------------------------------------------------------------------*/
46 #define CLK_CLKSEL0_HCLKSEL_HXT (0x0UL << CLK_CLKSEL0_HCLKSEL_Pos) /*!< Select HCLK clock source from high speed crystal \hideinitializer */
47 #define CLK_CLKSEL0_HCLKSEL_LXT (0x1UL << CLK_CLKSEL0_HCLKSEL_Pos) /*!< Select HCLK clock source from low speed crystal \hideinitializer */
48 #define CLK_CLKSEL0_HCLKSEL_PLL (0x2UL << CLK_CLKSEL0_HCLKSEL_Pos) /*!< Select HCLK clock source from PLL \hideinitializer */
49 #define CLK_CLKSEL0_HCLKSEL_LIRC (0x3UL << CLK_CLKSEL0_HCLKSEL_Pos) /*!< Select HCLK clock source from low speed oscillator \hideinitializer */
50 #define CLK_CLKSEL0_HCLKSEL_HIRC (0x7UL << CLK_CLKSEL0_HCLKSEL_Pos) /*!< Select HCLK clock source from high speed oscillator \hideinitializer */
51
52 #define CLK_CLKSEL0_STCLKSEL_HXT (0x0UL << CLK_CLKSEL0_STCLKSEL_Pos) /*!< Select SysTick clock source from high speed crystal \hideinitializer */
53 #define CLK_CLKSEL0_STCLKSEL_LXT (0x1UL << CLK_CLKSEL0_STCLKSEL_Pos) /*!< Select SysTick clock source from low speed crystal \hideinitializer */
54 #define CLK_CLKSEL0_STCLKSEL_HXT_DIV2 (0x2UL << CLK_CLKSEL0_STCLKSEL_Pos) /*!< Select SysTick clock source from HXT/2 \hideinitializer */
55 #define CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 (0x3UL << CLK_CLKSEL0_STCLKSEL_Pos) /*!< Select SysTick clock source from HCLK/2 \hideinitializer */
56 #define CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 (0x7UL << CLK_CLKSEL0_STCLKSEL_Pos) /*!< Select SysTick clock source from HIRC/2 \hideinitializer */
57 #define CLK_CLKSEL0_STCLKSEL_HCLK (0x01UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< Select SysTick clock source from HCLK \hideinitializer */
58
59 #define CLK_CLKSEL0_CCAPSEL_HXT (0x0UL << CLK_CLKSEL0_CCAPSEL_Pos) /*!< Select CCAP clock source from HXT \hideinitializer */
60 #define CLK_CLKSEL0_CCAPSEL_PLL (0x1UL << CLK_CLKSEL0_CCAPSEL_Pos) /*!< Select CCAP clock source from PLL \hideinitializer */
61 #define CLK_CLKSEL0_CCAPSEL_HCLK (0x2UL << CLK_CLKSEL0_CCAPSEL_Pos) /*!< Select CCAP clock source from HCLK \hideinitializer */
62 #define CLK_CLKSEL0_CCAPSEL_HIRC (0x3UL << CLK_CLKSEL0_CCAPSEL_Pos) /*!< Select CCAP clock source from HIRC \hideinitializer */
63
64
65 #if(0)
66 #define CLK_CLKSEL0_PCLK0DIV1 (0x0UL << CLK_CLKSEL0_PCLK0SEL_Pos) /*!< Select PCLK0 clock source from HCLK \hideinitializer */
67 #define CLK_CLKSEL0_PCLK0DIV2 (0x1UL << CLK_CLKSEL0_PCLK0SEL_Pos) /*!< Select PCLK0 clock source from 1/2 HCLK \hideinitializer */
68
69 #define CLK_CLKSEL0_PCLK1DIV1 (0x0UL << CLK_CLKSEL0_PCLK1SEL_Pos) /*!< Select PCLK1 clock source from HCLK \hideinitializer */
70 #define CLK_CLKSEL0_PCLK1DIV2 (0x1UL << CLK_CLKSEL0_PCLK1SEL_Pos) /*!< Select PCLK1 clock source from 1/2 HCLK \hideinitializer */
71 #endif
72
73 #define CLK_CLKSEL0_CCAPSEL_HXT (0x0UL << CLK_CLKSEL0_CCAPSEL_Pos) /*!< Select CCAP clock source from high speed crystal \hideinitializer */
74 #define CLK_CLKSEL0_CCAPSEL_PLL (0x1UL << CLK_CLKSEL0_CCAPSEL_Pos) /*!< Select CCAP clock source from PLL \hideinitializer */
75 #define CLK_CLKSEL0_CCAPSEL_HIRC (0x3UL << CLK_CLKSEL0_CCAPSEL_Pos) /*!< Select CCAP clock source from high speed oscillator \hideinitializer */
76 #define CLK_CLKSEL0_CCAPSEL_HCLK (0x2UL << CLK_CLKSEL0_CCAPSEL_Pos) /*!< Select CCAP clock source from HCLK \hideinitializer */
77
78 #define CLK_CLKSEL0_SDH0SEL_HXT (0x0UL << CLK_CLKSEL0_SDH0SEL_Pos) /*!< Select SDH0 clock source from high speed crystal \hideinitializer */
79 #define CLK_CLKSEL0_SDH0SEL_PLL (0x1UL << CLK_CLKSEL0_SDH0SEL_Pos) /*!< Select SDH0 clock source from PLL \hideinitializer */
80 #define CLK_CLKSEL0_SDH0SEL_HIRC (0x3UL << CLK_CLKSEL0_SDH0SEL_Pos) /*!< Select SDH0 clock source from high speed oscillator \hideinitializer */
81 #define CLK_CLKSEL0_SDH0SEL_HCLK (0x2UL << CLK_CLKSEL0_SDH0SEL_Pos) /*!< Select SDH0 clock source from HCLK \hideinitializer */
82
83 #define CLK_CLKSEL0_SDH1SEL_HXT (0x0UL << CLK_CLKSEL0_SDH1SEL_Pos) /*!< Select SDH1 clock source from high speed crystal \hideinitializer */
84 #define CLK_CLKSEL0_SDH1SEL_PLL (0x1UL << CLK_CLKSEL0_SDH1SEL_Pos) /*!< Select SDH1 clock source from PLL \hideinitializer */
85 #define CLK_CLKSEL0_SDH1SEL_HIRC (0x3UL << CLK_CLKSEL0_SDH1SEL_Pos) /*!< Select SDH1 clock source from high speed oscillator \hideinitializer */
86 #define CLK_CLKSEL0_SDH1SEL_HCLK (0x2UL << CLK_CLKSEL0_SDH1SEL_Pos) /*!< Select SDH1 clock source from HCLK \hideinitializer */
87
88
89 /*---------------------------------------------------------------------------------------------------------*/
90 /* CLKSEL1 constant definitions. */
91 /*---------------------------------------------------------------------------------------------------------*/
92 #define CLK_CLKSEL1_WDTSEL_LXT (0x1UL << CLK_CLKSEL1_WDTSEL_Pos) /*!< Select WDT clock source from low speed crystal \hideinitializer */
93 #define CLK_CLKSEL1_WDTSEL_LIRC (0x3UL << CLK_CLKSEL1_WDTSEL_Pos) /*!< Select WDT clock source from low speed oscillator \hideinitializer */
94 #define CLK_CLKSEL1_WDTSEL_HCLK_DIV2048 (0x2UL << CLK_CLKSEL1_WDTSEL_Pos) /*!< Select WDT clock source from HCLK/2048 \hideinitializer */
95
96 #define CLK_CLKSEL1_TMR0SEL_HXT (0x0UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from high speed crystal \hideinitializer */
97 #define CLK_CLKSEL1_TMR0SEL_LXT (0x1UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from low speed crystal \hideinitializer */
98 #define CLK_CLKSEL1_TMR0SEL_LIRC (0x5UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from low speed oscillator \hideinitializer */
99 #define CLK_CLKSEL1_TMR0SEL_HIRC (0x7UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from high speed oscillator \hideinitializer */
100 #define CLK_CLKSEL1_TMR0SEL_PCLK0 (0x2UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from PCLK0 \hideinitializer */
101 #define CLK_CLKSEL1_TMR0SEL_EXT (0x3UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from external trigger \hideinitializer */
102
103 #define CLK_CLKSEL1_TMR1SEL_HXT (0x0UL << CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from high speed crystal \hideinitializer */
104 #define CLK_CLKSEL1_TMR1SEL_LXT (0x1UL << CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from low speed crystal \hideinitializer */
105 #define CLK_CLKSEL1_TMR1SEL_LIRC (0x5UL << CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from low speed oscillator \hideinitializer */
106 #define CLK_CLKSEL1_TMR1SEL_HIRC (0x7UL << CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from high speed oscillator \hideinitializer */
107 #define CLK_CLKSEL1_TMR1SEL_PCLK0 (0x2UL << CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from PCLK0 \hideinitializer */
108 #define CLK_CLKSEL1_TMR1SEL_EXT (0x3UL << CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from external trigger \hideinitializer */
109
110 #define CLK_CLKSEL1_TMR2SEL_HXT (0x0UL << CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from high speed crystal \hideinitializer */
111 #define CLK_CLKSEL1_TMR2SEL_LXT (0x1UL << CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from low speed crystal \hideinitializer */
112 #define CLK_CLKSEL1_TMR2SEL_LIRC (0x5UL << CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from low speed oscillator \hideinitializer */
113 #define CLK_CLKSEL1_TMR2SEL_HIRC (0x7UL << CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from high speed oscillator \hideinitializer */
114 #define CLK_CLKSEL1_TMR2SEL_PCLK1 (0x2UL << CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from PCLK1 \hideinitializer */
115 #define CLK_CLKSEL1_TMR2SEL_EXT (0x3UL << CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from external trigger \hideinitializer */
116
117 #define CLK_CLKSEL1_TMR3SEL_HXT (0x0UL << CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from high speed crystal \hideinitializer */
118 #define CLK_CLKSEL1_TMR3SEL_LXT (0x1UL << CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from low speed crystal \hideinitializer */
119 #define CLK_CLKSEL1_TMR3SEL_LIRC (0x5UL << CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from low speed oscillator \hideinitializer */
120 #define CLK_CLKSEL1_TMR3SEL_HIRC (0x7UL << CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from high speed oscillator \hideinitializer */
121 #define CLK_CLKSEL1_TMR3SEL_PCLK1 (0x2UL << CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from PCLK1 \hideinitializer */
122 #define CLK_CLKSEL1_TMR3SEL_EXT (0x3UL << CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from external trigger \hideinitializer */
123
124 #define CLK_CLKSEL1_UART0SEL_HXT (0x0UL << CLK_CLKSEL1_UART0SEL_Pos) /*!< Select UART0 clock source from high speed crystal \hideinitializer */
125 #define CLK_CLKSEL1_UART0SEL_LXT (0x2UL << CLK_CLKSEL1_UART0SEL_Pos) /*!< Select UART0 clock source from low speed crystal \hideinitializer */
126 #define CLK_CLKSEL1_UART0SEL_PLL (0x1UL << CLK_CLKSEL1_UART0SEL_Pos) /*!< Select UART0 clock source from PLL \hideinitializer */
127 #define CLK_CLKSEL1_UART0SEL_HIRC (0x3UL << CLK_CLKSEL1_UART0SEL_Pos) /*!< Select UART0 clock source from high speed oscillator \hideinitializer */
128
129 #define CLK_CLKSEL1_UART1SEL_HXT (0x0UL << CLK_CLKSEL1_UART1SEL_Pos) /*!< Select UART1 clock source from high speed crystal \hideinitializer */
130 #define CLK_CLKSEL1_UART1SEL_LXT (0x2UL << CLK_CLKSEL1_UART1SEL_Pos) /*!< Select UART1 clock source from low speed crystal \hideinitializer */
131 #define CLK_CLKSEL1_UART1SEL_PLL (0x1UL << CLK_CLKSEL1_UART1SEL_Pos) /*!< Select UART1 clock source from PLL \hideinitializer */
132 #define CLK_CLKSEL1_UART1SEL_HIRC (0x3UL << CLK_CLKSEL1_UART1SEL_Pos) /*!< Select UART1 clock source from high speed oscillator \hideinitializer */
133
134 #define CLK_CLKSEL1_CLKOSEL_HXT (0x0UL << CLK_CLKSEL1_CLKOSEL_Pos) /*!< Select CLKO clock source from high speed crystal \hideinitializer */
135 #define CLK_CLKSEL1_CLKOSEL_LXT (0x1UL << CLK_CLKSEL1_CLKOSEL_Pos) /*!< Select CLKO clock source from low speed crystal \hideinitializer */
136 #define CLK_CLKSEL1_CLKOSEL_HIRC (0x3UL << CLK_CLKSEL1_CLKOSEL_Pos) /*!< Select CLKO clock source from high speed oscillator \hideinitializer */
137 #define CLK_CLKSEL1_CLKOSEL_HCLK (0x2UL << CLK_CLKSEL1_CLKOSEL_Pos) /*!< Select CLKO clock source from HCLK \hideinitializer */
138
139 #define CLK_CLKSEL1_WWDTSEL_LIRC (0x3UL << CLK_CLKSEL1_WWDTSEL_Pos) /*!< Select WWDT clock source from low speed oscillator \hideinitializer */
140 #define CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048 (0x2UL << CLK_CLKSEL1_WWDTSEL_Pos) /*!< Select WWDT clock source from HCLK/2048 \hideinitializer */
141
142
143 /*---------------------------------------------------------------------------------------------------------*/
144 /* CLKSEL2 constant definitions. */
145 /*---------------------------------------------------------------------------------------------------------*/
146 #define CLK_CLKSEL2_QSPI0SEL_HXT (0x0UL << CLK_CLKSEL2_QSPI0SEL_Pos) /*!< Select QSPI0 clock source from high speed crystal \hideinitializer */
147 #define CLK_CLKSEL2_QSPI0SEL_PLL (0x1UL << CLK_CLKSEL2_QSPI0SEL_Pos) /*!< Select QSPI0 clock source from PLL \hideinitializer */
148 #define CLK_CLKSEL2_QSPI0SEL_HIRC (0x3UL << CLK_CLKSEL2_QSPI0SEL_Pos) /*!< Select QSPI0 clock source from high speed oscillator \hideinitializer */
149 #define CLK_CLKSEL2_QSPI0SEL_PCLK0 (0x2UL << CLK_CLKSEL2_QSPI0SEL_Pos) /*!< Select QSPI0 clock source from PCLK0 \hideinitializer */
150
151 #define CLK_CLKSEL2_SPI0SEL_HXT (0x0UL << CLK_CLKSEL2_SPI0SEL_Pos) /*!< Select SPI0 clock source from high speed crystal \hideinitializer */
152 #define CLK_CLKSEL2_SPI0SEL_PLL (0x1UL << CLK_CLKSEL2_SPI0SEL_Pos) /*!< Select SPI0 clock source from PLL \hideinitializer */
153 #define CLK_CLKSEL2_SPI0SEL_HIRC (0x3UL << CLK_CLKSEL2_SPI0SEL_Pos) /*!< Select SPI0 clock source from high speed oscillator \hideinitializer */
154 #define CLK_CLKSEL2_SPI0SEL_PCLK1 (0x2UL << CLK_CLKSEL2_SPI0SEL_Pos) /*!< Select SPI0 clock source from PCLK1 \hideinitializer */
155
156 #define CLK_CLKSEL2_SPI1SEL_HXT (0x0UL << CLK_CLKSEL2_SPI1SEL_Pos) /*!< Select SPI1 clock source from high speed crystal \hideinitializer */
157 #define CLK_CLKSEL2_SPI1SEL_PLL (0x1UL << CLK_CLKSEL2_SPI1SEL_Pos) /*!< Select SPI1 clock source from PLL \hideinitializer */
158 #define CLK_CLKSEL2_SPI1SEL_HIRC (0x3UL << CLK_CLKSEL2_SPI1SEL_Pos) /*!< Select SPI1 clock source from high speed oscillator \hideinitializer */
159 #define CLK_CLKSEL2_SPI1SEL_PCLK0 (0x2UL << CLK_CLKSEL2_SPI1SEL_Pos) /*!< Select SPI1 clock source from PCLK0 \hideinitializer */
160
161 #define CLK_CLKSEL2_EPWM0SEL_PLL (0x0UL << CLK_CLKSEL2_EPWM0SEL_Pos) /*!< Select EPWM0 clock source from PLL \hideinitializer */
162 #define CLK_CLKSEL2_EPWM0SEL_PCLK0 (0x1UL << CLK_CLKSEL2_EPWM0SEL_Pos) /*!< Select EPWM0 clock source from PCLK0 \hideinitializer */
163
164 #define CLK_CLKSEL2_EPWM1SEL_PLL (0x0UL << CLK_CLKSEL2_EPWM1SEL_Pos) /*!< Select EPWM1 clock source from PLL \hideinitializer */
165 #define CLK_CLKSEL2_EPWM1SEL_PCLK1 (0x1UL << CLK_CLKSEL2_EPWM1SEL_Pos) /*!< Select EPWM1 clock source from PCLK1 \hideinitializer */
166
167 #define CLK_CLKSEL2_BPWM0SEL_PLL (0x0UL << CLK_CLKSEL2_BPWM0SEL_Pos) /*!< Select BPWM0 clock source from PLL \hideinitializer */
168 #define CLK_CLKSEL2_BPWM0SEL_PCLK0 (0x1UL << CLK_CLKSEL2_BPWM0SEL_Pos) /*!< Select BPWM0 clock source from PCLK0 \hideinitializer */
169
170 #define CLK_CLKSEL2_BPWM1SEL_PLL (0x0UL << CLK_CLKSEL2_BPWM1SEL_Pos) /*!< Select BPWM1 clock source from PLL \hideinitializer */
171 #define CLK_CLKSEL2_BPWM1SEL_PCLK1 (0x1UL << CLK_CLKSEL2_BPWM1SEL_Pos) /*!< Select BPWM1 clock source from PCLK1 \hideinitializer */
172
173 #define CLK_CLKSEL2_SPI2SEL_HXT (0x0UL << CLK_CLKSEL2_SPI2SEL_Pos) /*!< Select SPI2 clock source from high speed crystal \hideinitializer */
174 #define CLK_CLKSEL2_SPI2SEL_PLL (0x1UL << CLK_CLKSEL2_SPI2SEL_Pos) /*!< Select SPI2 clock source from PLL \hideinitializer */
175 #define CLK_CLKSEL2_SPI2SEL_HIRC (0x3UL << CLK_CLKSEL2_SPI2SEL_Pos) /*!< Select SPI2 clock source from high speed oscillator \hideinitializer */
176 #define CLK_CLKSEL2_SPI2SEL_PCLK1 (0x2UL << CLK_CLKSEL2_SPI2SEL_Pos) /*!< Select SPI2 clock source from PCLK1 \hideinitializer */
177
178 #define CLK_CLKSEL2_SPI3SEL_HXT (0x0UL << CLK_CLKSEL2_SPI3SEL_Pos) /*!< Select SPI3 clock source from high speed crystal \hideinitializer */
179 #define CLK_CLKSEL2_SPI3SEL_PLL (0x1UL << CLK_CLKSEL2_SPI3SEL_Pos) /*!< Select SPI3 clock source from PLL \hideinitializer */
180 #define CLK_CLKSEL2_SPI3SEL_HIRC (0x3UL << CLK_CLKSEL2_SPI3SEL_Pos) /*!< Select SPI3 clock source from high speed oscillator \hideinitializer */
181 #define CLK_CLKSEL2_SPI3SEL_PCLK0 (0x2UL << CLK_CLKSEL2_SPI3SEL_Pos) /*!< Select SPI3 clock source from PCLK0 \hideinitializer */
182
183
184 /*---------------------------------------------------------------------------------------------------------*/
185 /* CLKSEL3 constant definitions. */
186 /*---------------------------------------------------------------------------------------------------------*/
187 #define CLK_CLKSEL3_SC0SEL_HXT (0x0UL << CLK_CLKSEL3_SC0SEL_Pos) /*!< Select SC0 clock source from high speed crystal \hideinitializer */
188 #define CLK_CLKSEL3_SC0SEL_PLL (0x1UL << CLK_CLKSEL3_SC0SEL_Pos) /*!< Select SC0 clock source from PLL \hideinitializer */
189 #define CLK_CLKSEL3_SC0SEL_HIRC (0x3UL << CLK_CLKSEL3_SC0SEL_Pos) /*!< Select SC0 clock source from high speed oscillator \hideinitializer */
190 #define CLK_CLKSEL3_SC0SEL_PCLK0 (0x2UL << CLK_CLKSEL3_SC0SEL_Pos) /*!< Select SC0 clock source from PCLK0 \hideinitializer */
191
192 #define CLK_CLKSEL3_SC1SEL_HXT (0x0UL << CLK_CLKSEL3_SC1SEL_Pos) /*!< Select SC1 clock source from high speed crystal \hideinitializer */
193 #define CLK_CLKSEL3_SC1SEL_PLL (0x1UL << CLK_CLKSEL3_SC1SEL_Pos) /*!< Select SC1 clock source from PLL \hideinitializer */
194 #define CLK_CLKSEL3_SC1SEL_HIRC (0x3UL << CLK_CLKSEL3_SC1SEL_Pos) /*!< Select SC1 clock source from high speed oscillator \hideinitializer */
195 #define CLK_CLKSEL3_SC1SEL_PCLK1 (0x2UL << CLK_CLKSEL3_SC1SEL_Pos) /*!< Select SC1 clock source from PCLK1 \hideinitializer */
196
197 #define CLK_CLKSEL3_SC2SEL_HXT (0x0UL << CLK_CLKSEL3_SC2SEL_Pos) /*!< Select SC2 clock source from high speed crystal \hideinitializer */
198 #define CLK_CLKSEL3_SC2SEL_PLL (0x1UL << CLK_CLKSEL3_SC2SEL_Pos) /*!< Select SC2 clock source from PLL \hideinitializer */
199 #define CLK_CLKSEL3_SC2SEL_HIRC (0x3UL << CLK_CLKSEL3_SC2SEL_Pos) /*!< Select SC2 clock source from high speed oscillator \hideinitializer */
200 #define CLK_CLKSEL3_SC2SEL_PCLK0 (0x2UL << CLK_CLKSEL3_SC2SEL_Pos) /*!< Select SC2 clock source from PCLK0 \hideinitializer */
201
202 #define CLK_CLKSEL3_RTCSEL_LXT (0x0UL << CLK_CLKSEL3_RTCSEL_Pos) /*!< Select RTC clock source from low speed crystal \hideinitializer */
203 #define CLK_CLKSEL3_RTCSEL_LIRC (0x1UL << CLK_CLKSEL3_RTCSEL_Pos) /*!< Select RTC clock source from low speed oscillator \hideinitializer */
204
205 #define CLK_CLKSEL3_QSPI1SEL_HXT (0x0UL << CLK_CLKSEL3_QSPI1SEL_Pos) /*!< Select QSPI1 clock source from high speed crystal \hideinitializer */
206 #define CLK_CLKSEL3_QSPI1SEL_PLL (0x1UL << CLK_CLKSEL3_QSPI1SEL_Pos) /*!< Select QSPI1 clock source from PLL \hideinitializer */
207 #define CLK_CLKSEL3_QSPI1SEL_HIRC (0x3UL << CLK_CLKSEL3_QSPI1SEL_Pos) /*!< Select QSPI1 clock source from high speed oscillator \hideinitializer */
208 #define CLK_CLKSEL3_QSPI1SEL_PCLK1 (0x2UL << CLK_CLKSEL3_QSPI1SEL_Pos) /*!< Select QSPI1 clock source from PCLK1 \hideinitializer */
209
210 #define CLK_CLKSEL3_I2S0SEL_HXT (0x0UL << CLK_CLKSEL3_I2S0SEL_Pos) /*!< Select I2S0 clock source from high speed crystal \hideinitializer */
211 #define CLK_CLKSEL3_I2S0SEL_PLL (0x1UL << CLK_CLKSEL3_I2S0SEL_Pos) /*!< Select I2S0 clock source from PLL \hideinitializer */
212 #define CLK_CLKSEL3_I2S0SEL_HIRC (0x3UL << CLK_CLKSEL3_I2S0SEL_Pos) /*!< Select I2S0 clock source from high speed oscillator \hideinitializer */
213 #define CLK_CLKSEL3_I2S0SEL_PCLK0 (0x2UL << CLK_CLKSEL3_I2S0SEL_Pos) /*!< Select I2S0 clock source from PCLK0 \hideinitializer */
214
215 #define CLK_CLKSEL3_UART2SEL_HXT (0x0UL << CLK_CLKSEL3_UART2SEL_Pos) /*!< Select UART2 clock source from high speed crystal \hideinitializer */
216 #define CLK_CLKSEL3_UART2SEL_LXT (0x2UL << CLK_CLKSEL3_UART2SEL_Pos) /*!< Select UART2 clock source from low speed crystal \hideinitializer */
217 #define CLK_CLKSEL3_UART2SEL_PLL (0x1UL << CLK_CLKSEL3_UART2SEL_Pos) /*!< Select UART2 clock source from PLL \hideinitializer */
218 #define CLK_CLKSEL3_UART2SEL_HIRC (0x3UL << CLK_CLKSEL3_UART2SEL_Pos) /*!< Select UART2 clock source from high speed oscillator \hideinitializer */
219
220 #define CLK_CLKSEL3_UART3SEL_HXT (0x0UL << CLK_CLKSEL3_UART3SEL_Pos) /*!< Select UART3 clock source from high speed crystal \hideinitializer */
221 #define CLK_CLKSEL3_UART3SEL_LXT (0x2UL << CLK_CLKSEL3_UART3SEL_Pos) /*!< Select UART3 clock source from low speed crystal \hideinitializer */
222 #define CLK_CLKSEL3_UART3SEL_PLL (0x1UL << CLK_CLKSEL3_UART3SEL_Pos) /*!< Select UART3 clock source from PLL \hideinitializer */
223 #define CLK_CLKSEL3_UART3SEL_HIRC (0x3UL << CLK_CLKSEL3_UART3SEL_Pos) /*!< Select UART3 clock source from high speed oscillator \hideinitializer */
224
225 #define CLK_CLKSEL3_UART4SEL_HXT (0x0UL << CLK_CLKSEL3_UART4SEL_Pos) /*!< Select UART4 clock source from high speed crystal \hideinitializer */
226 #define CLK_CLKSEL3_UART4SEL_LXT (0x2UL << CLK_CLKSEL3_UART4SEL_Pos) /*!< Select UART4 clock source from low speed crystal \hideinitializer */
227 #define CLK_CLKSEL3_UART4SEL_PLL (0x1UL << CLK_CLKSEL3_UART4SEL_Pos) /*!< Select UART4 clock source from PLL \hideinitializer */
228 #define CLK_CLKSEL3_UART4SEL_HIRC (0x3UL << CLK_CLKSEL3_UART4SEL_Pos) /*!< Select UART4 clock source from high speed oscillator \hideinitializer */
229
230 #define CLK_CLKSEL3_UART5SEL_HXT (0x0UL << CLK_CLKSEL3_UART5SEL_Pos) /*!< Select UART5 clock source from high speed crystal \hideinitializer */
231 #define CLK_CLKSEL3_UART5SEL_LXT (0x2UL << CLK_CLKSEL3_UART5SEL_Pos) /*!< Select UART5 clock source from low speed crystal \hideinitializer */
232 #define CLK_CLKSEL3_UART5SEL_PLL (0x1UL << CLK_CLKSEL3_UART5SEL_Pos) /*!< Select UART5 clock source from PLL \hideinitializer */
233 #define CLK_CLKSEL3_UART5SEL_HIRC (0x3UL << CLK_CLKSEL3_UART5SEL_Pos) /*!< Select UART5 clock source from high speed oscillator \hideinitializer */
234
235 #define CLK_CLKSEL3_UART6SEL_HXT (0x0UL << CLK_CLKSEL3_UART6SEL_Pos) /*!< Select UART6 clock source from high speed crystal \hideinitializer */
236 #define CLK_CLKSEL3_UART6SEL_LXT (0x2UL << CLK_CLKSEL3_UART6SEL_Pos) /*!< Select UART6 clock source from low speed crystal \hideinitializer */
237 #define CLK_CLKSEL3_UART6SEL_PLL (0x1UL << CLK_CLKSEL3_UART6SEL_Pos) /*!< Select UART6 clock source from PLL \hideinitializer */
238 #define CLK_CLKSEL3_UART6SEL_HIRC (0x3UL << CLK_CLKSEL3_UART6SEL_Pos) /*!< Select UART6 clock source from high speed oscillator \hideinitializer */
239
240 #define CLK_CLKSEL3_UART7SEL_HXT (0x0UL << CLK_CLKSEL3_UART7SEL_Pos) /*!< Select UART7 clock source from high speed crystal \hideinitializer */
241 #define CLK_CLKSEL3_UART7SEL_LXT (0x2UL << CLK_CLKSEL3_UART7SEL_Pos) /*!< Select UART7 clock source from low speed crystal \hideinitializer */
242 #define CLK_CLKSEL3_UART7SEL_PLL (0x1UL << CLK_CLKSEL3_UART7SEL_Pos) /*!< Select UART7 clock source from PLL \hideinitializer */
243 #define CLK_CLKSEL3_UART7SEL_HIRC (0x3UL << CLK_CLKSEL3_UART7SEL_Pos) /*!< Select UART7 clock source from high speed oscillator \hideinitializer */
244
245 /*---------------------------------------------------------------------------------------------------------*/
246 /* CLKDIV0 constant definitions. */
247 /*---------------------------------------------------------------------------------------------------------*/
248 #define CLK_CLKDIV0_HCLK(x) (((x) - 1UL) << CLK_CLKDIV0_HCLKDIV_Pos) /*!< CLKDIV0 Setting for HCLK clock divider. It could be 1~16 \hideinitializer */
249 #define CLK_CLKDIV0_USB(x) (((x) - 1UL) << CLK_CLKDIV0_USBDIV_Pos) /*!< CLKDIV0 Setting for USB clock divider. It could be 1~16 \hideinitializer */
250 #define CLK_CLKDIV0_SDH0(x) (((x) - 1UL) << CLK_CLKDIV0_SDH0DIV_Pos) /*!< CLKDIV0 Setting for SDH0 clock divider. It could be 1~256 \hideinitializer */
251 #define CLK_CLKDIV0_UART0(x) (((x) - 1UL) << CLK_CLKDIV0_UART0DIV_Pos) /*!< CLKDIV0 Setting for UART0 clock divider. It could be 1~16 \hideinitializer */
252 #define CLK_CLKDIV0_UART1(x) (((x) - 1UL) << CLK_CLKDIV0_UART1DIV_Pos) /*!< CLKDIV0 Setting for UART1 clock divider. It could be 1~16 \hideinitializer */
253 #define CLK_CLKDIV0_EADC(x) (((x) - 1UL) << CLK_CLKDIV0_EADCDIV_Pos) /*!< CLKDIV0 Setting for EADC clock divider. It could be 1~256 \hideinitializer */
254
255 /*---------------------------------------------------------------------------------------------------------*/
256 /* CLKDIV1 constant definitions. */
257 /*---------------------------------------------------------------------------------------------------------*/
258 #define CLK_CLKDIV1_SC0(x) (((x) - 1UL) << CLK_CLKDIV1_SC0DIV_Pos) /*!< CLKDIV1 Setting for SC0 clock divider. It could be 1~256 \hideinitializer */
259 #define CLK_CLKDIV1_SC1(x) (((x) - 1UL) << CLK_CLKDIV1_SC1DIV_Pos) /*!< CLKDIV1 Setting for SC1 clock divider. It could be 1~256 \hideinitializer */
260 #define CLK_CLKDIV1_SC2(x) (((x) - 1UL) << CLK_CLKDIV1_SC2DIV_Pos) /*!< CLKDIV1 Setting for SC2 clock divider. It could be 1~256 \hideinitializer */
261
262 /*---------------------------------------------------------------------------------------------------------*/
263 /* CLKDIV2 constant definitions. */
264 /*---------------------------------------------------------------------------------------------------------*/
265 #define CLK_CLKDIV2_I2S0(x) (((x) - 1UL) << CLK_CLKDIV2_I2SDIV_Pos) /*!< CLKDIV2 Setting for I2S0 clock divider. It could be 1~16 */
266 #define CLK_CLKDIV2_EADC1(x) (((x) - 1UL) << CLK_CLKDIV2_EADC1DIV_Pos) /*!< CLKDIV2 Setting for EADC1 clock divider. It could be 1~256 */
267
268 /*---------------------------------------------------------------------------------------------------------*/
269 /* CLKDIV3 constant definitions. */
270 /*---------------------------------------------------------------------------------------------------------*/
271 #define CLK_CLKDIV3_CCAP(x) (((x) - 1UL) << CLK_CLKDIV3_CCAPDIV_Pos) /*!< CLKDIV3 Setting for CCAP clock divider. It could be 1~256 */
272 #define CLK_CLKDIV3_VSENSE(x) (((x) - 1UL) << CLK_CLKDIV3_VSENSEDIV_Pos) /*!< CLKDIV3 Setting for VSENSE clock divider. It could be 1~256 */
273 #define CLK_CLKDIV3_EMAC(x) (((x) - 1UL) << CLK_CLKDIV3_EMACDIV_Pos) /*!< CLKDIV3 Setting for EMAC clock divider. It could be 1~256 \hideinitializer */
274 #define CLK_CLKDIV3_SDH1(x) (((x) - 1UL) << CLK_CLKDIV3_SDH1DIV_Pos) /*!< CLKDIV3 Setting for SDH1 clock divider. It could be 1~256 \hideinitializer */
275
276 /*---------------------------------------------------------------------------------------------------------*/
277 /* CLKDIV4 constant definitions. */
278 /*---------------------------------------------------------------------------------------------------------*/
279 #define CLK_CLKDIV4_UART2(x) (((x) - 1UL) << CLK_CLKDIV4_UART2DIV_Pos) /*!< CLKDIV4 Setting for UART2 clock divider. It could be 1~16 \hideinitializer */
280 #define CLK_CLKDIV4_UART3(x) (((x) - 1UL) << CLK_CLKDIV4_UART3DIV_Pos) /*!< CLKDIV4 Setting for UART3 clock divider. It could be 1~16 \hideinitializer */
281 #define CLK_CLKDIV4_UART4(x) (((x) - 1UL) << CLK_CLKDIV4_UART4DIV_Pos) /*!< CLKDIV4 Setting for UART4 clock divider. It could be 1~16 \hideinitializer */
282 #define CLK_CLKDIV4_UART5(x) (((x) - 1UL) << CLK_CLKDIV4_UART5DIV_Pos) /*!< CLKDIV4 Setting for UART5 clock divider. It could be 1~16 \hideinitializer */
283 #define CLK_CLKDIV4_UART6(x) (((x) - 1UL) << CLK_CLKDIV4_UART6DIV_Pos) /*!< CLKDIV4 Setting for UART6 clock divider. It could be 1~16 */
284 #define CLK_CLKDIV4_UART7(x) (((x) - 1UL) << CLK_CLKDIV4_UART7DIV_Pos) /*!< CLKDIV4 Setting for UART7 clock divider. It could be 1~16 */
285
286 /*---------------------------------------------------------------------------------------------------------*/
287 /* PCLKDIV constant definitions. */
288 /*---------------------------------------------------------------------------------------------------------*/
289 #define CLK_PCLKDIV_PCLK0DIV1 (0x0UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = HCLK \hideinitializer */
290 #define CLK_PCLKDIV_PCLK0DIV2 (0x1UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/2 HCLK \hideinitializer */
291 #define CLK_PCLKDIV_PCLK0DIV4 (0x2UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/4 HCLK \hideinitializer */
292 #define CLK_PCLKDIV_PCLK0DIV8 (0x3UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/8 HCLK \hideinitializer */
293 #define CLK_PCLKDIV_PCLK0DIV16 (0x4UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/16 HCLK \hideinitializer */
294 #define CLK_PCLKDIV_PCLK1DIV1 (0x0UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = HCLK \hideinitializer */
295 #define CLK_PCLKDIV_PCLK1DIV2 (0x1UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/2 HCLK \hideinitializer */
296 #define CLK_PCLKDIV_PCLK1DIV4 (0x2UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/4 HCLK \hideinitializer */
297 #define CLK_PCLKDIV_PCLK1DIV8 (0x3UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/8 HCLK \hideinitializer */
298 #define CLK_PCLKDIV_PCLK1DIV16 (0x4UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/16 HCLK \hideinitializer */
299 //
300 #define CLK_PCLKDIV_APB0DIV_DIV1 (0x0UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = HCLK \hideinitializer */
301 #define CLK_PCLKDIV_APB0DIV_DIV2 (0x1UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/2 HCLK \hideinitializer */
302 #define CLK_PCLKDIV_APB0DIV_DIV4 (0x2UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/4 HCLK \hideinitializer */
303 #define CLK_PCLKDIV_APB0DIV_DIV8 (0x3UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/8 HCLK \hideinitializer */
304 #define CLK_PCLKDIV_APB0DIV_DIV16 (0x4UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/16 HCLK \hideinitializer */
305 #define CLK_PCLKDIV_APB1DIV_DIV1 (0x0UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = HCLK \hideinitializer */
306 #define CLK_PCLKDIV_APB1DIV_DIV2 (0x1UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/2 HCLK \hideinitializer */
307 #define CLK_PCLKDIV_APB1DIV_DIV4 (0x2UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/4 HCLK \hideinitializer */
308 #define CLK_PCLKDIV_APB1DIV_DIV8 (0x3UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/8 HCLK \hideinitializer */
309 #define CLK_PCLKDIV_APB1DIV_DIV16 (0x4UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/16 HCLK \hideinitializer */
310
311 /*---------------------------------------------------------------------------------------------------------*/
312 /* PLLCTL constant definitions. PLL = FIN * 2 * NF / NR / NO */
313 /*---------------------------------------------------------------------------------------------------------*/
314 #define CLK_PLLCTL_PLLSRC_HXT 0x00000000UL /*!< For PLL clock source is HXT. 4MHz < FIN/NR < 8MHz \hideinitializer */
315 #define CLK_PLLCTL_PLLSRC_HIRC 0x00080000UL /*!< For PLL clock source is HIRC. 4MHz < FIN/NR < 8MHz \hideinitializer */
316
317 #define CLK_PLLCTL_NF(x) (((x)-2UL)) /*!< x must be constant and 2 <= x <= 513. 200MHz < FIN*2*NF/NR < 500MHz. \hideinitializer */
318 #define CLK_PLLCTL_NR(x) (((x)-1UL)<<9) /*!< x must be constant and 1 <= x <= 32. 4MHz < FIN/NR < 8MHz \hideinitializer */
319
320 #define CLK_PLLCTL_NO_1 0x0000UL /*!< For output divider is 1 \hideinitializer */
321 #define CLK_PLLCTL_NO_2 0x4000UL /*!< For output divider is 2 \hideinitializer */
322 #define CLK_PLLCTL_NO_4 0xC000UL /*!< For output divider is 4 \hideinitializer */
323
324 #define CLK_PLLCTL_72MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 36UL) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 72MHz PLL output with HXT(12MHz X'tal) \hideinitializer */
325 #define CLK_PLLCTL_80MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 40UL) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 80MHz PLL output with HXT(12MHz X'tal) \hideinitializer */
326 #define CLK_PLLCTL_144MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF( 24UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 144MHz PLL output with HXT(12MHz X'tal) \hideinitializer */
327 #define CLK_PLLCTL_160MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 40UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 160MHz PLL output with HXT(12MHz X'tal) \hideinitializer */
328 #define CLK_PLLCTL_192MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF( 32UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 192MHz PLL output with HXT(12MHz X'tal) \hideinitializer */
329
330 #define CLK_PLLCTL_72MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 36UL) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 72MHz PLL output with HIRC(12MHz IRC) \hideinitializer */
331 #define CLK_PLLCTL_80MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 40UL) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 80MHz PLL output with HIRC(12MHz IRC) \hideinitializer */
332 #define CLK_PLLCTL_144MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF( 24UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 144MHz PLL output with HIRC(12MHz IRC) \hideinitializer */
333 #define CLK_PLLCTL_160MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 40UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 160MHz PLL output with HIRC(12MHz IRC) \hideinitializer */
334 #define CLK_PLLCTL_192MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF( 32UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 192MHz PLL output with HIRC(12MHz IRC) \hideinitializer */
335
336 /*---------------------------------------------------------------------------------------------------------*/
337 /* MODULE constant definitions. */
338 /*---------------------------------------------------------------------------------------------------------*/
339
340 /* APBCLK(31:30)|CLKSEL(29:28)|CLKSEL_Msk(27:25) |CLKSEL_Pos(24:20)|CLKDIV(19:18)|CLKDIV_Msk(17:10)|CLKDIV_Pos(9:5)|IP_EN_Pos(4:0) */
341
342 #define MODULE_APBCLK(x) (((x) >>30) & 0x3UL) /*!< Calculate AHBCLK/APBCLK offset on MODULE index, 0x0:AHBCLK, 0x1:APBCLK0, 0x2:APBCLK1 \hideinitializer */
343 #define MODULE_CLKSEL(x) (((x) >>28) & 0x3UL) /*!< Calculate CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3 \hideinitializer */
344 #define MODULE_CLKSEL_Msk(x) (((x) >>25) & 0x7UL) /*!< Calculate CLKSEL mask offset on MODULE index \hideinitializer */
345 #define MODULE_CLKSEL_Pos(x) (((x) >>20) & 0x1fUL) /*!< Calculate CLKSEL position offset on MODULE index \hideinitializer */
346 #define MODULE_CLKDIV(x) (((x) >>18) & 0x3UL) /*!< Calculate APBCLK CLKDIV on MODULE index, 0x0:CLKDIV0, 0x1:CLKDIV1, 0x2:CLKDIV3, 0x3:CLKDIV4 \hideinitializer */
347 #define MODULE_CLKDIV_Msk(x) (((x) >>10) & 0xffUL) /*!< Calculate CLKDIV mask offset on MODULE index \hideinitializer */
348 #define MODULE_CLKDIV_Pos(x) (((x) >>5 ) & 0x1fUL) /*!< Calculate CLKDIV position offset on MODULE index \hideinitializer */
349 #define MODULE_IP_EN_Pos(x) (((x) >>0 ) & 0x1fUL) /*!< Calculate APBCLK offset on MODULE index \hideinitializer */
350 #define MODULE_NoMsk 0x0UL /*!< Not mask on MODULE index \hideinitializer */
351 #define NA MODULE_NoMsk /*!< Not Available \hideinitializer */
352
353 #define MODULE_APBCLK_ENC(x) (((x) & 0x03UL) << 30) /*!< MODULE index, 0x0:AHBCLK, 0x1:APBCLK0, 0x2:APBCLK1 \hideinitializer */
354 #define MODULE_CLKSEL_ENC(x) (((x) & 0x03UL) << 28) /*!< CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3 \hideinitializer */
355 #define MODULE_CLKSEL_Msk_ENC(x) (((x) & 0x07UL) << 25) /*!< CLKSEL mask offset on MODULE index \hideinitializer */
356 #define MODULE_CLKSEL_Pos_ENC(x) (((x) & 0x1fUL) << 20) /*!< CLKSEL position offset on MODULE index \hideinitializer */
357 #define MODULE_CLKDIV_ENC(x) (((x) & 0x03UL) << 18) /*!< APBCLK CLKDIV on MODULE index, 0x0:CLKDIV0, 0x1:CLKDIV1, 0x2:CLKDIV3, 0x3:CLKDIV4 \hideinitializer */
358 #define MODULE_CLKDIV_Msk_ENC(x) (((x) & 0xffUL) << 10) /*!< CLKDIV mask offset on MODULE index \hideinitializer */
359 #define MODULE_CLKDIV_Pos_ENC(x) (((x) & 0x1fUL) << 5) /*!< CLKDIV position offset on MODULE index \hideinitializer */
360 #define MODULE_IP_EN_Pos_ENC(x) (((x) & 0x1fUL) << 0) /*!< AHBCLK/APBCLK offset on MODULE index \hideinitializer */
361
362 #define PDMA_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(1UL<<0)) /*!< PDMA Module \hideinitializer */
363 #define ISP_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(2UL<<0)) /*!< ISP Module \hideinitializer */
364 #define EBI_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(3UL<<0)) /*!< EBI Module \hideinitializer */
365 #define USBH_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(16UL<<0)) /*!< USBH Module \hideinitializer */
366 #define EMAC_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(2UL<<18) |(0xFFUL<<10) |(16UL<<5) |(5UL<<0)) /*!< EMAC Module \hideinitializer */
367 #define SDH0_MODULE ((0UL<<30)|(0UL<<28) |(0x3UL<<25) |(20UL<<20) |(0UL<<18) |(0xFFUL<<10) |(24UL<<5) |(6UL<<0)) /*!< SDH0 Module \hideinitializer */
368 #define CRC_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(7UL<<0)) /*!< CRC Module \hideinitializer */
369 #define CCAP_MODULE ((0UL<<30)|(0UL<<28) |(0x3UL<<25) |(16UL<<20) |(2UL<<18) |(0xFFUL<<10) |(0UL<<5) |(8UL<<0)) /*!< CCAP Module \hideinitializer */
370 #define SEN_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(9UL<<0)) /*!< SEN Module \hideinitializer */
371 #define HSUSBD_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(10UL<<0)) /*!< HSUSBD Module \hideinitializer */
372 #define CRPT_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(12UL<<0)) /*!< CRPT Module \hideinitializer */
373 #define SPIM_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(14UL<<0)) /*!< SPIM Module \hideinitializer */
374 #define FMCIDLE_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(15UL<<0)) /*!< FMCIDLE Module \hideinitializer */
375 #define SDH1_MODULE ((0UL<<30)|(0UL<<28) |(0x3UL<<25) |(22UL<<20) |(2UL<<18) |(0xFFUL<<10) |(24UL<<5) |(17UL<<0)) /*!< SDH1 Module \hideinitializer */
376 #define WDT_MODULE ((1UL<<30)|(1UL<<28) |(0x3UL<<25) |(0UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(0UL<<0)) /*!< WDT Module \hideinitializer */
377 #define RTC_MODULE ((1UL<<30)|(3UL<<28) |(0x1UL<<25) |(8UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(1UL<<0)) /*!< RTC Module \hideinitializer */
378 #define TMR0_MODULE ((1UL<<30)|(1UL<<28) |(0x7UL<<25) |(8UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(2UL<<0)) /*!< TMR0 Module \hideinitializer */
379 #define TMR1_MODULE ((1UL<<30)|(1UL<<28) |(0x7UL<<25) |(12UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(3UL<<0)) /*!< TMR1 Module \hideinitializer */
380 #define TMR2_MODULE ((1UL<<30)|(1UL<<28) |(0x7UL<<25) |(16UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(4UL<<0)) /*!< TMR2 Module \hideinitializer */
381 #define TMR3_MODULE ((1UL<<30)|(1UL<<28) |(0x7UL<<25) |(20UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(5UL<<0)) /*!< TMR3 Module \hideinitializer */
382 #define CLKO_MODULE ((1UL<<30)|(1UL<<28) |(0x3UL<<25) |(28UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(6UL<<0)) /*!< CLKO Module \hideinitializer */
383 #define WWDT_MODULE ((1UL<<30)|(1UL<<28) |(0x3UL<<25) |(30UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(0UL<<0)) /*!< WWDT Module \hideinitializer */
384 #define ACMP01_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(7UL<<0)) /*!< ACMP01 Module \hideinitializer */
385 #define I2C0_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(8UL<<0)) /*!< I2C0 Module \hideinitializer */
386 #define I2C1_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(9UL<<0)) /*!< I2C1 Module \hideinitializer */
387 #define I2C2_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(10UL<<0)) /*!< I2C2 Module \hideinitializer */
388 #define QSPI0_MODULE ((1UL<<30)|(2UL<<28) |(0x3UL<<25) |(2UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(12UL<<0)) /*!< QSPI0 Module \hideinitializer */
389 #define SPI0_MODULE ((1UL<<30)|(2UL<<28) |(0x3UL<<25) |(4UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(13UL<<0)) /*!< SPI0 Module \hideinitializer */
390 #define SPI1_MODULE ((1UL<<30)|(2UL<<28) |(0x3UL<<25) |(6UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(14UL<<0)) /*!< SPI1 Module \hideinitializer */
391 #define SPI2_MODULE ((1UL<<30)|(2UL<<28) |(0x3UL<<25) |(10UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(15UL<<0)) /*!< SPI2 Module \hideinitializer */
392 #define UART0_MODULE ((1UL<<30)|(1UL<<28) |(0x3UL<<25) |(24UL<<20) |(0UL<<18) |(0xFUL<<10) |(8UL<<5) |(16UL<<0)) /*!< UART0 Module \hideinitializer */
393 #define UART1_MODULE ((1UL<<30)|(1UL<<28) |(0x3UL<<25) |(26UL<<20) |(0UL<<18) |(0xFUL<<10) |(12UL<<5) |(17UL<<0)) /*!< UART1 Module \hideinitializer */
394 #define UART2_MODULE ((1UL<<30)|(3UL<<28) |(0x3UL<<25) |(24UL<<20) |(3UL<<18) |(0xFUL<<10) |(0UL<<5) |(18UL<<0)) /*!< UART2 Module \hideinitializer */
395 #define UART3_MODULE ((1UL<<30)|(3UL<<28) |(0x3UL<<25) |(26UL<<20) |(3UL<<18) |(0xFUL<<10) |(4UL<<5) |(19UL<<0)) /*!< UART3 Module \hideinitializer */
396 #define UART4_MODULE ((1UL<<30)|(3UL<<28) |(0x3UL<<25) |(28UL<<20) |(3UL<<18) |(0xFUL<<10) |(8UL<<5) |(20UL<<0)) /*!< UART4 Module \hideinitializer */
397 #define UART5_MODULE ((1UL<<30)|(3UL<<28) |(0x3UL<<25) |(30UL<<20) |(3UL<<18) |(0xFUL<<10) |(12UL<<5) |(21UL<<0)) /*!< UART5 Module \hideinitializer */
398 #define UART6_MODULE ((1UL<<30)|(3UL<<28) |(0x3UL<<25) |(20UL<<20) |(3UL<<18) |(0xFUL<<10) |(16UL<<5) |(22UL<<0)) /*!< UART6 Module \hideinitializer */
399 #define UART7_MODULE ((1UL<<30)|(3UL<<28) |(0x3UL<<25) |(22UL<<20) |(3UL<<18) |(0xFUL<<10) |(20UL<<5) |(23UL<<0)) /*!< UART7 Module \hideinitializer */
400 #define CAN0_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(24UL<<0)) /*!< CAN0 Module \hideinitializer */
401 #define CAN1_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(25UL<<0)) /*!< CAN1 Module \hideinitializer */
402 #define OTG_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(26UL<<0)) /*!< OTG Module \hideinitializer */
403 #define USBD_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(27UL<<0)) /*!< USBD Module \hideinitializer */
404 #define EADC_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(0UL<<18) |(0xFFUL<<10) |(16UL<<5) |(28UL<<0)) /*!< EADC Module \hideinitializer */
405 #define I2S0_MODULE ((1UL<<30)|(3UL<<28) |(0x3UL<<25) |(16UL<<20) |(2UL<<18) |(0xFUL<<10) |(0UL<<5) |(29UL<<0)) /*!< I2S0 Module \hideinitializer */
406 #define HSOTG_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(30UL<<0)) /*!< HSOTG Module \hideinitializer */
407 #define SC0_MODULE ((2UL<<30)|(3UL<<28) |(0x3UL<<25) |(0UL<<20) |(1UL<<18) |(0xFFUL<<10) |(0UL<<5) |(0UL<<0)) /*!< SC0 Module \hideinitializer */
408 #define SC1_MODULE ((2UL<<30)|(3UL<<28) |(0x3UL<<25) |(2UL<<20) |(1UL<<18) |(0xFFUL<<10) |(8UL<<5) |(1UL<<0)) /*!< SC1 Module \hideinitializer */
409 #define SC2_MODULE ((2UL<<30)|(3UL<<28) |(0x3UL<<25) |(4UL<<20) |(1UL<<18) |(0xFFUL<<10) |(16UL<<5) |(2UL<<0)) /*!< SC2 Module \hideinitializer */
410 #define QSPI1_MODULE ((2UL<<30)|(3UL<<28) |(0x3UL<<25) |(12UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(4UL<<0)) /*!< QSPI1 Module \hideinitializer */
411 #define SPI3_MODULE ((2UL<<30)|(2UL<<28) |(0x3UL<<25) |(12UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(6UL<<0)) /*!< SPI3 Module \hideinitializer */
412 #define USCI0_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(8UL<<0)) /*!< USCI0 Module \hideinitializer */
413 #define USCI1_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(9UL<<0)) /*!< USCI1 Module \hideinitializer */
414 #define DAC_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(12UL<<0)) /*!< DAC Module \hideinitializer */
415 #define CAN2_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(28UL<<0)) /*!< CAN2 Module \hideinitializer */
416 #define EPWM0_MODULE ((2UL<<30)|(2UL<<28) |(0x1UL<<25) |(0UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(16UL<<0)) /*!< EPWM0 Module \hideinitializer */
417 #define EPWM1_MODULE ((2UL<<30)|(2UL<<28) |(0x1UL<<25) |(1UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(17UL<<0)) /*!< EPWM1 Module \hideinitializer */
418 #define BPWM0_MODULE ((2UL<<30)|(2UL<<28) |(0x1UL<<25) |(8UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(18UL<<0)) /*!< BPWM0 Module \hideinitializer */
419 #define BPWM1_MODULE ((2UL<<30)|(2UL<<28) |(0x1UL<<25) |(9UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(19UL<<0)) /*!< BPWM1 Module \hideinitializer */
420 #define QEI0_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(22UL<<0)) /*!< QEI0 Module \hideinitializer */
421 #define QEI1_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(23UL<<0)) /*!< QEI1 Module \hideinitializer */
422 #define TRNG_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(25UL<<0)) /*!< TRNG Module \hideinitializer */
423 #define ECAP0_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(26UL<<0)) /*!< ECAP0 Module \hideinitializer */
424 #define ECAP1_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(27UL<<0)) /*!< ECAP1 Module \hideinitializer */
425 #define OPA_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(30UL<<0)) /*!< OPA Module \hideinitializer */
426 #define EADC1_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(2UL<<18) |(0xFFUL<<10) |(24UL<<5) |(31UL<<0)) /*!< EADC1 Module \hideinitializer */
427
428 /*---------------------------------------------------------------------------------------------------------*/
429 /* PDMSEL constant definitions. */
430 /*---------------------------------------------------------------------------------------------------------*/
431 #define CLK_PMUCTL_PDMSEL_PD (0x0UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mode is Power-down mode \hideinitializer */
432 #define CLK_PMUCTL_PDMSEL_LLPD (0x1UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mode is Low leakage Power-down mode \hideinitializer */
433 #define CLK_PMUCTL_PDMSEL_FWPD (0x2UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mode is Fast wake-up Power-down mode \hideinitializer */
434 #define CLK_PMUCTL_PDMSEL_SPD0 (0x4UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mode is Standby Power-down mode 0 \hideinitializer */
435 #define CLK_PMUCTL_PDMSEL_SPD1 (0x5UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mode is Standby Power-down mode 1 \hideinitializer */
436 #define CLK_PMUCTL_PDMSEL_DPD (0x6UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mode is Deep Power-down mode \hideinitializer */
437
438 /*---------------------------------------------------------------------------------------------------------*/
439 /* WKTMRIS constant definitions. */
440 /*---------------------------------------------------------------------------------------------------------*/
441 #define CLK_PMUCTL_WKTMRIS_128 (0x0UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 128 OSC10K clocks (12.8 ms) \hideinitializer */
442 #define CLK_PMUCTL_WKTMRIS_256 (0x1UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 256 OSC10K clocks (25.6 ms) \hideinitializer */
443 #define CLK_PMUCTL_WKTMRIS_512 (0x2UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 512 OSC10K clocks (51.2 ms) \hideinitializer */
444 #define CLK_PMUCTL_WKTMRIS_1024 (0x3UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 1024 OSC10K clocks (102.4ms) \hideinitializer */
445 #define CLK_PMUCTL_WKTMRIS_4096 (0x4UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 4096 OSC10K clocks (409.6ms) \hideinitializer */
446 #define CLK_PMUCTL_WKTMRIS_8192 (0x5UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 8192 OSC10K clocks (819.2ms) \hideinitializer */
447 #define CLK_PMUCTL_WKTMRIS_16384 (0x6UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 16384 OSC10K clocks (1638.4ms) \hideinitializer */
448 #define CLK_PMUCTL_WKTMRIS_65536 (0x7UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 65536 OSC10K clocks (6553.6ms) \hideinitializer */
449 #define CLK_PMUCTL_WKTMRIS_131072 (0x8UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 131072 OSC10K clocks (13107.2 ms) \hideinitializer */
450 #define CLK_PMUCTL_WKTMRIS_262144 (0x9UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 262144 OSC10K clocks (26214.4 ms) \hideinitializer */
451 #define CLK_PMUCTL_WKTMRIS_524288 (0xaUL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 524288 OSC10K clocks (52428.8ms) \hideinitializer */
452 #define CLK_PMUCTL_WKTMRIS_1048576 (0xbUL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 1048576 OSC10K clocks (104857.6ms) \hideinitializer */
453
454 /*---------------------------------------------------------------------------------------------------------*/
455 /* SWKDBCLKSEL constant definitions. */
456 /*---------------------------------------------------------------------------------------------------------*/
457 #define CLK_SWKDBCTL_SWKDBCLKSEL_1 (0x0UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 1 clocks \hideinitializer */
458 #define CLK_SWKDBCTL_SWKDBCLKSEL_2 (0x1UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 2 clocks \hideinitializer */
459 #define CLK_SWKDBCTL_SWKDBCLKSEL_4 (0x2UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 4 clocks \hideinitializer */
460 #define CLK_SWKDBCTL_SWKDBCLKSEL_8 (0x3UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 8 clocks \hideinitializer */
461 #define CLK_SWKDBCTL_SWKDBCLKSEL_16 (0x4UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 16 clocks \hideinitializer */
462 #define CLK_SWKDBCTL_SWKDBCLKSEL_32 (0x5UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 32 clocks \hideinitializer */
463 #define CLK_SWKDBCTL_SWKDBCLKSEL_64 (0x6UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 64 clocks \hideinitializer */
464 #define CLK_SWKDBCTL_SWKDBCLKSEL_128 (0x7UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 128 clocks \hideinitializer */
465 #define CLK_SWKDBCTL_SWKDBCLKSEL_256 (0x8UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 256 clocks \hideinitializer */
466 #define CLK_SWKDBCTL_SWKDBCLKSEL_2x256 (0x9UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 2x256 clocks \hideinitializer */
467 #define CLK_SWKDBCTL_SWKDBCLKSEL_4x256 (0xaUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 4x256 clocks \hideinitializer */
468 #define CLK_SWKDBCTL_SWKDBCLKSEL_8x256 (0xbUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 8x256 clocks \hideinitializer */
469 #define CLK_SWKDBCTL_SWKDBCLKSEL_16x256 (0xcUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 16x256 clocks \hideinitializer */
470 #define CLK_SWKDBCTL_SWKDBCLKSEL_32x256 (0xdUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 32x256 clocks \hideinitializer */
471 #define CLK_SWKDBCTL_SWKDBCLKSEL_64x256 (0xeUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 64x256 clocks \hideinitializer */
472 #define CLK_SWKDBCTL_SWKDBCLKSEL_128x256 (0xfUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 128x256 clocks \hideinitializer */
473
474 /*---------------------------------------------------------------------------------------------------------*/
475 /* DPD Pin Rising/Falling Edge Wake-up Enable constant definitions. */
476 /*---------------------------------------------------------------------------------------------------------*/
477 #define CLK_DPDWKPIN_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Disable Wake-up pin at Deep Power-down mode \hideinitializer */
478 #define CLK_DPDWKPIN_RISING (0x1UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Enable Wake-up pin rising edge at Deep Power-down mode \hideinitializer */
479 #define CLK_DPDWKPIN_FALLING (0x2UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Enable Wake-up pin falling edge at Deep Power-down mode \hideinitializer */
480 #define CLK_DPDWKPIN_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Enable Wake-up pin both edge at Deep Power-down mode \hideinitializer */
481
482 #define CLK_DPDWKPIN0_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Disable Wake-up pin0 (GPC.0) at Deep Power-down mode \hideinitializer */
483 #define CLK_DPDWKPIN0_RISING (0x1UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Enable Wake-up pin0 (GPC.0) rising edge at Deep Power-down mode \hideinitializer */
484 #define CLK_DPDWKPIN0_FALLING (0x2UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Enable Wake-up pin0 (GPC.0) falling edge at Deep Power-down mode \hideinitializer */
485 #define CLK_DPDWKPIN0_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Enable Wake-up pin0 (GPC.0) both edge at Deep Power-down mode \hideinitializer */
486
487 #define CLK_DPDWKPIN1_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN1_Pos) /*!< Disable Wake-up pin1 (GPB.0) at Deep Power-down mode \hideinitializer */
488 #define CLK_DPDWKPIN1_RISING (0x1UL << CLK_PMUCTL_WKPINEN1_Pos) /*!< Enable Wake-up pin1 (GPB.0) rising edge at Deep Power-down mode \hideinitializer */
489 #define CLK_DPDWKPIN1_FALLING (0x2UL << CLK_PMUCTL_WKPINEN1_Pos) /*!< Enable Wake-up pin1 (GPB.0) falling edge at Deep Power-down mode \hideinitializer */
490 #define CLK_DPDWKPIN1_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN1_Pos) /*!< Enable Wake-up pin1 (GPB.0) both edge at Deep Power-down mode \hideinitializer */
491
492 #define CLK_DPDWKPIN2_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN2_Pos) /*!< Disable Wake-up pin2 (GPB.2) at Deep Power-down mode \hideinitializer */
493 #define CLK_DPDWKPIN2_RISING (0x1UL << CLK_PMUCTL_WKPINEN2_Pos) /*!< Enable Wake-up pin2 (GPB.2) rising edge at Deep Power-down mode \hideinitializer */
494 #define CLK_DPDWKPIN2_FALLING (0x2UL << CLK_PMUCTL_WKPINEN2_Pos) /*!< Enable Wake-up pin2 (GPB.2) falling edge at Deep Power-down mode \hideinitializer */
495 #define CLK_DPDWKPIN2_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN2_Pos) /*!< Enable Wake-up pin2 (GPB.2) both edge at Deep Power-down mode \hideinitializer */
496
497 #define CLK_DPDWKPIN3_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN3_Pos) /*!< Disable Wake-up pin3 (GPB.12) at Deep Power-down mode \hideinitializer */
498 #define CLK_DPDWKPIN3_RISING (0x1UL << CLK_PMUCTL_WKPINEN3_Pos) /*!< Enable Wake-up pin3 (GPB.12) rising edge at Deep Power-down mode \hideinitializer */
499 #define CLK_DPDWKPIN3_FALLING (0x2UL << CLK_PMUCTL_WKPINEN3_Pos) /*!< Enable Wake-up pin3 (GPB.12) falling edge at Deep Power-down mode \hideinitializer */
500 #define CLK_DPDWKPIN3_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN3_Pos) /*!< Enable Wake-up pin3 (GPB.12) both edge at Deep Power-down mode \hideinitializer */
501
502 #define CLK_DPDWKPIN4_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN4_Pos) /*!< Disable Wake-up pin4 (GPF.6) at Deep Power-down mode \hideinitializer */
503 #define CLK_DPDWKPIN4_RISING (0x1UL << CLK_PMUCTL_WKPINEN4_Pos) /*!< Enable Wake-up pin4 (GPF.6) rising edge at Deep Power-down mode \hideinitializer */
504 #define CLK_DPDWKPIN4_FALLING (0x2UL << CLK_PMUCTL_WKPINEN4_Pos) /*!< Enable Wake-up pin4 (GPF.6) falling edge at Deep Power-down mode \hideinitializer */
505 #define CLK_DPDWKPIN4_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN4_Pos) /*!< Enable Wake-up pin4 (GPF.6) both edge at Deep Power-down mode \hideinitializer */
506
507 /*---------------------------------------------------------------------------------------------------------*/
508 /* SPD Pin Rising/Falling Edge Wake-up Enable constant definitions. */
509 /*---------------------------------------------------------------------------------------------------------*/
510 #define CLK_SPDWKPIN_ENABLE (0x1UL << 0) /*!< Enable Standby Power-down Pin Wake-up \hideinitializer */
511 #define CLK_SPDWKPIN_RISING (0x1UL << 1) /*!< Standby Power-down Wake-up on Standby Power-down Pin rising edge \hideinitializer */
512 #define CLK_SPDWKPIN_FALLING (0x1UL << 2) /*!< Standby Power-down Wake-up on Standby Power-down Pin falling edge \hideinitializer */
513 #define CLK_SPDWKPIN_DEBOUNCEEN (0x1UL << 8) /*!< Enable Standby power-down pin De-bounce function \hideinitializer */
514 #define CLK_SPDWKPIN_DEBOUNCEDIS (0x0UL << 8) /*!< Disable Standby power-down pin De-bounce function \hideinitializer */
515
516 #define CLK_SPDSRETSEL_NO (0x0UL << CLK_PMUCTL_SRETSEL_Pos) /*!< No SRAM retention when chip enter SPD mode \hideinitializer */
517 #define CLK_SPDSRETSEL_16K (0x1UL << CLK_PMUCTL_SRETSEL_Pos) /*!< 16K SRAM retention when chip enter SPD mode \hideinitializer */
518 #define CLK_SPDSRETSEL_32K (0x2UL << CLK_PMUCTL_SRETSEL_Pos) /*!< 32K SRAM retention when chip enter SPD mode \hideinitializer */
519 #define CLK_SPDSRETSEL_64K (0x3UL << CLK_PMUCTL_SRETSEL_Pos) /*!< 64K SRAM retention when chip enter SPD mode \hideinitializer */
520 #define CLK_SPDSRETSEL_128K (0x4UL << CLK_PMUCTL_SRETSEL_Pos) /*!< 128K SRAM retention when chip enter SPD mode \hideinitializer */
521
522 #define CLK_DISABLE_WKTMR(void) (CLK->PMUCTL &= ~CLK_PMUCTL_WKTMREN_Msk) /*!< Disable Wake-up timer at Standby or Deep Power-down mode \hideinitializer */
523 #define CLK_ENABLE_WKTMR(void) (CLK->PMUCTL |= CLK_PMUCTL_WKTMREN_Msk) /*!< Enable Wake-up timer at Standby or Deep Power-down mode \hideinitializer */
524 #define CLK_DISABLE_DPDWKPIN(void) (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN_Msk) /*!< Disable Wake-up pin at Deep Power-down mode \hideinitializer */
525 #define CLK_DISABLE_DPDWKPIN0(void) (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN_Msk) /*!< Disable Wake-up pin0 (GPC.0) at Deep Power-down mode \hideinitializer */
526 #define CLK_DISABLE_DPDWKPIN1(void) (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN1_Msk) /*!< Disable Wake-up pin1 (GPB.0) at Deep Power-down mode \hideinitializer */
527 #define CLK_DISABLE_DPDWKPIN2(void) (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN2_Msk) /*!< Disable Wake-up pin2 (GPB.2) at Deep Power-down mode \hideinitializer */
528 #define CLK_DISABLE_DPDWKPIN3(void) (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN3_Msk) /*!< Disable Wake-up pin3 (GPB.12) at Deep Power-down mode \hideinitializer */
529 #define CLK_DISABLE_DPDWKPIN4(void) (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN4_Msk) /*!< Disable Wake-up pin4 (GPF.6) at Deep Power-down mode \hideinitializer */
530 #define CLK_DISABLE_SPDACMP(void) (CLK->PMUCTL &= ~CLK_PMUCTL_ACMPSPWK_Msk) /*!< Disable ACMP wake-up at Standby Power-down mode \hideinitializer */
531 #define CLK_ENABLE_SPDACMP(void) (CLK->PMUCTL |= CLK_PMUCTL_ACMPSPWK_Msk) /*!< Enable ACMP wake-up at Standby Power-down mode \hideinitializer */
532 #define CLK_DISABLE_RTCWK(void) (CLK->PMUCTL &= ~CLK_PMUCTL_RTCWKEN_Msk) /*!< Disable RTC Wake-up at Standby or Deep Power-down mode \hideinitializer */
533 #define CLK_ENABLE_RTCWK(void) (CLK->PMUCTL |= CLK_PMUCTL_RTCWKEN_Msk) /*!< Enable RTC Wake-up at Standby or Deep Power-down mode \hideinitializer */
534
535 /*@}*/ /* end of group CLK_EXPORTED_CONSTANTS */
536
537 /** @addtogroup CLK_EXPORTED_FUNCTIONS CLK Exported Functions
538 @{
539 */
540
541 /**
542 * @brief Set Wake-up Timer Time-out Interval
543 *
544 * @param[in] u32Interval The Wake-up Timer Time-out Interval selection. It could be
545 * - \ref CLK_PMUCTL_WKTMRIS_128
546 * - \ref CLK_PMUCTL_WKTMRIS_256
547 * - \ref CLK_PMUCTL_WKTMRIS_512
548 * - \ref CLK_PMUCTL_WKTMRIS_1024
549 * - \ref CLK_PMUCTL_WKTMRIS_4096
550 * - \ref CLK_PMUCTL_WKTMRIS_8192
551 * - \ref CLK_PMUCTL_WKTMRIS_16384
552 * - \ref CLK_PMUCTL_WKTMRIS_65536
553 * - \ref CLK_PMUCTL_WKTMRIS_131072
554 * - \ref CLK_PMUCTL_WKTMRIS_262144
555 * - \ref CLK_PMUCTL_WKTMRIS_524288
556 * - \ref CLK_PMUCTL_WKTMRIS_1048576
557 *
558 * @return None
559 *
560 * @details This function set Wake-up Timer Time-out Interval.
561 *
562 * \hideinitializer
563 */
564 #define CLK_SET_WKTMR_INTERVAL(u32Interval) (CLK->PMUCTL |= (u32Interval))
565
566 /**
567 * @brief Set De-bounce Sampling Cycle Time
568 *
569 * @param[in] u32CycleSel The de-bounce sampling cycle selection. It could be
570 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_1
571 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_2
572 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_4
573 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_8
574 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_16
575 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_32
576 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_64
577 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_128
578 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_256
579 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_2x256
580 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_4x256
581 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_8x256
582 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_16x256
583 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_32x256
584 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_64x256
585 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_128x256
586 *
587 * @return None
588 *
589 * @details This function set Set De-bounce Sampling Cycle Time.
590 *
591 * \hideinitializer
592 */
593 #define CLK_SET_SPDDEBOUNCETIME(u32CycleSel) (CLK->SWKDBCTL = (u32CycleSel))
594
595 /*---------------------------------------------------------------------------------------------------------*/
596 /* static inline functions */
597 /*---------------------------------------------------------------------------------------------------------*/
598 /* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
599 __STATIC_INLINE void CLK_SysTickDelay(uint32_t us);
600 __STATIC_INLINE void CLK_SysTickLongDelay(uint32_t us);
601
602 /**
603 * @brief This function execute delay function.
604 * @param[in] us Delay time. The Max value is 2^24 / CPU Clock(MHz). Ex:
605 * 72MHz => 233016us, 50MHz => 335544us,
606 * 48MHz => 349525us, 28MHz => 699050us ...
607 * @return None
608 * @details Use the SysTick to generate the delay time and the unit is in us.
609 * The SysTick clock source is from HCLK, i.e the same as system core clock.
610 */
CLK_SysTickDelay(uint32_t us)611 __STATIC_INLINE void CLK_SysTickDelay(uint32_t us)
612 {
613 SysTick->LOAD = us * CyclesPerUs;
614 SysTick->VAL = 0x0UL;
615 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
616
617 /* Waiting for down-count to zero */
618 while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0UL)
619 {
620 }
621
622 /* Disable SysTick counter */
623 SysTick->CTRL = 0UL;
624 }
625
626 /**
627 * @brief This function execute long delay function.
628 * @param[in] us Delay time.
629 * @return None
630 * @details Use the SysTick to generate the long delay time and the UNIT is in us.
631 * The SysTick clock source is from HCLK, i.e the same as system core clock.
632 * User can use SystemCoreClockUpdate() to calculate CyclesPerUs automatically before using this function.
633 */
CLK_SysTickLongDelay(uint32_t us)634 __STATIC_INLINE void CLK_SysTickLongDelay(uint32_t us)
635 {
636 uint32_t delay;
637
638 /* It should <= 349525us for each delay loop */
639 delay = 349525UL;
640
641 do
642 {
643 if(us > delay)
644 {
645 us -= delay;
646 }
647 else
648 {
649 delay = us;
650 us = 0UL;
651 }
652
653 SysTick->LOAD = delay * CyclesPerUs;
654 SysTick->VAL = (0x0UL);
655 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
656
657 /* Waiting for down-count to zero */
658 while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0UL);
659
660 /* Disable SysTick counter */
661 SysTick->CTRL = 0UL;
662
663 }
664 while(us > 0UL);
665
666 }
667
668
669 void CLK_DisableCKO(void);
670 void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En);
671 void CLK_PowerDown(void);
672 void CLK_Idle(void);
673 uint32_t CLK_GetHXTFreq(void);
674 uint32_t CLK_GetLXTFreq(void);
675 uint32_t CLK_GetHCLKFreq(void);
676 uint32_t CLK_GetPCLK0Freq(void);
677 uint32_t CLK_GetPCLK1Freq(void);
678 uint32_t CLK_GetCPUFreq(void);
679 uint32_t CLK_SetCoreClock(uint32_t u32Hclk);
680 void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv);
681 void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv);
682 void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc);
683 void CLK_EnableXtalRC(uint32_t u32ClkMask);
684 void CLK_DisableXtalRC(uint32_t u32ClkMask);
685 void CLK_EnableModuleClock(uint32_t u32ModuleIdx);
686 void CLK_DisableModuleClock(uint32_t u32ModuleIdx);
687 uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq);
688 void CLK_DisablePLL(void);
689 uint32_t CLK_WaitClockReady(uint32_t u32ClkMask);
690 void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count);
691 void CLK_DisableSysTick(void);
692 void CLK_SetPowerDownMode(uint32_t u32PDMode);
693 void CLK_EnableDPDWKPin(uint32_t u32TriggerType);
694 uint32_t CLK_GetPMUWKSrc(void);
695 void CLK_EnableSPDWKPin(uint32_t u32Port, uint32_t u32Pin, uint32_t u32TriggerType, uint32_t u32DebounceEn);
696 uint32_t CLK_GetPLLClockFreq(void);
697 uint32_t CLK_GetModuleClockSource(uint32_t u32ModuleIdx);
698 uint32_t CLK_GetModuleClockDivider(uint32_t u32ModuleIdx);
699
700 /*@}*/ /* end of group CLK_EXPORTED_FUNCTIONS */
701
702 /*@}*/ /* end of group CLK_Driver */
703
704 /*@}*/ /* end of group Standard_Driver */
705
706 #ifdef __cplusplus
707 }
708 #endif
709
710 #endif /* __CLK_H__ */
711
712 /*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
713
