1 /**************************************************************************//** 2 * @file timer_reg.h 3 * @version V1.00 4 * @brief TIMER register definition header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __TIMER_REG_H__ 10 #define __TIMER_REG_H__ 11 12 #if defined ( __CC_ARM ) 13 #pragma anon_unions 14 #endif 15 16 /** 17 @addtogroup REGISTER Control Register 18 @{ 19 */ 20 21 /** 22 @addtogroup TIMER Timer Controller(TIMER) 23 Memory Mapped Structure for TIMER Controller 24 @{ */ 25 26 typedef struct 27 { 28 29 30 /** 31 * @var TIMER_T::CTL 32 * Offset: 0x00 Timer Control Register 33 * --------------------------------------------------------------------------------------------------- 34 * |Bits |Field |Descriptions 35 * | :----: | :----: | :---- | 36 * |[7:0] |PSC |Prescale Counter 37 * | | |Timer input clock or event source is divided by (PSC+1) before it is fed to the timer up counter 38 * | | |If this field is 0 (PSC = 0), then there is no scaling. 39 * | | |Note: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value. 40 * |[19] |INTRGEN |Inter-timer Trigger Mode Enable Control 41 * | | |Setting this bit will enable the inter-timer trigger capture function. 42 * | | |The Timer0/2 will be in event counter mode and counting with external clock source or event 43 * | | |Also, Timer1/3 will be in trigger-counting mode of capture function. 44 * | | |0 = Inter-Timer Trigger Capture mode Disabled. 45 * | | |1 = Inter-Timer Trigger Capture mode Enabled. 46 * | | |Note: For Timer1/3, this bit is ignored and the read back value is always 0. 47 * |[20] |PERIOSEL |Periodic Mode Behavior Selection Enable Bit 48 * | | |0 = The behavior selection in periodic mode is Disabled. 49 * | | |When user updates CMPDAT while timer is running in periodic mode, 50 * | | |CNT will be reset to default value. 51 * | | |1 = The behavior selection in periodic mode is Enabled. 52 * | | |When user update CMPDAT while timer is running in periodic mode, the limitations as bellows list, 53 * | | |If updated CMPDAT value > CNT, CMPDAT will be updated and CNT keep running continually. 54 * | | |If updated CMPDAT value = CNT, timer time-out interrupt will be asserted immediately. 55 * | | |If updated CMPDAT value < CNT, CNT will be reset to default value. 56 * |[21] |TGLPINSEL |Toggle-output Pin Select 57 * | | |0 = Toggle mode output to TMx (Timer Event Counter Pin). 58 * | | |1 = Toggle mode output to TMx_EXT (Timer External Capture Pin). 59 * |[22] |CAPSRC |Capture Pin Source Selection 60 * | | |0 = Capture Function source is from TMx_EXT (x= 0~3) pin. 61 * | | |1 = Capture Function source is from internal ACMP output signal 62 * | | |User can set ACMPSSEL (TIMERx_EXTCTL[8]) to decide which internal ACMP output signal as timer capture source. 63 * |[23] |WKEN |Wake-up Function Enable Bit 64 * | | |If this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU. 65 * | | |0 = Wake-up function Disabled if timer interrupt signal generated. 66 * | | |1 = Wake-up function Enabled if timer interrupt signal generated. 67 * |[24] |EXTCNTEN |Event Counter Mode Enable Bit 68 * | | |This bit is for external counting pin function enabled. 69 * | | |0 = Event counter mode Disabled. 70 * | | |1 = Event counter mode Enabled. 71 * | | |Note: When timer is used as an event counter, this bit should be set to 1 and select PCLK as timer clock source. 72 * |[25] |ACTSTS |Timer Active Status Bit (Read Only) 73 * | | |This bit indicates the 24-bit up counter status. 74 * | | |0 = 24-bit up counter is not active. 75 * | | |1 = 24-bit up counter is active. 76 * | | |Note: This bit may active when CNT 0 transition to CNT 1. 77 * |[28:27] |OPMODE |Timer Counting Mode Select 78 * | | |00 = The Timer controller is operated in One-shot mode. 79 * | | |01 = The Timer controller is operated in Periodic mode. 80 * | | |10 = The Timer controller is operated in Toggle-output mode. 81 * | | |11 = The Timer controller is operated in Continuous Counting mode. 82 * |[29] |INTEN |Timer Interrupt Enable Bit 83 * | | |0 = Timer time-out interrupt Disabled. 84 * | | |1 = Timer time-out interrupt Enabled. 85 * | | |Note: If this bit is enabled, when the timer time-out interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU. 86 * |[30] |CNTEN |Timer Counting Enable Bit 87 * | | |0 = Stops/Suspends counting. 88 * | | |1 = Starts counting. 89 * | | |Note1: In stop status, and then set CNTEN to 1 will enable the 24-bit up counter to keep counting from the last stop counting value. 90 * | | |Note2: This bit is auto-cleared by hardware in one-shot mode (TIMER_CTL[28:27] = 00) when the timer time-out interrupt flag TIF (TIMERx_INTSTS[0]) is generated. 91 * | | |Note3: Set enable/disable this bit needs 2 * TMR_CLK period to become active, user can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not. 92 * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Control (Write Protect) 93 * | | |0 = ICE debug mode acknowledgement effects TIMER counting. 94 * | | |TIMER counter will be held while CPU is held by ICE. 95 * | | |1 = ICE debug mode acknowledgement Disabled. 96 * | | |TIMER counter will keep going no matter CPU is held by ICE or not. 97 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 98 * @var TIMER_T::CMP 99 * Offset: 0x04 Timer Comparator Register 100 * --------------------------------------------------------------------------------------------------- 101 * |Bits |Field |Descriptions 102 * | :----: | :----: | :---- | 103 * |[23:0] |CMPDAT |Timer Comparator Value 104 * | | |CMPDAT is a 24-bit compared value register 105 * | | |When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1. 106 * | | |Time-out period = (Period of timer clock input) * (8-bit PSC + 1) * (24-bit CMPDAT). 107 * | | |Note1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state. 108 * | | |Note2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field 109 * | | |But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the timer compared value while user writes a new value into CMPDAT field. 110 * @var TIMER_T::INTSTS 111 * Offset: 0x08 Timer Interrupt Status Register 112 * --------------------------------------------------------------------------------------------------- 113 * |Bits |Field |Descriptions 114 * | :----: | :----: | :---- | 115 * |[0] |TIF |Timer Interrupt Flag 116 * | | |This bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value. 117 * | | |0 = No effect. 118 * | | |1 = CNT value matches the CMPDAT value. 119 * | | |Note: This bit is cleared by writing 1 to it. 120 * |[1] |TWKF |Timer Wake-up Flag 121 * | | |This bit indicates the interrupt wake-up flag status of timer. 122 * | | |0 = Timer does not cause CPU wake-up. 123 * | | |1 = CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated. 124 * | | |Note: This bit is cleared by writing 1 to it. 125 * @var TIMER_T::CNT 126 * Offset: 0x0C Timer Data Register 127 * --------------------------------------------------------------------------------------------------- 128 * |Bits |Field |Descriptions 129 * | :----: | :----: | :---- | 130 * |[23:0] |CNT |Timer Data Register 131 * | | |Read operation. 132 * | | |Read this register to get CNT value. For example: 133 * | | |If EXTCNTEN (TIMERx_CTL[24] ) is 0, user can read CNT value for getting current 24-bit counter value. 134 * | | |If EXTCNTEN (TIMERx_CTL[24] ) is 1, user can read CNT value for getting current 24-bit event input counter value. 135 * | | |Write operation. 136 * | | |Writing any value to this register will reset current CNT value to 0 and reload internal 8-bit prescale counter. 137 * |[31] |RSTACT |Timer Data Register Reset Active (Read Only) 138 * | | |This bit indicates if the counter reset operation active. 139 * | | |When user writes this CNT register, timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter 140 * | | |At the same time, timer set this flag to 1 to indicate the counter reset operation is in progress 141 * | | |Once the counter reset operation done, timer clear this bit to 0 automatically. 142 * | | |0 = Reset operation is done. 143 * | | |1 = Reset operation triggered by writing TIMERx_CNT is in progress. 144 * | | |Note: This bit is read only. 145 * @var TIMER_T::CAP 146 * Offset: 0x10 Timer Capture Data Register 147 * --------------------------------------------------------------------------------------------------- 148 * |Bits |Field |Descriptions 149 * | :----: | :----: | :---- | 150 * |[23:0] |CAPDAT |Timer Capture Data Register 151 * | | |When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field. 152 * @var TIMER_T::EXTCTL 153 * Offset: 0x14 Timer External Control Register 154 * --------------------------------------------------------------------------------------------------- 155 * |Bits |Field |Descriptions 156 * | :----: | :----: | :---- | 157 * |[0] |CNTPHASE |Timer External Count Phase 158 * | | |This bit indicates the detection phase of external counting pin TMx (x= 0~3). 159 * | | |0 = A falling edge of external counting pin will be counted. 160 * | | |1 = A rising edge of external counting pin will be counted. 161 * |[3] |CAPEN |Timer External Capture Pin Enable Bit 162 * | | |This bit enables the TMx_EXT capture pin input function. 163 * | | |0 =TMx_EXT (x= 0~3) pin Disabled. 164 * | | |1 =TMx_EXT (x= 0~3) pin Enabled. 165 * |[4] |CAPFUNCS |Capture Function Selection 166 * | | |0 = External Capture Mode Enabled. 167 * | | |1 = External Reset Mode Enabled. 168 * | | |Note1: When CAPFUNCS is 0, transition on TMx_EXT (x= 0~3) pin is using to save current 24-bit timer counter value (CNT value) to CAPDAT field. 169 * | | |Note2: When CAPFUNCS is 1, transition on TMx_EXT (x= 0~3) pin is using to save current 24-bit timer counter value (CNT value) to CAPDAT field then CNT value will be reset immediately. 170 * |[5] |CAPIEN |Timer External Capture Interrupt Enable Bit 171 * | | |0 = TMx_EXT (x= 0~3) pin detection Interrupt Disabled. 172 * | | |1 = TMx_EXT (x= 0~3) pin detection Interrupt Enabled. 173 * | | |Note: CAPIEN is used to enable timer external interrupt 174 * | | |If CAPIEN enabled, timer will rise an interrupt when CAPIF (TIMERx_EINTSTS[0]) is 1. 175 * | | |For example, while CAPIEN = 1, CAPEN = 1, and CAPEDGE = 00, a 1 to 0 transition on the TMx_EXT pin will cause the CAPIF to be set then the interrupt signal is generated and sent to NVIC to inform CPU. 176 * |[6] |CAPDBEN |Timer External Capture Pin De-bounce Enable Bit 177 * | | |0 = TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Disabled. 178 * | | |1 = TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Enabled. 179 * | | |Note: If this bit is enabled, the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit. 180 * |[7] |CNTDBEN |Timer Counter Pin De-bounce Enable Bit 181 * | | |0 = TMx (x= 0~3) pin de-bounce Disabled. 182 * | | |1 = TMx (x= 0~3) pin de-bounce Enabled. 183 * | | |Note: If this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit. 184 * |[8:10] |ICAPSEL |Internal Capture Source Select 185 * | | |000 = Capture Function source is from internal ACMP0 output signal. 186 * | | |001 = Capture Function source is from internal ACMP1 output signal. 187 * | | |010 = Capture Function source is from HXT. 188 * | | |011 = Capture Function source is from LXT. 189 * | | |100 = Capture Function source is from HIRC. 190 * | | |101 = Capture Function source is from LIRC. 191 * | | |110 = Reserved. 192 * | | |111 = Reserved. 193 * | | |Note: these bits only available when CAPSRC (TIMERx_CTL[22]) is 1. 194 * |[14:12] |CAPEDGE |Timer External Capture Pin Edge Detect 195 * | | |When first capture event is generated, the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0. 196 * | | |000 = Capture event occurred when detect falling edge transfer on TMx_EXT (x= 0~3) pin. 197 * | | |001 = Capture event occurred when detect rising edge transfer on TMx_EXT (x= 0~3) pin. 198 * | | |010 = Capture event occurred when detect both falling and rising edge transfer on TMx_EXT (x= 0~3) pin, and first capture event occurred at falling edge transfer. 199 * | | |011 = Capture event occurred when detect both rising and falling edge transfer on TMx_EXT (x= 0~3) pin, and first capture event occurred at rising edge transfer.. 200 * | | |110 = First capture event occurred at falling edge, follows capture events are at rising edge transfer on TMx_EXT (x= 0~3) pin. 201 * | | |111 = First capture event occurred at rising edge, follows capture events are at falling edge transfer on TMx_EXT (x= 0~3) pin. 202 * | | |100, 101 = Reserved. 203 * |[16] |ECNTSSEL |Event Counter Source Selection to Trigger Event Counter Function 204 * | | |0 = Event Counter input source is from TMx (x= 0~3) pin. 205 * | | |1 = Event Counter input source is from USB internal SOF output signal. 206 * |[31:28] |CAPDIVSCL |Timer Capture Source Divider 207 * | | |This bits indicate the divide scale for capture source divider 208 * | | |0000 = Capture source/1. 209 * | | |0001 = Capture source/2. 210 * | | |0010 = Capture source/4. 211 * | | |0011 = Capture source/8. 212 * | | |0100 = Capture source/16. 213 * | | |0101 = Capture source/32. 214 * | | |0110 = Capture source/64. 215 * | | |0111 = Capture source/128. 216 * | | |1000 = Capture source/256. 217 * | | |1001~1111 = Reserved. 218 * | | |Note: Sets INTERCAPSEL (TIMERx_EXTCTL[10:8]) and CAPSRC (TIMERx_CTL[22]) to select capture source. * @var TIMER_T::EINTSTS 219 * Offset: 0x18 Timer External Interrupt Status Register 220 * --------------------------------------------------------------------------------------------------- 221 * |Bits |Field |Descriptions 222 * | :----: | :----: | :---- | 223 * |[0] |CAPIF |Timer External Capture Interrupt Flag 224 * | | |This bit indicates the timer external capture interrupt flag status. 225 * | | |0 = TMx_EXT (x= 0~3) pin interrupt did not occur. 226 * | | |1 = TMx_EXT (x= 0~3) pin interrupt occurred. 227 * | | |Note1: This bit is cleared by writing 1 to it. 228 * | | |Note2: When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on TMx_EXT (x= 0~3) pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, this bit will set to 1 by hardware. 229 * | | |Note3: There is a new incoming capture event detected before CPU clearing the CAPIF status 230 * | | |If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value. 231 * @var TIMER_T::TRGCTL 232 * Offset: 0x1C Timer Trigger Control Register 233 * --------------------------------------------------------------------------------------------------- 234 * |Bits |Field |Descriptions 235 * | :----: | :----: | :---- | 236 * |[0] |TRGSSEL |Trigger Source Select Bit 237 * | | |This bit is used to select internal trigger source is form timer time-out interrupt signal or 238 * | | |capture interrupt signal. 239 * | | |0 = Time-out interrupt signal is used to internal trigger EPWM, BPWM, PDMA, DAC, and EADC. 240 * | | |1 = Capture interrupt signal is used to internal trigger EPWM, BPWM, PDMA, DAC, and EADC. 241 * |[1] |TRGEPWM |Trigger EPWM and BPWM Enable Bit 242 * | | |If this bit is set to 1, each timer time-out event or capture event can be as EPWM and BPWM counter clock source. 243 * | | |0 = Timer interrupt trigger EPWM and BPWM Disabled. 244 * | | |1 = Timer interrupt trigger EPWM and BPWM Enabled. 245 * | | |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal as EPWM and BPWM counter clock source. 246 * | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal as EPWM counter clock source. 247 * |[2] |TRGEADC |Trigger EADC Enable Bit 248 * | | |If this bit is set to 1, each timer time-out event or capture event can be triggered EADC conversion. 249 * | | |0 = Timer interrupt trigger EADC Disabled. 250 * | | |1 = Timer interrupt trigger EADC Enabled. 251 * | | |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal will trigger EADC conversion. 252 * | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal will trigger EADC conversion. 253 * |[3] |TRGDAC |Trigger DAC Enable Bit 254 * | | |If this bit is set to 1, timer time-out interrupt or capture interrupt can be triggered DAC. 255 * | | |0 = Timer interrupt trigger DAC Disabled. 256 * | | |1 = Timer interrupt trigger DAC Enabled. 257 * | | |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal will trigger DAC. 258 * | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal will trigger DAC. 259 * |[4] |TRGPDMA |Trigger PDMA Enable Bit 260 * | | |If this bit is set to 1, each timer time-out event or capture event can be triggered PDMA transfer. 261 * | | |0 = Timer interrupt trigger PDMA Disabled. 262 * | | |1 = Timer interrupt trigger PDMA Enabled. 263 * | | |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal will trigger PDMA transfer. 264 * | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal will trigger PDMA transfer. 265 * @var TIMER_T::ALTCTL 266 * Offset: 0x20 Timer Alternative Control Register 267 * --------------------------------------------------------------------------------------------------- 268 * |Bits |Field |Descriptions 269 * | :----: | :----: | :---- | 270 * |[0] |FUNCSEL |Function Selection 271 * | | |0 = Timer controller is used as timer function. 272 * | | |1 = Timer controller is used as PWM function. 273 * | | |Note: When timer is used as PWM, the clock source of time controller will be forced to PCLKx automatically. 274 * @var TIMER_T::PWMCTL 275 * Offset: 0x40 Timer PWM Control Register 276 * --------------------------------------------------------------------------------------------------- 277 * |Bits |Field |Descriptions 278 * | :----: | :----: | :---- | 279 * |[0] |CNTEN |PWM Counter Enable Bit 280 * | | |0 = PWM counter and clock prescale Stop Running. 281 * | | |1 = PWM counter and clock prescale Start Running. 282 * |[2:1] |CNTTYPE |PWM Counter Behavior Type 283 * | | |00 = Up count type. 284 * | | |01 = Down count type. 285 * | | |10 = Up-down count type. 286 * | | |11 = Reserved. 287 * |[3] |CNTMODE |PWM Counter Mode 288 * | | |0 = Auto-reload mode. 289 * | | |1 = One-shot mode. 290 * |[8] |CTRLD |Center Re-load 291 * | | |In up-down count type, PERIOD will load to PBUF when current PWM period is completed always and CMP will load to CMPBUF at the center point of current period. 292 * |[9] |IMMLDEN |Immediately Load Enable Bit 293 * | | |0 = PERIOD will load to PBUF when current PWM period is completed no matter CTRLD is enabled/disabled 294 * | | |If CTRLD is disabled, CMP will load to CMPBUF when current PWM period is completed; if CTRLD is enabled in up-down count type, CMP will load to CMPBUF at the center point of current period. 295 * | | |1 = PERIOD/CMP will load to PBUF/CMPBUF immediately when user update PERIOD/CMP. 296 * | | |Note: If IMMLDEN is enabled, CTRLD will be invalid. 297 * |[16] |OUTMODE |PWM Output Mode 298 * | | |This bit controls the output mode of corresponding PWM channel. 299 * | | |0 = PWM independent mode. 300 * | | |1 = PWM complementary mode. 301 * |[30] |DBGHALT |ICE Debug Mode Counter Halt (Write Protect) 302 * | | |If debug mode counter halt is enabled, PWM counter will keep current value until exit ICE debug mode. 303 * | | |0 = ICE debug mode counter halt disable. 304 * | | |1 = ICE debug mode counter halt enable. 305 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 306 * |[31] |DBGTRIOFF |ICE Debug Mode Acknowledge Disable Bit (Write Protect) 307 * | | |0 = ICE debug mode acknowledgement effects PWM output. 308 * | | |PWM output pin will be forced as tri-state while ICE debug mode acknowledged. 309 * | | |1 = ICE debug mode acknowledgement disabled. 310 * | | |PWM output pin will keep output no matter ICE debug mode acknowledged or not. 311 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 312 * @var TIMER_T::PWMCLKSRC 313 * Offset: 0x44 Timer PWM Counter Clock Source Register 314 * --------------------------------------------------------------------------------------------------- 315 * |Bits |Field |Descriptions 316 * | :----: | :----: | :---- | 317 * |[2:0] |CLKSRC |PWM Counter Clock Source Select 318 * | | |The PWM counter clock source can be selected from TMRx_CLK or internal timer time-out or capture event. 319 * | | |000 = TMRx_CLK. 320 * | | |001 = Internal TIMER0 time-out or capture event. 321 * | | |010 = Internal TIMER1 time-out or capture event. 322 * | | |011 = Internal TIMER2 time-out or capture event. 323 * | | |100 = Internal TIMER3 time-out or capture event. 324 * | | |Others = Reserved. 325 * | | |Note: If TIMER0 PWM function is enabled, the PWM counter clock source can be selected from TMR0_CLK, TIMER1 interrupt events, TIMER2 interrupt events, or TIMER3 interrupt events. 326 * @var TIMER_T::PWMCLKPSC 327 * Offset: 0x48 Timer PWM Counter Clock Pre-scale Register 328 * --------------------------------------------------------------------------------------------------- 329 * |Bits |Field |Descriptions 330 * | :----: | :----: | :---- | 331 * |[11:0] |CLKPSC |PWM Counter Clock Pre-scale 332 * | | |The active clock of PWM counter is decided by counter clock prescale and divided by (CLKPSC + 1) 333 * | | |If CLKPSC is 0, then there is no scaling in PWM counter clock source. 334 * @var TIMER_T::PWMCNTCLR 335 * Offset: 0x4C Timer PWM Clear Counter Register 336 * --------------------------------------------------------------------------------------------------- 337 * |Bits |Field |Descriptions 338 * | :----: | :----: | :---- | 339 * |[0] |CNTCLR |Clear PWM Counter Control Bit 340 * | | |It is automatically cleared by hardware. 341 * | | |0 = No effect. 342 * | | |1 = Clear 16-bit PWM counter to 0x10000 in up and up-down count type and reset counter value to PERIOD in down count type. 343 * @var TIMER_T::PWMPERIOD 344 * Offset: 0x50 Timer PWM Period Register 345 * --------------------------------------------------------------------------------------------------- 346 * |Bits |Field |Descriptions 347 * | :----: | :----: | :---- | 348 * |[15:0] |PERIOD |PWM Period Register 349 * | | |In up count type: PWM counter counts from 0 to PERIOD, and restarts from 0. 350 * | | |In down count type: PWM counter counts from PERIOD to 0, and restarts from PERIOD. 351 * | | |In up-down count type: PWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again. 352 * | | |In up and down count type: 353 * | | |PWM period time = (PERIOD + 1) * (CLKPSC + 1) * TMRx_PWMCLK. 354 * | | |In up-down count type: 355 * | | |PWM period time = 2 * PERIOD * (CLKPSC+ 1) * TMRx_PWMCLK. 356 * | | |Note: User should take care DIRF (TIMERx_PWMCNT[16]) bit in up/down/up-down count type to monitor current counter direction in each count type. 357 * @var TIMER_T::PWMCMPDAT 358 * Offset: 0x54 Timer PWM Comparator Register 359 * --------------------------------------------------------------------------------------------------- 360 * |Bits |Field |Descriptions 361 * | :----: | :----: | :---- | 362 * |[15:0] |CMP |PWM Comparator Register 363 * | | |PWM CMP is used to compare with PWM CNT to generate PWM output waveform, interrupt events and trigger ADC to start convert. 364 * @var TIMER_T::PWMDTCTL 365 * Offset: 0x58 Timer PWM Dead-Time Control Register 366 * --------------------------------------------------------------------------------------------------- 367 * |Bits |Field |Descriptions 368 * | :----: | :----: | :---- | 369 * |[11:0] |DTCNT |Dead-time Counter (Write Protect) 370 * | | |The dead-time can be calculated from the following two formulas: 371 * | | |Dead-time = (DTCNT[11:0] + 1) * TMRx_PWMCLK, if DTCKSEL is 0. 372 * | | |Dead-time = (DTCNT[11:0] + 1) * TMRx_PWMCLK * (CLKPSC + 1), if DTCKSEL is 1. 373 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 374 * |[16] |DTEN |Enable Dead-time Insertion for PWMx_CH0 and PWMx_CH1 (Write Protect) 375 * | | |Dead-time insertion function is only active when PWM complementary mode is enabled 376 * | | |If dead- time insertion is inactive, the outputs of PWMx_CH0 and PWMx_CH1 are complementary without any delay. 377 * | | |0 = Dead-time insertion Disabled on the pin pair. 378 * | | |1 = Dead-time insertion Enabled on the pin pair. 379 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 380 * |[24] |DTCKSEL |Dead-time Clock Select (Write Protect) 381 * | | |0 = Dead-time clock source from TMRx_PWMCLK without counter clock prescale. 382 * | | |1 = Dead-time clock source from TMRx_PWMCLK with counter clock prescale. 383 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 384 * @var TIMER_T::PWMCNT 385 * Offset: 0x5C Timer PWM Counter Register 386 * --------------------------------------------------------------------------------------------------- 387 * |Bits |Field |Descriptions 388 * | :----: | :----: | :---- | 389 * |[15:0] |CNT |PWM Counter Value Register (Read Only) 390 * | | |User can monitor CNT to know the current counter value in 16-bit period counter. 391 * |[16] |DIRF |PWM Counter Direction Indicator Flag (Read Only) 392 * | | |0 = Counter is active in down count. 393 * | | |1 = Counter is active up count. 394 * @var TIMER_T::PWMMSKEN 395 * Offset: 0x60 Timer PWM Output Mask Enable Register 396 * --------------------------------------------------------------------------------------------------- 397 * |Bits |Field |Descriptions 398 * | :----: | :----: | :---- | 399 * |[0] |MSKEN0 |PWMx_CH0 Output Mask Enable Bit 400 * | | |The PWMx_CH0 output signal will be masked when this bit is enabled 401 * | | |The PWMx_CH0 will output MSKDAT0 (TIMER_PWMMSK[0]) data. 402 * | | |0 = PWMx_CH0 output signal is non-masked. 403 * | | |1 = PWMx_CH0 output signal is masked and output MSKDAT0 data. 404 * |[1] |MSKEN1 |PWMx_CH1 Output Mask Enable Bit 405 * | | |The PWMx_CH1 output signal will be masked when this bit is enabled 406 * | | |The PWMx_CH1 will output MSKDAT1 (TIMER_PWMMSK[1]) data. 407 * | | |0 = PWMx_CH1 output signal is non-masked. 408 * | | |1 = PWMx_CH1 output signal is masked and output MSKDAT1 data. 409 * @var TIMER_T::PWMMSK 410 * Offset: 0x64 Timer PWM Output Mask Data Control Register 411 * --------------------------------------------------------------------------------------------------- 412 * |Bits |Field |Descriptions 413 * | :----: | :----: | :---- | 414 * |[0] |MSKDAT0 |PWMx_CH0 Output Mask Data Control Bit 415 * | | |This bit is used to control the output state of PWMx_CH0 pin when PWMx_CH0 output mask function is enabled (MSKEN0 = 1). 416 * | | |0 = Output logic Low to PWMx_CH0. 417 * | | |1 = Output logic High to PWMx_CH0. 418 * |[1] |MSKDAT1 |PWMx_CH1 Output Mask Data Control Bit 419 * | | |This bit is used to control the output state of PWMx_CH1 pin when PWMx_CH1 output mask function is enabled (MSKEN1 = 1). 420 * | | |0 = Output logic Low to PWMx_CH1. 421 * | | |1 = Output logic High to PWMx_CH1. 422 * @var TIMER_T::PWMBNF 423 * Offset: 0x68 Timer PWM Brake Pin Noise Filter Register 424 * --------------------------------------------------------------------------------------------------- 425 * |Bits |Field |Descriptions 426 * | :----: | :----: | :---- | 427 * |[0] |BRKNFEN |Brake Pin Noise Filter Enable Bit 428 * | | |0 = Pin noise filter detect of PWMx_BRAKEy Disabled. 429 * | | |1 = Pin noise filter detect of PWMx_BRAKEy Enabled. 430 * |[3:1] |BRKNFSEL |Brake Pin Noise Filter Clock Selection 431 * | | |000 = Noise filter clock is PCLKx. 432 * | | |001 = Noise filter clock is PCLKx/2. 433 * | | |010 = Noise filter clock is PCLKx/4. 434 * | | |011 = Noise filter clock is PCLKx/8. 435 * | | |100 = Noise filter clock is PCLKx/16. 436 * | | |101 = Noise filter clock is PCLKx/32. 437 * | | |110 = Noise filter clock is PCLKx/64. 438 * | | |111 = Noise filter clock is PCLKx/128. 439 * |[6:4] |BRKFCNT |Brake Pin Noise Filter Count 440 * | | |The fields is used to control the active noise filter sample time. 441 * | | |Once noise filter sample time = (Period time of BRKDBCS) * BRKFCNT. 442 * |[7] |BRKPINV |Brake Pin Detection Control Bit 443 * | | |0 = Brake pin event will be detected if PWMx_BRAKEy pin status transfer from low to high in edge-detect, or pin status is high in level-detect. 444 * | | |1 = Brake pin event will be detected if PWMx_BRAKEy pin status transfer from high to low in edge-detect, or pin status is low in level-detect . 445 * |[17:16] |BKPINSRC |Brake Pin Source Select 446 * | | |00 = Brake pin source comes from PWM0_BRAKE0 pin. 447 * | | |01 = Brake pin source comes from PWM0_BRAKE1 pin. 448 * | | |10 = Brake pin source comes from PWM1_BRAKE0 pin. 449 * | | |11 = Brake pin source comes from PWM1_BRAKE1 pin. 450 * @var TIMER_T::PWMFAILBRK 451 * Offset: 0x6C Timer PWM System Fail Brake Control Register 452 * --------------------------------------------------------------------------------------------------- 453 * |Bits |Field |Descriptions 454 * | :----: | :----: | :---- | 455 * |[0] |CSSBRKEN |Clock Security System Detection Trigger PWM Brake Function Enable Bit 456 * | | |0 = Brake Function triggered by clock fail detection Disabled. 457 * | | |1 = Brake Function triggered by clock fail detection Enabled. 458 * |[1] |BODBRKEN |Brown-out Detection Trigger PWM Brake Function Enable Bit 459 * | | |0 = Brake Function triggered by BOD event Disabled. 460 * | | |1 = Brake Function triggered by BOD event Enabled. 461 * |[2] |RAMBRKEN |SRAM Parity Error Detection Trigger PWM Brake Function Enable Bit 462 * | | |0 = Brake Function triggered by SRAM parity error detection Disabled. 463 * | | |1 = Brake Function triggered by SRAM parity error detection Enabled. 464 * |[3] |CORBRKEN |Core Lockup Detection Trigger PWM Brake Function Enable Bit 465 * | | |0 = Brake Function triggered by core lockup event Disabled. 466 * | | |1 = Brake Function triggered by core lockup event Enabled. 467 * @var TIMER_T::PWMBRKCTL 468 * Offset: 0x70 Timer PWM Brake Control Register 469 * --------------------------------------------------------------------------------------------------- 470 * |Bits |Field |Descriptions 471 * | :----: | :----: | :---- | 472 * |[0] |CPO0EBEN |Enable Internal ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect) 473 * | | |0 = Internal ACMP0_O signal as edge-detect brake source Disabled. 474 * | | |1 = Internal ACMP0_O signal as edge-detect brake source Enabled. 475 * | | |Note1: Only internal ACMP0_O signal from low to high will be detected as brake event. 476 * | | |Note2: This register is write protected. Refer toSYS_REGLCTL register. 477 * |[1] |CPO1EBEN |Enable Internal ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect) 478 * | | |0 = Internal ACMP1_O signal as edge-detect brake source Disabled. 479 * | | |1 = Internal ACMP1_O signal as edge-detect brake source Enabled. 480 * | | |Note1: Only internal ACMP1_O signal from low to high will be detected as brake event. 481 * | | |Note2: This register is write protected. Refer toSYS_REGLCTL register. 482 * |[4] |BRKPEEN |Enable TM_BRAKEx Pin As Edge-detect Brake Source (Write Protect) 483 * | | |0 = PWMx_BRAKEy pin event as edge-detect brake source Disabled. 484 * | | |1 = PWMx_BRAKEy pin event as edge-detect brake source Enabled. 485 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 486 * |[7] |SYSEBEN |Enable System Fail As Edge-detect Brake Source (Write Protect) 487 * | | |0 = System fail condition as edge-detect brake source Disabled. 488 * | | |1 = System fail condition as edge-detect brake source Enabled. 489 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 490 * |[8] |CPO0LBEN |Enable Internal ACMP0_O Digital Output As Level-detect Brake Source (Write Protect) 491 * | | |0 = Internal ACMP0_O signal as level-detect brake source Disabled. 492 * | | |1 = Internal ACMP0_O signal as level-detect brake source Enabled. 493 * | | |Note1: Only internal ACMP0_O signal from low to high will be detected as brake event. 494 * | | |Note2: This register is write protected. Refer toSYS_REGLCTL register. 495 * |[9] |CPO1LBEN |Enable Internal ACMP1_O Digital Output As Level-detect Brake Source (Write Protect) 496 * | | |0 = Internal ACMP1_O signal as level-detect brake source Disabled. 497 * | | |1 = Internal ACMP1_O signal as level-detect brake source Enabled. 498 * | | |Note1: Only internal ACMP1_O signal from low to high will be detected as brake event. 499 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 500 * |[12] |BRKPLEN |Enable TM_BRAKEx Pin As Level-detect Brake Source (Write Protect) 501 * | | |0 = PWMx_BRAKEy pin event as level-detect brake source Disabled. 502 * | | |1 = PWMx_BRAKEy pin event as level-detect brake source Enabled. 503 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 504 * |[15] |SYSLBEN |Enable System Fail As Level-detect Brake Source (Write Protect) 505 * | | |0 = System fail condition as level-detect brake source Disabled. 506 * | | |1 = System fail condition as level-detect brake source Enabled. 507 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 508 * |[17:16] |BRKAEVEN |PWM Brake Action Select for PWMx_CH0 (Write Protect) 509 * | | |00 = PWMx_BRAKEy brake event will not affect PWMx_CH0 output. 510 * | | |01 = PWMx_CH0 output tri-state when PWMx_BRAKEy brake event happened. 511 * | | |10 = PWMx_CH0 output low level when PWMx_BRAKEy brake event happened. 512 * | | |11 = PWMx_CH0 output high level when PWMx_BRAKEy brake event happened. 513 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 514 * |[19:18] |BRKAODD |PWM Brake Action Select for PWMx_CH1 (Write Protect) 515 * | | |00 = PWMx_BRAKEy brake event will not affect PWMx_CH1 output. 516 * | | |01 = PWMx_CH1 output tri-state when PWMx_BRAKEy brake event happened. 517 * | | |10 = PWMx_CH1 output low level when PWMx_BRAKEy brake event happened. 518 * | | |11 = PWMx_CH1 output high level when PWMx_BRAKEy brake event happened. 519 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 520 * @var TIMER_T::PWMPOLCTL 521 * Offset: 0x74 Timer PWM Pin Output Polar Control Register 522 * --------------------------------------------------------------------------------------------------- 523 * |Bits |Field |Descriptions 524 * | :----: | :----: | :---- | 525 * |[0] |PINV0 |PWMx_CH0 Output Pin Polar Control Bit 526 * | | |The bit is used to control polarity state of PWMx_CH0 output pin. 527 * | | |0 = PWMx_CH0 output pin polar inverse Disabled. 528 * | | |1 = PWMx_CH0 output pin polar inverse Enabled. 529 * |[1] |PINV1 |PWMx_CH1 Output Pin Polar Control Bit 530 * | | |The bit is used to control polarity state of PWMx_CH1 output pin. 531 * | | |0 = PWMx_CH1 output pin polar inverse Disabled. 532 * | | |1 = PWMx_CH1 output pin polar inverse Enabled. 533 * @var TIMER_T::PWMPOEN 534 * Offset: 0x78 Timer PWM Pin Output Enable Register 535 * --------------------------------------------------------------------------------------------------- 536 * |Bits |Field |Descriptions 537 * | :----: | :----: | :---- | 538 * |[0] |POEN0 |PWMx_CH0 Output Pin Enable Bit 539 * | | |0 = PWMx_CH0 pin at tri-state mode. 540 * | | |1 = PWMx_CH0 pin in output mode. 541 * |[1] |POEN1 |PWMx_CH1 Output Pin Enable Bit 542 * | | |0 = PWMx_CH1 pin at tri-state mode. 543 * | | |1 = PWMx_CH1 pin in output mode. 544 * @var TIMER_T::PWMSWBRK 545 * Offset: 0x7C Timer PWM Software Trigger Brake Control Register 546 * --------------------------------------------------------------------------------------------------- 547 * |Bits |Field |Descriptions 548 * | :----: | :----: | :---- | 549 * |[0] |BRKETRG |Software Trigger Edge-detect Brake Source (Write Only) (Write Protect) 550 * | | |Write 1 to this bit will trigger PWM edge-detect brake source, then BRKEIF0 and BRKEIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register. 551 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 552 * |[8] |BRKLTRG |Software Trigger Level-detect Brake Source (Write Only) (Write Protect) 553 * | | |Write 1 to this bit will trigger PWM level-detect brake source, then BRKLIF0 and BRKLIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register. 554 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 555 * @var TIMER_T::PWMINTEN0 556 * Offset: 0x80 Timer PWM Interrupt Enable Register 0 557 * --------------------------------------------------------------------------------------------------- 558 * |Bits |Field |Descriptions 559 * | :----: | :----: | :---- | 560 * |[0] |ZIEN |PWM Zero Point Interrupt Enable Bit 561 * | | |0 = Zero point interrupt Disabled. 562 * | | |1 = Zero point interrupt Enabled. 563 * |[1] |PIEN |PWM Period Point Interrupt Enable Bit 564 * | | |0 = Period point interrupt Disabled. 565 * | | |1 = Period point interrupt Enabled. 566 * | | |Note: When in up-down count type, period point means the center point of current PWM period. 567 * |[2] |CMPUIEN |PWM Compare Up Count Interrupt Enable Bit 568 * | | |0 = Compare up count interrupt Disabled. 569 * | | |1 = Compare up count interrupt Enabled. 570 * |[3] |CMPDIEN |PWM Compare Down Count Interrupt Enable Bit 571 * | | |0 = Compare down count interrupt Disabled. 572 * | | |1 = Compare down count interrupt Enabled. 573 * @var TIMER_T::PWMINTEN1 574 * Offset: 0x84 Timer PWM Interrupt Enable Register 1 575 * --------------------------------------------------------------------------------------------------- 576 * |Bits |Field |Descriptions 577 * | :----: | :----: | :---- | 578 * |[0] |BRKEIEN |PWM Edge-detect Brake Interrupt Enable (Write Protect) 579 * | | |0 = PWM edge-detect brake interrupt Disabled. 580 * | | |1 = PWM edge-detect brake interrupt Enabled. 581 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 582 * |[8] |BRKLIEN |PWM Level-detect Brake Interrupt Enable (Write Protect) 583 * | | |0 = PWM level-detect brake interrupt Disabled. 584 * | | |1 = PWM level-detect brake interrupt Enabled. 585 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 586 * @var TIMER_T::PWMINTSTS0 587 * Offset: 0x88 Timer PWM Interrupt Status Register 0 588 * --------------------------------------------------------------------------------------------------- 589 * |Bits |Field |Descriptions 590 * | :----: | :----: | :---- | 591 * |[0] |ZIF |PWM Zero Point Interrupt Flag 592 * | | |This bit is set by hardware when TIMERx_PWM counter reaches zero. 593 * | | |Note: This bit is cleared by writing 1 to it. 594 * |[1] |PIF |PWM Period Point Interrupt Flag 595 * | | |This bit is set by hardware when TIMERx_PWM counter reaches PERIOD. 596 * | | |Note1: When in up-down count type, PIF flag means the center point flag of current PWM period. 597 * | | |Note2: This bit is cleared by writing 1 to it. 598 * |[2] |CMPUIF |PWM Compare Up Count Interrupt Flag 599 * | | |This bit is set by hardware when TIMERx_PWM counter in up count direction and reaches CMP. 600 * | | |Note1: If CMP equal to PERIOD, there is no CMPUIF flag in up count type and up-down count type. 601 * | | |Note2: This bit is cleared by writing 1 to it. 602 * |[3] |CMPDIF |PWM Compare Down Count Interrupt Flag 603 * | | |This bit is set by hardware when TIMERx_PWM counter in down count direction and reaches CMP. 604 * | | |Note1: If CMP equal to PERIOD, there is no CMPDIF flag in down count type. 605 * | | |Note2: This bit is cleared by writing 1 to it. 606 * @var TIMER_T::PWMINTSTS1 607 * Offset: 0x8C Timer PWM Interrupt Status Register 1 608 * --------------------------------------------------------------------------------------------------- 609 * |Bits |Field |Descriptions 610 * | :----: | :----: | :---- | 611 * |[0] |BRKEIF0 |Edge-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect) 612 * | | |0 = PWMx_CH0 edge-detect brake event do not happened. 613 * | | |1 = PWMx_CH0 edge-detect brake event happened. 614 * | | |Note1: This bit is cleared by writing 1 to it. 615 * | | |Note2: This register is write protected. Refer toSYS_REGLCTL register. 616 * |[1] |BRKEIF1 |Edge-detect Brake Interrupt Flag PWMx_CH1 (Write Protect) 617 * | | |0 = PWMx_CH1 edge-detect brake event do not happened. 618 * | | |1 = PWMx_CH1 edge-detect brake event happened. 619 * | | |Note1: This bit is cleared by writing 1 to it. 620 * | | |Note2: This register is write protected. Refer toSYS_REGLCTL register. 621 * |[8] |BRKLIF0 |Level-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect) 622 * | | |0 = PWMx_CH0 level-detect brake event do not happened. 623 * | | |1 = PWMx_CH0 level-detect brake event happened. 624 * | | |Note1: This bit is cleared by writing 1 to it. 625 * | | |Note2: This register is write protected. Refer toSYS_REGLCTL register. 626 * |[9] |BRKLIF1 |Level-detect Brake Interrupt Flag on PWMx_CH1 (Write Protect) 627 * | | |0 = PWMx_CH1 level-detect brake event do not happened. 628 * | | |1 = PWMx_CH1 level-detect brake event happened. 629 * | | |Note1: This bit is cleared by writing 1 to it. 630 * | | |Note2: This register is write protected. Refer toSYS_REGLCTL register. 631 * |[16] |BRKESTS0 |Edge -detect Brake Status of PWMx_CH0 (Read Only) 632 * | | |0 = PWMx_CH0 edge-detect brake state is released. 633 * | | |1 = PWMx_CH0 at edge-detect brake state. 634 * | | |Note: User can set BRKEIF0 1 to clear BRKEIF0 flag and PWMx_CH0 will release brake state when current PWM period finished and resume PWMx_CH0 output waveform start from next full PWM period. 635 * |[17] |BRKESTS1 |Edge-detect Brake Status of PWMx_CH1 (Read Only) 636 * | | |0 = PWMx_CH1 edge-detect brake state is released. 637 * | | |1 = PWMx_CH1 at edge-detect brake state. 638 * | | |Note: User can set BRKEIF1 1 to clear BRKEIF1 flag and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH1 output waveform start from next full PWM period. 639 * |[24] |BRKLSTS0 |Level-detect Brake Status of PWMx_CH0 (Read Only) 640 * | | |0 = PWMx_CH0 level-detect brake state is released. 641 * | | |1 = PWMx_CH0 at level-detect brake state. 642 * | | |Note: If TIMERx_PWM level-detect brake source has released, both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform start from next full PWM period. 643 * |[25] |BRKLSTS1 |Level-detect Brake Status of PWMx_CH1 (Read Only) 644 * | | |0 = PWMx_CH1 level-detect brake state is released. 645 * | | |1 = PWMx_CH1 at level-detect brake state. 646 * | | |Note: If TIMERx_PWM level-detect brake source has released, both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform start from next full PWM period. 647 * @var TIMER_T::PWMEADCTS 648 * Offset: 0x90 Timer PWM ADC Trigger Source Select Register 649 * --------------------------------------------------------------------------------------------------- 650 * |Bits |Field |Descriptions 651 * | :----: | :----: | :---- | 652 * |[2:0] |TRGSEL |PWM Counter Event Source Select to Trigger EADC Conversion 653 * | | |000 = Trigger EADC conversion at zero point (ZIF). 654 * | | |001 = Trigger EADC conversion at period point (PIF). 655 * | | |010 = Trigger EADC conversion at zero or period point (ZIF or PIF). 656 * | | |011 = Trigger EADC conversion at compare up count point (CMPUIF). 657 * | | |100 = Trigger EADC conversion at compare down count point (CMPDIF). 658 * | | |Others = Reserved. 659 * |[7] |TRGEN |PWM Counter Event Trigger EADC Conversion Enable Bit 660 * | | |0 = PWM counter event trigger EADC conversion Disabled. 661 * | | |1 = PWM counter event trigger EADC conversion Enabled. 662 * @var TIMER_T::PWMSCTL 663 * Offset: 0x94 Timer PWM Synchronous Control Register 664 * --------------------------------------------------------------------------------------------------- 665 * |Bits |Field |Descriptions 666 * | :----: | :----: | :---- | 667 * |[1:0] |SYNCMODE |PWM Synchronous Mode Enable Select 668 * | | |00 = PWM synchronous function Disabled. 669 * | | |01 = PWM synchronous counter start function Enabled. 670 * | | |10 = Reserved. 671 * | | |11 = PWM synchronous counter clear function Enabled. 672 * |[8] |SYNCSRC |PWM Synchronous Counter Start/Clear Source Select 673 * | | |0 = Counter synchronous start/clear by trigger TIMER0_PWMSTRG STRGEN. 674 * | | |1 = Counter synchronous start/clear by trigger TIMER2_PWMSTRG STRGEN. 675 * | | |Note1: If TIMER0/1/2/3 PWM counter synchronous source are from TIMER0, TIMER0_PWMSCTL[8], TIMER1_PWMSCTL[8], TIMER2_PWMSCTL[8] and TIMER3_PWMSCTL[8] should be 0. 676 * | | |Note2: If TIMER0/1/ PWM counter synchronous source are from TIMER0, TIMER0_PWMSCTL[8] and TIMER1_PWMSCTL[8] should be set 0, and TIMER2/3/ PWM counter synchronous source are from TIMER2, TIME2_PWMSCTL[8] and TIMER3_PWMSCTL[8] should be set 1. 677 * @var TIMER_T::PWMSTRG 678 * Offset: 0x98 Timer PWM Synchronous Trigger Register 679 * --------------------------------------------------------------------------------------------------- 680 * |Bits |Field |Descriptions 681 * | :----: | :----: | :---- | 682 * |[0] |STRGEN |PWM Counter Synchronous Trigger Enable Bit (Write Only) 683 * | | |PMW counter synchronous function is used to make selected PWM channels (include TIMER0/1/2/3 PWM, TIMER0/1 PWM and TIMER2/3 PWM) start counting or clear counter at the same time according to TIMERx_PWMSCTL setting. 684 * | | |Note: This bit is only available in TIMER0 and TIMER2. 685 * @var TIMER_T::PWMSTATUS 686 * Offset: 0x9C Timer PWM Status Register 687 * --------------------------------------------------------------------------------------------------- 688 * |Bits |Field |Descriptions 689 * | :----: | :----: | :---- | 690 * |[0] |CNTMAXF |PWM Counter Equal to 0xFFFF Flag 691 * | | |0 = Indicates the PWM counter value never reached its maximum value 0xFFFF. 692 * | | |1 = Indicates the PWM counter value has reached its maximum value. 693 * | | |Note: This bit is cleared by writing 1 to it. 694 * |[16] |EADCTRGF |Trigger EADC Start Conversion Flag 695 * | | |0 = PWM counter event trigger EADC start conversion is not occurred. 696 * | | |1 = PWM counter event trigger EADC start conversion has occurred. 697 * | | |Note: This bit is cleared by writing 1 to it. 698 * @var TIMER_T::PWMPBUF 699 * Offset: 0xA0 Timer PWM Period Buffer Register 700 * --------------------------------------------------------------------------------------------------- 701 * |Bits |Field |Descriptions 702 * | :----: | :----: | :---- | 703 * |[15:0] |PBUF |PWM Period Buffer Register (Read Only) 704 * | | |Used as PERIOD active register. 705 * @var TIMER_T::PWMCMPBUF 706 * Offset: 0xA4 Timer PWM Comparator Buffer Register 707 * --------------------------------------------------------------------------------------------------- 708 * |Bits |Field |Descriptions 709 * | :----: | :----: | :---- | 710 * |[15:0] |CMPBUF |PWM Comparator Buffer Register (Read Only) 711 * | | |Used as CMP active register. 712 */ 713 __IO uint32_t CTL; /*!< [0x0000] Timer Control Register */ 714 __IO uint32_t CMP; /*!< [0x0004] Timer Comparator Register */ 715 __IO uint32_t INTSTS; /*!< [0x0008] Timer Interrupt Status Register */ 716 __IO uint32_t CNT; /*!< [0x000c] Timer Data Register */ 717 __I uint32_t CAP; /*!< [0x0010] Timer Capture Data Register */ 718 __IO uint32_t EXTCTL; /*!< [0x0014] Timer External Control Register */ 719 __IO uint32_t EINTSTS; /*!< [0x0018] Timer External Interrupt Status Register */ 720 __IO uint32_t TRGCTL; /*!< [0x001c] Timer Trigger Control Register */ 721 __IO uint32_t ALTCTL; /*!< [0x0020] Timer Alternative Control Register */ 722 /** @cond HIDDEN_SYMBOLS */ 723 __I uint32_t RESERVE0[7]; 724 /** @endcond */ 725 __IO uint32_t PWMCTL; /*!< [0x0040] Timer PWM Control Register */ 726 __IO uint32_t PWMCLKSRC; /*!< [0x0044] Timer PWM Counter Clock Source Register */ 727 __IO uint32_t PWMCLKPSC; /*!< [0x0048] Timer PWM Counter Clock Pre-scale Register */ 728 __IO uint32_t PWMCNTCLR; /*!< [0x004c] Timer PWM Clear Counter Register */ 729 __IO uint32_t PWMPERIOD; /*!< [0x0050] Timer PWM Period Register */ 730 __IO uint32_t PWMCMPDAT; /*!< [0x0054] Timer PWM Comparator Register */ 731 __IO uint32_t PWMDTCTL; /*!< [0x0058] Timer PWM Dead-Time Control Register */ 732 __I uint32_t PWMCNT; /*!< [0x005c] Timer PWM Counter Register */ 733 __IO uint32_t PWMMSKEN; /*!< [0x0060] Timer PWM Output Mask Enable Register */ 734 __IO uint32_t PWMMSK; /*!< [0x0064] Timer PWM Output Mask Data Control Register */ 735 __IO uint32_t PWMBNF; /*!< [0x0068] Timer PWM Brake Pin Noise Filter Register */ 736 __IO uint32_t PWMFAILBRK; /*!< [0x006c] Timer PWM System Fail Brake Control Register */ 737 __IO uint32_t PWMBRKCTL; /*!< [0x0070] Timer PWM Brake Control Register */ 738 __IO uint32_t PWMPOLCTL; /*!< [0x0074] Timer PWM Pin Output Polar Control Register */ 739 __IO uint32_t PWMPOEN; /*!< [0x0078] Timer PWM Pin Output Enable Register */ 740 __O uint32_t PWMSWBRK; /*!< [0x007c] Timer PWM Software Trigger Brake Control Register */ 741 __IO uint32_t PWMINTEN0; /*!< [0x0080] Timer PWM Interrupt Enable Register 0 */ 742 __IO uint32_t PWMINTEN1; /*!< [0x0084] Timer PWM Interrupt Enable Register 1 */ 743 __IO uint32_t PWMINTSTS0; /*!< [0x0088] Timer PWM Interrupt Status Register 0 */ 744 __IO uint32_t PWMINTSTS1; /*!< [0x008c] Timer PWM Interrupt Status Register 1 */ 745 __IO uint32_t PWMEADCTS; /*!< [0x0090] Timer PWM EADC Trigger Source Select Register */ 746 __IO uint32_t PWMSCTL; /*!< [0x0094] Timer PWM Synchronous Control Register */ 747 __O uint32_t PWMSTRG; /*!< [0x0098] Timer PWM Synchronous Trigger Register */ 748 __IO uint32_t PWMSTATUS; /*!< [0x009c] Timer PWM Status Register */ 749 __I uint32_t PWMPBUF; /*!< [0x00a0] Timer PWM Period Buffer Register */ 750 __I uint32_t PWMCMPBUF; /*!< [0x00a4] Timer PWM Comparator Buffer Register */ 751 752 } TIMER_T; 753 754 /** 755 @addtogroup TIMER_CONST TIMER Bit Field Definition 756 Constant Definitions for TIMER Controller 757 @{ */ 758 759 #define TIMER_CTL_PSC_Pos (0) /*!< TIMER_T::CTL: PSC Position */ 760 #define TIMER_CTL_PSC_Msk (0xfful << TIMER_CTL_PSC_Pos) /*!< TIMER_T::CTL: PSC Mask */ 761 762 #define TIMER_CTL_INTRGEN_Pos (19) /*!< TIMER_T::CTL: INTRGEN Position */ 763 #define TIMER_CTL_INTRGEN_Msk (0x1ul << TIMER_CTL_INTRGEN_Pos) /*!< TIMER_T::CTL: INTRGEN Mask */ 764 765 #define TIMER_CTL_PERIOSEL_Pos (20) /*!< TIMER_T::CTL: PERIOSEL Position */ 766 #define TIMER_CTL_PERIOSEL_Msk (0x1ul << TIMER_CTL_PERIOSEL_Pos) /*!< TIMER_T::CTL: PERIOSEL Mask */ 767 768 #define TIMER_CTL_TGLPINSEL_Pos (21) /*!< TIMER_T::CTL: TGLPINSEL Position */ 769 #define TIMER_CTL_TGLPINSEL_Msk (0x1ul << TIMER_CTL_TGLPINSEL_Pos) /*!< TIMER_T::CTL: TGLPINSEL Mask */ 770 771 #define TIMER_CTL_CAPSRC_Pos (22) /*!< TIMER_T::CTL: CAPSRC Position */ 772 #define TIMER_CTL_CAPSRC_Msk (0x1ul << TIMER_CTL_CAPSRC_Pos) /*!< TIMER_T::CTL: CAPSRC Mask */ 773 774 #define TIMER_CTL_WKEN_Pos (23) /*!< TIMER_T::CTL: WKEN Position */ 775 #define TIMER_CTL_WKEN_Msk (0x1ul << TIMER_CTL_WKEN_Pos) /*!< TIMER_T::CTL: WKEN Mask */ 776 777 #define TIMER_CTL_EXTCNTEN_Pos (24) /*!< TIMER_T::CTL: EXTCNTEN Position */ 778 #define TIMER_CTL_EXTCNTEN_Msk (0x1ul << TIMER_CTL_EXTCNTEN_Pos) /*!< TIMER_T::CTL: EXTCNTEN Mask */ 779 780 #define TIMER_CTL_ACTSTS_Pos (25) /*!< TIMER_T::CTL: ACTSTS Position */ 781 #define TIMER_CTL_ACTSTS_Msk (0x1ul << TIMER_CTL_ACTSTS_Pos) /*!< TIMER_T::CTL: ACTSTS Mask */ 782 783 #define TIMER_CTL_OPMODE_Pos (27) /*!< TIMER_T::CTL: OPMODE Position */ 784 #define TIMER_CTL_OPMODE_Msk (0x3ul << TIMER_CTL_OPMODE_Pos) /*!< TIMER_T::CTL: OPMODE Mask */ 785 786 #define TIMER_CTL_INTEN_Pos (29) /*!< TIMER_T::CTL: INTEN Position */ 787 #define TIMER_CTL_INTEN_Msk (0x1ul << TIMER_CTL_INTEN_Pos) /*!< TIMER_T::CTL: INTEN Mask */ 788 789 #define TIMER_CTL_CNTEN_Pos (30) /*!< TIMER_T::CTL: CNTEN Position */ 790 #define TIMER_CTL_CNTEN_Msk (0x1ul << TIMER_CTL_CNTEN_Pos) /*!< TIMER_T::CTL: CNTEN Mask */ 791 792 #define TIMER_CTL_ICEDEBUG_Pos (31) /*!< TIMER_T::CTL: ICEDEBUG Position */ 793 #define TIMER_CTL_ICEDEBUG_Msk (0x1ul << TIMER_CTL_ICEDEBUG_Pos) /*!< TIMER_T::CTL: ICEDEBUG Mask */ 794 795 #define TIMER_CMP_CMPDAT_Pos (0) /*!< TIMER_T::CMP: CMPDAT Position */ 796 #define TIMER_CMP_CMPDAT_Msk (0xfffffful << TIMER_CMP_CMPDAT_Pos) /*!< TIMER_T::CMP: CMPDAT Mask */ 797 798 #define TIMER_INTSTS_TIF_Pos (0) /*!< TIMER_T::INTSTS: TIF Position */ 799 #define TIMER_INTSTS_TIF_Msk (0x1ul << TIMER_INTSTS_TIF_Pos) /*!< TIMER_T::INTSTS: TIF Mask */ 800 801 #define TIMER_INTSTS_TWKF_Pos (1) /*!< TIMER_T::INTSTS: TWKF Position */ 802 #define TIMER_INTSTS_TWKF_Msk (0x1ul << TIMER_INTSTS_TWKF_Pos) /*!< TIMER_T::INTSTS: TWKF Mask */ 803 804 #define TIMER_CNT_CNT_Pos (0) /*!< TIMER_T::CNT: CNT Position */ 805 #define TIMER_CNT_CNT_Msk (0xfffffful << TIMER_CNT_CNT_Pos) /*!< TIMER_T::CNT: CNT Mask */ 806 807 #define TIMER_CNT_RSTACT_Pos (31) /*!< TIMER_T::CNT: RSTACT Position */ 808 #define TIMER_CNT_RSTACT_Msk (0x1ul << TIMER_CNT_RSTACT_Pos) /*!< TIMER_T::CNT: RSTACT Mask */ 809 810 #define TIMER_CAP_CAPDAT_Pos (0) /*!< TIMER_T::CAP: CAPDAT Position */ 811 #define TIMER_CAP_CAPDAT_Msk (0xfffffful << TIMER_CAP_CAPDAT_Pos) /*!< TIMER_T::CAP: CAPDAT Mask */ 812 813 #define TIMER_EXTCTL_CNTPHASE_Pos (0) /*!< TIMER_T::EXTCTL: CNTPHASE Position */ 814 #define TIMER_EXTCTL_CNTPHASE_Msk (0x1ul << TIMER_EXTCTL_CNTPHASE_Pos) /*!< TIMER_T::EXTCTL: CNTPHASE Mask */ 815 816 #define TIMER_EXTCTL_CAPEN_Pos (3) /*!< TIMER_T::EXTCTL: CAPEN Position */ 817 #define TIMER_EXTCTL_CAPEN_Msk (0x1ul << TIMER_EXTCTL_CAPEN_Pos) /*!< TIMER_T::EXTCTL: CAPEN Mask */ 818 819 #define TIMER_EXTCTL_CAPFUNCS_Pos (4) /*!< TIMER_T::EXTCTL: CAPFUNCS Position */ 820 #define TIMER_EXTCTL_CAPFUNCS_Msk (0x1ul << TIMER_EXTCTL_CAPFUNCS_Pos) /*!< TIMER_T::EXTCTL: CAPFUNCS Mask */ 821 822 #define TIMER_EXTCTL_CAPIEN_Pos (5) /*!< TIMER_T::EXTCTL: CAPIEN Position */ 823 #define TIMER_EXTCTL_CAPIEN_Msk (0x1ul << TIMER_EXTCTL_CAPIEN_Pos) /*!< TIMER_T::EXTCTL: CAPIEN Mask */ 824 825 #define TIMER_EXTCTL_CAPDBEN_Pos (6) /*!< TIMER_T::EXTCTL: CAPDBEN Position */ 826 #define TIMER_EXTCTL_CAPDBEN_Msk (0x1ul << TIMER_EXTCTL_CAPDBEN_Pos) /*!< TIMER_T::EXTCTL: CAPDBEN Mask */ 827 828 #define TIMER_EXTCTL_CNTDBEN_Pos (7) /*!< TIMER_T::EXTCTL: CNTDBEN Position */ 829 #define TIMER_EXTCTL_CNTDBEN_Msk (0x1ul << TIMER_EXTCTL_CNTDBEN_Pos) /*!< TIMER_T::EXTCTL: CNTDBEN Mask */ 830 831 #define TIMER_EXTCTL_ICAPSEL_Pos (8) /*!< TIMER_T::EXTCTL: ICAPSEL Position */ 832 #define TIMER_EXTCTL_ICAPSEL_Msk (0x7ul << TIMER_EXTCTL_ICAPSEL_Pos) /*!< TIMER_T::EXTCTL: ICAPSEL Mask */ 833 834 #define TIMER_EXTCTL_CAPEDGE_Pos (12) /*!< TIMER_T::EXTCTL: CAPEDGE Position */ 835 #define TIMER_EXTCTL_CAPEDGE_Msk (0x7ul << TIMER_EXTCTL_CAPEDGE_Pos) /*!< TIMER_T::EXTCTL: CAPEDGE Mask */ 836 837 #define TIMER_EXTCTL_ECNTSSEL_Pos (16) /*!< TIMER_T::EXTCTL: ECNTSSEL Position */ 838 #define TIMER_EXTCTL_ECNTSSEL_Msk (0x1ul << TIMER_EXTCTL_ECNTSSEL_Pos) /*!< TIMER_T::EXTCTL: ECNTSSEL Mask */ 839 840 #define TIMER_EXTCTL_CAPDIVSCL_Pos (28) /*!< TIMER_T::EXTCTL: CAPDIVSCL Position */ 841 #define TIMER_EXTCTL_CAPDIVSCL_Msk (0xful << TIMER_EXTCTL_CAPDIVSCL_Pos) /*!< TIMER_T::EXTCTL: CAPDIVSCL Mask */ 842 843 #define TIMER_EINTSTS_CAPIF_Pos (0) /*!< TIMER_T::EINTSTS: CAPIF Position */ 844 #define TIMER_EINTSTS_CAPIF_Msk (0x1ul << TIMER_EINTSTS_CAPIF_Pos) /*!< TIMER_T::EINTSTS: CAPIF Mask */ 845 846 #define TIMER_TRGCTL_TRGSSEL_Pos (0) /*!< TIMER_T::TRGCTL: TRGSSEL Position */ 847 #define TIMER_TRGCTL_TRGSSEL_Msk (0x1ul << TIMER_TRGCTL_TRGSSEL_Pos) /*!< TIMER_T::TRGCTL: TRGSSEL Mask */ 848 849 #define TIMER_TRGCTL_TRGEPWM_Pos (1) /*!< TIMER_T::TRGCTL: TRGEPWM Position */ 850 #define TIMER_TRGCTL_TRGEPWM_Msk (0x1ul << TIMER_TRGCTL_TRGEPWM_Pos) /*!< TIMER_T::TRGCTL: TRGEPWM Mask */ 851 852 #define TIMER_TRGCTL_TRGEADC_Pos (2) /*!< TIMER_T::TRGCTL: TRGEADC Position */ 853 #define TIMER_TRGCTL_TRGEADC_Msk (0x1ul << TIMER_TRGCTL_TRGEADC_Pos) /*!< TIMER_T::TRGCTL: TRGEADC Mask */ 854 855 #define TIMER_TRGCTL_TRGDAC_Pos (3) /*!< TIMER_T::TRGCTL: TRGDAC Position */ 856 #define TIMER_TRGCTL_TRGDAC_Msk (0x1ul << TIMER_TRGCTL_TRGDAC_Pos) /*!< TIMER_T::TRGCTL: TRGDAC Mask */ 857 858 #define TIMER_TRGCTL_TRGPDMA_Pos (4) /*!< TIMER_T::TRGCTL: TRGPDMA Position */ 859 #define TIMER_TRGCTL_TRGPDMA_Msk (0x1ul << TIMER_TRGCTL_TRGPDMA_Pos) /*!< TIMER_T::TRGCTL: TRGPDMA Mask */ 860 861 #define TIMER_ALTCTL_FUNCSEL_Pos (0) /*!< TIMER_T::ALTCTL: FUNCSEL Position */ 862 #define TIMER_ALTCTL_FUNCSEL_Msk (0x1ul << TIMER_ALTCTL_FUNCSEL_Pos) /*!< TIMER_T::ALTCTL: FUNCSEL Mask */ 863 864 #define TIMER_PWMCTL_CNTEN_Pos (0) /*!< TIMER_T::PWMCTL: CNTEN Position */ 865 #define TIMER_PWMCTL_CNTEN_Msk (0x1ul << TIMER_PWMCTL_CNTEN_Pos) /*!< TIMER_T::PWMCTL: CNTEN Mask */ 866 867 #define TIMER_PWMCTL_CNTTYPE_Pos (1) /*!< TIMER_T::PWMCTL: CNTTYPE Position */ 868 #define TIMER_PWMCTL_CNTTYPE_Msk (0x3ul << TIMER_PWMCTL_CNTTYPE_Pos) /*!< TIMER_T::PWMCTL: CNTTYPE Mask */ 869 870 #define TIMER_PWMCTL_CNTMODE_Pos (3) /*!< TIMER_T::PWMCTL: CNTMODE Position */ 871 #define TIMER_PWMCTL_CNTMODE_Msk (0x1ul << TIMER_PWMCTL_CNTMODE_Pos) /*!< TIMER_T::PWMCTL: CNTMODE Mask */ 872 873 #define TIMER_PWMCTL_CTRLD_Pos (8) /*!< TIMER_T::PWMCTL: CTRLD Position */ 874 #define TIMER_PWMCTL_CTRLD_Msk (0x1ul << TIMER_PWMCTL_CTRLD_Pos) /*!< TIMER_T::PWMCTL: CTRLD Mask */ 875 876 #define TIMER_PWMCTL_IMMLDEN_Pos (9) /*!< TIMER_T::PWMCTL: IMMLDEN Position */ 877 #define TIMER_PWMCTL_IMMLDEN_Msk (0x1ul << TIMER_PWMCTL_IMMLDEN_Pos) /*!< TIMER_T::PWMCTL: IMMLDEN Mask */ 878 879 #define TIMER_PWMCTL_OUTMODE_Pos (16) /*!< TIMER_T::PWMCTL: OUTMODE Position */ 880 #define TIMER_PWMCTL_OUTMODE_Msk (0x1ul << TIMER_PWMCTL_OUTMODE_Pos) /*!< TIMER_T::PWMCTL: OUTMODE Mask */ 881 882 #define TIMER_PWMCTL_DBGHALT_Pos (30) /*!< TIMER_T::PWMCTL: DBGHALT Position */ 883 #define TIMER_PWMCTL_DBGHALT_Msk (0x1ul << TIMER_PWMCTL_DBGHALT_Pos) /*!< TIMER_T::PWMCTL: DBGHALT Mask */ 884 885 #define TIMER_PWMCTL_DBGTRIOFF_Pos (31) /*!< TIMER_T::PWMCTL: DBGTRIOFF Position */ 886 #define TIMER_PWMCTL_DBGTRIOFF_Msk (0x1ul << TIMER_PWMCTL_DBGTRIOFF_Pos) /*!< TIMER_T::PWMCTL: DBGTRIOFF Mask */ 887 888 #define TIMER_PWMCLKSRC_CLKSRC_Pos (0) /*!< TIMER_T::PWMCLKSRC: CLKSRC Position */ 889 #define TIMER_PWMCLKSRC_CLKSRC_Msk (0x7ul << TIMER_PWMCLKSRC_CLKSRC_Pos) /*!< TIMER_T::PWMCLKSRC: CLKSRC Mask */ 890 891 #define TIMER_PWMCLKPSC_CLKPSC_Pos (0) /*!< TIMER_T::PWMCLKPSC: CLKPSC Position */ 892 #define TIMER_PWMCLKPSC_CLKPSC_Msk (0xffful << TIMER_PWMCLKPSC_CLKPSC_Pos) /*!< TIMER_T::PWMCLKPSC: CLKPSC Mask */ 893 894 #define TIMER_PWMCNTCLR_CNTCLR_Pos (0) /*!< TIMER_T::PWMCNTCLR: CNTCLR Position */ 895 #define TIMER_PWMCNTCLR_CNTCLR_Msk (0x1ul << TIMER_PWMCNTCLR_CNTCLR_Pos) /*!< TIMER_T::PWMCNTCLR: CNTCLR Mask */ 896 897 #define TIMER_PWMPERIOD_PERIOD_Pos (0) /*!< TIMER_T::PWMPERIOD: PERIOD Position */ 898 #define TIMER_PWMPERIOD_PERIOD_Msk (0xfffful << TIMER_PWMPERIOD_PERIOD_Pos) /*!< TIMER_T::PWMPERIOD: PERIOD Mask */ 899 900 #define TIMER_PWMCMPDAT_CMP_Pos (0) /*!< TIMER_T::PWMCMPDAT: CMP Position */ 901 #define TIMER_PWMCMPDAT_CMP_Msk (0xfffful << TIMER_PWMCMPDAT_CMP_Pos) /*!< TIMER_T::PWMCMPDAT: CMP Mask */ 902 903 #define TIMER_PWMDTCTL_DTCNT_Pos (0) /*!< TIMER_T::PWMDTCTL: DTCNT Position */ 904 #define TIMER_PWMDTCTL_DTCNT_Msk (0xffful << TIMER_PWMDTCTL_DTCNT_Pos) /*!< TIMER_T::PWMDTCTL: DTCNT Mask */ 905 906 #define TIMER_PWMDTCTL_DTEN_Pos (16) /*!< TIMER_T::PWMDTCTL: DTEN Position */ 907 #define TIMER_PWMDTCTL_DTEN_Msk (0x1ul << TIMER_PWMDTCTL_DTEN_Pos) /*!< TIMER_T::PWMDTCTL: DTEN Mask */ 908 909 #define TIMER_PWMDTCTL_DTCKSEL_Pos (24) /*!< TIMER_T::PWMDTCTL: DTCKSEL Position */ 910 #define TIMER_PWMDTCTL_DTCKSEL_Msk (0x1ul << TIMER_PWMDTCTL_DTCKSEL_Pos) /*!< TIMER_T::PWMDTCTL: DTCKSEL Mask */ 911 912 #define TIMER_PWMCNT_CNT_Pos (0) /*!< TIMER_T::PWMCNT: CNT Position */ 913 #define TIMER_PWMCNT_CNT_Msk (0xfffful << TIMER_PWMCNT_CNT_Pos) /*!< TIMER_T::PWMCNT: CNT Mask */ 914 915 #define TIMER_PWMCNT_DIRF_Pos (16) /*!< TIMER_T::PWMCNT: DIRF Position */ 916 #define TIMER_PWMCNT_DIRF_Msk (0x1ul << TIMER_PWMCNT_DIRF_Pos) /*!< TIMER_T::PWMCNT: DIRF Mask */ 917 918 #define TIMER_PWMMSKEN_MSKEN0_Pos (0) /*!< TIMER_T::PWMMSKEN: MSKEN0 Position */ 919 #define TIMER_PWMMSKEN_MSKEN0_Msk (0x1ul << TIMER_PWMMSKEN_MSKEN0_Pos) /*!< TIMER_T::PWMMSKEN: MSKEN0 Mask */ 920 921 #define TIMER_PWMMSKEN_MSKEN1_Pos (1) /*!< TIMER_T::PWMMSKEN: MSKEN1 Position */ 922 #define TIMER_PWMMSKEN_MSKEN1_Msk (0x1ul << TIMER_PWMMSKEN_MSKEN1_Pos) /*!< TIMER_T::PWMMSKEN: MSKEN1 Mask */ 923 924 #define TIMER_PWMMSK_MSKDAT0_Pos (0) /*!< TIMER_T::PWMMSK: MSKDAT0 Position */ 925 #define TIMER_PWMMSK_MSKDAT0_Msk (0x1ul << TIMER_PWMMSK_MSKDAT0_Pos) /*!< TIMER_T::PWMMSK: MSKDAT0 Mask */ 926 927 #define TIMER_PWMMSK_MSKDAT1_Pos (1) /*!< TIMER_T::PWMMSK: MSKDAT1 Position */ 928 #define TIMER_PWMMSK_MSKDAT1_Msk (0x1ul << TIMER_PWMMSK_MSKDAT1_Pos) /*!< TIMER_T::PWMMSK: MSKDAT1 Mask */ 929 930 #define TIMER_PWMBNF_BRKNFEN_Pos (0) /*!< TIMER_T::PWMBNF: BRKNFEN Position */ 931 #define TIMER_PWMBNF_BRKNFEN_Msk (0x1ul << TIMER_PWMBNF_BRKNFEN_Pos) /*!< TIMER_T::PWMBNF: BRKNFEN Mask */ 932 933 #define TIMER_PWMBNF_BRKNFSEL_Pos (1) /*!< TIMER_T::PWMBNF: BRKNFSEL Position */ 934 #define TIMER_PWMBNF_BRKNFSEL_Msk (0x7ul << TIMER_PWMBNF_BRKNFSEL_Pos) /*!< TIMER_T::PWMBNF: BRKNFSEL Mask */ 935 936 #define TIMER_PWMBNF_BRKFCNT_Pos (4) /*!< TIMER_T::PWMBNF: BRKFCNT Position */ 937 #define TIMER_PWMBNF_BRKFCNT_Msk (0x7ul << TIMER_PWMBNF_BRKFCNT_Pos) /*!< TIMER_T::PWMBNF: BRKFCNT Mask */ 938 939 #define TIMER_PWMBNF_BRKPINV_Pos (7) /*!< TIMER_T::PWMBNF: BRKPINV Position */ 940 #define TIMER_PWMBNF_BRKPINV_Msk (0x1ul << TIMER_PWMBNF_BRKPINV_Pos) /*!< TIMER_T::PWMBNF: BRKPINV Mask */ 941 942 #define TIMER_PWMBNF_BKPINSRC_Pos (16) /*!< TIMER_T::PWMBNF: BKPINSRC Position */ 943 #define TIMER_PWMBNF_BKPINSRC_Msk (0x3ul << TIMER_PWMBNF_BKPINSRC_Pos) /*!< TIMER_T::PWMBNF: BKPINSRC Mask */ 944 945 #define TIMER_PWMFAILBRK_CSSBRKEN_Pos (0) /*!< TIMER_T::PWMFAILBRK: CSSBRKEN Position */ 946 #define TIMER_PWMFAILBRK_CSSBRKEN_Msk (0x1ul << TIMER_PWMFAILBRK_CSSBRKEN_Pos) /*!< TIMER_T::PWMFAILBRK: CSSBRKEN Mask */ 947 948 #define TIMER_PWMFAILBRK_BODBRKEN_Pos (1) /*!< TIMER_T::PWMFAILBRK: BODBRKEN Position */ 949 #define TIMER_PWMFAILBRK_BODBRKEN_Msk (0x1ul << TIMER_PWMFAILBRK_BODBRKEN_Pos) /*!< TIMER_T::PWMFAILBRK: BODBRKEN Mask */ 950 951 #define TIMER_PWMFAILBRK_RAMBRKEN_Pos (2) /*!< TIMER_T::PWMFAILBRK: RAMBRKEN Position */ 952 #define TIMER_PWMFAILBRK_RAMBRKEN_Msk (0x1ul << TIMER_PWMFAILBRK_RAMBRKEN_Pos) /*!< TIMER_T::PWMFAILBRK: RAMBRKEN Mask */ 953 954 #define TIMER_PWMFAILBRK_CORBRKEN_Pos (3) /*!< TIMER_T::PWMFAILBRK: CORBRKEN Position */ 955 #define TIMER_PWMFAILBRK_CORBRKEN_Msk (0x1ul << TIMER_PWMFAILBRK_CORBRKEN_Pos) /*!< TIMER_T::PWMFAILBRK: CORBRKEN Mask */ 956 957 #define TIMER_PWMBRKCTL_CPO0EBEN_Pos (0) /*!< TIMER_T::PWMBRKCTL: CPO0EBEN Position */ 958 #define TIMER_PWMBRKCTL_CPO0EBEN_Msk (0x1ul << TIMER_PWMBRKCTL_CPO0EBEN_Pos) /*!< TIMER_T::PWMBRKCTL: CPO0EBEN Mask */ 959 960 #define TIMER_PWMBRKCTL_CPO1EBEN_Pos (1) /*!< TIMER_T::PWMBRKCTL: CPO1EBEN Position */ 961 #define TIMER_PWMBRKCTL_CPO1EBEN_Msk (0x1ul << TIMER_PWMBRKCTL_CPO1EBEN_Pos) /*!< TIMER_T::PWMBRKCTL: CPO1EBEN Mask */ 962 963 #define TIMER_PWMBRKCTL_BRKPEEN_Pos (4) /*!< TIMER_T::PWMBRKCTL: BRKPEEN Position */ 964 #define TIMER_PWMBRKCTL_BRKPEEN_Msk (0x1ul << TIMER_PWMBRKCTL_BRKPEEN_Pos) /*!< TIMER_T::PWMBRKCTL: BRKPEEN Mask */ 965 966 #define TIMER_PWMBRKCTL_SYSEBEN_Pos (7) /*!< TIMER_T::PWMBRKCTL: SYSEBEN Position */ 967 #define TIMER_PWMBRKCTL_SYSEBEN_Msk (0x1ul << TIMER_PWMBRKCTL_SYSEBEN_Pos) /*!< TIMER_T::PWMBRKCTL: SYSEBEN Mask */ 968 969 #define TIMER_PWMBRKCTL_CPO0LBEN_Pos (8) /*!< TIMER_T::PWMBRKCTL: CPO0LBEN Position */ 970 #define TIMER_PWMBRKCTL_CPO0LBEN_Msk (0x1ul << TIMER_PWMBRKCTL_CPO0LBEN_Pos) /*!< TIMER_T::PWMBRKCTL: CPO0LBEN Mask */ 971 972 #define TIMER_PWMBRKCTL_CPO1LBEN_Pos (9) /*!< TIMER_T::PWMBRKCTL: CPO1LBEN Position */ 973 #define TIMER_PWMBRKCTL_CPO1LBEN_Msk (0x1ul << TIMER_PWMBRKCTL_CPO1LBEN_Pos) /*!< TIMER_T::PWMBRKCTL: CPO1LBEN Mask */ 974 975 #define TIMER_PWMBRKCTL_BRKPLEN_Pos (12) /*!< TIMER_T::PWMBRKCTL: BRKPLEN Position */ 976 #define TIMER_PWMBRKCTL_BRKPLEN_Msk (0x1ul << TIMER_PWMBRKCTL_BRKPLEN_Pos) /*!< TIMER_T::PWMBRKCTL: BRKPLEN Mask */ 977 978 #define TIMER_PWMBRKCTL_SYSLBEN_Pos (15) /*!< TIMER_T::PWMBRKCTL: SYSLBEN Position */ 979 #define TIMER_PWMBRKCTL_SYSLBEN_Msk (0x1ul << TIMER_PWMBRKCTL_SYSLBEN_Pos) /*!< TIMER_T::PWMBRKCTL: SYSLBEN Mask */ 980 981 #define TIMER_PWMBRKCTL_BRKAEVEN_Pos (16) /*!< TIMER_T::PWMBRKCTL: BRKAEVEN Position */ 982 #define TIMER_PWMBRKCTL_BRKAEVEN_Msk (0x3ul << TIMER_PWMBRKCTL_BRKAEVEN_Pos) /*!< TIMER_T::PWMBRKCTL: BRKAEVEN Mask */ 983 984 #define TIMER_PWMBRKCTL_BRKAODD_Pos (18) /*!< TIMER_T::PWMBRKCTL: BRKAODD Position */ 985 #define TIMER_PWMBRKCTL_BRKAODD_Msk (0x3ul << TIMER_PWMBRKCTL_BRKAODD_Pos) /*!< TIMER_T::PWMBRKCTL: BRKAODD Mask */ 986 987 #define TIMER_PWMPOLCTL_PINV0_Pos (0) /*!< TIMER_T::PWMPOLCTL: PINV0 Position */ 988 #define TIMER_PWMPOLCTL_PINV0_Msk (0x1ul << TIMER_PWMPOLCTL_PINV0_Pos) /*!< TIMER_T::PWMPOLCTL: PINV0 Mask */ 989 990 #define TIMER_PWMPOLCTL_PINV1_Pos (1) /*!< TIMER_T::PWMPOLCTL: PINV1 Position */ 991 #define TIMER_PWMPOLCTL_PINV1_Msk (0x1ul << TIMER_PWMPOLCTL_PINV1_Pos) /*!< TIMER_T::PWMPOLCTL: PINV1 Mask */ 992 993 #define TIMER_PWMPOEN_POEN0_Pos (0) /*!< TIMER_T::PWMPOEN: POEN0 Position */ 994 #define TIMER_PWMPOEN_POEN0_Msk (0x1ul << TIMER_PWMPOEN_POEN0_Pos) /*!< TIMER_T::PWMPOEN: POEN0 Mask */ 995 996 #define TIMER_PWMPOEN_POEN1_Pos (1) /*!< TIMER_T::PWMPOEN: POEN1 Position */ 997 #define TIMER_PWMPOEN_POEN1_Msk (0x1ul << TIMER_PWMPOEN_POEN1_Pos) /*!< TIMER_T::PWMPOEN: POEN1 Mask */ 998 999 #define TIMER_PWMSWBRK_BRKETRG_Pos (0) /*!< TIMER_T::PWMSWBRK: BRKETRG Position */ 1000 #define TIMER_PWMSWBRK_BRKETRG_Msk (0x1ul << TIMER_PWMSWBRK_BRKETRG_Pos) /*!< TIMER_T::PWMSWBRK: BRKETRG Mask */ 1001 1002 #define TIMER_PWMSWBRK_BRKLTRG_Pos (8) /*!< TIMER_T::PWMSWBRK: BRKLTRG Position */ 1003 #define TIMER_PWMSWBRK_BRKLTRG_Msk (0x1ul << TIMER_PWMSWBRK_BRKLTRG_Pos) /*!< TIMER_T::PWMSWBRK: BRKLTRG Mask */ 1004 1005 #define TIMER_PWMINTEN0_ZIEN_Pos (0) /*!< TIMER_T::PWMINTEN0: ZIEN Position */ 1006 #define TIMER_PWMINTEN0_ZIEN_Msk (0x1ul << TIMER_PWMINTEN0_ZIEN_Pos) /*!< TIMER_T::PWMINTEN0: ZIEN Mask */ 1007 1008 #define TIMER_PWMINTEN0_PIEN_Pos (1) /*!< TIMER_T::PWMINTEN0: PIEN Position */ 1009 #define TIMER_PWMINTEN0_PIEN_Msk (0x1ul << TIMER_PWMINTEN0_PIEN_Pos) /*!< TIMER_T::PWMINTEN0: PIEN Mask */ 1010 1011 #define TIMER_PWMINTEN0_CMPUIEN_Pos (2) /*!< TIMER_T::PWMINTEN0: CMPUIEN Position */ 1012 #define TIMER_PWMINTEN0_CMPUIEN_Msk (0x1ul << TIMER_PWMINTEN0_CMPUIEN_Pos) /*!< TIMER_T::PWMINTEN0: CMPUIEN Mask */ 1013 1014 #define TIMER_PWMINTEN0_CMPDIEN_Pos (3) /*!< TIMER_T::PWMINTEN0: CMPDIEN Position */ 1015 #define TIMER_PWMINTEN0_CMPDIEN_Msk (0x1ul << TIMER_PWMINTEN0_CMPDIEN_Pos) /*!< TIMER_T::PWMINTEN0: CMPDIEN Mask */ 1016 1017 #define TIMER_PWMINTEN1_BRKEIEN_Pos (0) /*!< TIMER_T::PWMINTEN1: BRKEIEN Position */ 1018 #define TIMER_PWMINTEN1_BRKEIEN_Msk (0x1ul << TIMER_PWMINTEN1_BRKEIEN_Pos) /*!< TIMER_T::PWMINTEN1: BRKEIEN Mask */ 1019 1020 #define TIMER_PWMINTEN1_BRKLIEN_Pos (8) /*!< TIMER_T::PWMINTEN1: BRKLIEN Position */ 1021 #define TIMER_PWMINTEN1_BRKLIEN_Msk (0x1ul << TIMER_PWMINTEN1_BRKLIEN_Pos) /*!< TIMER_T::PWMINTEN1: BRKLIEN Mask */ 1022 1023 #define TIMER_PWMINTSTS0_ZIF_Pos (0) /*!< TIMER_T::PWMINTSTS0: ZIF Position */ 1024 #define TIMER_PWMINTSTS0_ZIF_Msk (0x1ul << TIMER_PWMINTSTS0_ZIF_Pos) /*!< TIMER_T::PWMINTSTS0: ZIF Mask */ 1025 1026 #define TIMER_PWMINTSTS0_PIF_Pos (1) /*!< TIMER_T::PWMINTSTS0: PIF Position */ 1027 #define TIMER_PWMINTSTS0_PIF_Msk (0x1ul << TIMER_PWMINTSTS0_PIF_Pos) /*!< TIMER_T::PWMINTSTS0: PIF Mask */ 1028 1029 #define TIMER_PWMINTSTS0_CMPUIF_Pos (2) /*!< TIMER_T::PWMINTSTS0: CMPUIF Position */ 1030 #define TIMER_PWMINTSTS0_CMPUIF_Msk (0x1ul << TIMER_PWMINTSTS0_CMPUIF_Pos) /*!< TIMER_T::PWMINTSTS0: CMPUIF Mask */ 1031 1032 #define TIMER_PWMINTSTS0_CMPDIF_Pos (3) /*!< TIMER_T::PWMINTSTS0: CMPDIF Position */ 1033 #define TIMER_PWMINTSTS0_CMPDIF_Msk (0x1ul << TIMER_PWMINTSTS0_CMPDIF_Pos) /*!< TIMER_T::PWMINTSTS0: CMPDIF Mask */ 1034 1035 #define TIMER_PWMINTSTS1_BRKEIF0_Pos (0) /*!< TIMER_T::PWMINTSTS1: BRKEIF0 Position */ 1036 #define TIMER_PWMINTSTS1_BRKEIF0_Msk (0x1ul << TIMER_PWMINTSTS1_BRKEIF0_Pos) /*!< TIMER_T::PWMINTSTS1: BRKEIF0 Mask */ 1037 1038 #define TIMER_PWMINTSTS1_BRKEIF1_Pos (1) /*!< TIMER_T::PWMINTSTS1: BRKEIF1 Position */ 1039 #define TIMER_PWMINTSTS1_BRKEIF1_Msk (0x1ul << TIMER_PWMINTSTS1_BRKEIF1_Pos) /*!< TIMER_T::PWMINTSTS1: BRKEIF1 Mask */ 1040 1041 #define TIMER_PWMINTSTS1_BRKLIF0_Pos (8) /*!< TIMER_T::PWMINTSTS1: BRKLIF0 Position */ 1042 #define TIMER_PWMINTSTS1_BRKLIF0_Msk (0x1ul << TIMER_PWMINTSTS1_BRKLIF0_Pos) /*!< TIMER_T::PWMINTSTS1: BRKLIF0 Mask */ 1043 1044 #define TIMER_PWMINTSTS1_BRKLIF1_Pos (9) /*!< TIMER_T::PWMINTSTS1: BRKLIF1 Position */ 1045 #define TIMER_PWMINTSTS1_BRKLIF1_Msk (0x1ul << TIMER_PWMINTSTS1_BRKLIF1_Pos) /*!< TIMER_T::PWMINTSTS1: BRKLIF1 Mask */ 1046 1047 #define TIMER_PWMINTSTS1_BRKESTS0_Pos (16) /*!< TIMER_T::PWMINTSTS1: BRKESTS0 Position */ 1048 #define TIMER_PWMINTSTS1_BRKESTS0_Msk (0x1ul << TIMER_PWMINTSTS1_BRKESTS0_Pos) /*!< TIMER_T::PWMINTSTS1: BRKESTS0 Mask */ 1049 1050 #define TIMER_PWMINTSTS1_BRKESTS1_Pos (17) /*!< TIMER_T::PWMINTSTS1: BRKESTS1 Position */ 1051 #define TIMER_PWMINTSTS1_BRKESTS1_Msk (0x1ul << TIMER_PWMINTSTS1_BRKESTS1_Pos) /*!< TIMER_T::PWMINTSTS1: BRKESTS1 Mask */ 1052 1053 #define TIMER_PWMINTSTS1_BRKLSTS0_Pos (24) /*!< TIMER_T::PWMINTSTS1: BRKLSTS0 Position */ 1054 #define TIMER_PWMINTSTS1_BRKLSTS0_Msk (0x1ul << TIMER_PWMINTSTS1_BRKLSTS0_Pos) /*!< TIMER_T::PWMINTSTS1: BRKLSTS0 Mask */ 1055 1056 #define TIMER_PWMINTSTS1_BRKLSTS1_Pos (25) /*!< TIMER_T::PWMINTSTS1: BRKLSTS1 Position */ 1057 #define TIMER_PWMINTSTS1_BRKLSTS1_Msk (0x1ul << TIMER_PWMINTSTS1_BRKLSTS1_Pos) /*!< TIMER_T::PWMINTSTS1: BRKLSTS1 Mask */ 1058 1059 #define TIMER_PWMEADCTS_TRGSEL_Pos (0) /*!< TIMER_T::PWMEADCTS: TRGSEL Position */ 1060 #define TIMER_PWMEADCTS_TRGSEL_Msk (0x7ul << TIMER_PWMEADCTS_TRGSEL_Pos) /*!< TIMER_T::PWMEADCTS: TRGSEL Mask */ 1061 1062 #define TIMER_PWMEADCTS_TRGEN_Pos (7) /*!< TIMER_T::PWMEADCTS: TRGEN Position */ 1063 #define TIMER_PWMEADCTS_TRGEN_Msk (0x1ul << TIMER_PWMEADCTS_TRGEN_Pos) /*!< TIMER_T::PWMEADCTS: TRGEN Mask */ 1064 1065 #define TIMER_PWMSCTL_SYNCMODE_Pos (0) /*!< TIMER_T::PWMSCTL: SYNCMODE Position */ 1066 #define TIMER_PWMSCTL_SYNCMODE_Msk (0x3ul << TIMER_PWMSCTL_SYNCMODE_Pos) /*!< TIMER_T::PWMSCTL: SYNCMODE Mask */ 1067 1068 #define TIMER_PWMSCTL_SYNCSRC_Pos (8) /*!< TIMER_T::PWMSCTL: SYNCSRC Position */ 1069 #define TIMER_PWMSCTL_SYNCSRC_Msk (0x1ul << TIMER_PWMSCTL_SYNCSRC_Pos) /*!< TIMER_T::PWMSCTL: SYNCSRC Mask */ 1070 1071 #define TIMER_PWMSTRG_STRGEN_Pos (0) /*!< TIMER_T::PWMSTRG: STRGEN Position */ 1072 #define TIMER_PWMSTRG_STRGEN_Msk (0x1ul << TIMER_PWMSTRG_STRGEN_Pos) /*!< TIMER_T::PWMSTRG: STRGEN Mask */ 1073 1074 #define TIMER_PWMSTATUS_CNTMAXF_Pos (0) /*!< TIMER_T::PWMSTATUS: CNTMAXF Position */ 1075 #define TIMER_PWMSTATUS_CNTMAXF_Msk (0x1ul << TIMER_PWMSTATUS_CNTMAXF_Pos) /*!< TIMER_T::PWMSTATUS: CNTMAXF Mask */ 1076 1077 #define TIMER_PWMSTATUS_EADCTRGF_Pos (16) /*!< TIMER_T::PWMSTATUS: EADCTRGF Position */ 1078 #define TIMER_PWMSTATUS_EADCTRGF_Msk (0x1ul << TIMER_PWMSTATUS_EADCTRGF_Pos) /*!< TIMER_T::PWMSTATUS: EADCTRGF Mask */ 1079 1080 #define TIMER_PWMPBUF_PBUF_Pos (0) /*!< TIMER_T::PWMPBUF: PBUF Position */ 1081 #define TIMER_PWMPBUF_PBUF_Msk (0xfffful << TIMER_PWMPBUF_PBUF_Pos) /*!< TIMER_T::PWMPBUF: PBUF Mask */ 1082 1083 #define TIMER_PWMCMPBUF_CMPBUF_Pos (0) /*!< TIMER_T::PWMCMPBUF: CMPBUF Position */ 1084 #define TIMER_PWMCMPBUF_CMPBUF_Msk (0xfffful << TIMER_PWMCMPBUF_CMPBUF_Pos) /*!< TIMER_T::PWMCMPBUF: CMPBUF Mask */ 1085 1086 /**@}*/ /* TIMER_CONST */ 1087 /**@}*/ /* end of TIMER register group */ 1088 /**@}*/ /* end of REGISTER group */ 1089 1090 #if defined ( __CC_ARM ) 1091 #pragma no_anon_unions 1092 #endif 1093 1094 #endif /* __TIMER_REG_H__ */ 1095
