1 /**************************************************************************//** 2 * @file sys_reg.h 3 * @version V1.00 4 * @brief SYS register definition header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __SYS_REG_H__ 10 #define __SYS_REG_H__ 11 12 #if defined ( __CC_ARM ) 13 #pragma anon_unions 14 #endif 15 16 /** 17 @addtogroup REGISTER Control Register 18 @{ 19 */ 20 21 /** 22 @addtogroup SYS System Manger Controller(SYS) 23 Memory Mapped Structure for SYS Controller 24 @{ */ 25 26 typedef struct 27 { 28 29 30 /** 31 * @var SYS_T::PDID 32 * Offset: 0x00 Part Device Identification Number Register 33 * --------------------------------------------------------------------------------------------------- 34 * |Bits |Field |Descriptions 35 * | :----: | :----: | :---- | 36 * |[31:0] |PDID |Part Device Identification Number (Read Only) 37 * | | |This register reflects device part number code 38 * | | |Software can read this register to identify which device is used. 39 * @var SYS_T::RSTSTS 40 * Offset: 0x04 System Reset Status Register 41 * --------------------------------------------------------------------------------------------------- 42 * |Bits |Field |Descriptions 43 * | :----: | :----: | :---- | 44 * |[0] |PORF |POR Reset Flag 45 * | | |The POR reset flag is set by the "Reset Signal" from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source. 46 * | | |0 = No reset from POR or CHIPRST. 47 * | | |1 = Power-on Reset (POR) or CHIPRST had issued the reset signal to reset the system. 48 * | | |Note: Write 1 to clear this bit to 0. 49 * |[1] |PINRF |NRESET Pin Reset Flag 50 * | | |The nRESET pin reset flag is set by the "Reset Signal" from the nRESET Pin to indicate the previous reset source. 51 * | | |0 = No reset from nRESET pin. 52 * | | |1 = Pin nRESET had issued the reset signal to reset the system. 53 * | | |Note: Write 1 to clear this bit to 0. 54 * |[2] |WDTRF |WDT Reset Flag 55 * | | |The WDT reset flag is set by the "Reset Signal" from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source. 56 * | | |0 = No reset from watchdog timer or window watchdog timer. 57 * | | |1 = The watchdog timer or window watchdog timer had issued the reset signal to reset the system. 58 * | | |Note1: Write 1 to clear this bit to 0. 59 * | | |Note2: Watchdog Timer register RSTF(WDT_CTL[2]) bit is set if the system has been reset by WDT time-out reset 60 * | | |Window Watchdog Timer register WWDTRF(WWDT_STATUS[1]) bit is set if the system has been reset by WWDT time-out reset. 61 * |[3] |LVRF |LVR Reset Flag 62 * | | |The LVR reset flag is set by the "Reset Signal" from the Low Voltage Reset Controller to indicate the previous reset source. 63 * | | |0 = No reset from LVR. 64 * | | |1 = LVR controller had issued the reset signal to reset the system. 65 * | | |Note: Write 1 to clear this bit to 0. 66 * |[4] |BODRF |BOD Reset Flag 67 * | | |The BOD reset flag is set by the "Reset Signal" from the Brown-Out Detector to indicate the previous reset source. 68 * | | |0 = No reset from BOD. 69 * | | |1 = The BOD had issued the reset signal to reset the system. 70 * | | |Note: Write 1 to clear this bit to 0. 71 * |[5] |SYSRF |System Reset Flag 72 * | | |The system reset flag is set by the "Reset Signal" from the Cortex-M4 Core to indicate the previous reset source. 73 * | | |0 = No reset from Cortex-M4. 74 * | | |1 = The Cortex-M4 had issued the reset signal to reset the system by writing 1 to the bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M4 core. 75 * | | |Note: Write 1 to clear this bit to 0. 76 * |[7] |CPURF |CPU Reset Flag 77 * | | |The CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M4 Core and Flash Memory Controller (FMC). 78 * | | |0 = No reset from CPU. 79 * | | |1 = The Cortex-M4 Core and FMC are reset by software setting CPURST to 1. 80 * | | |Note: Write to clear this bit to 0. 81 * |[8] |CPULKRF |CPU Lock-up Reset Flag 82 * | | |0 = No reset from CPU lock-up happened. 83 * | | |1 = The Cortex-M4 lock-up happened and chip is reset. 84 * | | |Note: Write 1 to clear this bit to 0. 85 * | | |Note2: When CPU lock-up happened under ICE is connected, This flag will set to 1 but chip will not reset. 86 * @var SYS_T::IPRST0 87 * Offset: 0x08 Peripheral Reset Control Register 0 88 * --------------------------------------------------------------------------------------------------- 89 * |Bits |Field |Descriptions 90 * | :----: | :----: | :---- | 91 * |[0] |CHIPRST |Chip One-shot Reset (Write Protect) 92 * | | |Setting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles. 93 * | | |The CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from flash are also reload. 94 * | | |About the difference between CHIPRST and SYSRESETREQ(AIRCR[2]), please refer to section 6.2.2 95 * | | |0 = Chip normal operation. 96 * | | |1 = Chip one-shot reset. 97 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 98 * |[1] |CPURST |Processor Core One-shot Reset (Write Protect) 99 * | | |Setting this bit will only reset the processor core and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles. 100 * | | |0 = Processor core normal operation. 101 * | | |1 = Processor core one-shot reset. 102 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 103 * |[2] |PDMARST |PDMA Controller Reset (Write Protect) 104 * | | |Setting this bit to 1 will generate a reset signal to the PDMA 105 * | | |User needs to set this bit to 0 to release from reset state. 106 * | | |0 = PDMA controller normal operation. 107 * | | |1 = PDMA controller reset. 108 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 109 * |[3] |EBIRST |EBI Controller Reset (Write Protect) 110 * | | |Set this bit to 1 will generate a reset signal to the EBI 111 * | | |User needs to set this bit to 0 to release from the reset state. 112 * | | |0 = EBI controller normal operation. 113 * | | |1 = EBI controller reset. 114 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 115 * |[5] |EMACRST |EMAC Controller Reset (Write Protect) 116 * | | |Setting this bit to 1 will generate a reset signal to the EMAC controller 117 * | | |User needs to set this bit to 0 to release from the reset state. 118 * | | |0 = EMAC controller normal operation. 119 * | | |1 = EMAC controller reset. 120 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 121 * |[6] |SDH0RST |SDHOST0 Controller Reset (Write Protect) 122 * | | |Setting this bit to 1 will generate a reset signal to the SDHOST0 controller 123 * | | |User needs to set this bit to 0 to release from the reset state. 124 * | | |0 = SDHOST0 controller normal operation. 125 * | | |1 = SDHOST0 controller reset. 126 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 127 * |[7] |CRCRST |CRC Calculation Controller Reset (Write Protect) 128 * | | |Set this bit to 1 will generate a reset signal to the CRC calculation controller 129 * | | |User needs to set this bit to 0 to release from the reset state. 130 * | | |0 = CRC calculation controller normal operation. 131 * | | |1 = CRC calculation controller reset. 132 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 133 * |[8] |CCAPRST |CCAP Controller Reset (Write Protect) 134 * | | |Set this bit to 1 will generate a reset signal to the CCAP controller. 135 * | | |User needs to set this bit to 0 to release from the reset state. 136 * | | |0 = CCAP controller normal operation. 137 * | | |1 = CCAP controller reset. 138 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 139 * |[10] |HSUSBDRST |HSUSBD Controller Reset (Write Protect) 140 * | | |Setting this bit to 1 will generate a reset signal to the HSUSBD controller 141 * | | |User needs to set this bit to 0 to release from the reset state. 142 * | | |0 = HSUSBD controller normal operation. 143 * | | |1 = HSUSBD controller reset. 144 * |[12] |CRPTRST |CRYPTO Controller Reset (Write Protect) 145 * | | |Setting this bit to 1 will generate a reset signal to the CRYPTO controller 146 * | | |User needs to set this bit to 0 to release from the reset state. 147 * | | |0 = CRYPTO controller normal operation. 148 * | | |1 = CRYPTO controller reset. 149 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 150 * |[14] |SPIMRST |SPIM Controller Reset 151 * | | |Setting this bit to 1 will generate a reset signal to the SPIM controller 152 * | | |User needs to set this bit to 0 to release from the reset state. 153 * | | |0 = SPIM controller normal operation. 154 * | | |1 = SPIM controller reset. 155 * |[16] |USBHRST |USBH Controller Reset (Write Protect) 156 * | | |Set this bit to 1 will generate a reset signal to the USBH controller 157 * | | |User needs to set this bit to 0 to release from the reset state. 158 * | | |0 = USBH controller normal operation. 159 * | | |1 = USBH controller reset. 160 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 161 * |[17] |SDH1RST |SDHOST1 Controller Reset (Write Protect) 162 * | | |Setting this bit to 1 will generate a reset signal to the SDHOST1 controller 163 * | | |User needs to set this bit to 0 to release from the reset state. 164 * | | |0 = SDHOST1 controller normal operation. 165 * | | |1 = SDHOST1 controller reset. 166 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 167 * @var SYS_T::IPRST1 168 * Offset: 0x0C Peripheral Reset Control Register 1 169 * --------------------------------------------------------------------------------------------------- 170 * |Bits |Field |Descriptions 171 * | :----: | :----: | :---- | 172 * |[1] |GPIORST |GPIO Controller Reset 173 * | | |0 = GPIO controller normal operation. 174 * | | |1 = GPIO controller reset. 175 * |[2] |TMR0RST |Timer0 Controller Reset 176 * | | |0 = Timer0 controller normal operation. 177 * | | |1 = Timer0 controller reset. 178 * |[3] |TMR1RST |Timer1 Controller Reset 179 * | | |0 = Timer1 controller normal operation. 180 * | | |1 = Timer1 controller reset. 181 * |[4] |TMR2RST |Timer2 Controller Reset 182 * | | |0 = Timer2 controller normal operation. 183 * | | |1 = Timer2 controller reset. 184 * |[5] |TMR3RST |Timer3 Controller Reset 185 * | | |0 = Timer3 controller normal operation. 186 * | | |1 = Timer3 controller reset. 187 * |[7] |ACMP01RST |Analog Comparator 0/1 Controller Reset 188 * | | |0 = Analog Comparator 0/1 controller normal operation. 189 * | | |1 = Analog Comparator 0/1 controller reset. 190 * |[8] |I2C0RST |I2C0 Controller Reset 191 * | | |0 = I2C0 controller normal operation. 192 * | | |1 = I2C0 controller reset. 193 * |[9] |I2C1RST |I2C1 Controller Reset 194 * | | |0 = I2C1 controller normal operation. 195 * | | |1 = I2C1 controller reset. 196 * |[10] |I2C2RST |I2C2 Controller Reset 197 * | | |0 = I2C2 controller normal operation. 198 * | | |1 = I2C2 controller reset. 199 * |[12] |QSPI0RST |QSPI0 Controller Reset 200 * | | |0 = QSPI0 controller normal operation. 201 * | | |1 = QSPI0 controller reset. 202 * |[13] |SPI0RST |SPI0 Controller Reset 203 * | | |0 = SPI0 controller normal operation. 204 * | | |1 = SPI0 controller reset. 205 * |[14] |SPI1RST |SPI1 Controller Reset 206 * | | |0 = SPI1 controller normal operation. 207 * | | |1 = SPI1 controller reset. 208 * |[15] |SPI2RST |SPI2 Controller Reset 209 * | | |0 = SPI2 controller normal operation. 210 * | | |1 = SPI2 controller reset. 211 * |[16] |UART0RST |UART0 Controller Reset 212 * | | |0 = UART0 controller normal operation. 213 * | | |1 = UART0 controller reset. 214 * |[17] |UART1RST |UART1 Controller Reset 215 * | | |0 = UART1 controller normal operation. 216 * | | |1 = UART1 controller reset. 217 * |[18] |UART2RST |UART2 Controller Reset 218 * | | |0 = UART2 controller normal operation. 219 * | | |1 = UART2 controller reset. 220 * |[19] |UART3RST |UART3 Controller Reset 221 * | | |0 = UART3 controller normal operation. 222 * | | |1 = UART3 controller reset. 223 * |[20] |UART4RST |UART4 Controller Reset 224 * | | |0 = UART4 controller normal operation. 225 * | | |1 = UART4 controller reset. 226 * |[21] |UART5RST |UART5 Controller Reset 227 * | | |0 = UART5 controller normal operation. 228 * | | |1 = UART5 controller reset. 229 * |[24] |CAN0RST |CAN0 Controller Reset 230 * | | |0 = CAN0 controller normal operation. 231 * | | |1 = CAN0 controller reset. 232 * |[25] |CAN1RST |CAN1 Controller Reset 233 * | | |0 = CAN1 controller normal operation. 234 * | | |1 = CAN1 controller reset. 235 * |[27] |USBDRST |USBD Controller Reset 236 * | | |0 = USBD controller normal operation. 237 * | | |1 = USBD controller reset. 238 * |[28] |EADCRST |EADC Controller Reset 239 * | | |0 = EADC controller normal operation. 240 * | | |1 = EADC controller reset. 241 * |[29] |I2S0RST |I2S0 Controller Reset 242 * | | |0 = I2S0 controller normal operation. 243 * | | |1 = I2S0 controller reset. 244 * @var SYS_T::IPRST2 245 * Offset: 0x10 Peripheral Reset Control Register 2 246 * --------------------------------------------------------------------------------------------------- 247 * |Bits |Field |Descriptions 248 * | :----: | :----: | :---- | 249 * |[0] |SC0RST |SC0 Controller Reset 250 * | | |0 = SC0 controller normal operation. 251 * | | |1 = SC0 controller reset. 252 * |[1] |SC1RST |SC1 Controller Reset 253 * | | |0 = SC1 controller normal operation. 254 * | | |1 = SC1 controller reset. 255 * |[2] |SC2RST |SC2 Controller Reset 256 * | | |0 = SC2 controller normal operation. 257 * | | |1 = SC2 controller reset. 258 * |[6] |SPI3RST |SPI3 Controller Reset 259 * | | |0 = SPI3 controller normal operation. 260 * | | |1 = SPI3 controller reset. 261 * |[8] |USCI0RST |USCI0 Controller Reset 262 * | | |0 = USCI0 controller normal operation. 263 * | | |1 = USCI0 controller reset. 264 * |[9] |USCI1RST |USCI1 Controller Reset 265 * | | |0 = USCI1 controller normal operation. 266 * | | |1 = USCI1 controller reset. 267 * |[12] |DACRST |DAC Controller Reset 268 * | | |0 = DAC controller normal operation. 269 * | | |1 = DAC controller reset. 270 * |[16] |EPWM0RST |EPWM0 Controller Reset 271 * | | |0 = EPWM0 controller normal operation. 272 * | | |1 = EPWM0 controller reset. 273 * |[17] |EPWM1RST |EPWM1 Controller Reset 274 * | | |0 = EPWM1 controller normal operation. 275 * | | |1 = EPWM1 controller reset. 276 * |[18] |BPWM0RST |BPWM0 Controller Reset 277 * | | |0 = BPWM0 controller normal operation. 278 * | | |1 = BPWM0 controller reset. 279 * |[19] |BPWM1RST |BPWM1 Controller Reset 280 * | | |0 = BPWM1 controller normal operation. 281 * | | |1 = BPWM1 controller reset. 282 * |[22] |QEI0RST |QEI0 Controller Reset 283 * | | |0 = QEI0 controller normal operation. 284 * | | |1 = QEI0 controller reset. 285 * |[23] |QEI1RST |QEI1 Controller Reset 286 * | | |0 = QEI1 controller normal operation. 287 * | | |1 = QEI1 controller reset. 288 * |[26] |ECAP0RST |ECAP0 Controller Reset 289 * | | |0 = ECAP0 controller normal operation. 290 * | | |1 = ECAP0 controller reset. 291 * |[27] |ECAP1RST |ECAP1 Controller Reset 292 * | | |0 = ECAP1 controller normal operation. 293 * | | |1 = ECAP1 controller reset. 294 * |[28] |CAN2RST |CAN2 Controller Reset 295 * | | |0 = CAN2 controller normal operation. 296 * | | |1 = CAN2 controller reset. 297 * |[30] |OPARST |OP Amplifier (OPA) Controller Reset 298 * | | |0 = OPA controller normal operation. 299 * | | |1 = OPA controller reset. 300 * @var SYS_T::BODCTL 301 * Offset: 0x18 Brown-Out Detector Control Register 302 * --------------------------------------------------------------------------------------------------- 303 * |Bits |Field |Descriptions 304 * | :----: | :----: | :---- | 305 * |[0] |BODEN |Brown-out Detector Enable Bit (Write Protect) 306 * | | |The default value is set by flash controller user configuration register CBODEN(CONFIG0 [19]). 307 * | | |0 = Brown-out Detector function Disabled. 308 * | | |1 = Brown-out Detector function Enabled. 309 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 310 * |[3] |BODRSTEN |Brown-out Reset Enable Bit (Write Protect) 311 * | | |The default value is set by flash controller user configuration register CBORST(CONFIG0[20]) bit . 312 * | | |0 = Brown-out INTERRUPT function Enabled. 313 * | | |1 = Brown-out RESET function Enabled. 314 * | | |Note1: 315 * | | |While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high). 316 * | | |While the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low), BOD will assert an interrupt if BODOUT is high 317 * | | |BOD interrupt will keep till to the BODEN set to 0 318 * | | |BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BODEN low). 319 * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register. 320 * |[4] |BODIF |Brown-out Detector Interrupt Flag 321 * | | |0 = Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BODVL setting. 322 * | | |1 = When Brown-out Detector detects the VDD is dropped down through the voltage of BODVL setting or the VDD is raised up through the voltage of BODVL setting, this bit is set to 1 and the brown-out interrupt is requested if brown-out interrupt is enabled. 323 * | | |Note: Write 1 to clear this bit to 0. 324 * |[5] |BODLPM |Brown-out Detector Low Power Mode (Write Protect) 325 * | | |0 = BOD operate in normal mode (default). 326 * | | |1 = BOD Low Power mode Enabled. 327 * | | |Note1: The BOD consumes about 100uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response. 328 * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register. 329 * |[6] |BODOUT |Brown-out Detector Output Status 330 * | | |0 = Brown-out Detector output status is 0. 331 * | | |It means the detected voltage is higher than BODVL setting or BODEN is 0. 332 * | | |1 = Brown-out Detector output status is 1. 333 * | | |It means the detected voltage is lower than BODVL setting 334 * | | |If the BODEN is 0, BOD function disabled , this bit always responds 0000. 335 * |[7] |LVREN |Low Voltage Reset Enable Bit (Write Protect) 336 * | | |The LVR function resets the chip when the input power voltage is lower than LVR circuit setting 337 * | | |LVR function is enabled by default. 338 * | | |0 = Low Voltage Reset function Disabled. 339 * | | |1 = Low Voltage Reset function Enabled. 340 * | | |Note1: After enabling the bit, the LVR function will be active with 100us delay for LVR output stable (default). 341 * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register. 342 * |[10:8] |BODDGSEL |Brown-out Detector Output De-glitch Time Select (Write Protect) 343 * | | |000 = BOD output is sampled by RC10K clock. 344 * | | |001 = 4 system clock (HCLK). 345 * | | |010 = 8 system clock (HCLK). 346 * | | |011 = 16 system clock (HCLK). 347 * | | |100 = 32 system clock (HCLK). 348 * | | |101 = 64 system clock (HCLK). 349 * | | |110 = 128 system clock (HCLK). 350 * | | |111 = 256 system clock (HCLK). 351 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 352 * |[14:12] |LVRDGSEL |LVR Output De-glitch Time Select (Write Protect) 353 * | | |000 = Without de-glitch function. 354 * | | |001 = 4 system clock (HCLK). 355 * | | |010 = 8 system clock (HCLK). 356 * | | |011 = 16 system clock (HCLK). 357 * | | |100 = 32 system clock (HCLK). 358 * | | |101 = 64 system clock (HCLK). 359 * | | |110 = 128 system clock (HCLK). 360 * | | |111 = 256 system clock (HCLK). 361 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 362 * |[18:16] |BODVL |Brown-out Detector Threshold Voltage Selection (Write Protect) 363 * | | |The default value is set by flash controller user configuration register CBOV (CONFIG0 [23:21]). 364 * | | |000 = Brown-Out Detector threshold voltage is 1.6V. 365 * | | |001 = Brown-Out Detector threshold voltage is 1.8V. 366 * | | |010 = Brown-Out Detector threshold voltage is 2.0V. 367 * | | |011 = Brown-Out Detector threshold voltage is 2.2V. 368 * | | |100 = Brown-Out Detector threshold voltage is 2.4V. 369 * | | |101 = Brown-Out Detector threshold voltage is 2.6V. 370 * | | |110 = Brown-Out Detector threshold voltage is 2.8V. 371 * | | |111 = Brown-Out Detector threshold voltage is 3.0V. 372 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 373 * @var SYS_T::IVSCTL 374 * Offset: 0x1C Internal Voltage Source Control Register 375 * --------------------------------------------------------------------------------------------------- 376 * |Bits |Field |Descriptions 377 * | :----: | :----: | :---- | 378 * |[0] |VTEMPEN |Temperature Sensor Enable Bit 379 * | | |This bit is used to enable/disable temperature sensor function. 380 * | | |0 = Temperature sensor function Disabled (default). 381 * | | |1 = Temperature sensor function Enabled. 382 * | | |Note: After this bit is set to 1, the value of temperature sensor output can be obtained through GPC.9. 383 * |[1] |VBATUGEN |VBAT Unity Gain Buffer Enable Bit 384 * | | |This bit is used to enable/disable VBAT unity gain buffer function. 385 * | | |0 = VBAT unity gain buffer function Disabled (default). 386 * | | |1 = VBAT unity gain buffer function Enabled. 387 * | | |Note: After this bit is set to 1, the value of VBAT unity gain buffer output voltage can be obtained from ADC conversion result 388 * @var SYS_T::PORCTL 389 * Offset: 0x24 Power-On-Reset Controller Register 390 * --------------------------------------------------------------------------------------------------- 391 * |Bits |Field |Descriptions 392 * | :----: | :----: | :---- | 393 * |[15:0] |POROFF |Power-on Reset Enable Bit (Write Protect) 394 * | | |When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again 395 * | | |User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field. 396 * | | |The POR function will be active again when this field is set to another value or chip is reset by other reset source, including: 397 * | | |nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function. 398 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 399 * @var SYS_T::VREFCTL 400 * Offset: 0x28 VREF Control Register 401 * --------------------------------------------------------------------------------------------------- 402 * |Bits |Field |Descriptions 403 * | :----: | :----: | :---- | 404 * |[4:0] |VREFCTL |VREF Control Bits (Write Protect) 405 * | | |00000 = VREF is from external pin. 406 * | | |00011 = VREF is internal 1.6V. 407 * | | |00111 = VREF is internal 2.0V. 408 * | | |01011 = VREF is internal 2.5V. 409 * | | |01111 = VREF is internal 3.0V. 410 * | | |Others = Reserved. 411 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 412 * |[7:6] |PRELOAD_SEL|Pre-load Timing Selection. 413 * | | |00 = pre-load time is 60us for 0.1uF Capacitor. 414 * | | |01 = pre-load time is 310us for 1uF Capacitor. 415 * | | |10 = pre-load time is 1270us for 4.7uF Capacitor. 416 * | | |11 = pre-load time is 2650us for 10uF Capacitor. 417 * @var SYS_T::USBPHY 418 * Offset: 0x2C USB PHY Control Register 419 * --------------------------------------------------------------------------------------------------- 420 * |Bits |Field |Descriptions 421 * | :----: | :----: | :---- | 422 * |[1:0] |USBROLE |USB Role Option (Write Protect) 423 * | | |These two bits are used to select the role of USB. 424 * | | |00 = Standard USB Device mode. 425 * | | |01 = Standard USB Host mode. 426 * | | |10 = ID dependent mode. 427 * | | |11 = Reserved. 428 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 429 * |[2] |SBO |Note: This bit must always be kept 1. If set to 0, the result is unpredictable 430 * |[8] |USBEN |USB PHY Enable (Write Protect) 431 * | | |This bit is used to enable/disable USB PHY. 432 * | | |0 = USB PHY Disabled. 433 * | | |1 = USB PHY Enabled. 434 * |[17:16] |HSUSBROLE |HSUSB Role Option (Write Protect) 435 * | | |These two bits are used to select the role of HSUSB 436 * | | |00 = Standard HSUSB Device mode. 437 * | | |01 = Standard HSUSB Host mode. 438 * | | |10 = ID dependent mode. 439 * | | |11 = Reserved. 440 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 441 * |[24] |HSUSBEN |HSUSB PHY Enable (Write Protect) 442 * | | |This bit is used to enable/disable HSUSB PHY. 443 * | | |0 = HSUSB PHY Disabled. 444 * | | |1 = HSUSB PHY Enabled. 445 * |[25] |HSUSBACT |HSUSB PHY Active Control 446 * | | |This bit is used to control HSUSB PHY at reset state or active state. 447 * | | |0 = HSUSB PHY at reset state. 448 * | | |1 = HSUSB PHY at active state. 449 * | | |Note: After set HSUSBEN (SYS_USBPHY[24]) to enable HSUSB PHY, user should keep HSUSB PHY at reset mode at lease 10uS before changing to active mode. 450 * @var SYS_T::GPA_MFPL 451 * Offset: 0x30 GPIOA Low Byte Multiple Function Control Register 452 * --------------------------------------------------------------------------------------------------- 453 * |Bits |Field |Descriptions 454 * | :----: | :----: | :---- | 455 * |[3:0] |PA0MFP |PA.0 Multi-function Pin Selection 456 * |[7:4] |PA1MFP |PA.1 Multi-function Pin Selection 457 * |[11:8] |PA2MFP |PA.2 Multi-function Pin Selection 458 * |[15:12] |PA3MFP |PA.3 Multi-function Pin Selection 459 * |[19:16] |PA4MFP |PA.4 Multi-function Pin Selection 460 * |[23:20] |PA5MFP |PA.5 Multi-function Pin Selection 461 * |[27:24] |PA6MFP |PA.6 Multi-function Pin Selection 462 * |[31:28] |PA7MFP |PA.7 Multi-function Pin Selection 463 * @var SYS_T::GPA_MFPH 464 * Offset: 0x34 GPIOA High Byte Multiple Function Control Register 465 * --------------------------------------------------------------------------------------------------- 466 * |Bits |Field |Descriptions 467 * | :----: | :----: | :---- | 468 * |[3:0] |PA8MFP |PA.8 Multi-function Pin Selection 469 * |[7:4] |PA9MFP |PA.9 Multi-function Pin Selection 470 * |[11:8] |PA10MFP |PA.10 Multi-function Pin Selection 471 * |[15:12] |PA11MFP |PA.11 Multi-function Pin Selection 472 * |[19:16] |PA12MFP |PA.12 Multi-function Pin Selection 473 * |[23:20] |PA13MFP |PA.13 Multi-function Pin Selection 474 * |[27:24] |PA14MFP |PA.14 Multi-function Pin Selection 475 * |[31:28] |PA15MFP |PA.15 Multi-function Pin Selection 476 * @var SYS_T::GPB_MFPL 477 * Offset: 0x38 GPIOB Low Byte Multiple Function Control Register 478 * --------------------------------------------------------------------------------------------------- 479 * |Bits |Field |Descriptions 480 * | :----: | :----: | :---- | 481 * |[3:0] |PB0MFP |PB.0 Multi-function Pin Selection 482 * |[7:4] |PB1MFP |PB.1 Multi-function Pin Selection 483 * |[11:8] |PB2MFP |PB.2 Multi-function Pin Selection 484 * |[15:12] |PB3MFP |PB.3 Multi-function Pin Selection 485 * |[19:16] |PB4MFP |PB.4 Multi-function Pin Selection 486 * |[23:20] |PB5MFP |PB.5 Multi-function Pin Selection 487 * |[27:24] |PB6MFP |PB.6 Multi-function Pin Selection 488 * |[31:28] |PB7MFP |PB.7 Multi-function Pin Selection 489 * @var SYS_T::GPB_MFPH 490 * Offset: 0x3C GPIOB High Byte Multiple Function Control Register 491 * --------------------------------------------------------------------------------------------------- 492 * |Bits |Field |Descriptions 493 * | :----: | :----: | :---- | 494 * |[3:0] |PB8MFP |PB.8 Multi-function Pin Selection 495 * |[7:4] |PB9MFP |PB.9 Multi-function Pin Selection 496 * |[11:8] |PB10MFP |PB.10 Multi-function Pin Selection 497 * |[15:12] |PB11MFP |PB.11 Multi-function Pin Selection 498 * |[19:16] |PB12MFP |PB.12 Multi-function Pin Selection 499 * |[23:20] |PB13MFP |PB.13 Multi-function Pin Selection 500 * |[27:24] |PB14MFP |PB.14 Multi-function Pin Selection 501 * |[31:28] |PB15MFP |PB.15 Multi-function Pin Selection 502 * @var SYS_T::GPC_MFPL 503 * Offset: 0x40 GPIOC Low Byte Multiple Function Control Register 504 * --------------------------------------------------------------------------------------------------- 505 * |Bits |Field |Descriptions 506 * | :----: | :----: | :---- | 507 * |[3:0] |PC0MFP |PC.0 Multi-function Pin Selection 508 * |[7:4] |PC1MFP |PC.1 Multi-function Pin Selection 509 * |[11:8] |PC2MFP |PC.2 Multi-function Pin Selection 510 * |[15:12] |PC3MFP |PC.3 Multi-function Pin Selection 511 * |[19:16] |PC4MFP |PC.4 Multi-function Pin Selection 512 * |[23:20] |PC5MFP |PC.5 Multi-function Pin Selection 513 * |[27:24] |PC6MFP |PC.6 Multi-function Pin Selection 514 * |[31:28] |PC7MFP |PC.7 Multi-function Pin Selection 515 * @var SYS_T::GPC_MFPH 516 * Offset: 0x44 GPIOC High Byte Multiple Function Control Register 517 * --------------------------------------------------------------------------------------------------- 518 * |Bits |Field |Descriptions 519 * | :----: | :----: | :---- | 520 * |[3:0] |PC8MFP |PC.8 Multi-function Pin Selection 521 * |[7:4] |PC9MFP |PC.9 Multi-function Pin Selection 522 * |[11:8] |PC10MFP |PC.10 Multi-function Pin Selection 523 * |[15:12] |PC11MFP |PC.11 Multi-function Pin Selection 524 * |[19:16] |PC12MFP |PC.12 Multi-function Pin Selection 525 * |[23:20] |PC13MFP |PC.13 Multi-function Pin Selection 526 * |[27:24] |PC14MFP |PC.14 Multi-function Pin Selection 527 * |[31:28] |PC15MFP |PC.15 Multi-function Pin Selection 528 * @var SYS_T::GPD_MFPL 529 * Offset: 0x48 GPIOD Low Byte Multiple Function Control Register 530 * --------------------------------------------------------------------------------------------------- 531 * |Bits |Field |Descriptions 532 * | :----: | :----: | :---- | 533 * |[3:0] |PD0MFP |PD.0 Multi-function Pin Selection 534 * |[7:4] |PD1MFP |PD.1 Multi-function Pin Selection 535 * |[11:8] |PD2MFP |PD.2 Multi-function Pin Selection 536 * |[15:12] |PD3MFP |PD.3 Multi-function Pin Selection 537 * |[19:16] |PD4MFP |PD.4 Multi-function Pin Selection 538 * |[23:20] |PD5MFP |PD.5 Multi-function Pin Selection 539 * |[27:24] |PD6MFP |PD.6 Multi-function Pin Selection 540 * |[31:28] |PD7MFP |PD.7 Multi-function Pin Selection 541 * @var SYS_T::GPD_MFPH 542 * Offset: 0x4C GPIOD High Byte Multiple Function Control Register 543 * --------------------------------------------------------------------------------------------------- 544 * |Bits |Field |Descriptions 545 * | :----: | :----: | :---- | 546 * |[3:0] |PD8MFP |PD.8 Multi-function Pin Selection 547 * |[7:4] |PD9MFP |PD.9 Multi-function Pin Selection 548 * |[11:8] |PD10MFP |PD.10 Multi-function Pin Selection 549 * |[15:12] |PD11MFP |PD.11 Multi-function Pin Selection 550 * |[19:16] |PD12MFP |PD.12 Multi-function Pin Selection 551 * |[23:20] |PD13MFP |PD.13 Multi-function Pin Selection 552 * |[27:24] |PD14MFP |PD.14 Multi-function Pin Selection 553 * |[31:28] |PD15MFP |PD.15 Multi-function Pin Selection 554 * @var SYS_T::GPE_MFPL 555 * Offset: 0x50 GPIOE Low Byte Multiple Function Control Register 556 * --------------------------------------------------------------------------------------------------- 557 * |Bits |Field |Descriptions 558 * | :----: | :----: | :---- | 559 * |[3:0] |PE0MFP |PE.0 Multi-function Pin Selection 560 * |[7:4] |PE1MFP |PE.1 Multi-function Pin Selection 561 * |[11:8] |PE2MFP |PE.2 Multi-function Pin Selection 562 * |[15:12] |PE3MFP |PE.3 Multi-function Pin Selection 563 * |[19:16] |PE4MFP |PE.4 Multi-function Pin Selection 564 * |[23:20] |PE5MFP |PE.5 Multi-function Pin Selection 565 * |[27:24] |PE6MFP |PE.6 Multi-function Pin Selection 566 * |[31:28] |PE7MFP |PE.7 Multi-function Pin Selection 567 * @var SYS_T::GPE_MFPH 568 * Offset: 0x54 GPIOE High Byte Multiple Function Control Register 569 * --------------------------------------------------------------------------------------------------- 570 * |Bits |Field |Descriptions 571 * | :----: | :----: | :---- | 572 * |[3:0] |PE8MFP |PE.8 Multi-function Pin Selection 573 * |[7:4] |PE9MFP |PE.9 Multi-function Pin Selection 574 * |[11:8] |PE10MFP |PE.10 Multi-function Pin Selection 575 * |[15:12] |PE11MFP |PE.11 Multi-function Pin Selection 576 * |[19:16] |PE12MFP |PE.12 Multi-function Pin Selection 577 * |[23:20] |PE13MFP |PE.13 Multi-function Pin Selection 578 * |[27:24] |PE14MFP |PE.14 Multi-function Pin Selection 579 * |[31:28] |PE15MFP |PE.15 Multi-function Pin Selection 580 * @var SYS_T::GPF_MFPL 581 * Offset: 0x58 GPIOF Low Byte Multiple Function Control Register 582 * --------------------------------------------------------------------------------------------------- 583 * |Bits |Field |Descriptions 584 * | :----: | :----: | :---- | 585 * |[3:0] |PF0MFP |PF.0 Multi-function Pin Selection 586 * |[7:4] |PF1MFP |PF.1 Multi-function Pin Selection 587 * |[11:8] |PF2MFP |PF.2 Multi-function Pin Selection 588 * |[15:12] |PF3MFP |PF.3 Multi-function Pin Selection 589 * |[19:16] |PF4MFP |PF.4 Multi-function Pin Selection 590 * |[23:20] |PF5MFP |PF.5 Multi-function Pin Selection 591 * |[27:24] |PF6MFP |PF.6 Multi-function Pin Selection 592 * |[31:28] |PF7MFP |PF.7 Multi-function Pin Selection 593 * @var SYS_T::GPF_MFPH 594 * Offset: 0x5C GPIOF High Byte Multiple Function Control Register 595 * --------------------------------------------------------------------------------------------------- 596 * |Bits |Field |Descriptions 597 * | :----: | :----: | :---- | 598 * |[3:0] |PF8MFP |PF.8 Multi-function Pin Selection 599 * |[7:4] |PF9MFP |PF.9 Multi-function Pin Selection 600 * |[11:8] |PF10MFP |PF.10 Multi-function Pin Selection 601 * |[15:12] |PF11MFP |PF.11 Multi-function Pin Selection 602 * |[19:16] |PF12MFP |PF.12 Multi-function Pin Selection 603 * |[23:20] |PF13MFP |PF.13 Multi-function Pin Selection 604 * |[27:24] |PF14MFP |PF.14 Multi-function Pin Selection 605 * |[31:28] |PF15MFP |PF.15 Multi-function Pin Selection 606 * @var SYS_T::GPG_MFPL 607 * Offset: 0x60 GPIOG Low Byte Multiple Function Control Register 608 * --------------------------------------------------------------------------------------------------- 609 * |Bits |Field |Descriptions 610 * | :----: | :----: | :---- | 611 * |[3:0] |PG0MFP |PG.0 Multi-function Pin Selection 612 * |[7:4] |PG1MFP |PG.1 Multi-function Pin Selection 613 * |[11:8] |PG2MFP |PG.2 Multi-function Pin Selection 614 * |[15:12] |PG3MFP |PG.3 Multi-function Pin Selection 615 * |[19:16] |PG4MFP |PG.4 Multi-function Pin Selection 616 * |[23:20] |PG5MFP |PG.5 Multi-function Pin Selection 617 * |[27:24] |PG6MFP |PG.6 Multi-function Pin Selection 618 * |[31:28] |PG7MFP |PG.7 Multi-function Pin Selection 619 * @var SYS_T::GPG_MFPH 620 * Offset: 0x64 GPIOG High Byte Multiple Function Control Register 621 * --------------------------------------------------------------------------------------------------- 622 * |Bits |Field |Descriptions 623 * | :----: | :----: | :---- | 624 * |[3:0] |PG8MFP |PG.8 Multi-function Pin Selection 625 * |[7:4] |PG9MFP |PG.9 Multi-function Pin Selection 626 * |[11:8] |PG10MFP |PG.10 Multi-function Pin Selection 627 * |[15:12] |PG11MFP |PG.11 Multi-function Pin Selection 628 * |[19:16] |PG12MFP |PG.12 Multi-function Pin Selection 629 * |[23:20] |PG13MFP |PG.13 Multi-function Pin Selection 630 * |[27:24] |PG14MFP |PG.14 Multi-function Pin Selection 631 * |[31:28] |PG15MFP |PG.15 Multi-function Pin Selection 632 * @var SYS_T::GPH_MFPL 633 * Offset: 0x68 GPIOH Low Byte Multiple Function Control Register 634 * --------------------------------------------------------------------------------------------------- 635 * |Bits |Field |Descriptions 636 * | :----: | :----: | :---- | 637 * |[3:0] |PH0MFP |PH.0 Multi-function Pin Selection 638 * |[7:4] |PH1MFP |PH.1 Multi-function Pin Selection 639 * |[11:8] |PH2MFP |PH.2 Multi-function Pin Selection 640 * |[15:12] |PH3MFP |PH.3 Multi-function Pin Selection 641 * |[19:16] |PH4MFP |PH.4 Multi-function Pin Selection 642 * |[23:20] |PH5MFP |PH.5 Multi-function Pin Selection 643 * |[27:24] |PH6MFP |PH.6 Multi-function Pin Selection 644 * |[31:28] |PH7MFP |PH.7 Multi-function Pin Selection 645 * @var SYS_T::GPH_MFPH 646 * Offset: 0x6C GPIOH High Byte Multiple Function Control Register 647 * --------------------------------------------------------------------------------------------------- 648 * |Bits |Field |Descriptions 649 * | :----: | :----: | :---- | 650 * |[3:0] |PH8MFP |PH.8 Multi-function Pin Selection 651 * |[7:4] |PH9MFP |PH.9 Multi-function Pin Selection 652 * |[11:8] |PH10MFP |PH.10 Multi-function Pin Selection 653 * |[15:12] |PH11MFP |PH.11 Multi-function Pin Selection 654 * |[19:16] |PH12MFP |PH.12 Multi-function Pin Selection 655 * |[23:20] |PH13MFP |PH.13 Multi-function Pin Selection 656 * |[27:24] |PH14MFP |PH.14 Multi-function Pin Selection 657 * |[31:28] |PH15MFP |PH.15 Multi-function Pin Selection 658 * @var SYS_T::GPA_MFOS 659 * Offset: 0x80 GPIOA Multiple Function Output Select Register 660 * --------------------------------------------------------------------------------------------------- 661 * |Bits |Field |Descriptions 662 * | :----: | :----: | :---- | 663 * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 664 * | | |This bit used to select multiple function pin output mode type for Px.n pin 665 * | | |0 = Multiple function pin output mode type is Push-pull mode. 666 * | | |1 = Multiple function pin output mode type is Open-drain mode. 667 * | | |Note: 668 * | | |Max. n=15 for port A/B/E/G. 669 * | | |Max. n=14 for port C/D. 670 * | | |Max. n=11 for port F/H. 671 * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 672 * | | |This bit used to select multiple function pin output mode type for Px.n pin 673 * | | |0 = Multiple function pin output mode type is Push-pull mode. 674 * | | |1 = Multiple function pin output mode type is Open-drain mode. 675 * | | |Note: 676 * | | |Max. n=15 for port A/B/E/G. 677 * | | |Max. n=14 for port C/D. 678 * | | |Max. n=11 for port F/H. 679 * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 680 * | | |This bit used to select multiple function pin output mode type for Px.n pin 681 * | | |0 = Multiple function pin output mode type is Push-pull mode. 682 * | | |1 = Multiple function pin output mode type is Open-drain mode. 683 * | | |Note: 684 * | | |Max. n=15 for port A/B/E/G. 685 * | | |Max. n=14 for port C/D. 686 * | | |Max. n=11 for port F/H. 687 * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 688 * | | |This bit used to select multiple function pin output mode type for Px.n pin 689 * | | |0 = Multiple function pin output mode type is Push-pull mode. 690 * | | |1 = Multiple function pin output mode type is Open-drain mode. 691 * | | |Note: 692 * | | |Max. n=15 for port A/B/E/G. 693 * | | |Max. n=14 for port C/D. 694 * | | |Max. n=11 for port F/H. 695 * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 696 * | | |This bit used to select multiple function pin output mode type for Px.n pin 697 * | | |0 = Multiple function pin output mode type is Push-pull mode. 698 * | | |1 = Multiple function pin output mode type is Open-drain mode. 699 * | | |Note: 700 * | | |Max. n=15 for port A/B/E/G. 701 * | | |Max. n=14 for port C/D. 702 * | | |Max. n=11 for port F/H. 703 * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 704 * | | |This bit used to select multiple function pin output mode type for Px.n pin 705 * | | |0 = Multiple function pin output mode type is Push-pull mode. 706 * | | |1 = Multiple function pin output mode type is Open-drain mode. 707 * | | |Note: 708 * | | |Max. n=15 for port A/B/E/G. 709 * | | |Max. n=14 for port C/D. 710 * | | |Max. n=11 for port F/H. 711 * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 712 * | | |This bit used to select multiple function pin output mode type for Px.n pin 713 * | | |0 = Multiple function pin output mode type is Push-pull mode. 714 * | | |1 = Multiple function pin output mode type is Open-drain mode. 715 * | | |Note: 716 * | | |Max. n=15 for port A/B/E/G. 717 * | | |Max. n=14 for port C/D. 718 * | | |Max. n=11 for port F/H. 719 * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 720 * | | |This bit used to select multiple function pin output mode type for Px.n pin 721 * | | |0 = Multiple function pin output mode type is Push-pull mode. 722 * | | |1 = Multiple function pin output mode type is Open-drain mode. 723 * | | |Note: 724 * | | |Max. n=15 for port A/B/E/G. 725 * | | |Max. n=14 for port C/D. 726 * | | |Max. n=11 for port F/H. 727 * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 728 * | | |This bit used to select multiple function pin output mode type for Px.n pin 729 * | | |0 = Multiple function pin output mode type is Push-pull mode. 730 * | | |1 = Multiple function pin output mode type is Open-drain mode. 731 * | | |Note: 732 * | | |Max. n=15 for port A/B/E/G. 733 * | | |Max. n=14 for port C/D. 734 * | | |Max. n=11 for port F/H. 735 * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 736 * | | |This bit used to select multiple function pin output mode type for Px.n pin 737 * | | |0 = Multiple function pin output mode type is Push-pull mode. 738 * | | |1 = Multiple function pin output mode type is Open-drain mode. 739 * | | |Note: 740 * | | |Max. n=15 for port A/B/E/G. 741 * | | |Max. n=14 for port C/D. 742 * | | |Max. n=11 for port F/H. 743 * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 744 * | | |This bit used to select multiple function pin output mode type for Px.n pin 745 * | | |0 = Multiple function pin output mode type is Push-pull mode. 746 * | | |1 = Multiple function pin output mode type is Open-drain mode. 747 * | | |Note: 748 * | | |Max. n=15 for port A/B/E/G. 749 * | | |Max. n=14 for port C/D. 750 * | | |Max. n=11 for port F/H. 751 * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 752 * | | |This bit used to select multiple function pin output mode type for Px.n pin 753 * | | |0 = Multiple function pin output mode type is Push-pull mode. 754 * | | |1 = Multiple function pin output mode type is Open-drain mode. 755 * | | |Note: 756 * | | |Max. n=15 for port A/B/E/G. 757 * | | |Max. n=14 for port C/D. 758 * | | |Max. n=11 for port F/H. 759 * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 760 * | | |This bit used to select multiple function pin output mode type for Px.n pin 761 * | | |0 = Multiple function pin output mode type is Push-pull mode. 762 * | | |1 = Multiple function pin output mode type is Open-drain mode. 763 * | | |Note: 764 * | | |Max. n=15 for port A/B/E/G. 765 * | | |Max. n=14 for port C/D. 766 * | | |Max. n=11 for port F/H. 767 * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 768 * | | |This bit used to select multiple function pin output mode type for Px.n pin 769 * | | |0 = Multiple function pin output mode type is Push-pull mode. 770 * | | |1 = Multiple function pin output mode type is Open-drain mode. 771 * | | |Note: 772 * | | |Max. n=15 for port A/B/E/G. 773 * | | |Max. n=14 for port C/D. 774 * | | |Max. n=11 for port F/H. 775 * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 776 * | | |This bit used to select multiple function pin output mode type for Px.n pin 777 * | | |0 = Multiple function pin output mode type is Push-pull mode. 778 * | | |1 = Multiple function pin output mode type is Open-drain mode. 779 * | | |Note: 780 * | | |Max. n=15 for port A/B/E/G. 781 * | | |Max. n=14 for port C/D. 782 * | | |Max. n=11 for port F/H. 783 * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 784 * | | |This bit used to select multiple function pin output mode type for Px.n pin 785 * | | |0 = Multiple function pin output mode type is Push-pull mode. 786 * | | |1 = Multiple function pin output mode type is Open-drain mode. 787 * | | |Note: 788 * | | |Max. n=15 for port A/B/E/G. 789 * | | |Max. n=14 for port C/D. 790 * | | |Max. n=11 for port F/H. 791 * @var SYS_T::GPB_MFOS 792 * Offset: 0x84 GPIOB Multiple Function Output Select Register 793 * --------------------------------------------------------------------------------------------------- 794 * |Bits |Field |Descriptions 795 * | :----: | :----: | :---- | 796 * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 797 * | | |This bit used to select multiple function pin output mode type for Px.n pin 798 * | | |0 = Multiple function pin output mode type is Push-pull mode. 799 * | | |1 = Multiple function pin output mode type is Open-drain mode. 800 * | | |Note: 801 * | | |Max. n=15 for port A/B/E/G. 802 * | | |Max. n=14 for port C/D. 803 * | | |Max. n=11 for port F/H. 804 * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 805 * | | |This bit used to select multiple function pin output mode type for Px.n pin 806 * | | |0 = Multiple function pin output mode type is Push-pull mode. 807 * | | |1 = Multiple function pin output mode type is Open-drain mode. 808 * | | |Note: 809 * | | |Max. n=15 for port A/B/E/G. 810 * | | |Max. n=14 for port C/D. 811 * | | |Max. n=11 for port F/H. 812 * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 813 * | | |This bit used to select multiple function pin output mode type for Px.n pin 814 * | | |0 = Multiple function pin output mode type is Push-pull mode. 815 * | | |1 = Multiple function pin output mode type is Open-drain mode. 816 * | | |Note: 817 * | | |Max. n=15 for port A/B/E/G. 818 * | | |Max. n=14 for port C/D. 819 * | | |Max. n=11 for port F/H. 820 * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 821 * | | |This bit used to select multiple function pin output mode type for Px.n pin 822 * | | |0 = Multiple function pin output mode type is Push-pull mode. 823 * | | |1 = Multiple function pin output mode type is Open-drain mode. 824 * | | |Note: 825 * | | |Max. n=15 for port A/B/E/G. 826 * | | |Max. n=14 for port C/D. 827 * | | |Max. n=11 for port F/H. 828 * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 829 * | | |This bit used to select multiple function pin output mode type for Px.n pin 830 * | | |0 = Multiple function pin output mode type is Push-pull mode. 831 * | | |1 = Multiple function pin output mode type is Open-drain mode. 832 * | | |Note: 833 * | | |Max. n=15 for port A/B/E/G. 834 * | | |Max. n=14 for port C/D. 835 * | | |Max. n=11 for port F/H. 836 * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 837 * | | |This bit used to select multiple function pin output mode type for Px.n pin 838 * | | |0 = Multiple function pin output mode type is Push-pull mode. 839 * | | |1 = Multiple function pin output mode type is Open-drain mode. 840 * | | |Note: 841 * | | |Max. n=15 for port A/B/E/G. 842 * | | |Max. n=14 for port C/D. 843 * | | |Max. n=11 for port F/H. 844 * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 845 * | | |This bit used to select multiple function pin output mode type for Px.n pin 846 * | | |0 = Multiple function pin output mode type is Push-pull mode. 847 * | | |1 = Multiple function pin output mode type is Open-drain mode. 848 * | | |Note: 849 * | | |Max. n=15 for port A/B/E/G. 850 * | | |Max. n=14 for port C/D. 851 * | | |Max. n=11 for port F/H. 852 * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 853 * | | |This bit used to select multiple function pin output mode type for Px.n pin 854 * | | |0 = Multiple function pin output mode type is Push-pull mode. 855 * | | |1 = Multiple function pin output mode type is Open-drain mode. 856 * | | |Note: 857 * | | |Max. n=15 for port A/B/E/G. 858 * | | |Max. n=14 for port C/D. 859 * | | |Max. n=11 for port F/H. 860 * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 861 * | | |This bit used to select multiple function pin output mode type for Px.n pin 862 * | | |0 = Multiple function pin output mode type is Push-pull mode. 863 * | | |1 = Multiple function pin output mode type is Open-drain mode. 864 * | | |Note: 865 * | | |Max. n=15 for port A/B/E/G. 866 * | | |Max. n=14 for port C/D. 867 * | | |Max. n=11 for port F/H. 868 * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 869 * | | |This bit used to select multiple function pin output mode type for Px.n pin 870 * | | |0 = Multiple function pin output mode type is Push-pull mode. 871 * | | |1 = Multiple function pin output mode type is Open-drain mode. 872 * | | |Note: 873 * | | |Max. n=15 for port A/B/E/G. 874 * | | |Max. n=14 for port C/D. 875 * | | |Max. n=11 for port F/H. 876 * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 877 * | | |This bit used to select multiple function pin output mode type for Px.n pin 878 * | | |0 = Multiple function pin output mode type is Push-pull mode. 879 * | | |1 = Multiple function pin output mode type is Open-drain mode. 880 * | | |Note: 881 * | | |Max. n=15 for port A/B/E/G. 882 * | | |Max. n=14 for port C/D. 883 * | | |Max. n=11 for port F/H. 884 * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 885 * | | |This bit used to select multiple function pin output mode type for Px.n pin 886 * | | |0 = Multiple function pin output mode type is Push-pull mode. 887 * | | |1 = Multiple function pin output mode type is Open-drain mode. 888 * | | |Note: 889 * | | |Max. n=15 for port A/B/E/G. 890 * | | |Max. n=14 for port C/D. 891 * | | |Max. n=11 for port F/H. 892 * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 893 * | | |This bit used to select multiple function pin output mode type for Px.n pin 894 * | | |0 = Multiple function pin output mode type is Push-pull mode. 895 * | | |1 = Multiple function pin output mode type is Open-drain mode. 896 * | | |Note: 897 * | | |Max. n=15 for port A/B/E/G. 898 * | | |Max. n=14 for port C/D. 899 * | | |Max. n=11 for port F/H. 900 * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 901 * | | |This bit used to select multiple function pin output mode type for Px.n pin 902 * | | |0 = Multiple function pin output mode type is Push-pull mode. 903 * | | |1 = Multiple function pin output mode type is Open-drain mode. 904 * | | |Note: 905 * | | |Max. n=15 for port A/B/E/G. 906 * | | |Max. n=14 for port C/D. 907 * | | |Max. n=11 for port F/H. 908 * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 909 * | | |This bit used to select multiple function pin output mode type for Px.n pin 910 * | | |0 = Multiple function pin output mode type is Push-pull mode. 911 * | | |1 = Multiple function pin output mode type is Open-drain mode. 912 * | | |Note: 913 * | | |Max. n=15 for port A/B/E/G. 914 * | | |Max. n=14 for port C/D. 915 * | | |Max. n=11 for port F/H. 916 * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 917 * | | |This bit used to select multiple function pin output mode type for Px.n pin 918 * | | |0 = Multiple function pin output mode type is Push-pull mode. 919 * | | |1 = Multiple function pin output mode type is Open-drain mode. 920 * | | |Note: 921 * | | |Max. n=15 for port A/B/E/G. 922 * | | |Max. n=14 for port C/D. 923 * | | |Max. n=11 for port F/H. 924 * @var SYS_T::GPC_MFOS 925 * Offset: 0x88 GPIOC Multiple Function Output Select Register 926 * --------------------------------------------------------------------------------------------------- 927 * |Bits |Field |Descriptions 928 * | :----: | :----: | :---- | 929 * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 930 * | | |This bit used to select multiple function pin output mode type for Px.n pin 931 * | | |0 = Multiple function pin output mode type is Push-pull mode. 932 * | | |1 = Multiple function pin output mode type is Open-drain mode. 933 * | | |Note: 934 * | | |Max. n=15 for port A/B/E/G. 935 * | | |Max. n=14 for port C/D. 936 * | | |Max. n=11 for port F/H. 937 * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 938 * | | |This bit used to select multiple function pin output mode type for Px.n pin 939 * | | |0 = Multiple function pin output mode type is Push-pull mode. 940 * | | |1 = Multiple function pin output mode type is Open-drain mode. 941 * | | |Note: 942 * | | |Max. n=15 for port A/B/E/G. 943 * | | |Max. n=14 for port C/D. 944 * | | |Max. n=11 for port F/H. 945 * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 946 * | | |This bit used to select multiple function pin output mode type for Px.n pin 947 * | | |0 = Multiple function pin output mode type is Push-pull mode. 948 * | | |1 = Multiple function pin output mode type is Open-drain mode. 949 * | | |Note: 950 * | | |Max. n=15 for port A/B/E/G. 951 * | | |Max. n=14 for port C/D. 952 * | | |Max. n=11 for port F/H. 953 * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 954 * | | |This bit used to select multiple function pin output mode type for Px.n pin 955 * | | |0 = Multiple function pin output mode type is Push-pull mode. 956 * | | |1 = Multiple function pin output mode type is Open-drain mode. 957 * | | |Note: 958 * | | |Max. n=15 for port A/B/E/G. 959 * | | |Max. n=14 for port C/D. 960 * | | |Max. n=11 for port F/H. 961 * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 962 * | | |This bit used to select multiple function pin output mode type for Px.n pin 963 * | | |0 = Multiple function pin output mode type is Push-pull mode. 964 * | | |1 = Multiple function pin output mode type is Open-drain mode. 965 * | | |Note: 966 * | | |Max. n=15 for port A/B/E/G. 967 * | | |Max. n=14 for port C/D. 968 * | | |Max. n=11 for port F/H. 969 * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 970 * | | |This bit used to select multiple function pin output mode type for Px.n pin 971 * | | |0 = Multiple function pin output mode type is Push-pull mode. 972 * | | |1 = Multiple function pin output mode type is Open-drain mode. 973 * | | |Note: 974 * | | |Max. n=15 for port A/B/E/G. 975 * | | |Max. n=14 for port C/D. 976 * | | |Max. n=11 for port F/H. 977 * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 978 * | | |This bit used to select multiple function pin output mode type for Px.n pin 979 * | | |0 = Multiple function pin output mode type is Push-pull mode. 980 * | | |1 = Multiple function pin output mode type is Open-drain mode. 981 * | | |Note: 982 * | | |Max. n=15 for port A/B/E/G. 983 * | | |Max. n=14 for port C/D. 984 * | | |Max. n=11 for port F/H. 985 * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 986 * | | |This bit used to select multiple function pin output mode type for Px.n pin 987 * | | |0 = Multiple function pin output mode type is Push-pull mode. 988 * | | |1 = Multiple function pin output mode type is Open-drain mode. 989 * | | |Note: 990 * | | |Max. n=15 for port A/B/E/G. 991 * | | |Max. n=14 for port C/D. 992 * | | |Max. n=11 for port F/H. 993 * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 994 * | | |This bit used to select multiple function pin output mode type for Px.n pin 995 * | | |0 = Multiple function pin output mode type is Push-pull mode. 996 * | | |1 = Multiple function pin output mode type is Open-drain mode. 997 * | | |Note: 998 * | | |Max. n=15 for port A/B/E/G. 999 * | | |Max. n=14 for port C/D. 1000 * | | |Max. n=11 for port F/H. 1001 * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1002 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1003 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1004 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1005 * | | |Note: 1006 * | | |Max. n=15 for port A/B/E/G. 1007 * | | |Max. n=14 for port C/D. 1008 * | | |Max. n=11 for port F/H. 1009 * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1010 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1011 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1012 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1013 * | | |Note: 1014 * | | |Max. n=15 for port A/B/E/G. 1015 * | | |Max. n=14 for port C/D. 1016 * | | |Max. n=11 for port F/H. 1017 * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1018 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1019 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1020 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1021 * | | |Note: 1022 * | | |Max. n=15 for port A/B/E/G. 1023 * | | |Max. n=14 for port C/D. 1024 * | | |Max. n=11 for port F/H. 1025 * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1026 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1027 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1028 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1029 * | | |Note: 1030 * | | |Max. n=15 for port A/B/E/G. 1031 * | | |Max. n=14 for port C/D. 1032 * | | |Max. n=11 for port F/H. 1033 * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1034 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1035 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1036 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1037 * | | |Note: 1038 * | | |Max. n=15 for port A/B/E/G. 1039 * | | |Max. n=14 for port C/D. 1040 * | | |Max. n=11 for port F/H. 1041 * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1042 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1043 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1044 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1045 * | | |Note: 1046 * | | |Max. n=15 for port A/B/E/G. 1047 * | | |Max. n=14 for port C/D. 1048 * | | |Max. n=11 for port F/H. 1049 * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1050 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1051 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1052 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1053 * | | |Note: 1054 * | | |Max. n=15 for port A/B/E/G. 1055 * | | |Max. n=14 for port C/D. 1056 * | | |Max. n=11 for port F/H. 1057 * @var SYS_T::GPD_MFOS 1058 * Offset: 0x8C GPIOD Multiple Function Output Select Register 1059 * --------------------------------------------------------------------------------------------------- 1060 * |Bits |Field |Descriptions 1061 * | :----: | :----: | :---- | 1062 * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1063 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1064 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1065 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1066 * | | |Note: 1067 * | | |Max. n=15 for port A/B/E/G. 1068 * | | |Max. n=14 for port C/D. 1069 * | | |Max. n=11 for port F/H. 1070 * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1071 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1072 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1073 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1074 * | | |Note: 1075 * | | |Max. n=15 for port A/B/E/G. 1076 * | | |Max. n=14 for port C/D. 1077 * | | |Max. n=11 for port F/H. 1078 * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1079 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1080 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1081 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1082 * | | |Note: 1083 * | | |Max. n=15 for port A/B/E/G. 1084 * | | |Max. n=14 for port C/D. 1085 * | | |Max. n=11 for port F/H. 1086 * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1087 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1088 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1089 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1090 * | | |Note: 1091 * | | |Max. n=15 for port A/B/E/G. 1092 * | | |Max. n=14 for port C/D. 1093 * | | |Max. n=11 for port F/H. 1094 * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1095 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1096 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1097 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1098 * | | |Note: 1099 * | | |Max. n=15 for port A/B/E/G. 1100 * | | |Max. n=14 for port C/D. 1101 * | | |Max. n=11 for port F/H. 1102 * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1103 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1104 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1105 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1106 * | | |Note: 1107 * | | |Max. n=15 for port A/B/E/G. 1108 * | | |Max. n=14 for port C/D. 1109 * | | |Max. n=11 for port F/H. 1110 * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1111 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1112 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1113 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1114 * | | |Note: 1115 * | | |Max. n=15 for port A/B/E/G. 1116 * | | |Max. n=14 for port C/D. 1117 * | | |Max. n=11 for port F/H. 1118 * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1119 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1120 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1121 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1122 * | | |Note: 1123 * | | |Max. n=15 for port A/B/E/G. 1124 * | | |Max. n=14 for port C/D. 1125 * | | |Max. n=11 for port F/H. 1126 * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1127 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1128 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1129 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1130 * | | |Note: 1131 * | | |Max. n=15 for port A/B/E/G. 1132 * | | |Max. n=14 for port C/D. 1133 * | | |Max. n=11 for port F/H. 1134 * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1135 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1136 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1137 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1138 * | | |Note: 1139 * | | |Max. n=15 for port A/B/E/G. 1140 * | | |Max. n=14 for port C/D. 1141 * | | |Max. n=11 for port F/H. 1142 * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1143 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1144 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1145 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1146 * | | |Note: 1147 * | | |Max. n=15 for port A/B/E/G. 1148 * | | |Max. n=14 for port C/D. 1149 * | | |Max. n=11 for port F/H. 1150 * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1151 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1152 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1153 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1154 * | | |Note: 1155 * | | |Max. n=15 for port A/B/E/G. 1156 * | | |Max. n=14 for port C/D. 1157 * | | |Max. n=11 for port F/H. 1158 * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1159 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1160 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1161 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1162 * | | |Note: 1163 * | | |Max. n=15 for port A/B/E/G. 1164 * | | |Max. n=14 for port C/D. 1165 * | | |Max. n=11 for port F/H. 1166 * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1167 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1168 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1169 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1170 * | | |Note: 1171 * | | |Max. n=15 for port A/B/E/G. 1172 * | | |Max. n=14 for port C/D. 1173 * | | |Max. n=11 for port F/H. 1174 * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1175 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1176 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1177 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1178 * | | |Note: 1179 * | | |Max. n=15 for port A/B/E/G. 1180 * | | |Max. n=14 for port C/D. 1181 * | | |Max. n=11 for port F/H. 1182 * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1183 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1184 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1185 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1186 * | | |Note: 1187 * | | |Max. n=15 for port A/B/E/G. 1188 * | | |Max. n=14 for port C/D. 1189 * | | |Max. n=11 for port F/H. 1190 * @var SYS_T::GPE_MFOS 1191 * Offset: 0x90 GPIOE Multiple Function Output Select Register 1192 * --------------------------------------------------------------------------------------------------- 1193 * |Bits |Field |Descriptions 1194 * | :----: | :----: | :---- | 1195 * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1196 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1197 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1198 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1199 * | | |Note: 1200 * | | |Max. n=15 for port A/B/E/G. 1201 * | | |Max. n=14 for port C/D. 1202 * | | |Max. n=11 for port F/H. 1203 * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1204 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1205 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1206 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1207 * | | |Note: 1208 * | | |Max. n=15 for port A/B/E/G. 1209 * | | |Max. n=14 for port C/D. 1210 * | | |Max. n=11 for port F/H. 1211 * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1212 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1213 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1214 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1215 * | | |Note: 1216 * | | |Max. n=15 for port A/B/E/G. 1217 * | | |Max. n=14 for port C/D. 1218 * | | |Max. n=11 for port F/H. 1219 * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1220 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1221 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1222 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1223 * | | |Note: 1224 * | | |Max. n=15 for port A/B/E/G. 1225 * | | |Max. n=14 for port C/D. 1226 * | | |Max. n=11 for port F/H. 1227 * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1228 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1229 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1230 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1231 * | | |Note: 1232 * | | |Max. n=15 for port A/B/E/G. 1233 * | | |Max. n=14 for port C/D. 1234 * | | |Max. n=11 for port F/H. 1235 * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1236 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1237 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1238 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1239 * | | |Note: 1240 * | | |Max. n=15 for port A/B/E/G. 1241 * | | |Max. n=14 for port C/D. 1242 * | | |Max. n=11 for port F/H. 1243 * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1244 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1245 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1246 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1247 * | | |Note: 1248 * | | |Max. n=15 for port A/B/E/G. 1249 * | | |Max. n=14 for port C/D. 1250 * | | |Max. n=11 for port F/H. 1251 * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1252 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1253 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1254 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1255 * | | |Note: 1256 * | | |Max. n=15 for port A/B/E/G. 1257 * | | |Max. n=14 for port C/D. 1258 * | | |Max. n=11 for port F/H. 1259 * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1260 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1261 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1262 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1263 * | | |Note: 1264 * | | |Max. n=15 for port A/B/E/G. 1265 * | | |Max. n=14 for port C/D. 1266 * | | |Max. n=11 for port F/H. 1267 * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1268 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1269 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1270 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1271 * | | |Note: 1272 * | | |Max. n=15 for port A/B/E/G. 1273 * | | |Max. n=14 for port C/D. 1274 * | | |Max. n=11 for port F/H. 1275 * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1276 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1277 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1278 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1279 * | | |Note: 1280 * | | |Max. n=15 for port A/B/E/G. 1281 * | | |Max. n=14 for port C/D. 1282 * | | |Max. n=11 for port F/H. 1283 * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1284 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1285 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1286 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1287 * | | |Note: 1288 * | | |Max. n=15 for port A/B/E/G. 1289 * | | |Max. n=14 for port C/D. 1290 * | | |Max. n=11 for port F/H. 1291 * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1292 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1293 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1294 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1295 * | | |Note: 1296 * | | |Max. n=15 for port A/B/E/G. 1297 * | | |Max. n=14 for port C/D. 1298 * | | |Max. n=11 for port F/H. 1299 * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1300 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1301 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1302 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1303 * | | |Note: 1304 * | | |Max. n=15 for port A/B/E/G. 1305 * | | |Max. n=14 for port C/D. 1306 * | | |Max. n=11 for port F/H. 1307 * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1308 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1309 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1310 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1311 * | | |Note: 1312 * | | |Max. n=15 for port A/B/E/G. 1313 * | | |Max. n=14 for port C/D. 1314 * | | |Max. n=11 for port F/H. 1315 * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1316 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1317 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1318 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1319 * | | |Note: 1320 * | | |Max. n=15 for port A/B/E/G. 1321 * | | |Max. n=14 for port C/D. 1322 * | | |Max. n=11 for port F/H. 1323 * @var SYS_T::GPF_MFOS 1324 * Offset: 0x94 GPIOF Multiple Function Output Select Register 1325 * --------------------------------------------------------------------------------------------------- 1326 * |Bits |Field |Descriptions 1327 * | :----: | :----: | :---- | 1328 * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1329 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1330 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1331 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1332 * | | |Note: 1333 * | | |Max. n=15 for port A/B/E/G. 1334 * | | |Max. n=14 for port C/D. 1335 * | | |Max. n=11 for port F/H. 1336 * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1337 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1338 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1339 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1340 * | | |Note: 1341 * | | |Max. n=15 for port A/B/E/G. 1342 * | | |Max. n=14 for port C/D. 1343 * | | |Max. n=11 for port F/H. 1344 * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1345 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1346 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1347 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1348 * | | |Note: 1349 * | | |Max. n=15 for port A/B/E/G. 1350 * | | |Max. n=14 for port C/D. 1351 * | | |Max. n=11 for port F/H. 1352 * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1353 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1354 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1355 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1356 * | | |Note: 1357 * | | |Max. n=15 for port A/B/E/G. 1358 * | | |Max. n=14 for port C/D. 1359 * | | |Max. n=11 for port F/H. 1360 * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1361 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1362 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1363 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1364 * | | |Note: 1365 * | | |Max. n=15 for port A/B/E/G. 1366 * | | |Max. n=14 for port C/D. 1367 * | | |Max. n=11 for port F/H. 1368 * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1369 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1370 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1371 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1372 * | | |Note: 1373 * | | |Max. n=15 for port A/B/E/G. 1374 * | | |Max. n=14 for port C/D. 1375 * | | |Max. n=11 for port F/H. 1376 * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1377 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1378 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1379 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1380 * | | |Note: 1381 * | | |Max. n=15 for port A/B/E/G. 1382 * | | |Max. n=14 for port C/D. 1383 * | | |Max. n=11 for port F/H. 1384 * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1385 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1386 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1387 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1388 * | | |Note: 1389 * | | |Max. n=15 for port A/B/E/G. 1390 * | | |Max. n=14 for port C/D. 1391 * | | |Max. n=11 for port F/H. 1392 * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1393 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1394 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1395 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1396 * | | |Note: 1397 * | | |Max. n=15 for port A/B/E/G. 1398 * | | |Max. n=14 for port C/D. 1399 * | | |Max. n=11 for port F/H. 1400 * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1401 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1402 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1403 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1404 * | | |Note: 1405 * | | |Max. n=15 for port A/B/E/G. 1406 * | | |Max. n=14 for port C/D. 1407 * | | |Max. n=11 for port F/H. 1408 * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1409 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1410 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1411 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1412 * | | |Note: 1413 * | | |Max. n=15 for port A/B/E/G. 1414 * | | |Max. n=14 for port C/D. 1415 * | | |Max. n=11 for port F/H. 1416 * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1417 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1418 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1419 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1420 * | | |Note: 1421 * | | |Max. n=15 for port A/B/E/G. 1422 * | | |Max. n=14 for port C/D. 1423 * | | |Max. n=11 for port F/H. 1424 * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1425 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1426 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1427 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1428 * | | |Note: 1429 * | | |Max. n=15 for port A/B/E/G. 1430 * | | |Max. n=14 for port C/D. 1431 * | | |Max. n=11 for port F/H. 1432 * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1433 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1434 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1435 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1436 * | | |Note: 1437 * | | |Max. n=15 for port A/B/E/G. 1438 * | | |Max. n=14 for port C/D. 1439 * | | |Max. n=11 for port F/H. 1440 * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1441 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1442 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1443 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1444 * | | |Note: 1445 * | | |Max. n=15 for port A/B/E/G. 1446 * | | |Max. n=14 for port C/D. 1447 * | | |Max. n=11 for port F/H. 1448 * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1449 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1450 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1451 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1452 * | | |Note: 1453 * | | |Max. n=15 for port A/B/E/G. 1454 * | | |Max. n=14 for port C/D. 1455 * | | |Max. n=11 for port F/H. 1456 * @var SYS_T::GPG_MFOS 1457 * Offset: 0x98 GPIOG Multiple Function Output Select Register 1458 * --------------------------------------------------------------------------------------------------- 1459 * |Bits |Field |Descriptions 1460 * | :----: | :----: | :---- | 1461 * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1462 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1463 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1464 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1465 * | | |Note: 1466 * | | |Max. n=15 for port A/B/E/G. 1467 * | | |Max. n=14 for port C/D. 1468 * | | |Max. n=11 for port F/H. 1469 * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1470 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1471 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1472 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1473 * | | |Note: 1474 * | | |Max. n=15 for port A/B/E/G. 1475 * | | |Max. n=14 for port C/D. 1476 * | | |Max. n=11 for port F/H. 1477 * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1478 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1479 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1480 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1481 * | | |Note: 1482 * | | |Max. n=15 for port A/B/E/G. 1483 * | | |Max. n=14 for port C/D. 1484 * | | |Max. n=11 for port F/H. 1485 * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1486 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1487 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1488 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1489 * | | |Note: 1490 * | | |Max. n=15 for port A/B/E/G. 1491 * | | |Max. n=14 for port C/D. 1492 * | | |Max. n=11 for port F/H. 1493 * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1494 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1495 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1496 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1497 * | | |Note: 1498 * | | |Max. n=15 for port A/B/E/G. 1499 * | | |Max. n=14 for port C/D. 1500 * | | |Max. n=11 for port F/H. 1501 * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1502 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1503 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1504 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1505 * | | |Note: 1506 * | | |Max. n=15 for port A/B/E/G. 1507 * | | |Max. n=14 for port C/D. 1508 * | | |Max. n=11 for port F/H. 1509 * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1510 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1511 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1512 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1513 * | | |Note: 1514 * | | |Max. n=15 for port A/B/E/G. 1515 * | | |Max. n=14 for port C/D. 1516 * | | |Max. n=11 for port F/H. 1517 * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1518 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1519 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1520 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1521 * | | |Note: 1522 * | | |Max. n=15 for port A/B/E/G. 1523 * | | |Max. n=14 for port C/D. 1524 * | | |Max. n=11 for port F/H. 1525 * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1526 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1527 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1528 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1529 * | | |Note: 1530 * | | |Max. n=15 for port A/B/E/G. 1531 * | | |Max. n=14 for port C/D. 1532 * | | |Max. n=11 for port F/H. 1533 * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1534 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1535 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1536 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1537 * | | |Note: 1538 * | | |Max. n=15 for port A/B/E/G. 1539 * | | |Max. n=14 for port C/D. 1540 * | | |Max. n=11 for port F/H. 1541 * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1542 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1543 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1544 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1545 * | | |Note: 1546 * | | |Max. n=15 for port A/B/E/G. 1547 * | | |Max. n=14 for port C/D. 1548 * | | |Max. n=11 for port F/H. 1549 * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1550 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1551 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1552 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1553 * | | |Note: 1554 * | | |Max. n=15 for port A/B/E/G. 1555 * | | |Max. n=14 for port C/D. 1556 * | | |Max. n=11 for port F/H. 1557 * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1558 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1559 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1560 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1561 * | | |Note: 1562 * | | |Max. n=15 for port A/B/E/G. 1563 * | | |Max. n=14 for port C/D. 1564 * | | |Max. n=11 for port F/H. 1565 * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1566 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1567 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1568 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1569 * | | |Note: 1570 * | | |Max. n=15 for port A/B/E/G. 1571 * | | |Max. n=14 for port C/D. 1572 * | | |Max. n=11 for port F/H. 1573 * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1574 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1575 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1576 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1577 * | | |Note: 1578 * | | |Max. n=15 for port A/B/E/G. 1579 * | | |Max. n=14 for port C/D. 1580 * | | |Max. n=11 for port F/H. 1581 * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1582 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1583 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1584 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1585 * | | |Note: 1586 * | | |Max. n=15 for port A/B/E/G. 1587 * | | |Max. n=14 for port C/D. 1588 * | | |Max. n=11 for port F/H. 1589 * @var SYS_T::GPH_MFOS 1590 * Offset: 0x9C GPIOH Multiple Function Output Select Register 1591 * --------------------------------------------------------------------------------------------------- 1592 * |Bits |Field |Descriptions 1593 * | :----: | :----: | :---- | 1594 * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1595 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1596 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1597 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1598 * | | |Note: 1599 * | | |Max. n=15 for port A/B/E/G. 1600 * | | |Max. n=14 for port C/D. 1601 * | | |Max. n=11 for port F/H. 1602 * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1603 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1604 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1605 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1606 * | | |Note: 1607 * | | |Max. n=15 for port A/B/E/G. 1608 * | | |Max. n=14 for port C/D. 1609 * | | |Max. n=11 for port F/H. 1610 * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1611 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1612 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1613 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1614 * | | |Note: 1615 * | | |Max. n=15 for port A/B/E/G. 1616 * | | |Max. n=14 for port C/D. 1617 * | | |Max. n=11 for port F/H. 1618 * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1619 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1620 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1621 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1622 * | | |Note: 1623 * | | |Max. n=15 for port A/B/E/G. 1624 * | | |Max. n=14 for port C/D. 1625 * | | |Max. n=11 for port F/H. 1626 * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1627 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1628 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1629 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1630 * | | |Note: 1631 * | | |Max. n=15 for port A/B/E/G. 1632 * | | |Max. n=14 for port C/D. 1633 * | | |Max. n=11 for port F/H. 1634 * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1635 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1636 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1637 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1638 * | | |Note: 1639 * | | |Max. n=15 for port A/B/E/G. 1640 * | | |Max. n=14 for port C/D. 1641 * | | |Max. n=11 for port F/H. 1642 * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1643 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1644 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1645 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1646 * | | |Note: 1647 * | | |Max. n=15 for port A/B/E/G. 1648 * | | |Max. n=14 for port C/D. 1649 * | | |Max. n=11 for port F/H. 1650 * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1651 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1652 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1653 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1654 * | | |Note: 1655 * | | |Max. n=15 for port A/B/E/G. 1656 * | | |Max. n=14 for port C/D. 1657 * | | |Max. n=11 for port F/H. 1658 * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1659 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1660 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1661 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1662 * | | |Note: 1663 * | | |Max. n=15 for port A/B/E/G. 1664 * | | |Max. n=14 for port C/D. 1665 * | | |Max. n=11 for port F/H. 1666 * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1667 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1668 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1669 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1670 * | | |Note: 1671 * | | |Max. n=15 for port A/B/E/G. 1672 * | | |Max. n=14 for port C/D. 1673 * | | |Max. n=11 for port F/H. 1674 * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1675 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1676 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1677 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1678 * | | |Note: 1679 * | | |Max. n=15 for port A/B/E/G. 1680 * | | |Max. n=14 for port C/D. 1681 * | | |Max. n=11 for port F/H. 1682 * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1683 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1684 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1685 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1686 * | | |Note: 1687 * | | |Max. n=15 for port A/B/E/G. 1688 * | | |Max. n=14 for port C/D. 1689 * | | |Max. n=11 for port F/H. 1690 * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1691 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1692 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1693 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1694 * | | |Note: 1695 * | | |Max. n=15 for port A/B/E/G. 1696 * | | |Max. n=14 for port C/D. 1697 * | | |Max. n=11 for port F/H. 1698 * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1699 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1700 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1701 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1702 * | | |Note: 1703 * | | |Max. n=15 for port A/B/E/G. 1704 * | | |Max. n=14 for port C/D. 1705 * | | |Max. n=11 for port F/H. 1706 * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1707 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1708 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1709 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1710 * | | |Note: 1711 * | | |Max. n=15 for port A/B/E/G. 1712 * | | |Max. n=14 for port C/D. 1713 * | | |Max. n=11 for port F/H. 1714 * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1715 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1716 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1717 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1718 * | | |Note: 1719 * | | |Max. n=15 for port A/B/E/G. 1720 * | | |Max. n=14 for port C/D. 1721 * | | |Max. n=11 for port F/H. 1722 * @var SYS_T::SRAM_INTCTL 1723 * Offset: 0xC0 System SRAM Interrupt Enable Control Register 1724 * --------------------------------------------------------------------------------------------------- 1725 * |Bits |Field |Descriptions 1726 * | :----: | :----: | :---- | 1727 * |[0] |PERRIEN |SRAM Parity Check Error Interrupt Enable Bit 1728 * | | |0 = SRAM parity check error interrupt Disabled. 1729 * | | |1 = SRAM parity check error interrupt Enabled. 1730 * @var SYS_T::SRAM_STATUS 1731 * Offset: 0xC4 System SRAM Parity Error Status Register 1732 * --------------------------------------------------------------------------------------------------- 1733 * |Bits |Field |Descriptions 1734 * | :----: | :----: | :---- | 1735 * |[0] |PERRIF |SRAM Parity Check Error Flag 1736 * | | |This bit indicates the System SRAM parity error occurred. Write 1 to clear this to 0. 1737 * | | |0 = No System SRAM parity error. 1738 * | | |1 = System SRAM parity error occur. 1739 * @var SYS_T::SRAM_ERRADDR 1740 * Offset: 0xC8 System SRAM Parity Check Error Address Register 1741 * --------------------------------------------------------------------------------------------------- 1742 * |Bits |Field |Descriptions 1743 * | :----: | :----: | :---- | 1744 * |[31:0] |ERRADDR |System SRAM Parity Error Address 1745 * | | |This register shows system SRAM parity error byte address. 1746 * @var SYS_T::SRAM_BISTCTL 1747 * Offset: 0xD0 System SRAM BIST Test Control Register 1748 * --------------------------------------------------------------------------------------------------- 1749 * |Bits |Field |Descriptions 1750 * | :----: | :----: | :---- | 1751 * |[0] |SRBIST0 |SRAM Bank0 BIST Enable Bit (Write Protect) 1752 * | | |This bit enables BIST test for SRAM bank0. 1753 * | | |0 = system SRAM bank0 BIST Disabled. 1754 * | | |1 = system SRAM bank0 BIST Enabled. 1755 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 1756 * |[1] |SRBIST1 |SRAM Bank1 BIST Enable Bit (Write Protect) 1757 * | | |This bit enables BIST test for SRAM bank1. 1758 * | | |0 = system SRAM bank1 BIST Disabled. 1759 * | | |1 = system SRAM bank1 BIST Enabled. 1760 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 1761 * |[2] |CRBIST |CACHE BIST Enable Bit (Write Protect) 1762 * | | |This bit enables BIST test for CACHE RAM 1763 * | | |0 = system CACHE BIST Disabled. 1764 * | | |1 = system CACHE BIST Enabled. 1765 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 1766 * |[3] |CANBIST |CAN BIST Enable Bit (Write Protect) 1767 * | | |This bit enables BIST test for CAN RAM 1768 * | | |0 = system CAN BIST Disabled. 1769 * | | |1 = system CAN BIST Enabled. 1770 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 1771 * |[4] |USBBIST |USB BIST Enable Bit (Write Protect) 1772 * | | |This bit enables BIST test for USB RAM 1773 * | | |0 = system USB BIST Disabled. 1774 * | | |1 = system USB BIST Enabled. 1775 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 1776 * |[5] |SPIMBIST |SPIM BIST Enable Bit (Write Protect) 1777 * | | |This bit enables BIST test for SPIM RAM 1778 * | | |0 = system SPIM BIST Disabled. 1779 * | | |1 = system SPIM BIST Enabled. 1780 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 1781 * |[6] |EMCBIST |EMC BIST Enable Bit (Write Protect) 1782 * | | |This bit enables BIST test for EMC RAM 1783 * | | |0 = system EMC BIST Disabled. 1784 * | | |1 = system EMC BIST Enabled. 1785 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 1786 * |[7] |PDMABIST |PDMA BIST Enable Bit (Write Protect) 1787 * | | |This bit enables BIST test for PDMA RAM 1788 * | | |0 = system PDMA BIST Disabled. 1789 * | | |1 = system PDMA BIST Enabled. 1790 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 1791 * |[8] |HSUSBDBIST|HSUSBD BIST Enable Bit (Write Protect) 1792 * | | |This bit enables BIST test for HSUSBD RAM 1793 * | | |0 = system HSUSBD BIST Disabled. 1794 * | | |1 = system HSUSBD BIST Enabled. 1795 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 1796 * |[9] |HSUSBHBIST|HSUSBH BIST Enable Bit (Write Protect) 1797 * | | |This bit enables BIST test for HSUSBH RAM 1798 * | | |0 = system HSUSBH BIST Disabled. 1799 * | | |1 = system HSUSBH BIST Enabled. 1800 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 1801 * |[16] |SRB0S0 |SRAM Bank0 Section 0 BIST Select (Write Protect) 1802 * | | |This bit define if the first 16KB section of SRAM bank0 is selected or not when doing bist test. 1803 * | | |0 = SRAM bank0 section 0 is deselected when doing bist test. 1804 * | | |1 = SRAM bank0 section 0 is selected when doing bist test. 1805 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 1806 * | | |Note: At least one section of SRAM bank0 should be selected when doing SRAM bank0 bist test. 1807 * |[17] |SRB0S1 |SRAM Bank0 Section 1 BIST Select (Write Protect) 1808 * | | |This bit define if the second 16KB section of SRAM bank0 is selected or not when doing bist test. 1809 * | | |0 = SRAM bank0 section 1 is deselected when doing bist test. 1810 * | | |1 = SRAM bank0 section 1 is selected when doing bist test. 1811 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 1812 * | | |Note: At least one section of SRAM bank0 should be selected when doing SRAM bank0 bist test. 1813 * |[18] |SRB1S0 |SRAM Bank1 Section 0 BIST Select (Write Protect) 1814 * | | |This bit define if the first 16KB section of SRAM bank1 is selected or not when doing bist test. 1815 * | | |0 = SRAM bank1 first 16KB section is deselected when doing bist test. 1816 * | | |1 = SRAM bank1 first 16KB section is selected when doing bist test. 1817 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 1818 * | | |Note: At least one section of SRAM bank1 should be selected when doing SRAM bank1 bist test. 1819 * |[19] |SRB1S1 |SRAM Bank1 Section 1 BIST Select (Write Protect) 1820 * | | |This bit define if the second 16KB section of SRAM bank1 is selected or not when doing bist test. 1821 * | | |0 = SRAM bank1 second 16KB section is deselected when doing bist test. 1822 * | | |1 = SRAM bank1 second 16KB section is selected when doing bist test. 1823 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 1824 * | | |Note: At least one section of SRAM bank1 should be selected when doing SRAM bank1 bist test. 1825 * |[20] |SRB1S2 |SRAM Bank1 Section 0 BIST Select (Write Protect) 1826 * | | |This bit define if the third 16KB section of SRAM bank1 is selected or not when doing bist test. 1827 * | | |0 = SRAM bank1 third 16KB section is deselected when doing bist test. 1828 * | | |1 = SRAM bank1 third 16KB section is selected when doing bist test. 1829 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 1830 * | | |Note: At least one section of SRAM bank1 should be selected when doing SRAM bank1 bist test. 1831 * |[21] |SRB1S3 |SRAM Bank1 Section 1 BIST Select (Write Protect) 1832 * | | |This bit define if the fourth 16KB section of SRAM bank1 is selected or not when doing bist test. 1833 * | | |0 = SRAM bank1 fourth 16KB section is deselected when doing bist test. 1834 * | | |1 = SRAM bank1 fourth 16KB section is selected when doing bist test. 1835 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 1836 * | | |Note: At least one section of SRAM bank1 should be selected when doing SRAM bank1 bist test. 1837 * |[22] |SRB1S4 |SRAM Bank1 Section 0 BIST Select (Write Protect) 1838 * | | |This bit define if the fifth 16KB section of SRAM bank1 is selected or not when doing bist test. 1839 * | | |0 = SRAM bank1 fifth 16KB section is deselected when doing bist test. 1840 * | | |1 = SRAM bank1 fifth 16KB section is selected when doing bist test. 1841 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 1842 * | | |Note: At least one section of SRAM bank1 should be selected when doing SRAM bank1 bist test. 1843 * |[23] |SRB1S5 |SRAM Bank1 Section 1 BIST Select (Write Protect) 1844 * | | |This bit define if the sixth 16KB section of SRAM bank1 is selected or not when doing bist test. 1845 * | | |0 = SRAM bank1 sixth 16KB section is deselected when doing bist test. 1846 * | | |1 = SRAM bank1 sixth 16KB section is selected when doing bist test. 1847 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 1848 * | | |Note: At least one section of SRAM bank1 should be selected when doing SRAM bank1 bist test. 1849 * @var SYS_T::SRAM_BISTSTS 1850 * Offset: 0xD4 System SRAM BIST Test Status Register 1851 * --------------------------------------------------------------------------------------------------- 1852 * |Bits |Field |Descriptions 1853 * | :----: | :----: | :---- | 1854 * |[0] |SRBISTEF0 |1st System SRAM BIST Fail Flag 1855 * | | |0 = 1st system SRAM BIST test pass. 1856 * | | |1 = 1st system SRAM BIST test fail. 1857 * |[1] |SRBISTEF1 |2nd System SRAM BIST Fail Flag 1858 * | | |0 = 2nd system SRAM BIST test pass. 1859 * | | |1 = 2nd system SRAM BIST test fail. 1860 * |[2] |CRBISTEF |CACHE SRAM BIST Fail Flag 1861 * | | |0 = System CACHE RAM BIST test pass. 1862 * | | |1 = System CACHE RAM BIST test fail. 1863 * |[3] |CANBEF |CAN SRAM BIST Fail Flag 1864 * | | |0 = CAN SRAM BIST test pass. 1865 * | | |1 = CAN SRAM BIST test fail. 1866 * |[4] |USBBEF |USB SRAM BIST Fail Flag 1867 * | | |0 = USB SRAM BIST test pass. 1868 * | | |1 = USB SRAM BIST test fail. 1869 * |[16] |SRBEND0 |1st SRAM BIST Test Finish 1870 * | | |0 = 1st system SRAM BIST active. 1871 * | | |1 =1st system SRAM BIST finish. 1872 * |[17] |SRBEND1 |2nd SRAM BIST Test Finish 1873 * | | |0 = 2nd system SRAM BIST is active. 1874 * | | |1 = 2nd system SRAM BIST finish. 1875 * |[18] |CRBEND |CACHE SRAM BIST Test Finish 1876 * | | |0 = System CACHE RAM BIST is active. 1877 * | | |1 = System CACHE RAM BIST test finish. 1878 * |[19] |CANBEND |CAN SRAM BIST Test Finish 1879 * | | |0 = CAN SRAM BIST is active. 1880 * | | |1 = CAN SRAM BIST test finish. 1881 * |[20] |USBBEND |USB SRAM BIST Test Finish 1882 * | | |0 = USB SRAM BIST is active. 1883 * | | |1 = USB SRAM BIST test finish. 1884 * @var SYS_T::HIRCTCTL 1885 * Offset: 0xE4 HIRC48M Trim Control Register 1886 * --------------------------------------------------------------------------------------------------- 1887 * |Bits |Field |Descriptions 1888 * | :----: | :----: | :---- | 1889 * |[1:0] |FREQSEL |Trim Frequency Selection 1890 * | | |This field indicates the target frequency of 48 MHz internal high speed RC oscillator (HIRC) auto trim. 1891 * | | |During auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically. 1892 * | | |00 = Disable HIRC auto trim function. 1893 * | | |01 = Enable HIRC auto trim function and trim HIRC to 48 MHz. 1894 * | | |10 = Reserved.. 1895 * | | |11 = Reserved. 1896 * |[5:4] |LOOPSEL |Trim Calculation Loop Selection 1897 * | | |This field defines that trim value calculation is based on how many reference clocks. 1898 * | | |00 = Trim value calculation is based on average difference in 4 clocks of reference clock. 1899 * | | |01 = Trim value calculation is based on average difference in 8 clocks of reference clock. 1900 * | | |10 = Trim value calculation is based on average difference in 16 clocks of reference clock. 1901 * | | |11 = Trim value calculation is based on average difference in 32 clocks of reference clock. 1902 * | | |Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock. 1903 * |[7:6] |RETRYCNT |Trim Value Update Limitation Count 1904 * | | |This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked. 1905 * | | |Once the HIRC locked, the internal trim value update counter will be reset. 1906 * | | |If the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00. 1907 * | | |00 = Trim retry count limitation is 64 loops. 1908 * | | |01 = Trim retry count limitation is 128 loops. 1909 * | | |10 = Trim retry count limitation is 256 loops. 1910 * | | |11 = Trim retry count limitation is 512 loops. 1911 * |[8] |CESTOPEN |Clock Error Stop Enable Bit 1912 * | | |0 = The trim operation is keep going if clock is inaccuracy. 1913 * | | |1 = The trim operation is stopped if clock is inaccuracy. 1914 * |[9] |BOUNDEN |Boundary Enable Bit 1915 * | | |0 = Boundary function is disable. 1916 * | | |1 = Boundary function is enable. 1917 * |[10] |REFCKSEL |Reference Clock Selection 1918 * | | |0 = HIRC trim reference from external 32.768 kHz crystal oscillator. 1919 * | | |1 = HIRC trim reference from internal USB synchronous mode. 1920 * | | |Note: HIRC trim reference clock is 20Khz in test mode. 1921 * |[20:16 |BOUNDARY |Boundary Selection 1922 * | | |Fill the boundary range from 0x1 to 0x31, 0x0 is reserved. 1923 * | | |Note1: This field is effective only when the BOUNDEN(SYS_HIRCTRIMCTL[9]) is enable. 1924 * @var SYS_T::HIRCTIEN 1925 * Offset: 0xE8 HIRC48M Trim Interrupt Enable Register 1926 * --------------------------------------------------------------------------------------------------- 1927 * |Bits |Field |Descriptions 1928 * | :----: | :----: | :---- | 1929 * |[1] |TFAILIEN |Trim Failure Interrupt Enable Bit 1930 * | | |This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_HIRCTCTL[1:0]). 1931 * | | |If this bit is high and TFAILIF(SYS_HIRCTISTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. 1932 * | | |0 = Disable TFAILIF(SYS_HIRCTISTS[1]) status to trigger an interrupt to CPU. 1933 * | | |1 = Enable TFAILIF(SYS_HIRCTISTS[1]) status to trigger an interrupt to CPU. 1934 * |[2] |CLKEIEN |Clock Error Interrupt Enable Bit 1935 * | | |This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation. 1936 * | | |If this bit is set to1, and CLKERRIF(SYS_HIRCTISTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy. 1937 * | | |0 = Disable CLKERRIF(SYS_HIRCTISTS[2]) status to trigger an interrupt to CPU. 1938 * | | |1 = Enable CLKERRIF(SYS_HIRCTISTS[2]) status to trigger an interrupt to CPU. 1939 * @var SYS_T::HIRCTISTS 1940 * Offset: 0xEC HIRC48M Trim Interrupt Status Register 1941 * --------------------------------------------------------------------------------------------------- 1942 * |Bits |Field |Descriptions 1943 * | :----: | :----: | :---- | 1944 * |[0] |FREQLOCK |HIRC Frequency Lock Status 1945 * | | |This bit indicates the HIRC frequency is locked. 1946 * | | |This is a status bit and doesn't trigger any interrupt 1947 * | | |Write 1 to clear this to 0 1948 * | | |This bit will be set automatically, if the frequency is lock and the RC_TRIM is enabled. 1949 * | | |0 = The internal high-speed oscillator frequency doesn't lock at 48 MHz yet. 1950 * | | |1 = The internal high-speed oscillator frequency locked at 48 MHz. 1951 * |[1] |TFAILIF |Trim Failure Interrupt Status 1952 * | | |This bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked 1953 * | | |Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_HIRCTCTL[1:0]) will be cleared to 00 by hardware automatically. 1954 * | | |If this bit is set and TFAILIEN(SYS_HIRCTIEN[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached 1955 * | | |Write 1 to clear this to 0. 1956 * | | |0 = Trim value update limitation count does not reach. 1957 * | | |1 = Trim value update limitation count reached and HIRC frequency still not locked. 1958 * |[2] |CLKERRIF |Clock Error Interrupt Status 1959 * | | |When the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 48MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy. 1960 * | | |Once this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_HIRCTCL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_HIRCTCTL[8]) is set to 1. 1961 * | | |If this bit is set and CLKEIEN(SYS_HIRCTIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. 1962 * | | |Write 1 to clear this to 0. 1963 * | | |0 = Clock frequency is accurate. 1964 * | | |1 = Clock frequency is inaccurate. 1965 * |[3] |OVBDIF |Over Boundary Status 1966 * | | |When the over boundary function is set, if there occurs the over boundary condition, this flag will be set. 1967 * | | |Note1: Write 1 to clear this flag. 1968 * | | |Note2: This function is only supported in M48xGC/M48xG8. 1969 * | | |0 = Over boundary condition did not occur. 1970 * | | |1 = Over boundary condition occurred. 1971 * @var SYS_T::IRCTCTL 1972 * Offset: 0xF0 HIRC Trim Control Register 1973 * --------------------------------------------------------------------------------------------------- 1974 * |Bits |Field |Descriptions 1975 * | :----: | :----: | :---- | 1976 * |[1:0] |FREQSEL |Trim Frequency Selection 1977 * | | |This field indicates the target frequency of 12 MHz internal high speed RC oscillator (HIRC) auto trim. 1978 * | | |During auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically. 1979 * | | |00 = Disable HIRC auto trim function. 1980 * | | |01 = Enable HIRC auto trim function and trim HIRC to 12 MHz. 1981 * | | |10 = Reserved.. 1982 * | | |11 = Reserved. 1983 * |[5:4] |LOOPSEL |Trim Calculation Loop Selection 1984 * | | |This field defines that trim value calculation is based on how many reference clocks. 1985 * | | |00 = Trim value calculation is based on average difference in 4 clocks of reference clock. 1986 * | | |01 = Trim value calculation is based on average difference in 8 clocks of reference clock. 1987 * | | |10 = Trim value calculation is based on average difference in 16 clocks of reference clock. 1988 * | | |11 = Trim value calculation is based on average difference in 32 clocks of reference clock. 1989 * | | |Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock. 1990 * |[7:6] |RETRYCNT |Trim Value Update Limitation Count 1991 * | | |This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked. 1992 * | | |Once the HIRC locked, the internal trim value update counter will be reset. 1993 * | | |If the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00. 1994 * | | |00 = Trim retry count limitation is 64 loops. 1995 * | | |01 = Trim retry count limitation is 128 loops. 1996 * | | |10 = Trim retry count limitation is 256 loops. 1997 * | | |11 = Trim retry count limitation is 512 loops. 1998 * |[8] |CESTOPEN |Clock Error Stop Enable Bit 1999 * | | |0 = The trim operation is keep going if clock is inaccuracy. 2000 * | | |1 = The trim operation is stopped if clock is inaccuracy. 2001 * |[10] |REFCKSEL |Reference Clock Selection 2002 * | | |0 = HIRC trim reference from external 32.768 kHz crystal oscillator. 2003 * | | |1 = HIRC trim reference from internal USB synchronous mode. 2004 * | | |Note: HIRC trim reference clock is 20Khz in test mode. 2005 * @var SYS_T::IRCTIEN 2006 * Offset: 0xF4 HIRC Trim Interrupt Enable Register 2007 * --------------------------------------------------------------------------------------------------- 2008 * |Bits |Field |Descriptions 2009 * | :----: | :----: | :---- | 2010 * |[1] |TFAILIEN |Trim Failure Interrupt Enable Bit 2011 * | | |This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_IRCTCTL[1:0]). 2012 * | | |If this bit is high and TFAILIF(SYS_IRCTISTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. 2013 * | | |0 = Disable TFAILIF(SYS_IRCTISTS[1]) status to trigger an interrupt to CPU. 2014 * | | |1 = Enable TFAILIF(SYS_IRCTISTS[1]) status to trigger an interrupt to CPU. 2015 * |[2] |CLKEIEN |Clock Error Interrupt Enable Bit 2016 * | | |This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation. 2017 * | | |If this bit is set to1, and CLKERRIF(SYS_IRCTISTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy. 2018 * | | |0 = Disable CLKERRIF(SYS_IRCTISTS[2]) status to trigger an interrupt to CPU. 2019 * | | |1 = Enable CLKERRIF(SYS_IRCTISTS[2]) status to trigger an interrupt to CPU. 2020 * @var SYS_T::IRCTISTS 2021 * Offset: 0xF8 HIRC Trim Interrupt Status Register 2022 * --------------------------------------------------------------------------------------------------- 2023 * |Bits |Field |Descriptions 2024 * | :----: | :----: | :---- | 2025 * |[0] |FREQLOCK |HIRC Frequency Lock Status 2026 * | | |This bit indicates the HIRC frequency is locked. 2027 * | | |This is a status bit and doesn't trigger any interrupt 2028 * | | |Write 1 to clear this to 0 2029 * | | |This bit will be set automatically, if the frequency is lock and the RC_TRIM is enabled. 2030 * | | |0 = The internal high-speed oscillator frequency doesn't lock at 12 MHz yet. 2031 * | | |1 = The internal high-speed oscillator frequency locked at 12 MHz. 2032 * |[1] |TFAILIF |Trim Failure Interrupt Status 2033 * | | |This bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked 2034 * | | |Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_IRCTCTL[1:0]) will be cleared to 00 by hardware automatically. 2035 * | | |If this bit is set and TFAILIEN(SYS_IRCTIEN[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached 2036 * | | |Write 1 to clear this to 0. 2037 * | | |0 = Trim value update limitation count does not reach. 2038 * | | |1 = Trim value update limitation count reached and HIRC frequency still not locked. 2039 * |[2] |CLKERRIF |Clock Error Interrupt Status 2040 * | | |When the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 12MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy. 2041 * | | |Once this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_IRCTCL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_IRCTCTL[8]) is set to 1. 2042 * | | |If this bit is set and CLKEIEN(SYS_IRCTIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. 2043 * | | |Write 1 to clear this to 0. 2044 * | | |0 = Clock frequency is accurate. 2045 * | | |1 = Clock frequency is inaccurate. 2046 * @var SYS_T::REGLCTL 2047 * Offset: 0x100 Register Lock Control Register 2048 * --------------------------------------------------------------------------------------------------- 2049 * |Bits |Field |Descriptions 2050 * | :----: | :----: | :---- | 2051 * |[7:0] |REGLCTL |Register Lock Control Code 2052 * | | |Some registers have write-protection function 2053 * | | |Writing these registers have to disable the protected function by writing the sequence value "59h", "16h", "88h" to this field. 2054 * | | |After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write. 2055 * | | |Register Lock Control Code 2056 * | | |0 = Write-protection Enabled for writing protected registers 2057 * | | |Any write to the protected register is ignored. 2058 * | | |1 = Write-protection Disabled for writing protected registers. 2059 * @var SYS_T::PORDISAN 2060 * Offset: 0x1EC Analog POR Disable Control Register 2061 * --------------------------------------------------------------------------------------------------- 2062 * |Bits |Field |Descriptions 2063 * | :----: | :----: | :---- | 2064 * |[15:0] |POROFFAN |Power-on Reset Enable Bit (Write Protect) 2065 * | | |After powered on, User can turn off internal analog POR circuit to save power by writing 0x5AA5 to this field. 2066 * | | |The analog POR circuit will be active again when this field is set to another value or chip is reset by other reset source, including: 2067 * | | |nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function. 2068 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 2069 * @var SYS_T::PLCTL 2070 * Offset: 0x1F8 Power Level Control Register 2071 * --------------------------------------------------------------------------------------------------- 2072 * |Bits |Field |Descriptions 2073 * | :----: | :----: | :---- | 2074 * |[1:0] |PLSEL |Power Level Select(Write Protect) 2075 * | | |00 = Power level is PL0. 2076 * | | |01 = Power level is PL1. 2077 * | | |Others = Reserved. 2078 * |[21:16] |LVSSTEP |LDO Voltage Scaling Step(Write Protect) 2079 * | | |The LVSSTEP value is LDO voltage rising step. 2080 * | | |Core voltage scaling voltage step = (LVSSTEP + 1) * 10mV. 2081 * |[31:24] |LVSPRD |LDO Voltage Scaling Period(Write Protect) 2082 * | | |The LVSPRD value is the period of each LDO voltage rising step. 2083 * | | |LDO voltage scaling period = (LVSPRD + 1) * 1us. 2084 * @var SYS_T::PLSTS 2085 * Offset: 0x1FC Power Level Status Register 2086 * --------------------------------------------------------------------------------------------------- 2087 * |Bits |Field |Descriptions 2088 * | :----: | :----: | :---- | 2089 * |[0] |PLCBUSY |Power Level Change Busy Bit (Read Only) 2090 * | | |This bit is set by hardware when core voltage is changing 2091 * | | |After core voltage change is completed, this bit will be cleared automatically by hardware. 2092 * | | |0 = Core voltage change is completed. 2093 * | | |1 = Core voltage change is ongoing. 2094 * |[9:8] |PLSTATUS |Power Level Status (Read Only) 2095 * | | |00 = Power level is PL0. 2096 * | | |01 = Power level is PL1. 2097 * | | |Others = Reserved. 2098 * @var SYS_T::AHBMCTL 2099 * Offset: 0x400 AHB Bus Matrix Priority Control Register 2100 * --------------------------------------------------------------------------------------------------- 2101 * |Bits |Field |Descriptions 2102 * | :----: | :----: | :---- | 2103 * |[0] |INTACTEN |Highest AHB Bus Priority of Cortex M4 Core Enable Bit (Write Protect) 2104 * | | |Enable Cortex-M4 Core With Highest AHB Bus Priority In AHB Bus Matrix 2105 * | | |0 = Run robin mode. 2106 * | | |1 = Cortex-M4 CPU with highest bus priority when interrupt occurred. 2107 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 2108 */ 2109 __I uint32_t PDID; /*!< [0x0000] Part Device Identification Number Register */ 2110 __IO uint32_t RSTSTS; /*!< [0x0004] System Reset Status Register */ 2111 __IO uint32_t IPRST0; /*!< [0x0008] Peripheral Reset Control Register 0 */ 2112 __IO uint32_t IPRST1; /*!< [0x000c] Peripheral Reset Control Register 1 */ 2113 __IO uint32_t IPRST2; /*!< [0x0010] Peripheral Reset Control Register 2 */ 2114 /** @cond HIDDEN_SYMBOLS */ 2115 __I uint32_t RESERVE0[1]; 2116 /** @endcond */ 2117 __IO uint32_t BODCTL; /*!< [0x0018] Brown-Out Detector Control Register */ 2118 __IO uint32_t IVSCTL; /*!< [0x001c] Internal Voltage Source Control Register */ 2119 /** @cond HIDDEN_SYMBOLS */ 2120 __I uint32_t RESERVE1[1]; 2121 /** @endcond */ 2122 __IO uint32_t PORCTL; /*!< [0x0024] Power-On-Reset Controller Register */ 2123 __IO uint32_t VREFCTL; /*!< [0x0028] VREF Control Register */ 2124 __IO uint32_t USBPHY; /*!< [0x002c] USB PHY Control Register */ 2125 __IO uint32_t GPA_MFPL; /*!< [0x0030] GPIOA Low Byte Multiple Function Control Register */ 2126 __IO uint32_t GPA_MFPH; /*!< [0x0034] GPIOA High Byte Multiple Function Control Register */ 2127 __IO uint32_t GPB_MFPL; /*!< [0x0038] GPIOB Low Byte Multiple Function Control Register */ 2128 __IO uint32_t GPB_MFPH; /*!< [0x003c] GPIOB High Byte Multiple Function Control Register */ 2129 __IO uint32_t GPC_MFPL; /*!< [0x0040] GPIOC Low Byte Multiple Function Control Register */ 2130 __IO uint32_t GPC_MFPH; /*!< [0x0044] GPIOC High Byte Multiple Function Control Register */ 2131 __IO uint32_t GPD_MFPL; /*!< [0x0048] GPIOD Low Byte Multiple Function Control Register */ 2132 __IO uint32_t GPD_MFPH; /*!< [0x004c] GPIOD High Byte Multiple Function Control Register */ 2133 __IO uint32_t GPE_MFPL; /*!< [0x0050] GPIOE Low Byte Multiple Function Control Register */ 2134 __IO uint32_t GPE_MFPH; /*!< [0x0054] GPIOE High Byte Multiple Function Control Register */ 2135 __IO uint32_t GPF_MFPL; /*!< [0x0058] GPIOF Low Byte Multiple Function Control Register */ 2136 __IO uint32_t GPF_MFPH; /*!< [0x005c] GPIOF High Byte Multiple Function Control Register */ 2137 __IO uint32_t GPG_MFPL; /*!< [0x0060] GPIOG Low Byte Multiple Function Control Register */ 2138 __IO uint32_t GPG_MFPH; /*!< [0x0064] GPIOG High Byte Multiple Function Control Register */ 2139 __IO uint32_t GPH_MFPL; /*!< [0x0068] GPIOH Low Byte Multiple Function Control Register */ 2140 __IO uint32_t GPH_MFPH; /*!< [0x006c] GPIOH High Byte Multiple Function Control Register */ 2141 /** @cond HIDDEN_SYMBOLS */ 2142 __I uint32_t RESERVE2[4]; 2143 /** @endcond */ 2144 __IO uint32_t GPA_MFOS; /*!< [0x0080] GPIOA Multiple Function Output Select Register */ 2145 __IO uint32_t GPB_MFOS; /*!< [0x0084] GPIOB Multiple Function Output Select Register */ 2146 __IO uint32_t GPC_MFOS; /*!< [0x0088] GPIOC Multiple Function Output Select Register */ 2147 __IO uint32_t GPD_MFOS; /*!< [0x008c] GPIOD Multiple Function Output Select Register */ 2148 __IO uint32_t GPE_MFOS; /*!< [0x0090] GPIOE Multiple Function Output Select Register */ 2149 __IO uint32_t GPF_MFOS; /*!< [0x0094] GPIOF Multiple Function Output Select Register */ 2150 __IO uint32_t GPG_MFOS; /*!< [0x0098] GPIOG Multiple Function Output Select Register */ 2151 __IO uint32_t GPH_MFOS; /*!< [0x009c] GPIOH Multiple Function Output Select Register */ 2152 /** @cond HIDDEN_SYMBOLS */ 2153 __I uint32_t RESERVE3[8]; 2154 /** @endcond */ 2155 __IO uint32_t SRAM_INTCTL; /*!< [0x00c0] System SRAM Interrupt Enable Control Register */ 2156 __IO uint32_t SRAM_STATUS; /*!< [0x00c4] System SRAM Parity Error Status Register */ 2157 __I uint32_t SRAM_ERRADDR; /*!< [0x00c8] System SRAM Parity Check Error Address Register */ 2158 /** @cond HIDDEN_SYMBOLS */ 2159 __I uint32_t RESERVE4[1]; 2160 /** @endcond */ 2161 __IO uint32_t SRAM_BISTCTL; /*!< [0x00d0] System SRAM BIST Test Control Register */ 2162 __I uint32_t SRAM_BISTSTS; /*!< [0x00d4] System SRAM BIST Test Status Register */ 2163 /** @cond HIDDEN_SYMBOLS */ 2164 __I uint32_t RESERVE5[3]; 2165 /** @endcond */ 2166 __IO uint32_t HIRCTCTL; /*!< [0x00e4] HIRC48M Trim Control Register */ 2167 __IO uint32_t HIRCTIEN; /*!< [0x00e8] HIRC48M Trim Interrupt Enable Register */ 2168 __IO uint32_t HIRCTISTS; /*!< [0x00ec] HIRC48M Trim Interrupt Status Register */ 2169 __IO uint32_t IRCTCTL; /*!< [0x00f0] HIRC Trim Control Register */ 2170 __IO uint32_t IRCTIEN; /*!< [0x00f4] HIRC Trim Interrupt Enable Register */ 2171 __IO uint32_t IRCTISTS; /*!< [0x00f8] HIRC Trim Interrupt Status Register */ 2172 /** @cond HIDDEN_SYMBOLS */ 2173 __I uint32_t RESERVE6[1]; 2174 /** @endcond */ 2175 __IO uint32_t REGLCTL; /*!< [0x0100] Register Lock Control Register */ 2176 /** @cond HIDDEN_SYMBOLS */ 2177 __I uint32_t RESERVE7[58]; 2178 /** @endcond */ 2179 __IO uint32_t PORDISAN; /*!< [0x01ec] Analog POR Disable Control Register */ 2180 /** @cond HIDDEN_SYMBOLS */ 2181 __I uint32_t RESERVE8; 2182 /** @endcond */ 2183 __I uint32_t CSERVER; /*!< [0x01f4] Chip Series Version Register */ 2184 __IO uint32_t PLCTL; /*!< [0x01f8] Power Level Control Register */ 2185 __I uint32_t PLSTS; /*!< [0x01fc] Power Level Status Register */ 2186 /** @cond HIDDEN_SYMBOLS */ 2187 __I uint32_t RESERVE9[128]; 2188 /** @endcond */ 2189 __IO uint32_t AHBMCTL; /*!< [0x0400] AHB Bus Matrix Priority Control Register */ 2190 2191 } SYS_T; 2192 2193 /** 2194 @addtogroup SYS_CONST SYS Bit Field Definition 2195 Constant Definitions for SYS Controller 2196 @{ */ 2197 2198 #define SYS_PDID_PDID_Pos (0) /*!< SYS_T::PDID: PDID Position */ 2199 #define SYS_PDID_PDID_Msk (0xfffffffful << SYS_PDID_PDID_Pos) /*!< SYS_T::PDID: PDID Mask */ 2200 2201 #define SYS_RSTSTS_PORF_Pos (0) /*!< SYS_T::RSTSTS: PORF Position */ 2202 #define SYS_RSTSTS_PORF_Msk (0x1ul << SYS_RSTSTS_PORF_Pos) /*!< SYS_T::RSTSTS: PORF Mask */ 2203 2204 #define SYS_RSTSTS_PINRF_Pos (1) /*!< SYS_T::RSTSTS: PINRF Position */ 2205 #define SYS_RSTSTS_PINRF_Msk (0x1ul << SYS_RSTSTS_PINRF_Pos) /*!< SYS_T::RSTSTS: PINRF Mask */ 2206 2207 #define SYS_RSTSTS_WDTRF_Pos (2) /*!< SYS_T::RSTSTS: WDTRF Position */ 2208 #define SYS_RSTSTS_WDTRF_Msk (0x1ul << SYS_RSTSTS_WDTRF_Pos) /*!< SYS_T::RSTSTS: WDTRF Mask */ 2209 2210 #define SYS_RSTSTS_LVRF_Pos (3) /*!< SYS_T::RSTSTS: LVRF Position */ 2211 #define SYS_RSTSTS_LVRF_Msk (0x1ul << SYS_RSTSTS_LVRF_Pos) /*!< SYS_T::RSTSTS: LVRF Mask */ 2212 2213 #define SYS_RSTSTS_BODRF_Pos (4) /*!< SYS_T::RSTSTS: BODRF Position */ 2214 #define SYS_RSTSTS_BODRF_Msk (0x1ul << SYS_RSTSTS_BODRF_Pos) /*!< SYS_T::RSTSTS: BODRF Mask */ 2215 2216 #define SYS_RSTSTS_SYSRF_Pos (5) /*!< SYS_T::RSTSTS: SYSRF Position */ 2217 #define SYS_RSTSTS_SYSRF_Msk (0x1ul << SYS_RSTSTS_SYSRF_Pos) /*!< SYS_T::RSTSTS: SYSRF Mask */ 2218 2219 #define SYS_RSTSTS_CPURF_Pos (7) /*!< SYS_T::RSTSTS: CPURF Position */ 2220 #define SYS_RSTSTS_CPURF_Msk (0x1ul << SYS_RSTSTS_CPURF_Pos) /*!< SYS_T::RSTSTS: CPURF Mask */ 2221 2222 #define SYS_RSTSTS_CPULKRF_Pos (8) /*!< SYS_T::RSTSTS: CPULKRF Position */ 2223 #define SYS_RSTSTS_CPULKRF_Msk (0x1ul << SYS_RSTSTS_CPULKRF_Pos) /*!< SYS_T::RSTSTS: CPULKRF Mask */ 2224 2225 #define SYS_IPRST0_CHIPRST_Pos (0) /*!< SYS_T::IPRST0: CHIPRST Position */ 2226 #define SYS_IPRST0_CHIPRST_Msk (0x1ul << SYS_IPRST0_CHIPRST_Pos) /*!< SYS_T::IPRST0: CHIPRST Mask */ 2227 2228 #define SYS_IPRST0_CPURST_Pos (1) /*!< SYS_T::IPRST0: CPURST Position */ 2229 #define SYS_IPRST0_CPURST_Msk (0x1ul << SYS_IPRST0_CPURST_Pos) /*!< SYS_T::IPRST0: CPURST Mask */ 2230 2231 #define SYS_IPRST0_PDMARST_Pos (2) /*!< SYS_T::IPRST0: PDMARST Position */ 2232 #define SYS_IPRST0_PDMARST_Msk (0x1ul << SYS_IPRST0_PDMARST_Pos) /*!< SYS_T::IPRST0: PDMARST Mask */ 2233 2234 #define SYS_IPRST0_EBIRST_Pos (3) /*!< SYS_T::IPRST0: EBIRST Position */ 2235 #define SYS_IPRST0_EBIRST_Msk (0x1ul << SYS_IPRST0_EBIRST_Pos) /*!< SYS_T::IPRST0: EBIRST Mask */ 2236 2237 #define SYS_IPRST0_EMACRST_Pos (5) /*!< SYS_T::IPRST0: EMACRST Position */ 2238 #define SYS_IPRST0_EMACRST_Msk (0x1ul << SYS_IPRST0_EMACRST_Pos) /*!< SYS_T::IPRST0: EMACRST Mask */ 2239 2240 #define SYS_IPRST0_SDH0RST_Pos (6) /*!< SYS_T::IPRST0: SDH0RST Position */ 2241 #define SYS_IPRST0_SDH0RST_Msk (0x1ul << SYS_IPRST0_SDH0RST_Pos) /*!< SYS_T::IPRST0: SDH0RST Mask */ 2242 2243 #define SYS_IPRST0_CRCRST_Pos (7) /*!< SYS_T::IPRST0: CRCRST Position */ 2244 #define SYS_IPRST0_CRCRST_Msk (0x1ul << SYS_IPRST0_CRCRST_Pos) /*!< SYS_T::IPRST0: CRCRST Mask */ 2245 2246 #define SYS_IPRST0_CCAPRST_Pos (8) /*!< SYS_T::IPRST0: CCAPRST Position */ 2247 #define SYS_IPRST0_CCAPRST_Msk (0x1ul << SYS_IPRST0_CCAPRST_Pos) /*!< SYS_T::IPRST0: CCAPRST Mask */ 2248 2249 #define SYS_IPRST0_HSUSBDRST_Pos (10) /*!< SYS_T::IPRST0: HSUSBDRST Position */ 2250 #define SYS_IPRST0_HSUSBDRST_Msk (0x1ul << SYS_IPRST0_HSUSBDRST_Pos) /*!< SYS_T::IPRST0: HSUSBDRST Mask */ 2251 2252 #define SYS_IPRST0_CRPTRST_Pos (12) /*!< SYS_T::IPRST0: CRPTRST Position */ 2253 #define SYS_IPRST0_CRPTRST_Msk (0x1ul << SYS_IPRST0_CRPTRST_Pos) /*!< SYS_T::IPRST0: CRPTRST Mask */ 2254 2255 #define SYS_IPRST0_SPIMRST_Pos (14) /*!< SYS_T::IPRST0: SPIMRST Position */ 2256 #define SYS_IPRST0_SPIMRST_Msk (0x1ul << SYS_IPRST0_SPIMRST_Pos) /*!< SYS_T::IPRST0: SPIMRST Mask */ 2257 2258 #define SYS_IPRST0_USBHRST_Pos (16) /*!< SYS_T::IPRST0: USBHRST Position */ 2259 #define SYS_IPRST0_USBHRST_Msk (0x1ul << SYS_IPRST0_USBHRST_Pos) /*!< SYS_T::IPRST0: USBHRST Mask */ 2260 2261 #define SYS_IPRST0_SDH1RST_Pos (17) /*!< SYS_T::IPRST0: SDH1RST Position */ 2262 #define SYS_IPRST0_SDH1RST_Msk (0x1ul << SYS_IPRST0_SDH1RST_Pos) /*!< SYS_T::IPRST0: SDH1RST Mask */ 2263 2264 #define SYS_IPRST1_GPIORST_Pos (1) /*!< SYS_T::IPRST1: GPIORST Position */ 2265 #define SYS_IPRST1_GPIORST_Msk (0x1ul << SYS_IPRST1_GPIORST_Pos) /*!< SYS_T::IPRST1: GPIORST Mask */ 2266 2267 #define SYS_IPRST1_TMR0RST_Pos (2) /*!< SYS_T::IPRST1: TMR0RST Position */ 2268 #define SYS_IPRST1_TMR0RST_Msk (0x1ul << SYS_IPRST1_TMR0RST_Pos) /*!< SYS_T::IPRST1: TMR0RST Mask */ 2269 2270 #define SYS_IPRST1_TMR1RST_Pos (3) /*!< SYS_T::IPRST1: TMR1RST Position */ 2271 #define SYS_IPRST1_TMR1RST_Msk (0x1ul << SYS_IPRST1_TMR1RST_Pos) /*!< SYS_T::IPRST1: TMR1RST Mask */ 2272 2273 #define SYS_IPRST1_TMR2RST_Pos (4) /*!< SYS_T::IPRST1: TMR2RST Position */ 2274 #define SYS_IPRST1_TMR2RST_Msk (0x1ul << SYS_IPRST1_TMR2RST_Pos) /*!< SYS_T::IPRST1: TMR2RST Mask */ 2275 2276 #define SYS_IPRST1_TMR3RST_Pos (5) /*!< SYS_T::IPRST1: TMR3RST Position */ 2277 #define SYS_IPRST1_TMR3RST_Msk (0x1ul << SYS_IPRST1_TMR3RST_Pos) /*!< SYS_T::IPRST1: TMR3RST Mask */ 2278 2279 #define SYS_IPRST1_ACMP01RST_Pos (7) /*!< SYS_T::IPRST1: ACMP01RST Position */ 2280 #define SYS_IPRST1_ACMP01RST_Msk (0x1ul << SYS_IPRST1_ACMP01RST_Pos) /*!< SYS_T::IPRST1: ACMP01RST Mask */ 2281 2282 #define SYS_IPRST1_I2C0RST_Pos (8) /*!< SYS_T::IPRST1: I2C0RST Position */ 2283 #define SYS_IPRST1_I2C0RST_Msk (0x1ul << SYS_IPRST1_I2C0RST_Pos) /*!< SYS_T::IPRST1: I2C0RST Mask */ 2284 2285 #define SYS_IPRST1_I2C1RST_Pos (9) /*!< SYS_T::IPRST1: I2C1RST Position */ 2286 #define SYS_IPRST1_I2C1RST_Msk (0x1ul << SYS_IPRST1_I2C1RST_Pos) /*!< SYS_T::IPRST1: I2C1RST Mask */ 2287 2288 #define SYS_IPRST1_I2C2RST_Pos (10) /*!< SYS_T::IPRST1: I2C2RST Position */ 2289 #define SYS_IPRST1_I2C2RST_Msk (0x1ul << SYS_IPRST1_I2C2RST_Pos) /*!< SYS_T::IPRST1: I2C2RST Mask */ 2290 2291 #define SYS_IPRST1_QSPI0RST_Pos (12) /*!< SYS_T::IPRST1: QSPI0RST Position */ 2292 #define SYS_IPRST1_QSPI0RST_Msk (0x1ul << SYS_IPRST1_QSPI0RST_Pos) /*!< SYS_T::IPRST1: QSPI0RST Mask */ 2293 2294 #define SYS_IPRST1_SPI0RST_Pos (13) /*!< SYS_T::IPRST1: SPI0RST Position */ 2295 #define SYS_IPRST1_SPI0RST_Msk (0x1ul << SYS_IPRST1_SPI0RST_Pos) /*!< SYS_T::IPRST1: SPI0RST Mask */ 2296 2297 #define SYS_IPRST1_SPI1RST_Pos (14) /*!< SYS_T::IPRST1: SPI1RST Position */ 2298 #define SYS_IPRST1_SPI1RST_Msk (0x1ul << SYS_IPRST1_SPI1RST_Pos) /*!< SYS_T::IPRST1: SPI1RST Mask */ 2299 2300 #define SYS_IPRST1_SPI2RST_Pos (15) /*!< SYS_T::IPRST1: SPI2RST Position */ 2301 #define SYS_IPRST1_SPI2RST_Msk (0x1ul << SYS_IPRST1_SPI2RST_Pos) /*!< SYS_T::IPRST1: SPI2RST Mask */ 2302 2303 #define SYS_IPRST1_UART0RST_Pos (16) /*!< SYS_T::IPRST1: UART0RST Position */ 2304 #define SYS_IPRST1_UART0RST_Msk (0x1ul << SYS_IPRST1_UART0RST_Pos) /*!< SYS_T::IPRST1: UART0RST Mask */ 2305 2306 #define SYS_IPRST1_UART1RST_Pos (17) /*!< SYS_T::IPRST1: UART1RST Position */ 2307 #define SYS_IPRST1_UART1RST_Msk (0x1ul << SYS_IPRST1_UART1RST_Pos) /*!< SYS_T::IPRST1: UART1RST Mask */ 2308 2309 #define SYS_IPRST1_UART2RST_Pos (18) /*!< SYS_T::IPRST1: UART2RST Position */ 2310 #define SYS_IPRST1_UART2RST_Msk (0x1ul << SYS_IPRST1_UART2RST_Pos) /*!< SYS_T::IPRST1: UART2RST Mask */ 2311 2312 #define SYS_IPRST1_UART3RST_Pos (19) /*!< SYS_T::IPRST1: UART3RST Position */ 2313 #define SYS_IPRST1_UART3RST_Msk (0x1ul << SYS_IPRST1_UART3RST_Pos) /*!< SYS_T::IPRST1: UART3RST Mask */ 2314 2315 #define SYS_IPRST1_UART4RST_Pos (20) /*!< SYS_T::IPRST1: UART4RST Position */ 2316 #define SYS_IPRST1_UART4RST_Msk (0x1ul << SYS_IPRST1_UART4RST_Pos) /*!< SYS_T::IPRST1: UART4RST Mask */ 2317 2318 #define SYS_IPRST1_UART5RST_Pos (21) /*!< SYS_T::IPRST1: UART5RST Position */ 2319 #define SYS_IPRST1_UART5RST_Msk (0x1ul << SYS_IPRST1_UART5RST_Pos) /*!< SYS_T::IPRST1: UART5RST Mask */ 2320 2321 #define SYS_IPRST1_UART6RST_Pos (22) /*!< SYS_T::IPRST1: UART6RST Position */ 2322 #define SYS_IPRST1_UART6RST_Msk (0x1ul << SYS_IPRST1_UART6RST_Pos) /*!< SYS_T::IPRST1: UART6RST Mask */ 2323 2324 #define SYS_IPRST1_UART7RST_Pos (23) /*!< SYS_T::IPRST1: UART7RST Position */ 2325 #define SYS_IPRST1_UART7RST_Msk (0x1ul << SYS_IPRST1_UART7RST_Pos) /*!< SYS_T::IPRST1: UART7RST Mask */ 2326 2327 #define SYS_IPRST1_CAN0RST_Pos (24) /*!< SYS_T::IPRST1: CAN0RST Position */ 2328 #define SYS_IPRST1_CAN0RST_Msk (0x1ul << SYS_IPRST1_CAN0RST_Pos) /*!< SYS_T::IPRST1: CAN0RST Mask */ 2329 2330 #define SYS_IPRST1_CAN1RST_Pos (25) /*!< SYS_T::IPRST1: CAN1RST Position */ 2331 #define SYS_IPRST1_CAN1RST_Msk (0x1ul << SYS_IPRST1_CAN1RST_Pos) /*!< SYS_T::IPRST1: CAN1RST Mask */ 2332 2333 #define SYS_IPRST1_OTGRST_Pos (26) /*!< SYS_T::IPRST1: OTGRST Position */ 2334 #define SYS_IPRST1_OTGRST_Msk (0x1ul << SYS_IPRST1_OTGRST_Pos) /*!< SYS_T::IPRST1: OTGRST Mask */ 2335 2336 #define SYS_IPRST1_USBDRST_Pos (27) /*!< SYS_T::IPRST1: USBDRST Position */ 2337 #define SYS_IPRST1_USBDRST_Msk (0x1ul << SYS_IPRST1_USBDRST_Pos) /*!< SYS_T::IPRST1: USBDRST Mask */ 2338 2339 #define SYS_IPRST1_EADCRST_Pos (28) /*!< SYS_T::IPRST1: EADCRST Position */ 2340 #define SYS_IPRST1_EADCRST_Msk (0x1ul << SYS_IPRST1_EADCRST_Pos) /*!< SYS_T::IPRST1: EADCRST Mask */ 2341 2342 #define SYS_IPRST1_I2S0RST_Pos (29) /*!< SYS_T::IPRST1: I2S0RST Position */ 2343 #define SYS_IPRST1_I2S0RST_Msk (0x1ul << SYS_IPRST1_I2S0RST_Pos) /*!< SYS_T::IPRST1: I2S0RST Mask */ 2344 2345 #define SYS_IPRST1_HSOTGRST_Pos (30) /*!< SYS_T::IPRST1: HSOTGRST Position */ 2346 #define SYS_IPRST1_HSOTGRST_Msk (0x1ul << SYS_IPRST1_HSOTGRST_Pos) /*!< SYS_T::IPRST1: HSOTGRST Mask */ 2347 2348 #define SYS_IPRST1_TRNGRST_Pos (31) /*!< SYS_T::IPRST1: TRNGRST Position */ 2349 #define SYS_IPRST1_TRNGRST_Msk (0x1ul << SYS_IPRST1_TRNGRST_Pos) /*!< SYS_T::IPRST1: TRNGRST Mask */ 2350 2351 #define SYS_IPRST2_SC0RST_Pos (0) /*!< SYS_T::IPRST2: SC0RST Position */ 2352 #define SYS_IPRST2_SC0RST_Msk (0x1ul << SYS_IPRST2_SC0RST_Pos) /*!< SYS_T::IPRST2: SC0RST Mask */ 2353 2354 #define SYS_IPRST2_SC1RST_Pos (1) /*!< SYS_T::IPRST2: SC1RST Position */ 2355 #define SYS_IPRST2_SC1RST_Msk (0x1ul << SYS_IPRST2_SC1RST_Pos) /*!< SYS_T::IPRST2: SC1RST Mask */ 2356 2357 #define SYS_IPRST2_SC2RST_Pos (2) /*!< SYS_T::IPRST2: SC2RST Position */ 2358 #define SYS_IPRST2_SC2RST_Msk (0x1ul << SYS_IPRST2_SC2RST_Pos) /*!< SYS_T::IPRST2: SC2RST Mask */ 2359 2360 #define SYS_IPRST2_QSPI1RST_Pos (4) /*!< SYS_T::IPRST2: QSPI1RST Position */ 2361 #define SYS_IPRST2_QSPI1RST_Msk (0x1ul << SYS_IPRST2_QSPI1RST_Pos) /*!< SYS_T::IPRST2: QSPI1RST Mask */ 2362 2363 #define SYS_IPRST2_SPI3RST_Pos (6) /*!< SYS_T::IPRST2: SPI3RST Position */ 2364 #define SYS_IPRST2_SPI3RST_Msk (0x1ul << SYS_IPRST2_SPI3RST_Pos) /*!< SYS_T::IPRST2: SPI3RST Mask */ 2365 2366 #define SYS_IPRST2_USCI0RST_Pos (8) /*!< SYS_T::IPRST2: USCI0RST Position */ 2367 #define SYS_IPRST2_USCI0RST_Msk (0x1ul << SYS_IPRST2_USCI0RST_Pos) /*!< SYS_T::IPRST2: USCI0RST Mask */ 2368 2369 #define SYS_IPRST2_USCI1RST_Pos (9) /*!< SYS_T::IPRST2: USCI1RST Position */ 2370 #define SYS_IPRST2_USCI1RST_Msk (0x1ul << SYS_IPRST2_USCI1RST_Pos) /*!< SYS_T::IPRST2: USCI1RST Mask */ 2371 2372 #define SYS_IPRST2_DACRST_Pos (12) /*!< SYS_T::IPRST2: DACRST Position */ 2373 #define SYS_IPRST2_DACRST_Msk (0x1ul << SYS_IPRST2_DACRST_Pos) /*!< SYS_T::IPRST2: DACRST Mask */ 2374 2375 #define SYS_IPRST2_EPWM0RST_Pos (16) /*!< SYS_T::IPRST2: EPWM0RST Position */ 2376 #define SYS_IPRST2_EPWM0RST_Msk (0x1ul << SYS_IPRST2_EPWM0RST_Pos) /*!< SYS_T::IPRST2: EPWM0RST Mask */ 2377 2378 #define SYS_IPRST2_EPWM1RST_Pos (17) /*!< SYS_T::IPRST2: EPWM1RST Position */ 2379 #define SYS_IPRST2_EPWM1RST_Msk (0x1ul << SYS_IPRST2_EPWM1RST_Pos) /*!< SYS_T::IPRST2: EPWM1RST Mask */ 2380 2381 #define SYS_IPRST2_BPWM0RST_Pos (18) /*!< SYS_T::IPRST2: BPWM0RST Position */ 2382 #define SYS_IPRST2_BPWM0RST_Msk (0x1ul << SYS_IPRST2_BPWM0RST_Pos) /*!< SYS_T::IPRST2: BPWM0RST Mask */ 2383 2384 #define SYS_IPRST2_BPWM1RST_Pos (19) /*!< SYS_T::IPRST2: BPWM1RST Position */ 2385 #define SYS_IPRST2_BPWM1RST_Msk (0x1ul << SYS_IPRST2_BPWM1RST_Pos) /*!< SYS_T::IPRST2: BPWM1RST Mask */ 2386 2387 #define SYS_IPRST2_QEI0RST_Pos (22) /*!< SYS_T::IPRST2: QEI0RST Position */ 2388 #define SYS_IPRST2_QEI0RST_Msk (0x1ul << SYS_IPRST2_QEI0RST_Pos) /*!< SYS_T::IPRST2: QEI0RST Mask */ 2389 2390 #define SYS_IPRST2_QEI1RST_Pos (23) /*!< SYS_T::IPRST2: QEI1RST Position */ 2391 #define SYS_IPRST2_QEI1RST_Msk (0x1ul << SYS_IPRST2_QEI1RST_Pos) /*!< SYS_T::IPRST2: QEI1RST Mask */ 2392 2393 #define SYS_IPRST2_ECAP0RST_Pos (26) /*!< SYS_T::IPRST2: ECAP0RST Position */ 2394 #define SYS_IPRST2_ECAP0RST_Msk (0x1ul << SYS_IPRST2_ECAP0RST_Pos) /*!< SYS_T::IPRST2: ECAP0RST Mask */ 2395 2396 #define SYS_IPRST2_ECAP1RST_Pos (27) /*!< SYS_T::IPRST2: ECAP1RST Position */ 2397 #define SYS_IPRST2_ECAP1RST_Msk (0x1ul << SYS_IPRST2_ECAP1RST_Pos) /*!< SYS_T::IPRST2: ECAP1RST Mask */ 2398 2399 #define SYS_IPRST2_CAN2RST_Pos (28) /*!< SYS_T::IPRST2: CAN2RST Position */ 2400 #define SYS_IPRST2_CAN2RST_Msk (0x1ul << SYS_IPRST2_CAN2RST_Pos) /*!< SYS_T::IPRST2: CAN2RST Mask */ 2401 2402 #define SYS_IPRST2_OPARST_Pos (30) /*!< SYS_T::IPRST2: OPARST Position */ 2403 #define SYS_IPRST2_OPARST_Msk (0x1ul << SYS_IPRST2_OPARST_Pos) /*!< SYS_T::IPRST2: OPARST Mask */ 2404 2405 #define SYS_IPRST2_EADC1RST_Pos (31) /*!< SYS_T::IPRST2: EADC1RST Position */ 2406 #define SYS_IPRST2_EADC1RST_Msk (0x1ul << SYS_IPRST2_EADC1RST_Pos) /*!< SYS_T::IPRST2: EADC1RST Mask */ 2407 2408 #define SYS_BODCTL_BODEN_Pos (0) /*!< SYS_T::BODCTL: BODEN Position */ 2409 #define SYS_BODCTL_BODEN_Msk (0x1ul << SYS_BODCTL_BODEN_Pos) /*!< SYS_T::BODCTL: BODEN Mask */ 2410 2411 #define SYS_BODCTL_BODRSTEN_Pos (3) /*!< SYS_T::BODCTL: BODRSTEN Position */ 2412 #define SYS_BODCTL_BODRSTEN_Msk (0x1ul << SYS_BODCTL_BODRSTEN_Pos) /*!< SYS_T::BODCTL: BODRSTEN Mask */ 2413 2414 #define SYS_BODCTL_BODIF_Pos (4) /*!< SYS_T::BODCTL: BODIF Position */ 2415 #define SYS_BODCTL_BODIF_Msk (0x1ul << SYS_BODCTL_BODIF_Pos) /*!< SYS_T::BODCTL: BODIF Mask */ 2416 2417 #define SYS_BODCTL_BODLPM_Pos (5) /*!< SYS_T::BODCTL: BODLPM Position */ 2418 #define SYS_BODCTL_BODLPM_Msk (0x1ul << SYS_BODCTL_BODLPM_Pos) /*!< SYS_T::BODCTL: BODLPM Mask */ 2419 2420 #define SYS_BODCTL_BODOUT_Pos (6) /*!< SYS_T::BODCTL: BODOUT Position */ 2421 #define SYS_BODCTL_BODOUT_Msk (0x1ul << SYS_BODCTL_BODOUT_Pos) /*!< SYS_T::BODCTL: BODOUT Mask */ 2422 2423 #define SYS_BODCTL_LVREN_Pos (7) /*!< SYS_T::BODCTL: LVREN Position */ 2424 #define SYS_BODCTL_LVREN_Msk (0x1ul << SYS_BODCTL_LVREN_Pos) /*!< SYS_T::BODCTL: LVREN Mask */ 2425 2426 #define SYS_BODCTL_BODDGSEL_Pos (8) /*!< SYS_T::BODCTL: BODDGSEL Position */ 2427 #define SYS_BODCTL_BODDGSEL_Msk (0x7ul << SYS_BODCTL_BODDGSEL_Pos) /*!< SYS_T::BODCTL: BODDGSEL Mask */ 2428 2429 #define SYS_BODCTL_LVRDGSEL_Pos (12) /*!< SYS_T::BODCTL: LVRDGSEL Position */ 2430 #define SYS_BODCTL_LVRDGSEL_Msk (0x7ul << SYS_BODCTL_LVRDGSEL_Pos) /*!< SYS_T::BODCTL: LVRDGSEL Mask */ 2431 2432 #define SYS_BODCTL_BODVL_Pos (16) /*!< SYS_T::BODCTL: BODVL Position */ 2433 #define SYS_BODCTL_BODVL_Msk (0x7ul << SYS_BODCTL_BODVL_Pos) /*!< SYS_T::BODCTL: BODVL Mask */ 2434 2435 #define SYS_IVSCTL_VTEMPEN_Pos (0) /*!< SYS_T::IVSCTL: VTEMPEN Position */ 2436 #define SYS_IVSCTL_VTEMPEN_Msk (0x1ul << SYS_IVSCTL_VTEMPEN_Pos) /*!< SYS_T::IVSCTL: VTEMPEN Mask */ 2437 2438 #define SYS_IVSCTL_VBATUGEN_Pos (1) /*!< SYS_T::IVSCTL: VBATUGEN Position */ 2439 #define SYS_IVSCTL_VBATUGEN_Msk (0x1ul << SYS_IVSCTL_VBATUGEN_Pos) /*!< SYS_T::IVSCTL: VBATUGEN Mask */ 2440 2441 #define SYS_PORCTL_POROFF_Pos (0) /*!< SYS_T::PORCTL: POROFF Position */ 2442 #define SYS_PORCTL_POROFF_Msk (0xfffful << SYS_PORCTL_POROFF_Pos) /*!< SYS_T::PORCTL: POROFF Mask */ 2443 2444 #define SYS_VREFCTL_VREFCTL_Pos (0) /*!< SYS_T::VREFCTL: VREFCTL Position */ 2445 #define SYS_VREFCTL_VREFCTL_Msk (0x1ful << SYS_VREFCTL_VREFCTL_Pos) /*!< SYS_T::VREFCTL: VREFCTL Mask */ 2446 2447 #define SYS_VREFCTL_PRELOAD_SEL_Pos (6) /*!< SYS_T::VREFCTL: PRELOAD_SEL Position */ 2448 #define SYS_VREFCTL_PRELOAD_SEL_Msk (0x3ul << SYS_VREFCTL_PRELOAD_SEL_Pos) /*!< SYS_T::VREFCTL: PRELOAD_SEL Mask */ 2449 2450 #define SYS_USBPHY_USBROLE_Pos (0) /*!< SYS_T::USBPHY: USBROLE Position */ 2451 #define SYS_USBPHY_USBROLE_Msk (0x3ul << SYS_USBPHY_USBROLE_Pos) /*!< SYS_T::USBPHY: USBROLE Mask */ 2452 2453 #define SYS_USBPHY_SBO_Pos (2) /*!< SYS_T::USBPHY: SBO Position */ 2454 #define SYS_USBPHY_SBO_Msk (0x1ul << SYS_USBPHY_SBO_Pos) /*!< SYS_T::USBPHY: SBO Mask */ 2455 2456 #define SYS_USBPHY_USBEN_Pos (8) /*!< SYS_T::USBPHY: USBEN Position */ 2457 #define SYS_USBPHY_USBEN_Msk (0x1ul << SYS_USBPHY_USBEN_Pos) /*!< SYS_T::USBPHY: USBEN Mask */ 2458 2459 #define SYS_USBPHY_HSUSBROLE_Pos (16) /*!< SYS_T::USBPHY: HSUSBROLE Position */ 2460 #define SYS_USBPHY_HSUSBROLE_Msk (0x3ul << SYS_USBPHY_HSUSBROLE_Pos) /*!< SYS_T::USBPHY: HSUSBROLE Mask */ 2461 2462 #define SYS_USBPHY_HSUSBEN_Pos (24) /*!< SYS_T::USBPHY: HSUSBEN Position */ 2463 #define SYS_USBPHY_HSUSBEN_Msk (0x1ul << SYS_USBPHY_HSUSBEN_Pos) /*!< SYS_T::USBPHY: HSUSBEN Mask */ 2464 2465 #define SYS_USBPHY_HSUSBACT_Pos (25) /*!< SYS_T::USBPHY: HSUSBACT Position */ 2466 #define SYS_USBPHY_HSUSBACT_Msk (0x1ul << SYS_USBPHY_HSUSBACT_Pos) /*!< SYS_T::USBPHY: HSUSBACT Mask */ 2467 2468 #define SYS_GPA_MFPL_PA0MFP_Pos (0) /*!< SYS_T::GPA_MFPL: PA0MFP Position */ 2469 #define SYS_GPA_MFPL_PA0MFP_Msk (0xful << SYS_GPA_MFPL_PA0MFP_Pos) /*!< SYS_T::GPA_MFPL: PA0MFP Mask */ 2470 2471 #define SYS_GPA_MFPL_PA1MFP_Pos (4) /*!< SYS_T::GPA_MFPL: PA1MFP Position */ 2472 #define SYS_GPA_MFPL_PA1MFP_Msk (0xful << SYS_GPA_MFPL_PA1MFP_Pos) /*!< SYS_T::GPA_MFPL: PA1MFP Mask */ 2473 2474 #define SYS_GPA_MFPL_PA2MFP_Pos (8) /*!< SYS_T::GPA_MFPL: PA2MFP Position */ 2475 #define SYS_GPA_MFPL_PA2MFP_Msk (0xful << SYS_GPA_MFPL_PA2MFP_Pos) /*!< SYS_T::GPA_MFPL: PA2MFP Mask */ 2476 2477 #define SYS_GPA_MFPL_PA3MFP_Pos (12) /*!< SYS_T::GPA_MFPL: PA3MFP Position */ 2478 #define SYS_GPA_MFPL_PA3MFP_Msk (0xful << SYS_GPA_MFPL_PA3MFP_Pos) /*!< SYS_T::GPA_MFPL: PA3MFP Mask */ 2479 2480 #define SYS_GPA_MFPL_PA4MFP_Pos (16) /*!< SYS_T::GPA_MFPL: PA4MFP Position */ 2481 #define SYS_GPA_MFPL_PA4MFP_Msk (0xful << SYS_GPA_MFPL_PA4MFP_Pos) /*!< SYS_T::GPA_MFPL: PA4MFP Mask */ 2482 2483 #define SYS_GPA_MFPL_PA5MFP_Pos (20) /*!< SYS_T::GPA_MFPL: PA5MFP Position */ 2484 #define SYS_GPA_MFPL_PA5MFP_Msk (0xful << SYS_GPA_MFPL_PA5MFP_Pos) /*!< SYS_T::GPA_MFPL: PA5MFP Mask */ 2485 2486 #define SYS_GPA_MFPL_PA6MFP_Pos (24) /*!< SYS_T::GPA_MFPL: PA6MFP Position */ 2487 #define SYS_GPA_MFPL_PA6MFP_Msk (0xful << SYS_GPA_MFPL_PA6MFP_Pos) /*!< SYS_T::GPA_MFPL: PA6MFP Mask */ 2488 2489 #define SYS_GPA_MFPL_PA7MFP_Pos (28) /*!< SYS_T::GPA_MFPL: PA7MFP Position */ 2490 #define SYS_GPA_MFPL_PA7MFP_Msk (0xful << SYS_GPA_MFPL_PA7MFP_Pos) /*!< SYS_T::GPA_MFPL: PA7MFP Mask */ 2491 2492 #define SYS_GPA_MFPH_PA8MFP_Pos (0) /*!< SYS_T::GPA_MFPH: PA8MFP Position */ 2493 #define SYS_GPA_MFPH_PA8MFP_Msk (0xful << SYS_GPA_MFPH_PA8MFP_Pos) /*!< SYS_T::GPA_MFPH: PA8MFP Mask */ 2494 2495 #define SYS_GPA_MFPH_PA9MFP_Pos (4) /*!< SYS_T::GPA_MFPH: PA9MFP Position */ 2496 #define SYS_GPA_MFPH_PA9MFP_Msk (0xful << SYS_GPA_MFPH_PA9MFP_Pos) /*!< SYS_T::GPA_MFPH: PA9MFP Mask */ 2497 2498 #define SYS_GPA_MFPH_PA10MFP_Pos (8) /*!< SYS_T::GPA_MFPH: PA10MFP Position */ 2499 #define SYS_GPA_MFPH_PA10MFP_Msk (0xful << SYS_GPA_MFPH_PA10MFP_Pos) /*!< SYS_T::GPA_MFPH: PA10MFP Mask */ 2500 2501 #define SYS_GPA_MFPH_PA11MFP_Pos (12) /*!< SYS_T::GPA_MFPH: PA11MFP Position */ 2502 #define SYS_GPA_MFPH_PA11MFP_Msk (0xful << SYS_GPA_MFPH_PA11MFP_Pos) /*!< SYS_T::GPA_MFPH: PA11MFP Mask */ 2503 2504 #define SYS_GPA_MFPH_PA12MFP_Pos (16) /*!< SYS_T::GPA_MFPH: PA12MFP Position */ 2505 #define SYS_GPA_MFPH_PA12MFP_Msk (0xful << SYS_GPA_MFPH_PA12MFP_Pos) /*!< SYS_T::GPA_MFPH: PA12MFP Mask */ 2506 2507 #define SYS_GPA_MFPH_PA13MFP_Pos (20) /*!< SYS_T::GPA_MFPH: PA13MFP Position */ 2508 #define SYS_GPA_MFPH_PA13MFP_Msk (0xful << SYS_GPA_MFPH_PA13MFP_Pos) /*!< SYS_T::GPA_MFPH: PA13MFP Mask */ 2509 2510 #define SYS_GPA_MFPH_PA14MFP_Pos (24) /*!< SYS_T::GPA_MFPH: PA14MFP Position */ 2511 #define SYS_GPA_MFPH_PA14MFP_Msk (0xful << SYS_GPA_MFPH_PA14MFP_Pos) /*!< SYS_T::GPA_MFPH: PA14MFP Mask */ 2512 2513 #define SYS_GPA_MFPH_PA15MFP_Pos (28) /*!< SYS_T::GPA_MFPH: PA15MFP Position */ 2514 #define SYS_GPA_MFPH_PA15MFP_Msk (0xful << SYS_GPA_MFPH_PA15MFP_Pos) /*!< SYS_T::GPA_MFPH: PA15MFP Mask */ 2515 2516 #define SYS_GPB_MFPL_PB0MFP_Pos (0) /*!< SYS_T::GPB_MFPL: PB0MFP Position */ 2517 #define SYS_GPB_MFPL_PB0MFP_Msk (0xful << SYS_GPB_MFPL_PB0MFP_Pos) /*!< SYS_T::GPB_MFPL: PB0MFP Mask */ 2518 2519 #define SYS_GPB_MFPL_PB1MFP_Pos (4) /*!< SYS_T::GPB_MFPL: PB1MFP Position */ 2520 #define SYS_GPB_MFPL_PB1MFP_Msk (0xful << SYS_GPB_MFPL_PB1MFP_Pos) /*!< SYS_T::GPB_MFPL: PB1MFP Mask */ 2521 2522 #define SYS_GPB_MFPL_PB2MFP_Pos (8) /*!< SYS_T::GPB_MFPL: PB2MFP Position */ 2523 #define SYS_GPB_MFPL_PB2MFP_Msk (0xful << SYS_GPB_MFPL_PB2MFP_Pos) /*!< SYS_T::GPB_MFPL: PB2MFP Mask */ 2524 2525 #define SYS_GPB_MFPL_PB3MFP_Pos (12) /*!< SYS_T::GPB_MFPL: PB3MFP Position */ 2526 #define SYS_GPB_MFPL_PB3MFP_Msk (0xful << SYS_GPB_MFPL_PB3MFP_Pos) /*!< SYS_T::GPB_MFPL: PB3MFP Mask */ 2527 2528 #define SYS_GPB_MFPL_PB4MFP_Pos (16) /*!< SYS_T::GPB_MFPL: PB4MFP Position */ 2529 #define SYS_GPB_MFPL_PB4MFP_Msk (0xful << SYS_GPB_MFPL_PB4MFP_Pos) /*!< SYS_T::GPB_MFPL: PB4MFP Mask */ 2530 2531 #define SYS_GPB_MFPL_PB5MFP_Pos (20) /*!< SYS_T::GPB_MFPL: PB5MFP Position */ 2532 #define SYS_GPB_MFPL_PB5MFP_Msk (0xful << SYS_GPB_MFPL_PB5MFP_Pos) /*!< SYS_T::GPB_MFPL: PB5MFP Mask */ 2533 2534 #define SYS_GPB_MFPL_PB6MFP_Pos (24) /*!< SYS_T::GPB_MFPL: PB6MFP Position */ 2535 #define SYS_GPB_MFPL_PB6MFP_Msk (0xful << SYS_GPB_MFPL_PB6MFP_Pos) /*!< SYS_T::GPB_MFPL: PB6MFP Mask */ 2536 2537 #define SYS_GPB_MFPL_PB7MFP_Pos (28) /*!< SYS_T::GPB_MFPL: PB7MFP Position */ 2538 #define SYS_GPB_MFPL_PB7MFP_Msk (0xful << SYS_GPB_MFPL_PB7MFP_Pos) /*!< SYS_T::GPB_MFPL: PB7MFP Mask */ 2539 2540 #define SYS_GPB_MFPH_PB8MFP_Pos (0) /*!< SYS_T::GPB_MFPH: PB8MFP Position */ 2541 #define SYS_GPB_MFPH_PB8MFP_Msk (0xful << SYS_GPB_MFPH_PB8MFP_Pos) /*!< SYS_T::GPB_MFPH: PB8MFP Mask */ 2542 2543 #define SYS_GPB_MFPH_PB9MFP_Pos (4) /*!< SYS_T::GPB_MFPH: PB9MFP Position */ 2544 #define SYS_GPB_MFPH_PB9MFP_Msk (0xful << SYS_GPB_MFPH_PB9MFP_Pos) /*!< SYS_T::GPB_MFPH: PB9MFP Mask */ 2545 2546 #define SYS_GPB_MFPH_PB10MFP_Pos (8) /*!< SYS_T::GPB_MFPH: PB10MFP Position */ 2547 #define SYS_GPB_MFPH_PB10MFP_Msk (0xful << SYS_GPB_MFPH_PB10MFP_Pos) /*!< SYS_T::GPB_MFPH: PB10MFP Mask */ 2548 2549 #define SYS_GPB_MFPH_PB11MFP_Pos (12) /*!< SYS_T::GPB_MFPH: PB11MFP Position */ 2550 #define SYS_GPB_MFPH_PB11MFP_Msk (0xful << SYS_GPB_MFPH_PB11MFP_Pos) /*!< SYS_T::GPB_MFPH: PB11MFP Mask */ 2551 2552 #define SYS_GPB_MFPH_PB12MFP_Pos (16) /*!< SYS_T::GPB_MFPH: PB12MFP Position */ 2553 #define SYS_GPB_MFPH_PB12MFP_Msk (0xful << SYS_GPB_MFPH_PB12MFP_Pos) /*!< SYS_T::GPB_MFPH: PB12MFP Mask */ 2554 2555 #define SYS_GPB_MFPH_PB13MFP_Pos (20) /*!< SYS_T::GPB_MFPH: PB13MFP Position */ 2556 #define SYS_GPB_MFPH_PB13MFP_Msk (0xful << SYS_GPB_MFPH_PB13MFP_Pos) /*!< SYS_T::GPB_MFPH: PB13MFP Mask */ 2557 2558 #define SYS_GPB_MFPH_PB14MFP_Pos (24) /*!< SYS_T::GPB_MFPH: PB14MFP Position */ 2559 #define SYS_GPB_MFPH_PB14MFP_Msk (0xful << SYS_GPB_MFPH_PB14MFP_Pos) /*!< SYS_T::GPB_MFPH: PB14MFP Mask */ 2560 2561 #define SYS_GPB_MFPH_PB15MFP_Pos (28) /*!< SYS_T::GPB_MFPH: PB15MFP Position */ 2562 #define SYS_GPB_MFPH_PB15MFP_Msk (0xful << SYS_GPB_MFPH_PB15MFP_Pos) /*!< SYS_T::GPB_MFPH: PB15MFP Mask */ 2563 2564 #define SYS_GPC_MFPL_PC0MFP_Pos (0) /*!< SYS_T::GPC_MFPL: PC0MFP Position */ 2565 #define SYS_GPC_MFPL_PC0MFP_Msk (0xful << SYS_GPC_MFPL_PC0MFP_Pos) /*!< SYS_T::GPC_MFPL: PC0MFP Mask */ 2566 2567 #define SYS_GPC_MFPL_PC1MFP_Pos (4) /*!< SYS_T::GPC_MFPL: PC1MFP Position */ 2568 #define SYS_GPC_MFPL_PC1MFP_Msk (0xful << SYS_GPC_MFPL_PC1MFP_Pos) /*!< SYS_T::GPC_MFPL: PC1MFP Mask */ 2569 2570 #define SYS_GPC_MFPL_PC2MFP_Pos (8) /*!< SYS_T::GPC_MFPL: PC2MFP Position */ 2571 #define SYS_GPC_MFPL_PC2MFP_Msk (0xful << SYS_GPC_MFPL_PC2MFP_Pos) /*!< SYS_T::GPC_MFPL: PC2MFP Mask */ 2572 2573 #define SYS_GPC_MFPL_PC3MFP_Pos (12) /*!< SYS_T::GPC_MFPL: PC3MFP Position */ 2574 #define SYS_GPC_MFPL_PC3MFP_Msk (0xful << SYS_GPC_MFPL_PC3MFP_Pos) /*!< SYS_T::GPC_MFPL: PC3MFP Mask */ 2575 2576 #define SYS_GPC_MFPL_PC4MFP_Pos (16) /*!< SYS_T::GPC_MFPL: PC4MFP Position */ 2577 #define SYS_GPC_MFPL_PC4MFP_Msk (0xful << SYS_GPC_MFPL_PC4MFP_Pos) /*!< SYS_T::GPC_MFPL: PC4MFP Mask */ 2578 2579 #define SYS_GPC_MFPL_PC5MFP_Pos (20) /*!< SYS_T::GPC_MFPL: PC5MFP Position */ 2580 #define SYS_GPC_MFPL_PC5MFP_Msk (0xful << SYS_GPC_MFPL_PC5MFP_Pos) /*!< SYS_T::GPC_MFPL: PC5MFP Mask */ 2581 2582 #define SYS_GPC_MFPL_PC6MFP_Pos (24) /*!< SYS_T::GPC_MFPL: PC6MFP Position */ 2583 #define SYS_GPC_MFPL_PC6MFP_Msk (0xful << SYS_GPC_MFPL_PC6MFP_Pos) /*!< SYS_T::GPC_MFPL: PC6MFP Mask */ 2584 2585 #define SYS_GPC_MFPL_PC7MFP_Pos (28) /*!< SYS_T::GPC_MFPL: PC7MFP Position */ 2586 #define SYS_GPC_MFPL_PC7MFP_Msk (0xful << SYS_GPC_MFPL_PC7MFP_Pos) /*!< SYS_T::GPC_MFPL: PC7MFP Mask */ 2587 2588 #define SYS_GPC_MFPH_PC8MFP_Pos (0) /*!< SYS_T::GPC_MFPH: PC8MFP Position */ 2589 #define SYS_GPC_MFPH_PC8MFP_Msk (0xful << SYS_GPC_MFPH_PC8MFP_Pos) /*!< SYS_T::GPC_MFPH: PC8MFP Mask */ 2590 2591 #define SYS_GPC_MFPH_PC9MFP_Pos (4) /*!< SYS_T::GPC_MFPH: PC9MFP Position */ 2592 #define SYS_GPC_MFPH_PC9MFP_Msk (0xful << SYS_GPC_MFPH_PC9MFP_Pos) /*!< SYS_T::GPC_MFPH: PC9MFP Mask */ 2593 2594 #define SYS_GPC_MFPH_PC10MFP_Pos (8) /*!< SYS_T::GPC_MFPH: PC10MFP Position */ 2595 #define SYS_GPC_MFPH_PC10MFP_Msk (0xful << SYS_GPC_MFPH_PC10MFP_Pos) /*!< SYS_T::GPC_MFPH: PC10MFP Mask */ 2596 2597 #define SYS_GPC_MFPH_PC11MFP_Pos (12) /*!< SYS_T::GPC_MFPH: PC11MFP Position */ 2598 #define SYS_GPC_MFPH_PC11MFP_Msk (0xful << SYS_GPC_MFPH_PC11MFP_Pos) /*!< SYS_T::GPC_MFPH: PC11MFP Mask */ 2599 2600 #define SYS_GPC_MFPH_PC12MFP_Pos (16) /*!< SYS_T::GPC_MFPH: PC12MFP Position */ 2601 #define SYS_GPC_MFPH_PC12MFP_Msk (0xful << SYS_GPC_MFPH_PC12MFP_Pos) /*!< SYS_T::GPC_MFPH: PC12MFP Mask */ 2602 2603 #define SYS_GPC_MFPH_PC13MFP_Pos (20) /*!< SYS_T::GPC_MFPH: PC13MFP Position */ 2604 #define SYS_GPC_MFPH_PC13MFP_Msk (0xful << SYS_GPC_MFPH_PC13MFP_Pos) /*!< SYS_T::GPC_MFPH: PC13MFP Mask */ 2605 2606 #define SYS_GPC_MFPH_PC14MFP_Pos (24) /*!< SYS_T::GPC_MFPH: PC14MFP Position */ 2607 #define SYS_GPC_MFPH_PC14MFP_Msk (0xful << SYS_GPC_MFPH_PC14MFP_Pos) /*!< SYS_T::GPC_MFPH: PC14MFP Mask */ 2608 2609 #define SYS_GPC_MFPH_PC15MFP_Pos (28) /*!< SYS_T::GPC_MFPH: PC15MFP Position */ 2610 #define SYS_GPC_MFPH_PC15MFP_Msk (0xful << SYS_GPC_MFPH_PC15MFP_Pos) /*!< SYS_T::GPC_MFPH: PC15MFP Mask */ 2611 2612 #define SYS_GPD_MFPL_PD0MFP_Pos (0) /*!< SYS_T::GPD_MFPL: PD0MFP Position */ 2613 #define SYS_GPD_MFPL_PD0MFP_Msk (0xful << SYS_GPD_MFPL_PD0MFP_Pos) /*!< SYS_T::GPD_MFPL: PD0MFP Mask */ 2614 2615 #define SYS_GPD_MFPL_PD1MFP_Pos (4) /*!< SYS_T::GPD_MFPL: PD1MFP Position */ 2616 #define SYS_GPD_MFPL_PD1MFP_Msk (0xful << SYS_GPD_MFPL_PD1MFP_Pos) /*!< SYS_T::GPD_MFPL: PD1MFP Mask */ 2617 2618 #define SYS_GPD_MFPL_PD2MFP_Pos (8) /*!< SYS_T::GPD_MFPL: PD2MFP Position */ 2619 #define SYS_GPD_MFPL_PD2MFP_Msk (0xful << SYS_GPD_MFPL_PD2MFP_Pos) /*!< SYS_T::GPD_MFPL: PD2MFP Mask */ 2620 2621 #define SYS_GPD_MFPL_PD3MFP_Pos (12) /*!< SYS_T::GPD_MFPL: PD3MFP Position */ 2622 #define SYS_GPD_MFPL_PD3MFP_Msk (0xful << SYS_GPD_MFPL_PD3MFP_Pos) /*!< SYS_T::GPD_MFPL: PD3MFP Mask */ 2623 2624 #define SYS_GPD_MFPL_PD4MFP_Pos (16) /*!< SYS_T::GPD_MFPL: PD4MFP Position */ 2625 #define SYS_GPD_MFPL_PD4MFP_Msk (0xful << SYS_GPD_MFPL_PD4MFP_Pos) /*!< SYS_T::GPD_MFPL: PD4MFP Mask */ 2626 2627 #define SYS_GPD_MFPL_PD5MFP_Pos (20) /*!< SYS_T::GPD_MFPL: PD5MFP Position */ 2628 #define SYS_GPD_MFPL_PD5MFP_Msk (0xful << SYS_GPD_MFPL_PD5MFP_Pos) /*!< SYS_T::GPD_MFPL: PD5MFP Mask */ 2629 2630 #define SYS_GPD_MFPL_PD6MFP_Pos (24) /*!< SYS_T::GPD_MFPL: PD6MFP Position */ 2631 #define SYS_GPD_MFPL_PD6MFP_Msk (0xful << SYS_GPD_MFPL_PD6MFP_Pos) /*!< SYS_T::GPD_MFPL: PD6MFP Mask */ 2632 2633 #define SYS_GPD_MFPL_PD7MFP_Pos (28) /*!< SYS_T::GPD_MFPL: PD7MFP Position */ 2634 #define SYS_GPD_MFPL_PD7MFP_Msk (0xful << SYS_GPD_MFPL_PD7MFP_Pos) /*!< SYS_T::GPD_MFPL: PD7MFP Mask */ 2635 2636 #define SYS_GPD_MFPH_PD8MFP_Pos (0) /*!< SYS_T::GPD_MFPH: PD8MFP Position */ 2637 #define SYS_GPD_MFPH_PD8MFP_Msk (0xful << SYS_GPD_MFPH_PD8MFP_Pos) /*!< SYS_T::GPD_MFPH: PD8MFP Mask */ 2638 2639 #define SYS_GPD_MFPH_PD9MFP_Pos (4) /*!< SYS_T::GPD_MFPH: PD9MFP Position */ 2640 #define SYS_GPD_MFPH_PD9MFP_Msk (0xful << SYS_GPD_MFPH_PD9MFP_Pos) /*!< SYS_T::GPD_MFPH: PD9MFP Mask */ 2641 2642 #define SYS_GPD_MFPH_PD10MFP_Pos (8) /*!< SYS_T::GPD_MFPH: PD10MFP Position */ 2643 #define SYS_GPD_MFPH_PD10MFP_Msk (0xful << SYS_GPD_MFPH_PD10MFP_Pos) /*!< SYS_T::GPD_MFPH: PD10MFP Mask */ 2644 2645 #define SYS_GPD_MFPH_PD11MFP_Pos (12) /*!< SYS_T::GPD_MFPH: PD11MFP Position */ 2646 #define SYS_GPD_MFPH_PD11MFP_Msk (0xful << SYS_GPD_MFPH_PD11MFP_Pos) /*!< SYS_T::GPD_MFPH: PD11MFP Mask */ 2647 2648 #define SYS_GPD_MFPH_PD12MFP_Pos (16) /*!< SYS_T::GPD_MFPH: PD12MFP Position */ 2649 #define SYS_GPD_MFPH_PD12MFP_Msk (0xful << SYS_GPD_MFPH_PD12MFP_Pos) /*!< SYS_T::GPD_MFPH: PD12MFP Mask */ 2650 2651 #define SYS_GPD_MFPH_PD13MFP_Pos (20) /*!< SYS_T::GPD_MFPH: PD13MFP Position */ 2652 #define SYS_GPD_MFPH_PD13MFP_Msk (0xful << SYS_GPD_MFPH_PD13MFP_Pos) /*!< SYS_T::GPD_MFPH: PD13MFP Mask */ 2653 2654 #define SYS_GPD_MFPH_PD14MFP_Pos (24) /*!< SYS_T::GPD_MFPH: PD14MFP Position */ 2655 #define SYS_GPD_MFPH_PD14MFP_Msk (0xful << SYS_GPD_MFPH_PD14MFP_Pos) /*!< SYS_T::GPD_MFPH: PD14MFP Mask */ 2656 2657 #define SYS_GPD_MFPH_PD15MFP_Pos (28) /*!< SYS_T::GPD_MFPH: PD15MFP Position */ 2658 #define SYS_GPD_MFPH_PD15MFP_Msk (0xful << SYS_GPD_MFPH_PD15MFP_Pos) /*!< SYS_T::GPD_MFPH: PD15MFP Mask */ 2659 2660 #define SYS_GPE_MFPL_PE0MFP_Pos (0) /*!< SYS_T::GPE_MFPL: PE0MFP Position */ 2661 #define SYS_GPE_MFPL_PE0MFP_Msk (0xful << SYS_GPE_MFPL_PE0MFP_Pos) /*!< SYS_T::GPE_MFPL: PE0MFP Mask */ 2662 2663 #define SYS_GPE_MFPL_PE1MFP_Pos (4) /*!< SYS_T::GPE_MFPL: PE1MFP Position */ 2664 #define SYS_GPE_MFPL_PE1MFP_Msk (0xful << SYS_GPE_MFPL_PE1MFP_Pos) /*!< SYS_T::GPE_MFPL: PE1MFP Mask */ 2665 2666 #define SYS_GPE_MFPL_PE2MFP_Pos (8) /*!< SYS_T::GPE_MFPL: PE2MFP Position */ 2667 #define SYS_GPE_MFPL_PE2MFP_Msk (0xful << SYS_GPE_MFPL_PE2MFP_Pos) /*!< SYS_T::GPE_MFPL: PE2MFP Mask */ 2668 2669 #define SYS_GPE_MFPL_PE3MFP_Pos (12) /*!< SYS_T::GPE_MFPL: PE3MFP Position */ 2670 #define SYS_GPE_MFPL_PE3MFP_Msk (0xful << SYS_GPE_MFPL_PE3MFP_Pos) /*!< SYS_T::GPE_MFPL: PE3MFP Mask */ 2671 2672 #define SYS_GPE_MFPL_PE4MFP_Pos (16) /*!< SYS_T::GPE_MFPL: PE4MFP Position */ 2673 #define SYS_GPE_MFPL_PE4MFP_Msk (0xful << SYS_GPE_MFPL_PE4MFP_Pos) /*!< SYS_T::GPE_MFPL: PE4MFP Mask */ 2674 2675 #define SYS_GPE_MFPL_PE5MFP_Pos (20) /*!< SYS_T::GPE_MFPL: PE5MFP Position */ 2676 #define SYS_GPE_MFPL_PE5MFP_Msk (0xful << SYS_GPE_MFPL_PE5MFP_Pos) /*!< SYS_T::GPE_MFPL: PE5MFP Mask */ 2677 2678 #define SYS_GPE_MFPL_PE6MFP_Pos (24) /*!< SYS_T::GPE_MFPL: PE6MFP Position */ 2679 #define SYS_GPE_MFPL_PE6MFP_Msk (0xful << SYS_GPE_MFPL_PE6MFP_Pos) /*!< SYS_T::GPE_MFPL: PE6MFP Mask */ 2680 2681 #define SYS_GPE_MFPL_PE7MFP_Pos (28) /*!< SYS_T::GPE_MFPL: PE7MFP Position */ 2682 #define SYS_GPE_MFPL_PE7MFP_Msk (0xful << SYS_GPE_MFPL_PE7MFP_Pos) /*!< SYS_T::GPE_MFPL: PE7MFP Mask */ 2683 2684 #define SYS_GPE_MFPH_PE8MFP_Pos (0) /*!< SYS_T::GPE_MFPH: PE8MFP Position */ 2685 #define SYS_GPE_MFPH_PE8MFP_Msk (0xful << SYS_GPE_MFPH_PE8MFP_Pos) /*!< SYS_T::GPE_MFPH: PE8MFP Mask */ 2686 2687 #define SYS_GPE_MFPH_PE9MFP_Pos (4) /*!< SYS_T::GPE_MFPH: PE9MFP Position */ 2688 #define SYS_GPE_MFPH_PE9MFP_Msk (0xful << SYS_GPE_MFPH_PE9MFP_Pos) /*!< SYS_T::GPE_MFPH: PE9MFP Mask */ 2689 2690 #define SYS_GPE_MFPH_PE10MFP_Pos (8) /*!< SYS_T::GPE_MFPH: PE10MFP Position */ 2691 #define SYS_GPE_MFPH_PE10MFP_Msk (0xful << SYS_GPE_MFPH_PE10MFP_Pos) /*!< SYS_T::GPE_MFPH: PE10MFP Mask */ 2692 2693 #define SYS_GPE_MFPH_PE11MFP_Pos (12) /*!< SYS_T::GPE_MFPH: PE11MFP Position */ 2694 #define SYS_GPE_MFPH_PE11MFP_Msk (0xful << SYS_GPE_MFPH_PE11MFP_Pos) /*!< SYS_T::GPE_MFPH: PE11MFP Mask */ 2695 2696 #define SYS_GPE_MFPH_PE12MFP_Pos (16) /*!< SYS_T::GPE_MFPH: PE12MFP Position */ 2697 #define SYS_GPE_MFPH_PE12MFP_Msk (0xful << SYS_GPE_MFPH_PE12MFP_Pos) /*!< SYS_T::GPE_MFPH: PE12MFP Mask */ 2698 2699 #define SYS_GPE_MFPH_PE13MFP_Pos (20) /*!< SYS_T::GPE_MFPH: PE13MFP Position */ 2700 #define SYS_GPE_MFPH_PE13MFP_Msk (0xful << SYS_GPE_MFPH_PE13MFP_Pos) /*!< SYS_T::GPE_MFPH: PE13MFP Mask */ 2701 2702 #define SYS_GPE_MFPH_PE14MFP_Pos (24) /*!< SYS_T::GPE_MFPH: PE14MFP Position */ 2703 #define SYS_GPE_MFPH_PE14MFP_Msk (0xful << SYS_GPE_MFPH_PE14MFP_Pos) /*!< SYS_T::GPE_MFPH: PE14MFP Mask */ 2704 2705 #define SYS_GPE_MFPH_PE15MFP_Pos (28) /*!< SYS_T::GPE_MFPH: PE15MFP Position */ 2706 #define SYS_GPE_MFPH_PE15MFP_Msk (0xful << SYS_GPE_MFPH_PE15MFP_Pos) /*!< SYS_T::GPE_MFPH: PE15MFP Mask */ 2707 2708 #define SYS_GPF_MFPL_PF0MFP_Pos (0) /*!< SYS_T::GPF_MFPL: PF0MFP Position */ 2709 #define SYS_GPF_MFPL_PF0MFP_Msk (0xful << SYS_GPF_MFPL_PF0MFP_Pos) /*!< SYS_T::GPF_MFPL: PF0MFP Mask */ 2710 2711 #define SYS_GPF_MFPL_PF1MFP_Pos (4) /*!< SYS_T::GPF_MFPL: PF1MFP Position */ 2712 #define SYS_GPF_MFPL_PF1MFP_Msk (0xful << SYS_GPF_MFPL_PF1MFP_Pos) /*!< SYS_T::GPF_MFPL: PF1MFP Mask */ 2713 2714 #define SYS_GPF_MFPL_PF2MFP_Pos (8) /*!< SYS_T::GPF_MFPL: PF2MFP Position */ 2715 #define SYS_GPF_MFPL_PF2MFP_Msk (0xful << SYS_GPF_MFPL_PF2MFP_Pos) /*!< SYS_T::GPF_MFPL: PF2MFP Mask */ 2716 2717 #define SYS_GPF_MFPL_PF3MFP_Pos (12) /*!< SYS_T::GPF_MFPL: PF3MFP Position */ 2718 #define SYS_GPF_MFPL_PF3MFP_Msk (0xful << SYS_GPF_MFPL_PF3MFP_Pos) /*!< SYS_T::GPF_MFPL: PF3MFP Mask */ 2719 2720 #define SYS_GPF_MFPL_PF4MFP_Pos (16) /*!< SYS_T::GPF_MFPL: PF4MFP Position */ 2721 #define SYS_GPF_MFPL_PF4MFP_Msk (0xful << SYS_GPF_MFPL_PF4MFP_Pos) /*!< SYS_T::GPF_MFPL: PF4MFP Mask */ 2722 2723 #define SYS_GPF_MFPL_PF5MFP_Pos (20) /*!< SYS_T::GPF_MFPL: PF5MFP Position */ 2724 #define SYS_GPF_MFPL_PF5MFP_Msk (0xful << SYS_GPF_MFPL_PF5MFP_Pos) /*!< SYS_T::GPF_MFPL: PF5MFP Mask */ 2725 2726 #define SYS_GPF_MFPL_PF6MFP_Pos (24) /*!< SYS_T::GPF_MFPL: PF6MFP Position */ 2727 #define SYS_GPF_MFPL_PF6MFP_Msk (0xful << SYS_GPF_MFPL_PF6MFP_Pos) /*!< SYS_T::GPF_MFPL: PF6MFP Mask */ 2728 2729 #define SYS_GPF_MFPL_PF7MFP_Pos (28) /*!< SYS_T::GPF_MFPL: PF7MFP Position */ 2730 #define SYS_GPF_MFPL_PF7MFP_Msk (0xful << SYS_GPF_MFPL_PF7MFP_Pos) /*!< SYS_T::GPF_MFPL: PF7MFP Mask */ 2731 2732 #define SYS_GPF_MFPH_PF8MFP_Pos (0) /*!< SYS_T::GPF_MFPH: PF8MFP Position */ 2733 #define SYS_GPF_MFPH_PF8MFP_Msk (0xful << SYS_GPF_MFPH_PF8MFP_Pos) /*!< SYS_T::GPF_MFPH: PF8MFP Mask */ 2734 2735 #define SYS_GPF_MFPH_PF9MFP_Pos (4) /*!< SYS_T::GPF_MFPH: PF9MFP Position */ 2736 #define SYS_GPF_MFPH_PF9MFP_Msk (0xful << SYS_GPF_MFPH_PF9MFP_Pos) /*!< SYS_T::GPF_MFPH: PF9MFP Mask */ 2737 2738 #define SYS_GPF_MFPH_PF10MFP_Pos (8) /*!< SYS_T::GPF_MFPH: PF10MFP Position */ 2739 #define SYS_GPF_MFPH_PF10MFP_Msk (0xful << SYS_GPF_MFPH_PF10MFP_Pos) /*!< SYS_T::GPF_MFPH: PF10MFP Mask */ 2740 2741 #define SYS_GPF_MFPH_PF11MFP_Pos (12) /*!< SYS_T::GPF_MFPH: PF11MFP Position */ 2742 #define SYS_GPF_MFPH_PF11MFP_Msk (0xful << SYS_GPF_MFPH_PF11MFP_Pos) /*!< SYS_T::GPF_MFPH: PF11MFP Mask */ 2743 2744 #define SYS_GPF_MFPH_PF12MFP_Pos (16) /*!< SYS_T::GPF_MFPH: PF12MFP Position */ 2745 #define SYS_GPF_MFPH_PF12MFP_Msk (0xful << SYS_GPF_MFPH_PF12MFP_Pos) /*!< SYS_T::GPF_MFPH: PF12MFP Mask */ 2746 2747 #define SYS_GPF_MFPH_PF13MFP_Pos (20) /*!< SYS_T::GPF_MFPH: PF13MFP Position */ 2748 #define SYS_GPF_MFPH_PF13MFP_Msk (0xful << SYS_GPF_MFPH_PF13MFP_Pos) /*!< SYS_T::GPF_MFPH: PF13MFP Mask */ 2749 2750 #define SYS_GPF_MFPH_PF14MFP_Pos (24) /*!< SYS_T::GPF_MFPH: PF14MFP Position */ 2751 #define SYS_GPF_MFPH_PF14MFP_Msk (0xful << SYS_GPF_MFPH_PF14MFP_Pos) /*!< SYS_T::GPF_MFPH: PF14MFP Mask */ 2752 2753 #define SYS_GPF_MFPH_PF15MFP_Pos (28) /*!< SYS_T::GPF_MFPH: PF15MFP Position */ 2754 #define SYS_GPF_MFPH_PF15MFP_Msk (0xful << SYS_GPF_MFPH_PF15MFP_Pos) /*!< SYS_T::GPF_MFPH: PF15MFP Mask */ 2755 2756 #define SYS_GPG_MFPL_PG0MFP_Pos (0) /*!< SYS_T::GPG_MFPL: PG0MFP Position */ 2757 #define SYS_GPG_MFPL_PG0MFP_Msk (0xful << SYS_GPG_MFPL_PG0MFP_Pos) /*!< SYS_T::GPG_MFPL: PG0MFP Mask */ 2758 2759 #define SYS_GPG_MFPL_PG1MFP_Pos (4) /*!< SYS_T::GPG_MFPL: PG1MFP Position */ 2760 #define SYS_GPG_MFPL_PG1MFP_Msk (0xful << SYS_GPG_MFPL_PG1MFP_Pos) /*!< SYS_T::GPG_MFPL: PG1MFP Mask */ 2761 2762 #define SYS_GPG_MFPL_PG2MFP_Pos (8) /*!< SYS_T::GPG_MFPL: PG2MFP Position */ 2763 #define SYS_GPG_MFPL_PG2MFP_Msk (0xful << SYS_GPG_MFPL_PG2MFP_Pos) /*!< SYS_T::GPG_MFPL: PG2MFP Mask */ 2764 2765 #define SYS_GPG_MFPL_PG3MFP_Pos (12) /*!< SYS_T::GPG_MFPL: PG3MFP Position */ 2766 #define SYS_GPG_MFPL_PG3MFP_Msk (0xful << SYS_GPG_MFPL_PG3MFP_Pos) /*!< SYS_T::GPG_MFPL: PG3MFP Mask */ 2767 2768 #define SYS_GPG_MFPL_PG4MFP_Pos (16) /*!< SYS_T::GPG_MFPL: PG4MFP Position */ 2769 #define SYS_GPG_MFPL_PG4MFP_Msk (0xful << SYS_GPG_MFPL_PG4MFP_Pos) /*!< SYS_T::GPG_MFPL: PG4MFP Mask */ 2770 2771 #define SYS_GPG_MFPL_PG5MFP_Pos (20) /*!< SYS_T::GPG_MFPL: PG5MFP Position */ 2772 #define SYS_GPG_MFPL_PG5MFP_Msk (0xful << SYS_GPG_MFPL_PG5MFP_Pos) /*!< SYS_T::GPG_MFPL: PG5MFP Mask */ 2773 2774 #define SYS_GPG_MFPL_PG6MFP_Pos (24) /*!< SYS_T::GPG_MFPL: PG6MFP Position */ 2775 #define SYS_GPG_MFPL_PG6MFP_Msk (0xful << SYS_GPG_MFPL_PG6MFP_Pos) /*!< SYS_T::GPG_MFPL: PG6MFP Mask */ 2776 2777 #define SYS_GPG_MFPL_PG7MFP_Pos (28) /*!< SYS_T::GPG_MFPL: PG7MFP Position */ 2778 #define SYS_GPG_MFPL_PG7MFP_Msk (0xful << SYS_GPG_MFPL_PG7MFP_Pos) /*!< SYS_T::GPG_MFPL: PG7MFP Mask */ 2779 2780 #define SYS_GPG_MFPH_PG8MFP_Pos (0) /*!< SYS_T::GPG_MFPH: PG8MFP Position */ 2781 #define SYS_GPG_MFPH_PG8MFP_Msk (0xful << SYS_GPG_MFPH_PG8MFP_Pos) /*!< SYS_T::GPG_MFPH: PG8MFP Mask */ 2782 2783 #define SYS_GPG_MFPH_PG9MFP_Pos (4) /*!< SYS_T::GPG_MFPH: PG9MFP Position */ 2784 #define SYS_GPG_MFPH_PG9MFP_Msk (0xful << SYS_GPG_MFPH_PG9MFP_Pos) /*!< SYS_T::GPG_MFPH: PG9MFP Mask */ 2785 2786 #define SYS_GPG_MFPH_PG10MFP_Pos (8) /*!< SYS_T::GPG_MFPH: PG10MFP Position */ 2787 #define SYS_GPG_MFPH_PG10MFP_Msk (0xful << SYS_GPG_MFPH_PG10MFP_Pos) /*!< SYS_T::GPG_MFPH: PG10MFP Mask */ 2788 2789 #define SYS_GPG_MFPH_PG11MFP_Pos (12) /*!< SYS_T::GPG_MFPH: PG11MFP Position */ 2790 #define SYS_GPG_MFPH_PG11MFP_Msk (0xful << SYS_GPG_MFPH_PG11MFP_Pos) /*!< SYS_T::GPG_MFPH: PG11MFP Mask */ 2791 2792 #define SYS_GPG_MFPH_PG12MFP_Pos (16) /*!< SYS_T::GPG_MFPH: PG12MFP Position */ 2793 #define SYS_GPG_MFPH_PG12MFP_Msk (0xful << SYS_GPG_MFPH_PG12MFP_Pos) /*!< SYS_T::GPG_MFPH: PG12MFP Mask */ 2794 2795 #define SYS_GPG_MFPH_PG13MFP_Pos (20) /*!< SYS_T::GPG_MFPH: PG13MFP Position */ 2796 #define SYS_GPG_MFPH_PG13MFP_Msk (0xful << SYS_GPG_MFPH_PG13MFP_Pos) /*!< SYS_T::GPG_MFPH: PG13MFP Mask */ 2797 2798 #define SYS_GPG_MFPH_PG14MFP_Pos (24) /*!< SYS_T::GPG_MFPH: PG14MFP Position */ 2799 #define SYS_GPG_MFPH_PG14MFP_Msk (0xful << SYS_GPG_MFPH_PG14MFP_Pos) /*!< SYS_T::GPG_MFPH: PG14MFP Mask */ 2800 2801 #define SYS_GPG_MFPH_PG15MFP_Pos (28) /*!< SYS_T::GPG_MFPH: PG15MFP Position */ 2802 #define SYS_GPG_MFPH_PG15MFP_Msk (0xful << SYS_GPG_MFPH_PG15MFP_Pos) /*!< SYS_T::GPG_MFPH: PG15MFP Mask */ 2803 2804 #define SYS_GPH_MFPL_PH0MFP_Pos (0) /*!< SYS_T::GPH_MFPL: PH0MFP Position */ 2805 #define SYS_GPH_MFPL_PH0MFP_Msk (0xful << SYS_GPH_MFPL_PH0MFP_Pos) /*!< SYS_T::GPH_MFPL: PH0MFP Mask */ 2806 2807 #define SYS_GPH_MFPL_PH1MFP_Pos (4) /*!< SYS_T::GPH_MFPL: PH1MFP Position */ 2808 #define SYS_GPH_MFPL_PH1MFP_Msk (0xful << SYS_GPH_MFPL_PH1MFP_Pos) /*!< SYS_T::GPH_MFPL: PH1MFP Mask */ 2809 2810 #define SYS_GPH_MFPL_PH2MFP_Pos (8) /*!< SYS_T::GPH_MFPL: PH2MFP Position */ 2811 #define SYS_GPH_MFPL_PH2MFP_Msk (0xful << SYS_GPH_MFPL_PH2MFP_Pos) /*!< SYS_T::GPH_MFPL: PH2MFP Mask */ 2812 2813 #define SYS_GPH_MFPL_PH3MFP_Pos (12) /*!< SYS_T::GPH_MFPL: PH3MFP Position */ 2814 #define SYS_GPH_MFPL_PH3MFP_Msk (0xful << SYS_GPH_MFPL_PH3MFP_Pos) /*!< SYS_T::GPH_MFPL: PH3MFP Mask */ 2815 2816 #define SYS_GPH_MFPL_PH4MFP_Pos (16) /*!< SYS_T::GPH_MFPL: PH4MFP Position */ 2817 #define SYS_GPH_MFPL_PH4MFP_Msk (0xful << SYS_GPH_MFPL_PH4MFP_Pos) /*!< SYS_T::GPH_MFPL: PH4MFP Mask */ 2818 2819 #define SYS_GPH_MFPL_PH5MFP_Pos (20) /*!< SYS_T::GPH_MFPL: PH5MFP Position */ 2820 #define SYS_GPH_MFPL_PH5MFP_Msk (0xful << SYS_GPH_MFPL_PH5MFP_Pos) /*!< SYS_T::GPH_MFPL: PH5MFP Mask */ 2821 2822 #define SYS_GPH_MFPL_PH6MFP_Pos (24) /*!< SYS_T::GPH_MFPL: PH6MFP Position */ 2823 #define SYS_GPH_MFPL_PH6MFP_Msk (0xful << SYS_GPH_MFPL_PH6MFP_Pos) /*!< SYS_T::GPH_MFPL: PH6MFP Mask */ 2824 2825 #define SYS_GPH_MFPL_PH7MFP_Pos (28) /*!< SYS_T::GPH_MFPL: PH7MFP Position */ 2826 #define SYS_GPH_MFPL_PH7MFP_Msk (0xful << SYS_GPH_MFPL_PH7MFP_Pos) /*!< SYS_T::GPH_MFPL: PH7MFP Mask */ 2827 2828 #define SYS_GPH_MFPH_PH8MFP_Pos (0) /*!< SYS_T::GPH_MFPH: PH8MFP Position */ 2829 #define SYS_GPH_MFPH_PH8MFP_Msk (0xful << SYS_GPH_MFPH_PH8MFP_Pos) /*!< SYS_T::GPH_MFPH: PH8MFP Mask */ 2830 2831 #define SYS_GPH_MFPH_PH9MFP_Pos (4) /*!< SYS_T::GPH_MFPH: PH9MFP Position */ 2832 #define SYS_GPH_MFPH_PH9MFP_Msk (0xful << SYS_GPH_MFPH_PH9MFP_Pos) /*!< SYS_T::GPH_MFPH: PH9MFP Mask */ 2833 2834 #define SYS_GPH_MFPH_PH10MFP_Pos (8) /*!< SYS_T::GPH_MFPH: PH10MFP Position */ 2835 #define SYS_GPH_MFPH_PH10MFP_Msk (0xful << SYS_GPH_MFPH_PH10MFP_Pos) /*!< SYS_T::GPH_MFPH: PH10MFP Mask */ 2836 2837 #define SYS_GPH_MFPH_PH11MFP_Pos (12) /*!< SYS_T::GPH_MFPH: PH11MFP Position */ 2838 #define SYS_GPH_MFPH_PH11MFP_Msk (0xful << SYS_GPH_MFPH_PH11MFP_Pos) /*!< SYS_T::GPH_MFPH: PH11MFP Mask */ 2839 2840 #define SYS_GPH_MFPH_PH12MFP_Pos (16) /*!< SYS_T::GPH_MFPH: PH12MFP Position */ 2841 #define SYS_GPH_MFPH_PH12MFP_Msk (0xful << SYS_GPH_MFPH_PH12MFP_Pos) /*!< SYS_T::GPH_MFPH: PH12MFP Mask */ 2842 2843 #define SYS_GPH_MFPH_PH13MFP_Pos (20) /*!< SYS_T::GPH_MFPH: PH13MFP Position */ 2844 #define SYS_GPH_MFPH_PH13MFP_Msk (0xful << SYS_GPH_MFPH_PH13MFP_Pos) /*!< SYS_T::GPH_MFPH: PH13MFP Mask */ 2845 2846 #define SYS_GPH_MFPH_PH14MFP_Pos (24) /*!< SYS_T::GPH_MFPH: PH14MFP Position */ 2847 #define SYS_GPH_MFPH_PH14MFP_Msk (0xful << SYS_GPH_MFPH_PH14MFP_Pos) /*!< SYS_T::GPH_MFPH: PH14MFP Mask */ 2848 2849 #define SYS_GPH_MFPH_PH15MFP_Pos (28) /*!< SYS_T::GPH_MFPH: PH15MFP Position */ 2850 #define SYS_GPH_MFPH_PH15MFP_Msk (0xful << SYS_GPH_MFPH_PH15MFP_Pos) /*!< SYS_T::GPH_MFPH: PH15MFP Mask */ 2851 2852 #define SYS_GPA_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPA_MFOS: MFOS0 Position */ 2853 #define SYS_GPA_MFOS_MFOS0_Msk (0x1ul << SYS_GPA_MFOS_MFOS0_Pos) /*!< SYS_T::GPA_MFOS: MFOS0 Mask */ 2854 2855 #define SYS_GPA_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPA_MFOS: MFOS1 Position */ 2856 #define SYS_GPA_MFOS_MFOS1_Msk (0x1ul << SYS_GPA_MFOS_MFOS1_Pos) /*!< SYS_T::GPA_MFOS: MFOS1 Mask */ 2857 2858 #define SYS_GPA_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPA_MFOS: MFOS2 Position */ 2859 #define SYS_GPA_MFOS_MFOS2_Msk (0x1ul << SYS_GPA_MFOS_MFOS2_Pos) /*!< SYS_T::GPA_MFOS: MFOS2 Mask */ 2860 2861 #define SYS_GPA_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPA_MFOS: MFOS3 Position */ 2862 #define SYS_GPA_MFOS_MFOS3_Msk (0x1ul << SYS_GPA_MFOS_MFOS3_Pos) /*!< SYS_T::GPA_MFOS: MFOS3 Mask */ 2863 2864 #define SYS_GPA_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPA_MFOS: MFOS4 Position */ 2865 #define SYS_GPA_MFOS_MFOS4_Msk (0x1ul << SYS_GPA_MFOS_MFOS4_Pos) /*!< SYS_T::GPA_MFOS: MFOS4 Mask */ 2866 2867 #define SYS_GPA_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPA_MFOS: MFOS5 Position */ 2868 #define SYS_GPA_MFOS_MFOS5_Msk (0x1ul << SYS_GPA_MFOS_MFOS5_Pos) /*!< SYS_T::GPA_MFOS: MFOS5 Mask */ 2869 2870 #define SYS_GPA_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPA_MFOS: MFOS6 Position */ 2871 #define SYS_GPA_MFOS_MFOS6_Msk (0x1ul << SYS_GPA_MFOS_MFOS6_Pos) /*!< SYS_T::GPA_MFOS: MFOS6 Mask */ 2872 2873 #define SYS_GPA_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPA_MFOS: MFOS7 Position */ 2874 #define SYS_GPA_MFOS_MFOS7_Msk (0x1ul << SYS_GPA_MFOS_MFOS7_Pos) /*!< SYS_T::GPA_MFOS: MFOS7 Mask */ 2875 2876 #define SYS_GPA_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPA_MFOS: MFOS8 Position */ 2877 #define SYS_GPA_MFOS_MFOS8_Msk (0x1ul << SYS_GPA_MFOS_MFOS8_Pos) /*!< SYS_T::GPA_MFOS: MFOS8 Mask */ 2878 2879 #define SYS_GPA_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPA_MFOS: MFOS9 Position */ 2880 #define SYS_GPA_MFOS_MFOS9_Msk (0x1ul << SYS_GPA_MFOS_MFOS9_Pos) /*!< SYS_T::GPA_MFOS: MFOS9 Mask */ 2881 2882 #define SYS_GPA_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPA_MFOS: MFOS10 Position */ 2883 #define SYS_GPA_MFOS_MFOS10_Msk (0x1ul << SYS_GPA_MFOS_MFOS10_Pos) /*!< SYS_T::GPA_MFOS: MFOS10 Mask */ 2884 2885 #define SYS_GPA_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPA_MFOS: MFOS11 Position */ 2886 #define SYS_GPA_MFOS_MFOS11_Msk (0x1ul << SYS_GPA_MFOS_MFOS11_Pos) /*!< SYS_T::GPA_MFOS: MFOS11 Mask */ 2887 2888 #define SYS_GPA_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPA_MFOS: MFOS12 Position */ 2889 #define SYS_GPA_MFOS_MFOS12_Msk (0x1ul << SYS_GPA_MFOS_MFOS12_Pos) /*!< SYS_T::GPA_MFOS: MFOS12 Mask */ 2890 2891 #define SYS_GPA_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPA_MFOS: MFOS13 Position */ 2892 #define SYS_GPA_MFOS_MFOS13_Msk (0x1ul << SYS_GPA_MFOS_MFOS13_Pos) /*!< SYS_T::GPA_MFOS: MFOS13 Mask */ 2893 2894 #define SYS_GPA_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPA_MFOS: MFOS14 Position */ 2895 #define SYS_GPA_MFOS_MFOS14_Msk (0x1ul << SYS_GPA_MFOS_MFOS14_Pos) /*!< SYS_T::GPA_MFOS: MFOS14 Mask */ 2896 2897 #define SYS_GPA_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPA_MFOS: MFOS15 Position */ 2898 #define SYS_GPA_MFOS_MFOS15_Msk (0x1ul << SYS_GPA_MFOS_MFOS15_Pos) /*!< SYS_T::GPA_MFOS: MFOS15 Mask */ 2899 2900 #define SYS_GPB_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPB_MFOS: MFOS0 Position */ 2901 #define SYS_GPB_MFOS_MFOS0_Msk (0x1ul << SYS_GPB_MFOS_MFOS0_Pos) /*!< SYS_T::GPB_MFOS: MFOS0 Mask */ 2902 2903 #define SYS_GPB_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPB_MFOS: MFOS1 Position */ 2904 #define SYS_GPB_MFOS_MFOS1_Msk (0x1ul << SYS_GPB_MFOS_MFOS1_Pos) /*!< SYS_T::GPB_MFOS: MFOS1 Mask */ 2905 2906 #define SYS_GPB_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPB_MFOS: MFOS2 Position */ 2907 #define SYS_GPB_MFOS_MFOS2_Msk (0x1ul << SYS_GPB_MFOS_MFOS2_Pos) /*!< SYS_T::GPB_MFOS: MFOS2 Mask */ 2908 2909 #define SYS_GPB_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPB_MFOS: MFOS3 Position */ 2910 #define SYS_GPB_MFOS_MFOS3_Msk (0x1ul << SYS_GPB_MFOS_MFOS3_Pos) /*!< SYS_T::GPB_MFOS: MFOS3 Mask */ 2911 2912 #define SYS_GPB_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPB_MFOS: MFOS4 Position */ 2913 #define SYS_GPB_MFOS_MFOS4_Msk (0x1ul << SYS_GPB_MFOS_MFOS4_Pos) /*!< SYS_T::GPB_MFOS: MFOS4 Mask */ 2914 2915 #define SYS_GPB_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPB_MFOS: MFOS5 Position */ 2916 #define SYS_GPB_MFOS_MFOS5_Msk (0x1ul << SYS_GPB_MFOS_MFOS5_Pos) /*!< SYS_T::GPB_MFOS: MFOS5 Mask */ 2917 2918 #define SYS_GPB_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPB_MFOS: MFOS6 Position */ 2919 #define SYS_GPB_MFOS_MFOS6_Msk (0x1ul << SYS_GPB_MFOS_MFOS6_Pos) /*!< SYS_T::GPB_MFOS: MFOS6 Mask */ 2920 2921 #define SYS_GPB_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPB_MFOS: MFOS7 Position */ 2922 #define SYS_GPB_MFOS_MFOS7_Msk (0x1ul << SYS_GPB_MFOS_MFOS7_Pos) /*!< SYS_T::GPB_MFOS: MFOS7 Mask */ 2923 2924 #define SYS_GPB_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPB_MFOS: MFOS8 Position */ 2925 #define SYS_GPB_MFOS_MFOS8_Msk (0x1ul << SYS_GPB_MFOS_MFOS8_Pos) /*!< SYS_T::GPB_MFOS: MFOS8 Mask */ 2926 2927 #define SYS_GPB_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPB_MFOS: MFOS9 Position */ 2928 #define SYS_GPB_MFOS_MFOS9_Msk (0x1ul << SYS_GPB_MFOS_MFOS9_Pos) /*!< SYS_T::GPB_MFOS: MFOS9 Mask */ 2929 2930 #define SYS_GPB_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPB_MFOS: MFOS10 Position */ 2931 #define SYS_GPB_MFOS_MFOS10_Msk (0x1ul << SYS_GPB_MFOS_MFOS10_Pos) /*!< SYS_T::GPB_MFOS: MFOS10 Mask */ 2932 2933 #define SYS_GPB_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPB_MFOS: MFOS11 Position */ 2934 #define SYS_GPB_MFOS_MFOS11_Msk (0x1ul << SYS_GPB_MFOS_MFOS11_Pos) /*!< SYS_T::GPB_MFOS: MFOS11 Mask */ 2935 2936 #define SYS_GPB_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPB_MFOS: MFOS12 Position */ 2937 #define SYS_GPB_MFOS_MFOS12_Msk (0x1ul << SYS_GPB_MFOS_MFOS12_Pos) /*!< SYS_T::GPB_MFOS: MFOS12 Mask */ 2938 2939 #define SYS_GPB_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPB_MFOS: MFOS13 Position */ 2940 #define SYS_GPB_MFOS_MFOS13_Msk (0x1ul << SYS_GPB_MFOS_MFOS13_Pos) /*!< SYS_T::GPB_MFOS: MFOS13 Mask */ 2941 2942 #define SYS_GPB_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPB_MFOS: MFOS14 Position */ 2943 #define SYS_GPB_MFOS_MFOS14_Msk (0x1ul << SYS_GPB_MFOS_MFOS14_Pos) /*!< SYS_T::GPB_MFOS: MFOS14 Mask */ 2944 2945 #define SYS_GPB_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPB_MFOS: MFOS15 Position */ 2946 #define SYS_GPB_MFOS_MFOS15_Msk (0x1ul << SYS_GPB_MFOS_MFOS15_Pos) /*!< SYS_T::GPB_MFOS: MFOS15 Mask */ 2947 2948 #define SYS_GPC_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPC_MFOS: MFOS0 Position */ 2949 #define SYS_GPC_MFOS_MFOS0_Msk (0x1ul << SYS_GPC_MFOS_MFOS0_Pos) /*!< SYS_T::GPC_MFOS: MFOS0 Mask */ 2950 2951 #define SYS_GPC_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPC_MFOS: MFOS1 Position */ 2952 #define SYS_GPC_MFOS_MFOS1_Msk (0x1ul << SYS_GPC_MFOS_MFOS1_Pos) /*!< SYS_T::GPC_MFOS: MFOS1 Mask */ 2953 2954 #define SYS_GPC_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPC_MFOS: MFOS2 Position */ 2955 #define SYS_GPC_MFOS_MFOS2_Msk (0x1ul << SYS_GPC_MFOS_MFOS2_Pos) /*!< SYS_T::GPC_MFOS: MFOS2 Mask */ 2956 2957 #define SYS_GPC_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPC_MFOS: MFOS3 Position */ 2958 #define SYS_GPC_MFOS_MFOS3_Msk (0x1ul << SYS_GPC_MFOS_MFOS3_Pos) /*!< SYS_T::GPC_MFOS: MFOS3 Mask */ 2959 2960 #define SYS_GPC_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPC_MFOS: MFOS4 Position */ 2961 #define SYS_GPC_MFOS_MFOS4_Msk (0x1ul << SYS_GPC_MFOS_MFOS4_Pos) /*!< SYS_T::GPC_MFOS: MFOS4 Mask */ 2962 2963 #define SYS_GPC_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPC_MFOS: MFOS5 Position */ 2964 #define SYS_GPC_MFOS_MFOS5_Msk (0x1ul << SYS_GPC_MFOS_MFOS5_Pos) /*!< SYS_T::GPC_MFOS: MFOS5 Mask */ 2965 2966 #define SYS_GPC_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPC_MFOS: MFOS6 Position */ 2967 #define SYS_GPC_MFOS_MFOS6_Msk (0x1ul << SYS_GPC_MFOS_MFOS6_Pos) /*!< SYS_T::GPC_MFOS: MFOS6 Mask */ 2968 2969 #define SYS_GPC_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPC_MFOS: MFOS7 Position */ 2970 #define SYS_GPC_MFOS_MFOS7_Msk (0x1ul << SYS_GPC_MFOS_MFOS7_Pos) /*!< SYS_T::GPC_MFOS: MFOS7 Mask */ 2971 2972 #define SYS_GPC_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPC_MFOS: MFOS8 Position */ 2973 #define SYS_GPC_MFOS_MFOS8_Msk (0x1ul << SYS_GPC_MFOS_MFOS8_Pos) /*!< SYS_T::GPC_MFOS: MFOS8 Mask */ 2974 2975 #define SYS_GPC_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPC_MFOS: MFOS9 Position */ 2976 #define SYS_GPC_MFOS_MFOS9_Msk (0x1ul << SYS_GPC_MFOS_MFOS9_Pos) /*!< SYS_T::GPC_MFOS: MFOS9 Mask */ 2977 2978 #define SYS_GPC_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPC_MFOS: MFOS10 Position */ 2979 #define SYS_GPC_MFOS_MFOS10_Msk (0x1ul << SYS_GPC_MFOS_MFOS10_Pos) /*!< SYS_T::GPC_MFOS: MFOS10 Mask */ 2980 2981 #define SYS_GPC_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPC_MFOS: MFOS11 Position */ 2982 #define SYS_GPC_MFOS_MFOS11_Msk (0x1ul << SYS_GPC_MFOS_MFOS11_Pos) /*!< SYS_T::GPC_MFOS: MFOS11 Mask */ 2983 2984 #define SYS_GPC_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPC_MFOS: MFOS12 Position */ 2985 #define SYS_GPC_MFOS_MFOS12_Msk (0x1ul << SYS_GPC_MFOS_MFOS12_Pos) /*!< SYS_T::GPC_MFOS: MFOS12 Mask */ 2986 2987 #define SYS_GPC_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPC_MFOS: MFOS13 Position */ 2988 #define SYS_GPC_MFOS_MFOS13_Msk (0x1ul << SYS_GPC_MFOS_MFOS13_Pos) /*!< SYS_T::GPC_MFOS: MFOS13 Mask */ 2989 2990 #define SYS_GPC_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPC_MFOS: MFOS14 Position */ 2991 #define SYS_GPC_MFOS_MFOS14_Msk (0x1ul << SYS_GPC_MFOS_MFOS14_Pos) /*!< SYS_T::GPC_MFOS: MFOS14 Mask */ 2992 2993 #define SYS_GPC_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPC_MFOS: MFOS15 Position */ 2994 #define SYS_GPC_MFOS_MFOS15_Msk (0x1ul << SYS_GPC_MFOS_MFOS15_Pos) /*!< SYS_T::GPC_MFOS: MFOS15 Mask */ 2995 2996 #define SYS_GPD_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPD_MFOS: MFOS0 Position */ 2997 #define SYS_GPD_MFOS_MFOS0_Msk (0x1ul << SYS_GPD_MFOS_MFOS0_Pos) /*!< SYS_T::GPD_MFOS: MFOS0 Mask */ 2998 2999 #define SYS_GPD_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPD_MFOS: MFOS1 Position */ 3000 #define SYS_GPD_MFOS_MFOS1_Msk (0x1ul << SYS_GPD_MFOS_MFOS1_Pos) /*!< SYS_T::GPD_MFOS: MFOS1 Mask */ 3001 3002 #define SYS_GPD_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPD_MFOS: MFOS2 Position */ 3003 #define SYS_GPD_MFOS_MFOS2_Msk (0x1ul << SYS_GPD_MFOS_MFOS2_Pos) /*!< SYS_T::GPD_MFOS: MFOS2 Mask */ 3004 3005 #define SYS_GPD_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPD_MFOS: MFOS3 Position */ 3006 #define SYS_GPD_MFOS_MFOS3_Msk (0x1ul << SYS_GPD_MFOS_MFOS3_Pos) /*!< SYS_T::GPD_MFOS: MFOS3 Mask */ 3007 3008 #define SYS_GPD_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPD_MFOS: MFOS4 Position */ 3009 #define SYS_GPD_MFOS_MFOS4_Msk (0x1ul << SYS_GPD_MFOS_MFOS4_Pos) /*!< SYS_T::GPD_MFOS: MFOS4 Mask */ 3010 3011 #define SYS_GPD_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPD_MFOS: MFOS5 Position */ 3012 #define SYS_GPD_MFOS_MFOS5_Msk (0x1ul << SYS_GPD_MFOS_MFOS5_Pos) /*!< SYS_T::GPD_MFOS: MFOS5 Mask */ 3013 3014 #define SYS_GPD_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPD_MFOS: MFOS6 Position */ 3015 #define SYS_GPD_MFOS_MFOS6_Msk (0x1ul << SYS_GPD_MFOS_MFOS6_Pos) /*!< SYS_T::GPD_MFOS: MFOS6 Mask */ 3016 3017 #define SYS_GPD_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPD_MFOS: MFOS7 Position */ 3018 #define SYS_GPD_MFOS_MFOS7_Msk (0x1ul << SYS_GPD_MFOS_MFOS7_Pos) /*!< SYS_T::GPD_MFOS: MFOS7 Mask */ 3019 3020 #define SYS_GPD_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPD_MFOS: MFOS8 Position */ 3021 #define SYS_GPD_MFOS_MFOS8_Msk (0x1ul << SYS_GPD_MFOS_MFOS8_Pos) /*!< SYS_T::GPD_MFOS: MFOS8 Mask */ 3022 3023 #define SYS_GPD_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPD_MFOS: MFOS9 Position */ 3024 #define SYS_GPD_MFOS_MFOS9_Msk (0x1ul << SYS_GPD_MFOS_MFOS9_Pos) /*!< SYS_T::GPD_MFOS: MFOS9 Mask */ 3025 3026 #define SYS_GPD_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPD_MFOS: MFOS10 Position */ 3027 #define SYS_GPD_MFOS_MFOS10_Msk (0x1ul << SYS_GPD_MFOS_MFOS10_Pos) /*!< SYS_T::GPD_MFOS: MFOS10 Mask */ 3028 3029 #define SYS_GPD_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPD_MFOS: MFOS11 Position */ 3030 #define SYS_GPD_MFOS_MFOS11_Msk (0x1ul << SYS_GPD_MFOS_MFOS11_Pos) /*!< SYS_T::GPD_MFOS: MFOS11 Mask */ 3031 3032 #define SYS_GPD_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPD_MFOS: MFOS12 Position */ 3033 #define SYS_GPD_MFOS_MFOS12_Msk (0x1ul << SYS_GPD_MFOS_MFOS12_Pos) /*!< SYS_T::GPD_MFOS: MFOS12 Mask */ 3034 3035 #define SYS_GPD_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPD_MFOS: MFOS13 Position */ 3036 #define SYS_GPD_MFOS_MFOS13_Msk (0x1ul << SYS_GPD_MFOS_MFOS13_Pos) /*!< SYS_T::GPD_MFOS: MFOS13 Mask */ 3037 3038 #define SYS_GPD_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPD_MFOS: MFOS14 Position */ 3039 #define SYS_GPD_MFOS_MFOS14_Msk (0x1ul << SYS_GPD_MFOS_MFOS14_Pos) /*!< SYS_T::GPD_MFOS: MFOS14 Mask */ 3040 3041 #define SYS_GPD_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPD_MFOS: MFOS15 Position */ 3042 #define SYS_GPD_MFOS_MFOS15_Msk (0x1ul << SYS_GPD_MFOS_MFOS15_Pos) /*!< SYS_T::GPD_MFOS: MFOS15 Mask */ 3043 3044 #define SYS_GPE_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPE_MFOS: MFOS0 Position */ 3045 #define SYS_GPE_MFOS_MFOS0_Msk (0x1ul << SYS_GPE_MFOS_MFOS0_Pos) /*!< SYS_T::GPE_MFOS: MFOS0 Mask */ 3046 3047 #define SYS_GPE_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPE_MFOS: MFOS1 Position */ 3048 #define SYS_GPE_MFOS_MFOS1_Msk (0x1ul << SYS_GPE_MFOS_MFOS1_Pos) /*!< SYS_T::GPE_MFOS: MFOS1 Mask */ 3049 3050 #define SYS_GPE_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPE_MFOS: MFOS2 Position */ 3051 #define SYS_GPE_MFOS_MFOS2_Msk (0x1ul << SYS_GPE_MFOS_MFOS2_Pos) /*!< SYS_T::GPE_MFOS: MFOS2 Mask */ 3052 3053 #define SYS_GPE_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPE_MFOS: MFOS3 Position */ 3054 #define SYS_GPE_MFOS_MFOS3_Msk (0x1ul << SYS_GPE_MFOS_MFOS3_Pos) /*!< SYS_T::GPE_MFOS: MFOS3 Mask */ 3055 3056 #define SYS_GPE_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPE_MFOS: MFOS4 Position */ 3057 #define SYS_GPE_MFOS_MFOS4_Msk (0x1ul << SYS_GPE_MFOS_MFOS4_Pos) /*!< SYS_T::GPE_MFOS: MFOS4 Mask */ 3058 3059 #define SYS_GPE_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPE_MFOS: MFOS5 Position */ 3060 #define SYS_GPE_MFOS_MFOS5_Msk (0x1ul << SYS_GPE_MFOS_MFOS5_Pos) /*!< SYS_T::GPE_MFOS: MFOS5 Mask */ 3061 3062 #define SYS_GPE_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPE_MFOS: MFOS6 Position */ 3063 #define SYS_GPE_MFOS_MFOS6_Msk (0x1ul << SYS_GPE_MFOS_MFOS6_Pos) /*!< SYS_T::GPE_MFOS: MFOS6 Mask */ 3064 3065 #define SYS_GPE_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPE_MFOS: MFOS7 Position */ 3066 #define SYS_GPE_MFOS_MFOS7_Msk (0x1ul << SYS_GPE_MFOS_MFOS7_Pos) /*!< SYS_T::GPE_MFOS: MFOS7 Mask */ 3067 3068 #define SYS_GPE_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPE_MFOS: MFOS8 Position */ 3069 #define SYS_GPE_MFOS_MFOS8_Msk (0x1ul << SYS_GPE_MFOS_MFOS8_Pos) /*!< SYS_T::GPE_MFOS: MFOS8 Mask */ 3070 3071 #define SYS_GPE_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPE_MFOS: MFOS9 Position */ 3072 #define SYS_GPE_MFOS_MFOS9_Msk (0x1ul << SYS_GPE_MFOS_MFOS9_Pos) /*!< SYS_T::GPE_MFOS: MFOS9 Mask */ 3073 3074 #define SYS_GPE_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPE_MFOS: MFOS10 Position */ 3075 #define SYS_GPE_MFOS_MFOS10_Msk (0x1ul << SYS_GPE_MFOS_MFOS10_Pos) /*!< SYS_T::GPE_MFOS: MFOS10 Mask */ 3076 3077 #define SYS_GPE_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPE_MFOS: MFOS11 Position */ 3078 #define SYS_GPE_MFOS_MFOS11_Msk (0x1ul << SYS_GPE_MFOS_MFOS11_Pos) /*!< SYS_T::GPE_MFOS: MFOS11 Mask */ 3079 3080 #define SYS_GPE_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPE_MFOS: MFOS12 Position */ 3081 #define SYS_GPE_MFOS_MFOS12_Msk (0x1ul << SYS_GPE_MFOS_MFOS12_Pos) /*!< SYS_T::GPE_MFOS: MFOS12 Mask */ 3082 3083 #define SYS_GPE_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPE_MFOS: MFOS13 Position */ 3084 #define SYS_GPE_MFOS_MFOS13_Msk (0x1ul << SYS_GPE_MFOS_MFOS13_Pos) /*!< SYS_T::GPE_MFOS: MFOS13 Mask */ 3085 3086 #define SYS_GPE_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPE_MFOS: MFOS14 Position */ 3087 #define SYS_GPE_MFOS_MFOS14_Msk (0x1ul << SYS_GPE_MFOS_MFOS14_Pos) /*!< SYS_T::GPE_MFOS: MFOS14 Mask */ 3088 3089 #define SYS_GPE_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPE_MFOS: MFOS15 Position */ 3090 #define SYS_GPE_MFOS_MFOS15_Msk (0x1ul << SYS_GPE_MFOS_MFOS15_Pos) /*!< SYS_T::GPE_MFOS: MFOS15 Mask */ 3091 3092 #define SYS_GPF_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPF_MFOS: MFOS0 Position */ 3093 #define SYS_GPF_MFOS_MFOS0_Msk (0x1ul << SYS_GPF_MFOS_MFOS0_Pos) /*!< SYS_T::GPF_MFOS: MFOS0 Mask */ 3094 3095 #define SYS_GPF_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPF_MFOS: MFOS1 Position */ 3096 #define SYS_GPF_MFOS_MFOS1_Msk (0x1ul << SYS_GPF_MFOS_MFOS1_Pos) /*!< SYS_T::GPF_MFOS: MFOS1 Mask */ 3097 3098 #define SYS_GPF_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPF_MFOS: MFOS2 Position */ 3099 #define SYS_GPF_MFOS_MFOS2_Msk (0x1ul << SYS_GPF_MFOS_MFOS2_Pos) /*!< SYS_T::GPF_MFOS: MFOS2 Mask */ 3100 3101 #define SYS_GPF_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPF_MFOS: MFOS3 Position */ 3102 #define SYS_GPF_MFOS_MFOS3_Msk (0x1ul << SYS_GPF_MFOS_MFOS3_Pos) /*!< SYS_T::GPF_MFOS: MFOS3 Mask */ 3103 3104 #define SYS_GPF_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPF_MFOS: MFOS4 Position */ 3105 #define SYS_GPF_MFOS_MFOS4_Msk (0x1ul << SYS_GPF_MFOS_MFOS4_Pos) /*!< SYS_T::GPF_MFOS: MFOS4 Mask */ 3106 3107 #define SYS_GPF_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPF_MFOS: MFOS5 Position */ 3108 #define SYS_GPF_MFOS_MFOS5_Msk (0x1ul << SYS_GPF_MFOS_MFOS5_Pos) /*!< SYS_T::GPF_MFOS: MFOS5 Mask */ 3109 3110 #define SYS_GPF_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPF_MFOS: MFOS6 Position */ 3111 #define SYS_GPF_MFOS_MFOS6_Msk (0x1ul << SYS_GPF_MFOS_MFOS6_Pos) /*!< SYS_T::GPF_MFOS: MFOS6 Mask */ 3112 3113 #define SYS_GPF_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPF_MFOS: MFOS7 Position */ 3114 #define SYS_GPF_MFOS_MFOS7_Msk (0x1ul << SYS_GPF_MFOS_MFOS7_Pos) /*!< SYS_T::GPF_MFOS: MFOS7 Mask */ 3115 3116 #define SYS_GPF_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPF_MFOS: MFOS8 Position */ 3117 #define SYS_GPF_MFOS_MFOS8_Msk (0x1ul << SYS_GPF_MFOS_MFOS8_Pos) /*!< SYS_T::GPF_MFOS: MFOS8 Mask */ 3118 3119 #define SYS_GPF_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPF_MFOS: MFOS9 Position */ 3120 #define SYS_GPF_MFOS_MFOS9_Msk (0x1ul << SYS_GPF_MFOS_MFOS9_Pos) /*!< SYS_T::GPF_MFOS: MFOS9 Mask */ 3121 3122 #define SYS_GPF_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPF_MFOS: MFOS10 Position */ 3123 #define SYS_GPF_MFOS_MFOS10_Msk (0x1ul << SYS_GPF_MFOS_MFOS10_Pos) /*!< SYS_T::GPF_MFOS: MFOS10 Mask */ 3124 3125 #define SYS_GPF_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPF_MFOS: MFOS11 Position */ 3126 #define SYS_GPF_MFOS_MFOS11_Msk (0x1ul << SYS_GPF_MFOS_MFOS11_Pos) /*!< SYS_T::GPF_MFOS: MFOS11 Mask */ 3127 3128 #define SYS_GPF_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPF_MFOS: MFOS12 Position */ 3129 #define SYS_GPF_MFOS_MFOS12_Msk (0x1ul << SYS_GPF_MFOS_MFOS12_Pos) /*!< SYS_T::GPF_MFOS: MFOS12 Mask */ 3130 3131 #define SYS_GPF_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPF_MFOS: MFOS13 Position */ 3132 #define SYS_GPF_MFOS_MFOS13_Msk (0x1ul << SYS_GPF_MFOS_MFOS13_Pos) /*!< SYS_T::GPF_MFOS: MFOS13 Mask */ 3133 3134 #define SYS_GPF_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPF_MFOS: MFOS14 Position */ 3135 #define SYS_GPF_MFOS_MFOS14_Msk (0x1ul << SYS_GPF_MFOS_MFOS14_Pos) /*!< SYS_T::GPF_MFOS: MFOS14 Mask */ 3136 3137 #define SYS_GPF_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPF_MFOS: MFOS15 Position */ 3138 #define SYS_GPF_MFOS_MFOS15_Msk (0x1ul << SYS_GPF_MFOS_MFOS15_Pos) /*!< SYS_T::GPF_MFOS: MFOS15 Mask */ 3139 3140 #define SYS_GPG_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPG_MFOS: MFOS0 Position */ 3141 #define SYS_GPG_MFOS_MFOS0_Msk (0x1ul << SYS_GPG_MFOS_MFOS0_Pos) /*!< SYS_T::GPG_MFOS: MFOS0 Mask */ 3142 3143 #define SYS_GPG_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPG_MFOS: MFOS1 Position */ 3144 #define SYS_GPG_MFOS_MFOS1_Msk (0x1ul << SYS_GPG_MFOS_MFOS1_Pos) /*!< SYS_T::GPG_MFOS: MFOS1 Mask */ 3145 3146 #define SYS_GPG_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPG_MFOS: MFOS2 Position */ 3147 #define SYS_GPG_MFOS_MFOS2_Msk (0x1ul << SYS_GPG_MFOS_MFOS2_Pos) /*!< SYS_T::GPG_MFOS: MFOS2 Mask */ 3148 3149 #define SYS_GPG_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPG_MFOS: MFOS3 Position */ 3150 #define SYS_GPG_MFOS_MFOS3_Msk (0x1ul << SYS_GPG_MFOS_MFOS3_Pos) /*!< SYS_T::GPG_MFOS: MFOS3 Mask */ 3151 3152 #define SYS_GPG_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPG_MFOS: MFOS4 Position */ 3153 #define SYS_GPG_MFOS_MFOS4_Msk (0x1ul << SYS_GPG_MFOS_MFOS4_Pos) /*!< SYS_T::GPG_MFOS: MFOS4 Mask */ 3154 3155 #define SYS_GPG_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPG_MFOS: MFOS5 Position */ 3156 #define SYS_GPG_MFOS_MFOS5_Msk (0x1ul << SYS_GPG_MFOS_MFOS5_Pos) /*!< SYS_T::GPG_MFOS: MFOS5 Mask */ 3157 3158 #define SYS_GPG_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPG_MFOS: MFOS6 Position */ 3159 #define SYS_GPG_MFOS_MFOS6_Msk (0x1ul << SYS_GPG_MFOS_MFOS6_Pos) /*!< SYS_T::GPG_MFOS: MFOS6 Mask */ 3160 3161 #define SYS_GPG_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPG_MFOS: MFOS7 Position */ 3162 #define SYS_GPG_MFOS_MFOS7_Msk (0x1ul << SYS_GPG_MFOS_MFOS7_Pos) /*!< SYS_T::GPG_MFOS: MFOS7 Mask */ 3163 3164 #define SYS_GPG_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPG_MFOS: MFOS8 Position */ 3165 #define SYS_GPG_MFOS_MFOS8_Msk (0x1ul << SYS_GPG_MFOS_MFOS8_Pos) /*!< SYS_T::GPG_MFOS: MFOS8 Mask */ 3166 3167 #define SYS_GPG_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPG_MFOS: MFOS9 Position */ 3168 #define SYS_GPG_MFOS_MFOS9_Msk (0x1ul << SYS_GPG_MFOS_MFOS9_Pos) /*!< SYS_T::GPG_MFOS: MFOS9 Mask */ 3169 3170 #define SYS_GPG_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPG_MFOS: MFOS10 Position */ 3171 #define SYS_GPG_MFOS_MFOS10_Msk (0x1ul << SYS_GPG_MFOS_MFOS10_Pos) /*!< SYS_T::GPG_MFOS: MFOS10 Mask */ 3172 3173 #define SYS_GPG_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPG_MFOS: MFOS11 Position */ 3174 #define SYS_GPG_MFOS_MFOS11_Msk (0x1ul << SYS_GPG_MFOS_MFOS11_Pos) /*!< SYS_T::GPG_MFOS: MFOS11 Mask */ 3175 3176 #define SYS_GPG_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPG_MFOS: MFOS12 Position */ 3177 #define SYS_GPG_MFOS_MFOS12_Msk (0x1ul << SYS_GPG_MFOS_MFOS12_Pos) /*!< SYS_T::GPG_MFOS: MFOS12 Mask */ 3178 3179 #define SYS_GPG_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPG_MFOS: MFOS13 Position */ 3180 #define SYS_GPG_MFOS_MFOS13_Msk (0x1ul << SYS_GPG_MFOS_MFOS13_Pos) /*!< SYS_T::GPG_MFOS: MFOS13 Mask */ 3181 3182 #define SYS_GPG_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPG_MFOS: MFOS14 Position */ 3183 #define SYS_GPG_MFOS_MFOS14_Msk (0x1ul << SYS_GPG_MFOS_MFOS14_Pos) /*!< SYS_T::GPG_MFOS: MFOS14 Mask */ 3184 3185 #define SYS_GPG_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPG_MFOS: MFOS15 Position */ 3186 #define SYS_GPG_MFOS_MFOS15_Msk (0x1ul << SYS_GPG_MFOS_MFOS15_Pos) /*!< SYS_T::GPG_MFOS: MFOS15 Mask */ 3187 3188 #define SYS_GPH_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPH_MFOS: MFOS0 Position */ 3189 #define SYS_GPH_MFOS_MFOS0_Msk (0x1ul << SYS_GPH_MFOS_MFOS0_Pos) /*!< SYS_T::GPH_MFOS: MFOS0 Mask */ 3190 3191 #define SYS_GPH_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPH_MFOS: MFOS1 Position */ 3192 #define SYS_GPH_MFOS_MFOS1_Msk (0x1ul << SYS_GPH_MFOS_MFOS1_Pos) /*!< SYS_T::GPH_MFOS: MFOS1 Mask */ 3193 3194 #define SYS_GPH_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPH_MFOS: MFOS2 Position */ 3195 #define SYS_GPH_MFOS_MFOS2_Msk (0x1ul << SYS_GPH_MFOS_MFOS2_Pos) /*!< SYS_T::GPH_MFOS: MFOS2 Mask */ 3196 3197 #define SYS_GPH_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPH_MFOS: MFOS3 Position */ 3198 #define SYS_GPH_MFOS_MFOS3_Msk (0x1ul << SYS_GPH_MFOS_MFOS3_Pos) /*!< SYS_T::GPH_MFOS: MFOS3 Mask */ 3199 3200 #define SYS_GPH_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPH_MFOS: MFOS4 Position */ 3201 #define SYS_GPH_MFOS_MFOS4_Msk (0x1ul << SYS_GPH_MFOS_MFOS4_Pos) /*!< SYS_T::GPH_MFOS: MFOS4 Mask */ 3202 3203 #define SYS_GPH_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPH_MFOS: MFOS5 Position */ 3204 #define SYS_GPH_MFOS_MFOS5_Msk (0x1ul << SYS_GPH_MFOS_MFOS5_Pos) /*!< SYS_T::GPH_MFOS: MFOS5 Mask */ 3205 3206 #define SYS_GPH_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPH_MFOS: MFOS6 Position */ 3207 #define SYS_GPH_MFOS_MFOS6_Msk (0x1ul << SYS_GPH_MFOS_MFOS6_Pos) /*!< SYS_T::GPH_MFOS: MFOS6 Mask */ 3208 3209 #define SYS_GPH_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPH_MFOS: MFOS7 Position */ 3210 #define SYS_GPH_MFOS_MFOS7_Msk (0x1ul << SYS_GPH_MFOS_MFOS7_Pos) /*!< SYS_T::GPH_MFOS: MFOS7 Mask */ 3211 3212 #define SYS_GPH_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPH_MFOS: MFOS8 Position */ 3213 #define SYS_GPH_MFOS_MFOS8_Msk (0x1ul << SYS_GPH_MFOS_MFOS8_Pos) /*!< SYS_T::GPH_MFOS: MFOS8 Mask */ 3214 3215 #define SYS_GPH_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPH_MFOS: MFOS9 Position */ 3216 #define SYS_GPH_MFOS_MFOS9_Msk (0x1ul << SYS_GPH_MFOS_MFOS9_Pos) /*!< SYS_T::GPH_MFOS: MFOS9 Mask */ 3217 3218 #define SYS_GPH_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPH_MFOS: MFOS10 Position */ 3219 #define SYS_GPH_MFOS_MFOS10_Msk (0x1ul << SYS_GPH_MFOS_MFOS10_Pos) /*!< SYS_T::GPH_MFOS: MFOS10 Mask */ 3220 3221 #define SYS_GPH_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPH_MFOS: MFOS11 Position */ 3222 #define SYS_GPH_MFOS_MFOS11_Msk (0x1ul << SYS_GPH_MFOS_MFOS11_Pos) /*!< SYS_T::GPH_MFOS: MFOS11 Mask */ 3223 3224 #define SYS_GPH_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPH_MFOS: MFOS12 Position */ 3225 #define SYS_GPH_MFOS_MFOS12_Msk (0x1ul << SYS_GPH_MFOS_MFOS12_Pos) /*!< SYS_T::GPH_MFOS: MFOS12 Mask */ 3226 3227 #define SYS_GPH_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPH_MFOS: MFOS13 Position */ 3228 #define SYS_GPH_MFOS_MFOS13_Msk (0x1ul << SYS_GPH_MFOS_MFOS13_Pos) /*!< SYS_T::GPH_MFOS: MFOS13 Mask */ 3229 3230 #define SYS_GPH_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPH_MFOS: MFOS14 Position */ 3231 #define SYS_GPH_MFOS_MFOS14_Msk (0x1ul << SYS_GPH_MFOS_MFOS14_Pos) /*!< SYS_T::GPH_MFOS: MFOS14 Mask */ 3232 3233 #define SYS_GPH_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPH_MFOS: MFOS15 Position */ 3234 #define SYS_GPH_MFOS_MFOS15_Msk (0x1ul << SYS_GPH_MFOS_MFOS15_Pos) /*!< SYS_T::GPH_MFOS: MFOS15 Mask */ 3235 3236 #define SYS_SRAM_INTCTL_PERRIEN_Pos (0) /*!< SYS_T::SRAM_INTCTL: PERRIEN Position */ 3237 #define SYS_SRAM_INTCTL_PERRIEN_Msk (0x1ul << SYS_SRAM_INTCTL_PERRIEN_Pos) /*!< SYS_T::SRAM_INTCTL: PERRIEN Mask */ 3238 3239 #define SYS_SRAM_STATUS_PERRIF_Pos (0) /*!< SYS_T::SRAM_STATUS: PERRIF Position */ 3240 #define SYS_SRAM_STATUS_PERRIF_Msk (0x1ul << SYS_SRAM_STATUS_PERRIF_Pos) /*!< SYS_T::SRAM_STATUS: PERRIF Mask */ 3241 3242 #define SYS_SRAM_ERRADDR_ERRADDR_Pos (0) /*!< SYS_T::SRAM_ERRADDR: ERRADDR Position */ 3243 #define SYS_SRAM_ERRADDR_ERRADDR_Msk (0xfffffffful << SYS_SRAM_ERRADDR_ERRADDR_Pos) /*!< SYS_T::SRAM_ERRADDR: ERRADDR Mask */ 3244 3245 #define SYS_SRAM_BISTCTL_SRBIST0_Pos (0) /*!< SYS_T::SRAM_BISTCTL: SRBIST0 Position */ 3246 #define SYS_SRAM_BISTCTL_SRBIST0_Msk (0x1ul << SYS_SRAM_BISTCTL_SRBIST0_Pos) /*!< SYS_T::SRAM_BISTCTL: SRBIST0 Mask */ 3247 3248 #define SYS_SRAM_BISTCTL_SRBIST1_Pos (1) /*!< SYS_T::SRAM_BISTCTL: SRBIST1 Position */ 3249 #define SYS_SRAM_BISTCTL_SRBIST1_Msk (0x1ul << SYS_SRAM_BISTCTL_SRBIST1_Pos) /*!< SYS_T::SRAM_BISTCTL: SRBIST1 Mask */ 3250 3251 #define SYS_SRAM_BISTCTL_CRBIST_Pos (2) /*!< SYS_T::SRAM_BISTCTL: CRBIST Position */ 3252 #define SYS_SRAM_BISTCTL_CRBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_CRBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: CRBIST Mask */ 3253 3254 #define SYS_SRAM_BISTCTL_CANBIST_Pos (3) /*!< SYS_T::SRAM_BISTCTL: CANBIST Position */ 3255 #define SYS_SRAM_BISTCTL_CANBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_CANBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: CANBIST Mask */ 3256 3257 #define SYS_SRAM_BISTCTL_USBBIST_Pos (4) /*!< SYS_T::SRAM_BISTCTL: USBBIST Position */ 3258 #define SYS_SRAM_BISTCTL_USBBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_USBBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: USBBIST Mask */ 3259 3260 #define SYS_SRAM_BISTCTL_SPIMBIST_Pos (5) /*!< SYS_T::SRAM_BISTCTL: SPIMBIST Position */ 3261 #define SYS_SRAM_BISTCTL_SPIMBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_SPIMBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: SPIMBIST Mask */ 3262 3263 #define SYS_SRAM_BISTCTL_EMCBIST_Pos (6) /*!< SYS_T::SRAM_BISTCTL: EMCBIST Position */ 3264 #define SYS_SRAM_BISTCTL_EMCBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_EMCBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: EMCBIST Mask */ 3265 3266 #define SYS_SRAM_BISTCTL_PDMABIST_Pos (7) /*!< SYS_T::SRAM_BISTCTL: PDMABIST Position */ 3267 #define SYS_SRAM_BISTCTL_PDMABIST_Msk (0x1ul << SYS_SRAM_BISTCTL_PDMABIST_Pos) /*!< SYS_T::SRAM_BISTCTL: PDMABIST Mask */ 3268 3269 #define SYS_SRAM_BISTCTL_HSUSBDBIST_Pos (8) /*!< SYS_T::SRAM_BISTCTL: HSUSBDBIST Position*/ 3270 #define SYS_SRAM_BISTCTL_HSUSBDBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_HSUSBDBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: HSUSBDBIST Mask */ 3271 3272 #define SYS_SRAM_BISTCTL_HSUSBHBIST_Pos (9) /*!< SYS_T::SRAM_BISTCTL: HSUSBHBIST Position*/ 3273 #define SYS_SRAM_BISTCTL_HSUSBHBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_HSUSBHBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: HSUSBHBIST Mask */ 3274 3275 #define SYS_SRAM_BISTCTL_SRB0S0_Pos (16) /*!< SYS_T::SRAM_BISTCTL: SRB0S0 Position */ 3276 #define SYS_SRAM_BISTCTL_SRB0S0_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB0S0_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB0S0 Mask */ 3277 3278 #define SYS_SRAM_BISTCTL_SRB0S1_Pos (17) /*!< SYS_T::SRAM_BISTCTL: SRB0S1 Position */ 3279 #define SYS_SRAM_BISTCTL_SRB0S1_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB0S1_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB0S1 Mask */ 3280 3281 #define SYS_SRAM_BISTCTL_SRB1S0_Pos (18) /*!< SYS_T::SRAM_BISTCTL: SRB1S0 Position */ 3282 #define SYS_SRAM_BISTCTL_SRB1S0_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB1S0_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB1S0 Mask */ 3283 3284 #define SYS_SRAM_BISTCTL_SRB1S1_Pos (19) /*!< SYS_T::SRAM_BISTCTL: SRB1S1 Position */ 3285 #define SYS_SRAM_BISTCTL_SRB1S1_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB1S1_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB1S1 Mask */ 3286 3287 #define SYS_SRAM_BISTCTL_SRB1S2_Pos (20) /*!< SYS_T::SRAM_BISTCTL: SRB1S2 Position */ 3288 #define SYS_SRAM_BISTCTL_SRB1S2_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB1S2_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB1S2 Mask */ 3289 3290 #define SYS_SRAM_BISTCTL_SRB1S3_Pos (21) /*!< SYS_T::SRAM_BISTCTL: SRB1S3 Position */ 3291 #define SYS_SRAM_BISTCTL_SRB1S3_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB1S3_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB1S3 Mask */ 3292 3293 #define SYS_SRAM_BISTCTL_SRB1S4_Pos (22) /*!< SYS_T::SRAM_BISTCTL: SRB1S4 Position */ 3294 #define SYS_SRAM_BISTCTL_SRB1S4_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB1S4_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB1S4 Mask */ 3295 3296 #define SYS_SRAM_BISTCTL_SRB1S5_Pos (23) /*!< SYS_T::SRAM_BISTCTL: SRB1S5 Position */ 3297 #define SYS_SRAM_BISTCTL_SRB1S5_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB1S5_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB1S5 Mask */ 3298 3299 #define SYS_SRAM_BISTSTS_SRBISTEF0_Pos (0) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF0 Position*/ 3300 #define SYS_SRAM_BISTSTS_SRBISTEF0_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBISTEF0_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF0 Mask */ 3301 3302 #define SYS_SRAM_BISTSTS_SRBISTEF1_Pos (1) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF1 Position*/ 3303 #define SYS_SRAM_BISTSTS_SRBISTEF1_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBISTEF1_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF1 Mask */ 3304 3305 #define SYS_SRAM_BISTSTS_CRBISTEF_Pos (2) /*!< SYS_T::SRAM_BISTSTS: CRBISTEF Position */ 3306 #define SYS_SRAM_BISTSTS_CRBISTEF_Msk (0x1ul << SYS_SRAM_BISTSTS_CRBISTEF_Pos) /*!< SYS_T::SRAM_BISTSTS: CRBISTEF Mask */ 3307 3308 #define SYS_SRAM_BISTSTS_CANBEF_Pos (3) /*!< SYS_T::SRAM_BISTSTS: CANBEF Position */ 3309 #define SYS_SRAM_BISTSTS_CANBEF_Msk (0x1ul << SYS_SRAM_BISTSTS_CANBEF_Pos) /*!< SYS_T::SRAM_BISTSTS: CANBEF Mask */ 3310 3311 #define SYS_SRAM_BISTSTS_USBBEF_Pos (4) /*!< SYS_T::SRAM_BISTSTS: USBBEF Position */ 3312 #define SYS_SRAM_BISTSTS_USBBEF_Msk (0x1ul << SYS_SRAM_BISTSTS_USBBEF_Pos) /*!< SYS_T::SRAM_BISTSTS: USBBEF Mask */ 3313 3314 #define SYS_SRAM_BISTSTS_SRBEND0_Pos (16) /*!< SYS_T::SRAM_BISTSTS: SRBEND0 Position */ 3315 #define SYS_SRAM_BISTSTS_SRBEND0_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBEND0_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBEND0 Mask */ 3316 3317 #define SYS_SRAM_BISTSTS_SRBEND1_Pos (17) /*!< SYS_T::SRAM_BISTSTS: SRBEND1 Position */ 3318 #define SYS_SRAM_BISTSTS_SRBEND1_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBEND1_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBEND1 Mask */ 3319 3320 #define SYS_SRAM_BISTSTS_CRBEND_Pos (18) /*!< SYS_T::SRAM_BISTSTS: CRBEND Position */ 3321 #define SYS_SRAM_BISTSTS_CRBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_CRBEND_Pos) /*!< SYS_T::SRAM_BISTSTS: CRBEND Mask */ 3322 3323 #define SYS_SRAM_BISTSTS_CANBEND_Pos (19) /*!< SYS_T::SRAM_BISTSTS: CANBEND Position */ 3324 #define SYS_SRAM_BISTSTS_CANBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_CANBEND_Pos) /*!< SYS_T::SRAM_BISTSTS: CANBEND Mask */ 3325 3326 #define SYS_SRAM_BISTSTS_USBBEND_Pos (20) /*!< SYS_T::SRAM_BISTSTS: USBBEND Position */ 3327 #define SYS_SRAM_BISTSTS_USBBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_USBBEND_Pos) /*!< SYS_T::SRAM_BISTSTS: USBBEND Mask */ 3328 3329 #define SYS_HIRCTCTL_FREQSEL_Pos (0) /*!< SYS_T::HIRCTCTL: FREQSEL Position */ 3330 #define SYS_HIRCTCTL_FREQSEL_Msk (0x3ul << SYS_HIRCTCTL_FREQSEL_Pos) /*!< SYS_T::HIRCTCTL: FREQSEL Mask */ 3331 3332 #define SYS_HIRCTCTL_LOOPSEL_Pos (4) /*!< SYS_T::HIRCTCTL: LOOPSEL Position */ 3333 #define SYS_HIRCTCTL_LOOPSEL_Msk (0x3ul << SYS_HIRCTCTL_LOOPSEL_Pos) /*!< SYS_T::HIRCTCTL: LOOPSEL Mask */ 3334 3335 #define SYS_HIRCTCTL_RETRYCNT_Pos (6) /*!< SYS_T::HIRCTCTL: RETRYCNT Position */ 3336 #define SYS_HIRCTCTL_RETRYCNT_Msk (0x3ul << SYS_HIRCTCTL_RETRYCNT_Pos) /*!< SYS_T::HIRCTCTL: RETRYCNT Mask */ 3337 3338 #define SYS_HIRCTCTL_CESTOPEN_Pos (8) /*!< SYS_T::HIRCTCTL: CESTOPEN Position */ 3339 #define SYS_HIRCTCTL_CESTOPEN_Msk (0x1ul << SYS_HIRCTCTL_CESTOPEN_Pos) /*!< SYS_T::HIRCTCTL: CESTOPEN Mask */ 3340 3341 #define SYS_HIRCTCTL_BOUNDEN_Pos (9) /*!< SYS_T::HIRCTCTL: BOUNDEN Position */ 3342 #define SYS_HIRCTCTL_BOUNDEN_Msk (0x1ul << SYS_HIRCTCTL_BOUNDEN_Pos) /*!< SYS_T::HIRCTCTL: BOUNDEN Mask */ 3343 3344 #define SYS_HIRCTCTL_REFCKSEL_Pos (10) /*!< SYS_T::HIRCTCTL: REFCKSEL Position */ 3345 #define SYS_HIRCTCTL_REFCKSEL_Msk (0x1ul << SYS_HIRCTCTL_REFCKSEL_Pos) /*!< SYS_T::HIRCTCTL: REFCKSEL Mask */ 3346 3347 #define SYS_HIRCTCTL_BOUNDARY_Pos (16) /*!< SYS_T::HIRCTCTL: BOUNDARY Position */ 3348 #define SYS_HIRCTCTL_BOUNDARY_Msk (0x1ful << SYS_HIRCTCTL_BOUNDARY_Pos) /*!< SYS_T::HIRCTCTL: BOUNDARY Mask */ 3349 3350 #define SYS_HIRCTIEN_TFAILIEN_Pos (1) /*!< SYS_T::HIRCTIEN: TFAILIEN Position */ 3351 #define SYS_HIRCTIEN_TFAILIEN_Msk (0x1ul << SYS_HIRCTIEN_TFAILIEN_Pos) /*!< SYS_T::HIRCTIEN: TFAILIEN Mask */ 3352 3353 #define SYS_HIRCTIEN_CLKEIEN_Pos (2) /*!< SYS_T::HIRCTIEN: CLKEIEN Position */ 3354 #define SYS_HIRCTIEN_CLKEIEN_Msk (0x1ul << SYS_HIRCTIEN_CLKEIEN_Pos) /*!< SYS_T::HIRCTIEN: CLKEIEN Mask */ 3355 3356 #define SYS_HIRCTISTS_FREQLOCK_Pos (0) /*!< SYS_T::HIRCTISTS: FREQLOCK Position */ 3357 #define SYS_HIRCTISTS_FREQLOCK_Msk (0x1ul << SYS_HIRCTISTS_FREQLOCK_Pos) /*!< SYS_T::HIRCTISTS: FREQLOCK Mask */ 3358 3359 #define SYS_HIRCTISTS_TFAILIF_Pos (1) /*!< SYS_T::HIRCTISTS: TFAILIF Position */ 3360 #define SYS_HIRCTISTS_TFAILIF_Msk (0x1ul << SYS_HIRCTISTS_TFAILIF_Pos) /*!< SYS_T::HIRCTISTS: TFAILIF Mask */ 3361 3362 #define SYS_HIRCTISTS_CLKERRIF_Pos (2) /*!< SYS_T::HIRCTISTS: CLKERRIF Position */ 3363 #define SYS_HIRCTISTS_CLKERRIF_Msk (0x1ul << SYS_HIRCTISTS_CLKERRIF_Pos) /*!< SYS_T::HIRCTISTS: CLKERRIF Mask */ 3364 3365 #define SYS_HIRCTISTS_OVBDIF_Pos (3) /*!< SYS_T::HIRCTISTS: OVBDIF Position */ 3366 #define SYS_HIRCTISTS_OVBDIF_Msk (0x1ul << SYS_HIRCTISTS_OVBDIF_Pos) /*!< SYS_T::HIRCTISTS: OVBDIF Mask */ 3367 3368 #define SYS_IRCTCTL_FREQSEL_Pos (0) /*!< SYS_T::IRCTCTL: FREQSEL Position */ 3369 #define SYS_IRCTCTL_FREQSEL_Msk (0x3ul << SYS_IRCTCTL_FREQSEL_Pos) /*!< SYS_T::IRCTCTL: FREQSEL Mask */ 3370 3371 #define SYS_IRCTCTL_LOOPSEL_Pos (4) /*!< SYS_T::IRCTCTL: LOOPSEL Position */ 3372 #define SYS_IRCTCTL_LOOPSEL_Msk (0x3ul << SYS_IRCTCTL_LOOPSEL_Pos) /*!< SYS_T::IRCTCTL: LOOPSEL Mask */ 3373 3374 #define SYS_IRCTCTL_RETRYCNT_Pos (6) /*!< SYS_T::IRCTCTL: RETRYCNT Position */ 3375 #define SYS_IRCTCTL_RETRYCNT_Msk (0x3ul << SYS_IRCTCTL_RETRYCNT_Pos) /*!< SYS_T::IRCTCTL: RETRYCNT Mask */ 3376 3377 #define SYS_IRCTCTL_CESTOPEN_Pos (8) /*!< SYS_T::IRCTCTL: CESTOPEN Position */ 3378 #define SYS_IRCTCTL_CESTOPEN_Msk (0x1ul << SYS_IRCTCTL_CESTOPEN_Pos) /*!< SYS_T::IRCTCTL: CESTOPEN Mask */ 3379 3380 #define SYS_IRCTCTL_REFCKSEL_Pos (10) /*!< SYS_T::IRCTCTL: REFCKSEL Position */ 3381 #define SYS_IRCTCTL_REFCKSEL_Msk (0x1ul << SYS_IRCTCTL_REFCKSEL_Pos) /*!< SYS_T::IRCTCTL: REFCKSEL Mask */ 3382 3383 #define SYS_IRCTIEN_TFAILIEN_Pos (1) /*!< SYS_T::IRCTIEN: TFAILIEN Position */ 3384 #define SYS_IRCTIEN_TFAILIEN_Msk (0x1ul << SYS_IRCTIEN_TFAILIEN_Pos) /*!< SYS_T::IRCTIEN: TFAILIEN Mask */ 3385 3386 #define SYS_IRCTIEN_CLKEIEN_Pos (2) /*!< SYS_T::IRCTIEN: CLKEIEN Position */ 3387 #define SYS_IRCTIEN_CLKEIEN_Msk (0x1ul << SYS_IRCTIEN_CLKEIEN_Pos) /*!< SYS_T::IRCTIEN: CLKEIEN Mask */ 3388 3389 #define SYS_IRCTISTS_FREQLOCK_Pos (0) /*!< SYS_T::IRCTISTS: FREQLOCK Position */ 3390 #define SYS_IRCTISTS_FREQLOCK_Msk (0x1ul << SYS_IRCTISTS_FREQLOCK_Pos) /*!< SYS_T::IRCTISTS: FREQLOCK Mask */ 3391 3392 #define SYS_IRCTISTS_TFAILIF_Pos (1) /*!< SYS_T::IRCTISTS: TFAILIF Position */ 3393 #define SYS_IRCTISTS_TFAILIF_Msk (0x1ul << SYS_IRCTISTS_TFAILIF_Pos) /*!< SYS_T::IRCTISTS: TFAILIF Mask */ 3394 3395 #define SYS_IRCTISTS_CLKERRIF_Pos (2) /*!< SYS_T::IRCTISTS: CLKERRIF Position */ 3396 #define SYS_IRCTISTS_CLKERRIF_Msk (0x1ul << SYS_IRCTISTS_CLKERRIF_Pos) /*!< SYS_T::IRCTISTS: CLKERRIF Mask */ 3397 3398 #define SYS_REGLCTL_REGLCTL_Pos (0) /*!< SYS_T::REGLCTL: REGLCTL Position */ 3399 #define SYS_REGLCTL_REGLCTL_Msk (0x1ul << SYS_REGLCTL_REGLCTL_Pos) /*!< SYS_T::REGLCTL: REGLCTL Mask */ 3400 3401 #define SYS_PORDISAN_POROFFAN_Pos (0) /*!< SYS_T::PORDISAN: POROFFAN Position */ 3402 #define SYS_PORDISAN_POROFFAN_Msk (0xfffful << SYS_PORDISAN_POROFFAN_Pos) /*!< SYS_T::PORDISAN: POROFFAN Mask */ 3403 3404 #define SYS_CSERVER_VERSION_Pos (0) /*!< SYS_T::CSERVER: VERSION Position */ 3405 #define SYS_CSERVER_VERSION_Msk (0xfful << SYS_CSERVER_VERSION_Pos) /*!< SYS_T::CSERVER: VERSION Mask */ 3406 3407 #define SYS_PLCTL_PLSEL_Pos (0) /*!< SYS_T::PLCTL: PLSEL Position */ 3408 #define SYS_PLCTL_PLSEL_Msk (0x3ul << SYS_PLCTL_PLSEL_Pos) /*!< SYS_T::PLCTL: PLSEL Mask */ 3409 3410 #define SYS_PLCTL_LVSSTEP_Pos (16) /*!< SYS_T::PLCTL: LVSSTEP Position */ 3411 #define SYS_PLCTL_LVSSTEP_Msk (0x3ful << SYS_PLCTL_LVSSTEP_Pos) /*!< SYS_T::PLCTL: LVSSTEP Mask */ 3412 3413 #define SYS_PLCTL_LVSPRD_Pos (24) /*!< SYS_T::PLCTL: LVSPRD Position */ 3414 #define SYS_PLCTL_LVSPRD_Msk (0xfful << SYS_PLCTL_LVSPRD_Pos) /*!< SYS_T::PLCTL: LVSPRD Mask */ 3415 3416 #define SYS_PLSTS_PLCBUSY_Pos (0) /*!< SYS_T::PLSTS: PLCBUSY Position */ 3417 #define SYS_PLSTS_PLCBUSY_Msk (0x1ul << SYS_PLSTS_PLCBUSY_Pos) /*!< SYS_T::PLSTS: PLCBUSY Mask */ 3418 3419 #define SYS_PLSTS_PLSTATUS_Pos (8) /*!< SYS_T::PLSTS: PLSTATUS Position */ 3420 #define SYS_PLSTS_PLSTATUS_Msk (0x3ul << SYS_PLSTS_PLSTATUS_Pos) /*!< SYS_T::PLSTS: PLSTATUS Mask */ 3421 3422 #define SYS_AHBMCTL_INTACTEN_Pos (0) /*!< SYS_T::AHBMCTL: INTACTEN Position */ 3423 #define SYS_AHBMCTL_INTACTEN_Msk (0x1ul << SYS_AHBMCTL_INTACTEN_Pos) /*!< SYS_T::AHBMCTL: INTACTEN Mask */ 3424 3425 /**@}*/ /* SYS_CONST */ 3426 /**@}*/ /* end of SYS register group */ 3427 3428 /** 3429 @addtogroup NMI NMI Controller (NMI) 3430 Memory Mapped Structure for NMI Controller 3431 @{ */ 3432 3433 typedef struct 3434 { 3435 3436 3437 /** 3438 * @var NMI_T::NMIEN 3439 * Offset: 0x00 NMI Source Interrupt Enable Register 3440 * --------------------------------------------------------------------------------------------------- 3441 * |Bits |Field |Descriptions 3442 * | :----: | :----: | :---- | 3443 * |[0] |BODOUT |BOD NMI Source Enable (Write Protect) 3444 * | | |0 = BOD NMI source Disabled. 3445 * | | |1 = BOD NMI source Enabled. 3446 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 3447 * |[1] |IRC_INT |IRC TRIM NMI Source Enable (Write Protect) 3448 * | | |0 = IRC TRIM NMI source Disabled. 3449 * | | |1 = IRC TRIM NMI source Enabled. 3450 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 3451 * |[2] |PWRWU_INT |Power-down Mode Wake-up NMI Source Enable (Write Protect) 3452 * | | |0 = Power-down mode wake-up NMI source Disabled. 3453 * | | |1 = Power-down mode wake-up NMI source Enabled. 3454 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 3455 * |[3] |SRAM_PERR |SRAM Parity Check NMI Source Enable (Write Protect) 3456 * | | |0 = SRAM parity check error NMI source Disabled. 3457 * | | |1 = SRAM parity check error NMI source Enabled. 3458 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 3459 * |[4] |CLKFAIL |Clock Fail Detected and IRC Auto Trim Interrupt NMI Source Enable (Write Protect) 3460 * | | |0 = Clock fail detected and IRC Auto Trim interrupt NMI source Disabled. 3461 * | | |1 = Clock fail detected and IRC Auto Trim interrupt NMI source Enabled. 3462 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 3463 * |[6] |RTC_INT |RTC NMI Source Enable (Write Protect) 3464 * | | |0 = RTC NMI source Disabled. 3465 * | | |1 = RTC NMI source Enabled. 3466 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 3467 * |[7] |TAMPER_INT|TAMPER_INT NMI Source Enable (Write Protect) 3468 * | | |0 = Backup register tamper detected NMI source Disabled. 3469 * | | |1 = Backup register tamper detected NMI source Enabled. 3470 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 3471 * |[8] |EINT0 |External Interrupt From PA.6 or PB.5 Pin NMI Source Enable (Write Protect) 3472 * | | |0 = External interrupt from PA.6 or PB.5 pin NMI source Disabled. 3473 * | | |1 = External interrupt from PA.6 or PB.5 pin NMI source Enabled. 3474 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 3475 * |[9] |EINT1 |External Interrupt From PA.7, PB.4 or PD.15 Pin NMI Source Enable (Write Protect) 3476 * | | |0 = External interrupt from PA.7, PB.4 or PD.15 pin NMI source Disabled. 3477 * | | |1 = External interrupt from PA.7, PB.4 or PD.15 pin NMI source Enabled. 3478 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 3479 * |[10] |EINT2 |External Interrupt From PB.3 or PC.6 Pin NMI Source Enable (Write Protect) 3480 * | | |0 = External interrupt from PB.3 or PC.6 pin NMI source Disabled. 3481 * | | |1 = External interrupt from PB.3 or PC.6 pin NMI source Enabled. 3482 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 3483 * |[11] |EINT3 |External Interrupt From PB.2 or PC.7 Pin NMI Source Enable (Write Protect) 3484 * | | |0 = External interrupt from PB.2 or PC.7 pin NMI source Disabled. 3485 * | | |1 = External interrupt from PB.2 or PC.7 pin NMI source Enabled. 3486 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 3487 * |[12] |EINT4 |External Interrupt From PA.8, PB.6 or PF.15 Pin NMI Source Enable (Write Protect) 3488 * | | |0 = External interrupt from PA.8, PB.6 or PF.15 pin NMI source Disabled. 3489 * | | |1 = External interrupt from PA.8, PB.6 or PF.15 pin NMI source Enabled. 3490 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 3491 * |[13] |EINT5 |External Interrupt From PB.7 or PF.14 Pin NMI Source Enable (Write Protect) 3492 * | | |0 = External interrupt from PB.7 or PF.14 pin NMI source Disabled. 3493 * | | |1 = External interrupt from PB.7 or PF.14 pin NMI source Enabled. 3494 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 3495 * |[14] |UART0_INT |UART0 NMI Source Enable (Write Protect) 3496 * | | |0 = UART0 NMI source Disabled. 3497 * | | |1 = UART0 NMI source Enabled. 3498 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 3499 * |[15] |UART1_INT |UART1 NMI Source Enable (Write Protect) 3500 * | | |0 = UART1 NMI source Disabled. 3501 * | | |1 = UART1 NMI source Enabled. 3502 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 3503 * @var NMI_T::NMISTS 3504 * Offset: 0x04 NMI Source Interrupt Status Register 3505 * --------------------------------------------------------------------------------------------------- 3506 * |Bits |Field |Descriptions 3507 * | :----: | :----: | :---- | 3508 * |[0] |BODOUT |BOD Interrupt Flag (Read Only) 3509 * | | |0 = BOD interrupt is deasserted. 3510 * | | |1 = BOD interrupt is asserted. 3511 * |[1] |IRC_INT |IRC TRIM Interrupt Flag (Read Only) 3512 * | | |0 = HIRC TRIM interrupt is deasserted. 3513 * | | |1 = HIRC TRIM interrupt is asserted. 3514 * |[2] |PWRWU_INT |Power-down Mode Wake-up Interrupt Flag (Read Only) 3515 * | | |0 = Power-down mode wake-up interrupt is deasserted. 3516 * | | |1 = Power-down mode wake-up interrupt is asserted. 3517 * |[3] |SRAM_PERR |SRAM ParityCheck Error Interrupt Flag (Read Only) 3518 * | | |0 = SRAM parity check error interrupt is deasserted. 3519 * | | |1 = SRAM parity check error interrupt is asserted. 3520 * |[4] |CLKFAIL |Clock Fail Detected or IRC Auto Trim Interrupt Flag (Read Only) 3521 * | | |0 = Clock fail detected or IRC Auto Trim interrupt is deasserted. 3522 * | | |1 = Clock fail detected or IRC Auto Trim interrupt is asserted. 3523 * |[6] |RTC_INT |RTC Interrupt Flag (Read Only) 3524 * | | |0 = RTC interrupt is deasserted. 3525 * | | |1 = RTC interrupt is asserted. 3526 * |[7] |TAMPER_INT|TAMPER_INT Interrupt Flag (Read Only) 3527 * | | |0 = Backup register tamper detected interrupt is deasserted. 3528 * | | |1 = Backup register tamper detected interrupt is asserted. 3529 * |[8] |EINT0 |External Interrupt From PA.6 or PB.5 Pin Interrupt Flag (Read Only) 3530 * | | |0 = External Interrupt from PA.6 or PB.5 interrupt is deasserted. 3531 * | | |1 = External Interrupt from PA.6 or PB.5 interrupt is asserted. 3532 * |[9] |EINT1 |External Interrupt From PA.7, PB.4 or PD.15 Pin Interrupt Flag (Read Only) 3533 * | | |0 = External Interrupt from PA.7, PB.4 or PD.15 interrupt is deasserted. 3534 * | | |1 = External Interrupt from PA.7, PB.4 or PD.15 interrupt is asserted. 3535 * |[10] |EINT2 |External Interrupt From PB.3 or PC.6 Pin Interrupt Flag (Read Only) 3536 * | | |0 = External Interrupt from PB.3 or PC.6 interrupt is deasserted. 3537 * | | |1 = External Interrupt from PB.3 or PC.6 interrupt is asserted. 3538 * |[11] |EINT3 |External Interrupt From PB.2 or PC.7 Pin Interrupt Flag (Read Only) 3539 * | | |0 = External Interrupt from PB.2 or PC.7 interrupt is deasserted. 3540 * | | |1 = External Interrupt from PB.2 or PC.7 interrupt is asserted. 3541 * |[12] |EINT4 |External Interrupt From PA.8, PB.6 or PF.15 Pin Interrupt Flag (Read Only) 3542 * | | |0 = External Interrupt from PA.8, PB.6 or PF.15 interrupt is deasserted. 3543 * | | |1 = External Interrupt from PA.8, PB.6 or PF.15 interrupt is asserted. 3544 * |[13] |EINT5 |External Interrupt From PB.7 or PF.14 Pin Interrupt Flag (Read Only) 3545 * | | |0 = External Interrupt from PB.7 or PF.14 interrupt is deasserted. 3546 * | | |1 = External Interrupt from PB.7 or PF.14 interrupt is asserted. 3547 * |[14] |UART0_INT |UART0 Interrupt Flag (Read Only) 3548 * | | |0 = UART1 interrupt is deasserted. 3549 * | | |1 = UART1 interrupt is asserted. 3550 * |[15] |UART1_INT |UART1 Interrupt Flag (Read Only) 3551 * | | |0 = UART1 interrupt is deasserted. 3552 * | | |1 = UART1 interrupt is asserted. 3553 */ 3554 __IO uint32_t NMIEN; /*!< [0x0000] NMI Source Interrupt Enable Register */ 3555 __I uint32_t NMISTS; /*!< [0x0004] NMI Source Interrupt Status Register */ 3556 3557 } NMI_T; 3558 3559 /** 3560 @addtogroup NMI_CONST NMI Bit Field Definition 3561 Constant Definitions for NMI Controller 3562 @{ */ 3563 3564 #define NMI_NMIEN_BODOUT_Pos (0) /*!< NMI_T::NMIEN: BODOUT Position */ 3565 #define NMI_NMIEN_BODOUT_Msk (0x1ul << NMI_NMIEN_BODOUT_Pos) /*!< NMI_T::NMIEN: BODOUT Mask */ 3566 3567 #define NMI_NMIEN_IRC_INT_Pos (1) /*!< NMI_T::NMIEN: IRC_INT Position */ 3568 #define NMI_NMIEN_IRC_INT_Msk (0x1ul << NMI_NMIEN_IRC_INT_Pos) /*!< NMI_T::NMIEN: IRC_INT Mask */ 3569 3570 #define NMI_NMIEN_PWRWU_INT_Pos (2) /*!< NMI_T::NMIEN: PWRWU_INT Position */ 3571 #define NMI_NMIEN_PWRWU_INT_Msk (0x1ul << NMI_NMIEN_PWRWU_INT_Pos) /*!< NMI_T::NMIEN: PWRWU_INT Mask */ 3572 3573 #define NMI_NMIEN_SRAM_PERR_Pos (3) /*!< NMI_T::NMIEN: SRAM_PERR Position */ 3574 #define NMI_NMIEN_SRAM_PERR_Msk (0x1ul << NMI_NMIEN_SRAM_PERR_Pos) /*!< NMI_T::NMIEN: SRAM_PERR Mask */ 3575 3576 #define NMI_NMIEN_CLKFAIL_Pos (4) /*!< NMI_T::NMIEN: CLKFAIL Position */ 3577 #define NMI_NMIEN_CLKFAIL_Msk (0x1ul << NMI_NMIEN_CLKFAIL_Pos) /*!< NMI_T::NMIEN: CLKFAIL Mask */ 3578 3579 #define NMI_NMIEN_RTC_INT_Pos (6) /*!< NMI_T::NMIEN: RTC_INT Position */ 3580 #define NMI_NMIEN_RTC_INT_Msk (0x1ul << NMI_NMIEN_RTC_INT_Pos) /*!< NMI_T::NMIEN: RTC_INT Mask */ 3581 3582 #define NMI_NMIEN_TAMPER_INT_Pos (7) /*!< NMI_T::NMIEN: TAMPER_INT Position */ 3583 #define NMI_NMIEN_TAMPER_INT_Msk (0x1ul << NMI_NMIEN_TAMPER_INT_Pos) /*!< NMI_T::NMIEN: TAMPER_INT Mask */ 3584 3585 #define NMI_NMIEN_EINT0_Pos (8) /*!< NMI_T::NMIEN: EINT0 Position */ 3586 #define NMI_NMIEN_EINT0_Msk (0x1ul << NMI_NMIEN_EINT0_Pos) /*!< NMI_T::NMIEN: EINT0 Mask */ 3587 3588 #define NMI_NMIEN_EINT1_Pos (9) /*!< NMI_T::NMIEN: EINT1 Position */ 3589 #define NMI_NMIEN_EINT1_Msk (0x1ul << NMI_NMIEN_EINT1_Pos) /*!< NMI_T::NMIEN: EINT1 Mask */ 3590 3591 #define NMI_NMIEN_EINT2_Pos (10) /*!< NMI_T::NMIEN: EINT2 Position */ 3592 #define NMI_NMIEN_EINT2_Msk (0x1ul << NMI_NMIEN_EINT2_Pos) /*!< NMI_T::NMIEN: EINT2 Mask */ 3593 3594 #define NMI_NMIEN_EINT3_Pos (11) /*!< NMI_T::NMIEN: EINT3 Position */ 3595 #define NMI_NMIEN_EINT3_Msk (0x1ul << NMI_NMIEN_EINT3_Pos) /*!< NMI_T::NMIEN: EINT3 Mask */ 3596 3597 #define NMI_NMIEN_EINT4_Pos (12) /*!< NMI_T::NMIEN: EINT4 Position */ 3598 #define NMI_NMIEN_EINT4_Msk (0x1ul << NMI_NMIEN_EINT4_Pos) /*!< NMI_T::NMIEN: EINT4 Mask */ 3599 3600 #define NMI_NMIEN_EINT5_Pos (13) /*!< NMI_T::NMIEN: EINT5 Position */ 3601 #define NMI_NMIEN_EINT5_Msk (0x1ul << NMI_NMIEN_EINT5_Pos) /*!< NMI_T::NMIEN: EINT5 Mask */ 3602 3603 #define NMI_NMIEN_UART0_INT_Pos (14) /*!< NMI_T::NMIEN: UART0_INT Position */ 3604 #define NMI_NMIEN_UART0_INT_Msk (0x1ul << NMI_NMIEN_UART0_INT_Pos) /*!< NMI_T::NMIEN: UART0_INT Mask */ 3605 3606 #define NMI_NMIEN_UART1_INT_Pos (15) /*!< NMI_T::NMIEN: UART1_INT Position */ 3607 #define NMI_NMIEN_UART1_INT_Msk (0x1ul << NMI_NMIEN_UART1_INT_Pos) /*!< NMI_T::NMIEN: UART1_INT Mask */ 3608 3609 #define NMI_NMISTS_BODOUT_Pos (0) /*!< NMI_T::NMISTS: BODOUT Position */ 3610 #define NMI_NMISTS_BODOUT_Msk (0x1ul << NMI_NMISTS_BODOUT_Pos) /*!< NMI_T::NMISTS: BODOUT Mask */ 3611 3612 #define NMI_NMISTS_IRC_INT_Pos (1) /*!< NMI_T::NMISTS: IRC_INT Position */ 3613 #define NMI_NMISTS_IRC_INT_Msk (0x1ul << NMI_NMISTS_IRC_INT_Pos) /*!< NMI_T::NMISTS: IRC_INT Mask */ 3614 3615 #define NMI_NMISTS_PWRWU_INT_Pos (2) /*!< NMI_T::NMISTS: PWRWU_INT Position */ 3616 #define NMI_NMISTS_PWRWU_INT_Msk (0x1ul << NMI_NMISTS_PWRWU_INT_Pos) /*!< NMI_T::NMISTS: PWRWU_INT Mask */ 3617 3618 #define NMI_NMISTS_SRAM_PERR_Pos (3) /*!< NMI_T::NMISTS: SRAM_PERR Position */ 3619 #define NMI_NMISTS_SRAM_PERR_Msk (0x1ul << NMI_NMISTS_SRAM_PERR_Pos) /*!< NMI_T::NMISTS: SRAM_PERR Mask */ 3620 3621 #define NMI_NMISTS_CLKFAIL_Pos (4) /*!< NMI_T::NMISTS: CLKFAIL Position */ 3622 #define NMI_NMISTS_CLKFAIL_Msk (0x1ul << NMI_NMISTS_CLKFAIL_Pos) /*!< NMI_T::NMISTS: CLKFAIL Mask */ 3623 3624 #define NMI_NMISTS_RTC_INT_Pos (6) /*!< NMI_T::NMISTS: RTC_INT Position */ 3625 #define NMI_NMISTS_RTC_INT_Msk (0x1ul << NMI_NMISTS_RTC_INT_Pos) /*!< NMI_T::NMISTS: RTC_INT Mask */ 3626 3627 #define NMI_NMISTS_TAMPER_INT_Pos (7) /*!< NMI_T::NMISTS: TAMPER_INT Position */ 3628 #define NMI_NMISTS_TAMPER_INT_Msk (0x1ul << NMI_NMISTS_TAMPER_INT_Pos) /*!< NMI_T::NMISTS: TAMPER_INT Mask */ 3629 3630 #define NMI_NMISTS_EINT0_Pos (8) /*!< NMI_T::NMISTS: EINT0 Position */ 3631 #define NMI_NMISTS_EINT0_Msk (0x1ul << NMI_NMISTS_EINT0_Pos) /*!< NMI_T::NMISTS: EINT0 Mask */ 3632 3633 #define NMI_NMISTS_EINT1_Pos (9) /*!< NMI_T::NMISTS: EINT1 Position */ 3634 #define NMI_NMISTS_EINT1_Msk (0x1ul << NMI_NMISTS_EINT1_Pos) /*!< NMI_T::NMISTS: EINT1 Mask */ 3635 3636 #define NMI_NMISTS_EINT2_Pos (10) /*!< NMI_T::NMISTS: EINT2 Position */ 3637 #define NMI_NMISTS_EINT2_Msk (0x1ul << NMI_NMISTS_EINT2_Pos) /*!< NMI_T::NMISTS: EINT2 Mask */ 3638 3639 #define NMI_NMISTS_EINT3_Pos (11) /*!< NMI_T::NMISTS: EINT3 Position */ 3640 #define NMI_NMISTS_EINT3_Msk (0x1ul << NMI_NMISTS_EINT3_Pos) /*!< NMI_T::NMISTS: EINT3 Mask */ 3641 3642 #define NMI_NMISTS_EINT4_Pos (12) /*!< NMI_T::NMISTS: EINT4 Position */ 3643 #define NMI_NMISTS_EINT4_Msk (0x1ul << NMI_NMISTS_EINT4_Pos) /*!< NMI_T::NMISTS: EINT4 Mask */ 3644 3645 #define NMI_NMISTS_EINT5_Pos (13) /*!< NMI_T::NMISTS: EINT5 Position */ 3646 #define NMI_NMISTS_EINT5_Msk (0x1ul << NMI_NMISTS_EINT5_Pos) /*!< NMI_T::NMISTS: EINT5 Mask */ 3647 3648 #define NMI_NMISTS_UART0_INT_Pos (14) /*!< NMI_T::NMISTS: UART0_INT Position */ 3649 #define NMI_NMISTS_UART0_INT_Msk (0x1ul << NMI_NMISTS_UART0_INT_Pos) /*!< NMI_T::NMISTS: UART0_INT Mask */ 3650 3651 #define NMI_NMISTS_UART1_INT_Pos (15) /*!< NMI_T::NMISTS: UART1_INT Position */ 3652 #define NMI_NMISTS_UART1_INT_Msk (0x1ul << NMI_NMISTS_UART1_INT_Pos) /*!< NMI_T::NMISTS: UART1_INT Mask */ 3653 3654 /**@}*/ /* NMI_CONST */ 3655 /**@}*/ /* end of NMI register group */ 3656 /**@}*/ /* end of REGISTER group */ 3657 3658 #if defined ( __CC_ARM ) 3659 #pragma no_anon_unions 3660 #endif 3661 3662 #endif /* __SYS_REG_H__ */ 3663
